VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 77807

Last change on this file since 77807 was 77293, checked in by vboxsync, 6 years ago

x86.h: Added X86_GREG_COUNT similar to the existing X86_SREG_COUNT for upcoming change.
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File size: 165.6 KB
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2019 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403/** @} */
404
405
406/** @name CPUID Feature information.
407 * CPUID query with EAX=1.
408 * @{
409 */
410/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
411#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
412/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
413#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
414/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
415#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
416/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
417#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
418/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
419#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
420/** ECX Bit 5 - VMX - Virtual Machine Technology. */
421#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
422/** ECX Bit 6 - SMX - Safer Mode Extensions. */
423#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
424/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
425#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
426/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
427#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
428/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
429#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
430/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
431#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
432/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
433 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
434#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
435/** ECX Bit 12 - FMA. */
436#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
437/** ECX Bit 13 - CX16 - CMPXCHG16B. */
438#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
439/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
440#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
441/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
442#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
443/** ECX Bit 17 - PCID - Process-context identifiers. */
444#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
445/** ECX Bit 18 - DCA - Direct Cache Access. */
446#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
447/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
448#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
449/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
450#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
451/** ECX Bit 21 - x2APIC support. */
452#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
453/** ECX Bit 22 - MOVBE instruction. */
454#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
455/** ECX Bit 23 - POPCNT instruction. */
456#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
457/** ECX Bir 24 - TSC-Deadline. */
458#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
459/** ECX Bit 25 - AES instructions. */
460#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
461/** ECX Bit 26 - XSAVE instruction. */
462#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
463/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
464#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
465/** ECX Bit 28 - AVX. */
466#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
467/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
468#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
469/** ECX Bit 30 - RDRAND instruction. */
470#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
471/** ECX Bit 31 - Hypervisor Present (software only). */
472#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
473
474
475/** Bit 0 - FPU - x87 FPU on Chip. */
476#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
477/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
478#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
479/** Bit 2 - DE - Debugging extensions. */
480#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
481/** Bit 3 - PSE - Page Size Extension. */
482#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
483#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
484/** Bit 4 - TSC - Time Stamp Counter. */
485#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
486/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
487#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
488/** Bit 6 - PAE - Physical Address Extension. */
489#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
490#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
491/** Bit 7 - MCE - Machine Check Exception. */
492#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
493/** Bit 8 - CX8 - CMPXCHG8B instruction. */
494#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
495/** Bit 9 - APIC - APIC On-Chip. */
496#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
497/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
498#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
499/** Bit 12 - MTRR - Memory Type Range Registers. */
500#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
501/** Bit 13 - PGE - PTE Global Bit. */
502#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
503/** Bit 14 - MCA - Machine Check Architecture. */
504#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
505/** Bit 15 - CMOV - Conditional Move Instructions. */
506#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
507/** Bit 16 - PAT - Page Attribute Table. */
508#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
509/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
510#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
511/** Bit 18 - PSN - Processor Serial Number. */
512#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
513/** Bit 19 - CLFSH - CLFLUSH Instruction. */
514#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
515/** Bit 21 - DS - Debug Store. */
516#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
517/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
518#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
519/** Bit 23 - MMX - Intel MMX Technology. */
520#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
521/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
522#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
523/** Bit 25 - SSE - SSE Support. */
524#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
525/** Bit 26 - SSE2 - SSE2 Support. */
526#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
527/** Bit 27 - SS - Self Snoop. */
528#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
529/** Bit 28 - HTT - Hyper-Threading Technology. */
530#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
531/** Bit 29 - TM - Therm. Monitor. */
532#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
533/** Bit 31 - PBE - Pending Break Enabled. */
534#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
535/** @} */
536
537/** @name CPUID mwait/monitor information.
538 * CPUID query with EAX=5.
539 * @{
540 */
541/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
542#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
543/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
544#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
545/** @} */
546
547
548/** @name CPUID Structured Extended Feature information.
549 * CPUID query with EAX=7.
550 * @{
551 */
552/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
553#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
554/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
555#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
556/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
557#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
558/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
559#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
560/** EBX Bit 4 - HLE - Hardware Lock Elision. */
561#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
562/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
563#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
564/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
565#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
566/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
567#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
568/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
569#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
570/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
571#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
572/** EBX Bit 10 - INVPCID - Supports INVPCID. */
573#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
574/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
575#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
576/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
577#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
578/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
579#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
580/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
581#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
582/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
583#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
584/** EBX Bit 16 - AVX512F - Supports AVX512F. */
585#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
586/** EBX Bit 18 - RDSEED - Supports RDSEED. */
587#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
588/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
589#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
590/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
591#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
592/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
593#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
594/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
595#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
596/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
597#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
598/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
599#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
600/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
601#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
602/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
603#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
604
605/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
606#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
607/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
608#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
609/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
610#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
611/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
612#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
613/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
614#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
615/** ECX Bit 22 - RDPID - Support pread process ID. */
616#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
617/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
618#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
619
620/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
621 * IBPB command in IA32_PRED_CMD. */
622#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
623/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
624#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
625/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
626#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
627/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
628#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
629
630/** @} */
631
632
633/** @name CPUID Extended Feature information.
634 * CPUID query with EAX=0x80000001.
635 * @{
636 */
637/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
638#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
639
640/** EDX Bit 11 - SYSCALL/SYSRET. */
641#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
642/** EDX Bit 20 - No-Execute/Execute-Disable. */
643#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
644/** EDX Bit 26 - 1 GB large page. */
645#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
646/** EDX Bit 27 - RDTSCP. */
647#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
648/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
649#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
650/** @}*/
651
652/** @name CPUID AMD Feature information.
653 * CPUID query with EAX=0x80000001.
654 * @{
655 */
656/** Bit 0 - FPU - x87 FPU on Chip. */
657#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
658/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
659#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
660/** Bit 2 - DE - Debugging extensions. */
661#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
662/** Bit 3 - PSE - Page Size Extension. */
663#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
664/** Bit 4 - TSC - Time Stamp Counter. */
665#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
666/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
667#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
668/** Bit 6 - PAE - Physical Address Extension. */
669#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
670/** Bit 7 - MCE - Machine Check Exception. */
671#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
672/** Bit 8 - CX8 - CMPXCHG8B instruction. */
673#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
674/** Bit 9 - APIC - APIC On-Chip. */
675#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
676/** Bit 12 - MTRR - Memory Type Range Registers. */
677#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
678/** Bit 13 - PGE - PTE Global Bit. */
679#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
680/** Bit 14 - MCA - Machine Check Architecture. */
681#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
682/** Bit 15 - CMOV - Conditional Move Instructions. */
683#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
684/** Bit 16 - PAT - Page Attribute Table. */
685#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
686/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
687#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
688/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
689#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
690/** Bit 23 - MMX - Intel MMX Technology. */
691#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
692/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
693#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
694/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
695#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
696/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
697#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
698/** Bit 31 - 3DNOW - AMD 3DNow. */
699#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
700
701/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
702#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
703/** Bit 2 - SVM - AMD VM extensions. */
704#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
705/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
706#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
707/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
708#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
709/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
710#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
711/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
712#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
713/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
714#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
715/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
716#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
717/** Bit 9 - OSVW - AMD OS visible workaround. */
718#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
719/** Bit 10 - IBS - Instruct based sampling. */
720#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
721/** Bit 11 - XOP - Extended operation support (see APM6). */
722#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
723/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
724#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
725/** Bit 13 - WDT - AMD Watchdog timer support. */
726#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
727/** Bit 15 - LWP - Lightweight profiling support. */
728#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
729/** Bit 16 - FMA4 - Four operand FMA instruction support. */
730#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
731/** Bit 19 - NodeId - Indicates support for
732 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
733#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
734/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
735#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
736/** Bit 22 - TopologyExtensions - . */
737#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
738/** @} */
739
740
741/** @name CPUID AMD Feature information.
742 * CPUID query with EAX=0x80000007.
743 * @{
744 */
745/** Bit 0 - TS - Temperature Sensor. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
747/** Bit 1 - FID - Frequency ID Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
749/** Bit 2 - VID - Voltage ID Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
751/** Bit 3 - TTP - THERMTRIP. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
753/** Bit 4 - TM - Hardware Thermal Control. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
755/** Bit 5 - STC - Software Thermal Control. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
757/** Bit 6 - MC - 100 Mhz Multiplier Control. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
759/** Bit 7 - HWPSTATE - Hardware P-State Control. */
760#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
761/** Bit 8 - TSCINVAR - TSC Invariant. */
762#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
763/** Bit 9 - CPB - TSC Invariant. */
764#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
765/** Bit 10 - EffFreqRO - MPERF/APERF. */
766#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
767/** Bit 11 - PFI - Processor feedback interface (see EAX). */
768#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
769/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
770#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
771/** @} */
772
773
774/** @name CPUID AMD extended feature extensions ID (EBX).
775 * CPUID query with EAX=0x80000008.
776 * @{
777 */
778/** Bit 0 - CLZERO - Clear zero instruction. */
779#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
780/** Bit 1 - IRPerf - Instructions retired count support. */
781#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
782/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
783#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
784/* AMD pipeline length: 9 feature bits ;-) */
785/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
786#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
787/** @} */
788
789
790/** @name CPUID AMD SVM Feature information.
791 * CPUID query with EAX=0x8000000a.
792 * @{
793 */
794/** Bit 0 - NP - Nested Paging supported. */
795#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
796/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
797#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
798/** Bit 2 - SVML - SVM locking bit supported. */
799#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
800/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
801#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
802/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
803#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
804/** Bit 5 - VmcbClean - Support VMCB clean bits. */
805#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
806/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
807 * VMCB.TLB_Control is supported. */
808#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
809/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
810#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
811/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
812#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
813/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
814 * intercept filter cycle count threshold. */
815#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
816/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
817#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
818/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
819#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
820/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
821#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
822/** @} */
823
824
825/** @name CR0
826 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
827 * reserved flags.
828 * @{ */
829/** Bit 0 - PE - Protection Enabled */
830#define X86_CR0_PE RT_BIT_32(0)
831#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
832/** Bit 1 - MP - Monitor Coprocessor */
833#define X86_CR0_MP RT_BIT_32(1)
834#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
835/** Bit 2 - EM - Emulation. */
836#define X86_CR0_EM RT_BIT_32(2)
837#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
838/** Bit 3 - TS - Task Switch. */
839#define X86_CR0_TS RT_BIT_32(3)
840#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
841/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
842#define X86_CR0_ET RT_BIT_32(4)
843#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
844/** Bit 5 - NE - Numeric error (486+). */
845#define X86_CR0_NE RT_BIT_32(5)
846#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
847/** Bit 16 - WP - Write Protect (486+). */
848#define X86_CR0_WP RT_BIT_32(16)
849#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
850/** Bit 18 - AM - Alignment Mask (486+). */
851#define X86_CR0_AM RT_BIT_32(18)
852#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
853/** Bit 29 - NW - Not Write-though (486+). */
854#define X86_CR0_NW RT_BIT_32(29)
855#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
856/** Bit 30 - WP - Cache Disable (486+). */
857#define X86_CR0_CD RT_BIT_32(30)
858#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
859/** Bit 31 - PG - Paging. */
860#define X86_CR0_PG RT_BIT_32(31)
861#define X86_CR0_PAGING RT_BIT_32(31)
862#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
863/** @} */
864
865
866/** @name CR3
867 * @{ */
868/** Bit 3 - PWT - Page-level Writes Transparent. */
869#define X86_CR3_PWT RT_BIT_32(3)
870/** Bit 4 - PCD - Page-level Cache Disable. */
871#define X86_CR3_PCD RT_BIT_32(4)
872/** Bits 12-31 - - Page directory page number. */
873#define X86_CR3_PAGE_MASK (0xfffff000)
874/** Bits 5-31 - - PAE Page directory page number. */
875#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
876/** Bits 12-51 - - AMD64 Page directory page number. */
877#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
878/** @} */
879
880
881/** @name CR4
882 * @{ */
883/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
884#define X86_CR4_VME RT_BIT_32(0)
885/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
886#define X86_CR4_PVI RT_BIT_32(1)
887/** Bit 2 - TSD - Time Stamp Disable. */
888#define X86_CR4_TSD RT_BIT_32(2)
889/** Bit 3 - DE - Debugging Extensions. */
890#define X86_CR4_DE RT_BIT_32(3)
891/** Bit 4 - PSE - Page Size Extension. */
892#define X86_CR4_PSE RT_BIT_32(4)
893/** Bit 5 - PAE - Physical Address Extension. */
894#define X86_CR4_PAE RT_BIT_32(5)
895/** Bit 6 - MCE - Machine-Check Enable. */
896#define X86_CR4_MCE RT_BIT_32(6)
897/** Bit 7 - PGE - Page Global Enable. */
898#define X86_CR4_PGE RT_BIT_32(7)
899/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
900#define X86_CR4_PCE RT_BIT_32(8)
901/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
902#define X86_CR4_OSFXSR RT_BIT_32(9)
903/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
904#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
905/** Bit 13 - VMXE - VMX mode is enabled. */
906#define X86_CR4_VMXE RT_BIT_32(13)
907/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
908#define X86_CR4_SMXE RT_BIT_32(14)
909/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
910#define X86_CR4_FSGSBASE RT_BIT_32(16)
911/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
912#define X86_CR4_PCIDE RT_BIT_32(17)
913/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
914 * extended states. */
915#define X86_CR4_OSXSAVE RT_BIT_32(18)
916/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
917#define X86_CR4_SMEP RT_BIT_32(20)
918/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
919#define X86_CR4_SMAP RT_BIT_32(21)
920/** Bit 22 - PKE - Protection Key Enable. */
921#define X86_CR4_PKE RT_BIT_32(22)
922/** @} */
923
924
925/** @name DR6
926 * @{ */
927/** Bit 0 - B0 - Breakpoint 0 condition detected. */
928#define X86_DR6_B0 RT_BIT_32(0)
929/** Bit 1 - B1 - Breakpoint 1 condition detected. */
930#define X86_DR6_B1 RT_BIT_32(1)
931/** Bit 2 - B2 - Breakpoint 2 condition detected. */
932#define X86_DR6_B2 RT_BIT_32(2)
933/** Bit 3 - B3 - Breakpoint 3 condition detected. */
934#define X86_DR6_B3 RT_BIT_32(3)
935/** Mask of all the Bx bits. */
936#define X86_DR6_B_MASK UINT64_C(0x0000000f)
937/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
938#define X86_DR6_BD RT_BIT_32(13)
939/** Bit 14 - BS - Single step */
940#define X86_DR6_BS RT_BIT_32(14)
941/** Bit 15 - BT - Task switch. (TSS T bit.) */
942#define X86_DR6_BT RT_BIT_32(15)
943/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
944#define X86_DR6_RTM RT_BIT_32(16)
945/** Value of DR6 after powerup/reset. */
946#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
947/** Bits which must be 1s in DR6. */
948#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
949/** Bits which must be 1s in DR6, when RTM is supported. */
950#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
951/** Bits which must be 0s in DR6. */
952#define X86_DR6_RAZ_MASK RT_BIT_64(12)
953/** Bits which must be 0s on writes to DR6. */
954#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
955/** @} */
956
957/** Get the DR6.Bx bit for a the given breakpoint. */
958#define X86_DR6_B(iBp) RT_BIT_64(iBp)
959
960
961/** @name DR7
962 * @{ */
963/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
964#define X86_DR7_L0 RT_BIT_32(0)
965/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
966#define X86_DR7_G0 RT_BIT_32(1)
967/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
968#define X86_DR7_L1 RT_BIT_32(2)
969/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
970#define X86_DR7_G1 RT_BIT_32(3)
971/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
972#define X86_DR7_L2 RT_BIT_32(4)
973/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
974#define X86_DR7_G2 RT_BIT_32(5)
975/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
976#define X86_DR7_L3 RT_BIT_32(6)
977/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
978#define X86_DR7_G3 RT_BIT_32(7)
979/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
980#define X86_DR7_LE RT_BIT_32(8)
981/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
982#define X86_DR7_GE RT_BIT_32(9)
983
984/** L0, L1, L2, and L3. */
985#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
986/** L0, L1, L2, and L3. */
987#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
988
989/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
990 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
991#define X86_DR7_RTM RT_BIT_32(11)
992/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
993 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
994 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
995 * instruction is executed.
996 * @see http://www.rcollins.org/secrets/DR7.html */
997#define X86_DR7_ICE_IR RT_BIT_32(12)
998/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
999 * any DR register is accessed. */
1000#define X86_DR7_GD RT_BIT_32(13)
1001/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1002 * Pentium. */
1003#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1004/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1005#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1006/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1007#define X86_DR7_RW0_MASK (3 << 16)
1008/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1009#define X86_DR7_LEN0_MASK (3 << 18)
1010/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1011#define X86_DR7_RW1_MASK (3 << 20)
1012/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1013#define X86_DR7_LEN1_MASK (3 << 22)
1014/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1015#define X86_DR7_RW2_MASK (3 << 24)
1016/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1017#define X86_DR7_LEN2_MASK (3 << 26)
1018/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1019#define X86_DR7_RW3_MASK (3 << 28)
1020/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1021#define X86_DR7_LEN3_MASK (3 << 30)
1022
1023/** Bits which reads as 1s. */
1024#define X86_DR7_RA1_MASK RT_BIT_32(10)
1025/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1026#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1027/** Bits which must be 0s when writing to DR7. */
1028#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1029
1030/** Calcs the L bit of Nth breakpoint.
1031 * @param iBp The breakpoint number [0..3].
1032 */
1033#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1034
1035/** Calcs the G bit of Nth breakpoint.
1036 * @param iBp The breakpoint number [0..3].
1037 */
1038#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1039
1040/** Calcs the L and G bits of Nth breakpoint.
1041 * @param iBp The breakpoint number [0..3].
1042 */
1043#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1044
1045/** @name Read/Write values.
1046 * @{ */
1047/** Break on instruction fetch only. */
1048#define X86_DR7_RW_EO UINT32_C(0)
1049/** Break on write only. */
1050#define X86_DR7_RW_WO UINT32_C(1)
1051/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1052#define X86_DR7_RW_IO UINT32_C(2)
1053/** Break on read or write (but not instruction fetches). */
1054#define X86_DR7_RW_RW UINT32_C(3)
1055/** @} */
1056
1057/** Shifts a X86_DR7_RW_* value to its right place.
1058 * @param iBp The breakpoint number [0..3].
1059 * @param fRw One of the X86_DR7_RW_* value.
1060 */
1061#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1062
1063/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1064 * one of the X86_DR7_RW_XXX constants).
1065 *
1066 * @returns X86_DR7_RW_XXX
1067 * @param uDR7 DR7 value
1068 * @param iBp The breakpoint number [0..3].
1069 */
1070#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1071
1072/** R/W0, R/W1, R/W2, and R/W3. */
1073#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1074
1075#ifndef VBOX_FOR_DTRACE_LIB
1076/** Checks if there are any I/O breakpoint types configured in the RW
1077 * registers. Does NOT check if these are enabled, sorry. */
1078# define X86_DR7_ANY_RW_IO(uDR7) \
1079 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1080 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1081AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1082AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1083AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1084AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1085AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1086AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1087AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1088AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1089AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1090#endif /* !VBOX_FOR_DTRACE_LIB */
1091
1092/** @name Length values.
1093 * @{ */
1094#define X86_DR7_LEN_BYTE UINT32_C(0)
1095#define X86_DR7_LEN_WORD UINT32_C(1)
1096#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1097#define X86_DR7_LEN_DWORD UINT32_C(3)
1098/** @} */
1099
1100/** Shifts a X86_DR7_LEN_* value to its right place.
1101 * @param iBp The breakpoint number [0..3].
1102 * @param cb One of the X86_DR7_LEN_* values.
1103 */
1104#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1105
1106/** Fetch the breakpoint length bits from the DR7 value.
1107 * @param uDR7 DR7 value
1108 * @param iBp The breakpoint number [0..3].
1109 */
1110#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1111
1112/** Mask used to check if any breakpoints are enabled. */
1113#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1114
1115/** LEN0, LEN1, LEN2, and LEN3. */
1116#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1117/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1118#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1119
1120/** Value of DR7 after powerup/reset. */
1121#define X86_DR7_INIT_VAL 0x400
1122/** @} */
1123
1124
1125/** @name Machine Specific Registers
1126 * @{
1127 */
1128/** Machine check address register (P5). */
1129#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1130/** Machine check type register (P5). */
1131#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1132/** Time Stamp Counter. */
1133#define MSR_IA32_TSC 0x10
1134#define MSR_IA32_CESR UINT32_C(0x00000011)
1135#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1136#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1137
1138#define MSR_IA32_PLATFORM_ID 0x17
1139
1140#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1141# define MSR_IA32_APICBASE 0x1b
1142/** Local APIC enabled. */
1143# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1144/** X2APIC enabled (requires the EN bit to be set). */
1145# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1146/** The processor is the boot strap processor (BSP). */
1147# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1148/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1149 * width. */
1150# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1151/** The default physical base address of the APIC. */
1152# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1153/** Gets the physical base address from the MSR. */
1154# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1155#endif
1156
1157/** Undocumented intel MSR for reporting thread and core counts.
1158 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1159 * first 16 bits is the thread count. The next 16 bits the core count, except
1160 * on Westmere where it seems it's only the next 4 bits for some reason. */
1161#define MSR_CORE_THREAD_COUNT 0x35
1162
1163/** CPU Feature control. */
1164#define MSR_IA32_FEATURE_CONTROL 0x3A
1165/** Feature control - Lock MSR from writes (R/W0). */
1166#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1167/** Feature control - Enable VMX inside SMX operation (R/WL). */
1168#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1169/** Feature control - Enable VMX outside SMX operation (R/WL). */
1170#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1171/** Feature control - SENTER local functions enable (R/WL). */
1172#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1173#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1174#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1175#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1176#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1177#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1178#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1179/** Feature control - SENTER global enable (R/WL). */
1180#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1181/** Feature control - SGX launch control enable (R/WL). */
1182#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1183/** Feature control - SGX global enable (R/WL). */
1184#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1185/** Feature control - LMCE on (R/WL). */
1186#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1187
1188/** Per-processor TSC adjust MSR. */
1189#define MSR_IA32_TSC_ADJUST 0x3B
1190
1191/** Spectre control register.
1192 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1193#define MSR_IA32_SPEC_CTRL 0x48
1194/** IBRS - Indirect branch restricted speculation. */
1195#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1196/** STIBP - Single thread indirect branch predictors. */
1197#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1198
1199/** Prediction command register.
1200 * Write only, logical processor scope, no state since write only. */
1201#define MSR_IA32_PRED_CMD 0x49
1202/** IBPB - Indirect branch prediction barrie when written as 1. */
1203#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1204
1205/** BIOS update trigger (microcode update). */
1206#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1207
1208/** BIOS update signature (microcode). */
1209#define MSR_IA32_BIOS_SIGN_ID 0x8B
1210
1211/** SMM monitor control. */
1212#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1213/** SMM control - Valid. */
1214#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1215/** SMM control - VMXOFF unblocks SMI. */
1216#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1217/** SMM control - MSEG base physical address. */
1218#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1219
1220/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1221#define MSR_IA32_SMBASE 0x9E
1222
1223/** General performance counter no. 0. */
1224#define MSR_IA32_PMC0 0xC1
1225/** General performance counter no. 1. */
1226#define MSR_IA32_PMC1 0xC2
1227/** General performance counter no. 2. */
1228#define MSR_IA32_PMC2 0xC3
1229/** General performance counter no. 3. */
1230#define MSR_IA32_PMC3 0xC4
1231
1232/** Nehalem power control. */
1233#define MSR_IA32_PLATFORM_INFO 0xCE
1234
1235/** Get FSB clock status (Intel-specific). */
1236#define MSR_IA32_FSB_CLOCK_STS 0xCD
1237
1238/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1239#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1240
1241/** C0 Maximum Frequency Clock Count */
1242#define MSR_IA32_MPERF 0xE7
1243/** C0 Actual Frequency Clock Count */
1244#define MSR_IA32_APERF 0xE8
1245
1246/** MTRR Capabilities. */
1247#define MSR_IA32_MTRR_CAP 0xFE
1248
1249/** Architecture capabilities (bugfixes). */
1250#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1251/** CPU is no subject to meltdown problems. */
1252#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1253/** CPU has better IBRS and you can leave it on all the time. */
1254#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1255/** CPU has return stack buffer (RSB) override. */
1256#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1257/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1258 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1259#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1260
1261/** Flush command register. */
1262#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1263/** Flush the level 1 data cache when this bit is written. */
1264#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1265
1266/** Cache control/info. */
1267#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1268
1269#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1270/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1271 * R0 SS == CS + 8
1272 * R3 CS == CS + 16
1273 * R3 SS == CS + 24
1274 */
1275#define MSR_IA32_SYSENTER_CS 0x174
1276/** SYSENTER_ESP - the R0 ESP. */
1277#define MSR_IA32_SYSENTER_ESP 0x175
1278/** SYSENTER_EIP - the R0 EIP. */
1279#define MSR_IA32_SYSENTER_EIP 0x176
1280#endif
1281
1282/** Machine Check Global Capabilities Register. */
1283#define MSR_IA32_MCG_CAP 0x179
1284/** Machine Check Global Status Register. */
1285#define MSR_IA32_MCG_STATUS 0x17A
1286/** Machine Check Global Control Register. */
1287#define MSR_IA32_MCG_CTRL 0x17B
1288
1289/** Page Attribute Table. */
1290#define MSR_IA32_CR_PAT 0x277
1291/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1292 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1293#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1294
1295/** Performance counter MSRs. (Intel only) */
1296#define MSR_IA32_PERFEVTSEL0 0x186
1297#define MSR_IA32_PERFEVTSEL1 0x187
1298/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1299 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1300 * holds a ratio that Apple takes for TSC granularity.
1301 *
1302 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1303#define MSR_FLEX_RATIO 0x194
1304/** Performance state value and starting with Intel core more.
1305 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1306#define MSR_IA32_PERF_STATUS 0x198
1307#define MSR_IA32_PERF_CTL 0x199
1308#define MSR_IA32_THERM_STATUS 0x19c
1309
1310/** Enable misc. processor features (R/W). */
1311#define MSR_IA32_MISC_ENABLE 0x1A0
1312/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1313#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1314/** Automatic Thermal Control Circuit Enable (R/W). */
1315#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1316/** Performance Monitoring Available (R). */
1317#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1318/** Branch Trace Storage Unavailable (R/O). */
1319#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1320/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1321#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1322/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1323#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1324/** If MONITOR/MWAIT is supported (R/W). */
1325#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1326/** Limit CPUID Maxval to 3 leafs (R/W). */
1327#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1328/** When set to 1, xTPR messages are disabled (R/W). */
1329#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1330/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1331#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1332
1333/** Trace/Profile Resource Control (R/W) */
1334#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1335/** Last branch record. */
1336#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1337/** Branch trace flag (single step on branches). */
1338#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1339/** Performance monitoring pin control (AMD only). */
1340#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1341#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1342#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1343#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1344/** Trace message enable (Intel only). */
1345#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1346/** Branch trace store (Intel only). */
1347#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1348/** Branch trace interrupt (Intel only). */
1349#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1350/** Branch trace off in privileged code (Intel only). */
1351#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1352/** Branch trace off in user code (Intel only). */
1353#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1354/** Freeze LBR on PMI flag (Intel only). */
1355#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1356/** Freeze PERFMON on PMI flag (Intel only). */
1357#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1358/** Freeze while SMM enabled (Intel only). */
1359#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1360/** Advanced debugging of RTM regions (Intel only). */
1361#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1362/** Debug control MSR valid bits (Intel only). */
1363#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1364 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1365 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1366 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1367 | MSR_IA32_DEBUGCTL_RTM)
1368
1369/** The number (0..3 or 0..15) of the last branch record register on P4 and
1370 * related Xeons. */
1371#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1372/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1373 * @{ */
1374#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1375#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1376#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1377#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1378/** @} */
1379
1380
1381#define IA32_MTRR_PHYSBASE0 0x200
1382#define IA32_MTRR_PHYSMASK0 0x201
1383#define IA32_MTRR_PHYSBASE1 0x202
1384#define IA32_MTRR_PHYSMASK1 0x203
1385#define IA32_MTRR_PHYSBASE2 0x204
1386#define IA32_MTRR_PHYSMASK2 0x205
1387#define IA32_MTRR_PHYSBASE3 0x206
1388#define IA32_MTRR_PHYSMASK3 0x207
1389#define IA32_MTRR_PHYSBASE4 0x208
1390#define IA32_MTRR_PHYSMASK4 0x209
1391#define IA32_MTRR_PHYSBASE5 0x20a
1392#define IA32_MTRR_PHYSMASK5 0x20b
1393#define IA32_MTRR_PHYSBASE6 0x20c
1394#define IA32_MTRR_PHYSMASK6 0x20d
1395#define IA32_MTRR_PHYSBASE7 0x20e
1396#define IA32_MTRR_PHYSMASK7 0x20f
1397#define IA32_MTRR_PHYSBASE8 0x210
1398#define IA32_MTRR_PHYSMASK8 0x211
1399#define IA32_MTRR_PHYSBASE9 0x212
1400#define IA32_MTRR_PHYSMASK9 0x213
1401
1402/** Fixed range MTRRs.
1403 * @{ */
1404#define IA32_MTRR_FIX64K_00000 0x250
1405#define IA32_MTRR_FIX16K_80000 0x258
1406#define IA32_MTRR_FIX16K_A0000 0x259
1407#define IA32_MTRR_FIX4K_C0000 0x268
1408#define IA32_MTRR_FIX4K_C8000 0x269
1409#define IA32_MTRR_FIX4K_D0000 0x26a
1410#define IA32_MTRR_FIX4K_D8000 0x26b
1411#define IA32_MTRR_FIX4K_E0000 0x26c
1412#define IA32_MTRR_FIX4K_E8000 0x26d
1413#define IA32_MTRR_FIX4K_F0000 0x26e
1414#define IA32_MTRR_FIX4K_F8000 0x26f
1415/** @} */
1416
1417/** MTRR Default Range. */
1418#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1419
1420/** Global performance counter control facilities (Intel only). */
1421#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1422#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1423#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1424
1425/** Precise Event Based sampling (Intel only). */
1426#define MSR_IA32_PEBS_ENABLE 0x3F1
1427
1428#define MSR_IA32_MC0_CTL 0x400
1429#define MSR_IA32_MC0_STATUS 0x401
1430
1431/** Basic VMX information. */
1432#define MSR_IA32_VMX_BASIC 0x480
1433/** Allowed settings for pin-based VM execution controls. */
1434#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1435/** Allowed settings for proc-based VM execution controls. */
1436#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1437/** Allowed settings for the VM-exit controls. */
1438#define MSR_IA32_VMX_EXIT_CTLS 0x483
1439/** Allowed settings for the VM-entry controls. */
1440#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1441/** Misc VMX info. */
1442#define MSR_IA32_VMX_MISC 0x485
1443/** Fixed cleared bits in CR0. */
1444#define MSR_IA32_VMX_CR0_FIXED0 0x486
1445/** Fixed set bits in CR0. */
1446#define MSR_IA32_VMX_CR0_FIXED1 0x487
1447/** Fixed cleared bits in CR4. */
1448#define MSR_IA32_VMX_CR4_FIXED0 0x488
1449/** Fixed set bits in CR4. */
1450#define MSR_IA32_VMX_CR4_FIXED1 0x489
1451/** Information for enumerating fields in the VMCS. */
1452#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1453/** Allowed settings for secondary proc-based VM execution controls */
1454#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1455/** EPT capabilities. */
1456#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1457/** Allowed settings of all pin-based VM execution controls. */
1458#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1459/** Allowed settings of all proc-based VM execution controls. */
1460#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1461/** Allowed settings of all VMX exit controls. */
1462#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1463/** Allowed settings of all VMX entry controls. */
1464#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1465/** Allowed settings for the VM-function controls. */
1466#define MSR_IA32_VMX_VMFUNC 0x491
1467
1468/** Intel PT - Enable and control for trace packet generation. */
1469#define MSR_IA32_RTIT_CTL 0x570
1470
1471/** DS Save Area (R/W). */
1472#define MSR_IA32_DS_AREA 0x600
1473/** Running Average Power Limit (RAPL) power units. */
1474#define MSR_RAPL_POWER_UNIT 0x606
1475
1476/** X2APIC MSR range start. */
1477#define MSR_IA32_X2APIC_START 0x800
1478/** X2APIC MSR - APIC ID Register. */
1479#define MSR_IA32_X2APIC_ID 0x802
1480/** X2APIC MSR - APIC Version Register. */
1481#define MSR_IA32_X2APIC_VERSION 0x803
1482/** X2APIC MSR - Task Priority Register. */
1483#define MSR_IA32_X2APIC_TPR 0x808
1484/** X2APIC MSR - Processor Priority register. */
1485#define MSR_IA32_X2APIC_PPR 0x80A
1486/** X2APIC MSR - End Of Interrupt register. */
1487#define MSR_IA32_X2APIC_EOI 0x80B
1488/** X2APIC MSR - Logical Destination Register. */
1489#define MSR_IA32_X2APIC_LDR 0x80D
1490/** X2APIC MSR - Spurious Interrupt Vector Register. */
1491#define MSR_IA32_X2APIC_SVR 0x80F
1492/** X2APIC MSR - In-service Register (bits 31:0). */
1493#define MSR_IA32_X2APIC_ISR0 0x810
1494/** X2APIC MSR - In-service Register (bits 63:32). */
1495#define MSR_IA32_X2APIC_ISR1 0x811
1496/** X2APIC MSR - In-service Register (bits 95:64). */
1497#define MSR_IA32_X2APIC_ISR2 0x812
1498/** X2APIC MSR - In-service Register (bits 127:96). */
1499#define MSR_IA32_X2APIC_ISR3 0x813
1500/** X2APIC MSR - In-service Register (bits 159:128). */
1501#define MSR_IA32_X2APIC_ISR4 0x814
1502/** X2APIC MSR - In-service Register (bits 191:160). */
1503#define MSR_IA32_X2APIC_ISR5 0x815
1504/** X2APIC MSR - In-service Register (bits 223:192). */
1505#define MSR_IA32_X2APIC_ISR6 0x816
1506/** X2APIC MSR - In-service Register (bits 255:224). */
1507#define MSR_IA32_X2APIC_ISR7 0x817
1508/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1509#define MSR_IA32_X2APIC_TMR0 0x818
1510/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1511#define MSR_IA32_X2APIC_TMR1 0x819
1512/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1513#define MSR_IA32_X2APIC_TMR2 0x81A
1514/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1515#define MSR_IA32_X2APIC_TMR3 0x81B
1516/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1517#define MSR_IA32_X2APIC_TMR4 0x81C
1518/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1519#define MSR_IA32_X2APIC_TMR5 0x81D
1520/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1521#define MSR_IA32_X2APIC_TMR6 0x81E
1522/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1523#define MSR_IA32_X2APIC_TMR7 0x81F
1524/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1525#define MSR_IA32_X2APIC_IRR0 0x820
1526/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1527#define MSR_IA32_X2APIC_IRR1 0x821
1528/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1529#define MSR_IA32_X2APIC_IRR2 0x822
1530/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1531#define MSR_IA32_X2APIC_IRR3 0x823
1532/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1533#define MSR_IA32_X2APIC_IRR4 0x824
1534/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1535#define MSR_IA32_X2APIC_IRR5 0x825
1536/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1537#define MSR_IA32_X2APIC_IRR6 0x826
1538/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1539#define MSR_IA32_X2APIC_IRR7 0x827
1540/** X2APIC MSR - Error Status Register. */
1541#define MSR_IA32_X2APIC_ESR 0x828
1542/** X2APIC MSR - LVT CMCI Register. */
1543#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1544/** X2APIC MSR - Interrupt Command Register. */
1545#define MSR_IA32_X2APIC_ICR 0x830
1546/** X2APIC MSR - LVT Timer Register. */
1547#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1548/** X2APIC MSR - LVT Thermal Sensor Register. */
1549#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1550/** X2APIC MSR - LVT Performance Counter Register. */
1551#define MSR_IA32_X2APIC_LVT_PERF 0x834
1552/** X2APIC MSR - LVT LINT0 Register. */
1553#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1554/** X2APIC MSR - LVT LINT1 Register. */
1555#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1556/** X2APIC MSR - LVT Error Register . */
1557#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1558/** X2APIC MSR - Timer Initial Count Register. */
1559#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1560/** X2APIC MSR - Timer Current Count Register. */
1561#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1562/** X2APIC MSR - Timer Divide Configuration Register. */
1563#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1564/** X2APIC MSR - Self IPI. */
1565#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1566/** X2APIC MSR range end. */
1567#define MSR_IA32_X2APIC_END 0xBFF
1568/** X2APIC MSR - LVT start range. */
1569#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1570/** X2APIC MSR - LVT end range (inclusive). */
1571#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1572
1573/** K6 EFER - Extended Feature Enable Register. */
1574#define MSR_K6_EFER UINT32_C(0xc0000080)
1575/** @todo document EFER */
1576/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1577#define MSR_K6_EFER_SCE RT_BIT_32(0)
1578/** Bit 8 - LME - Long mode enabled. (R/W) */
1579#define MSR_K6_EFER_LME RT_BIT_32(8)
1580#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1581/** Bit 10 - LMA - Long mode active. (R) */
1582#define MSR_K6_EFER_LMA RT_BIT_32(10)
1583#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1584/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1585#define MSR_K6_EFER_NXE RT_BIT_32(11)
1586#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1587/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1588#define MSR_K6_EFER_SVME RT_BIT_32(12)
1589/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1590#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1591/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1592#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1593/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1594#define MSR_K6_EFER_TCE RT_BIT_32(15)
1595/** K6 STAR - SYSCALL/RET targets. */
1596#define MSR_K6_STAR UINT32_C(0xc0000081)
1597/** Shift value for getting the SYSRET CS and SS value. */
1598#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1599/** Shift value for getting the SYSCALL CS and SS value. */
1600#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1601/** Selector mask for use after shifting. */
1602#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1603/** The mask which give the SYSCALL EIP. */
1604#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1605/** K6 WHCR - Write Handling Control Register. */
1606#define MSR_K6_WHCR UINT32_C(0xc0000082)
1607/** K6 UWCCR - UC/WC Cacheability Control Register. */
1608#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1609/** K6 PSOR - Processor State Observability Register. */
1610#define MSR_K6_PSOR UINT32_C(0xc0000087)
1611/** K6 PFIR - Page Flush/Invalidate Register. */
1612#define MSR_K6_PFIR UINT32_C(0xc0000088)
1613
1614/** Performance counter MSRs. (AMD only) */
1615#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1616#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1617#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1618#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1619#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1620#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1621#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1622#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1623
1624/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1625#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1626/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1627#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1628/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1629#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1630/** K8 FS.base - The 64-bit base FS register. */
1631#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1632/** K8 GS.base - The 64-bit base GS register. */
1633#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1634/** K8 KernelGSbase - Used with SWAPGS. */
1635#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1636/** K8 TSC_AUX - Used with RDTSCP. */
1637#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1638#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1639#define MSR_K8_HWCR UINT32_C(0xc0010015)
1640#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1641#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1642#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1643#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1644#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1645#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1646/** North bridge config? See BIOS & Kernel dev guides for
1647 * details. */
1648#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1649
1650/** Hypertransport interrupt pending register.
1651 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1652#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1653
1654/** SVM Control. */
1655#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1656/** Disables HDT (Hardware Debug Tool) and certain internal debug
1657 * features. */
1658#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1659/** If set, non-intercepted INIT signals are converted to \#SX
1660 * exceptions. */
1661#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1662/** Disables A20 masking. */
1663#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1664/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1665#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1666/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1667 * clear, EFER.SVME can be written normally. */
1668#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1669
1670#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1671#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1672/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1673 * host state during world switch. */
1674#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1675
1676/** @} */
1677
1678
1679/** @name Page Table / Directory / Directory Pointers / L4.
1680 * @{
1681 */
1682
1683/** Page table/directory entry as an unsigned integer. */
1684typedef uint32_t X86PGUINT;
1685/** Pointer to a page table/directory table entry as an unsigned integer. */
1686typedef X86PGUINT *PX86PGUINT;
1687/** Pointer to an const page table/directory table entry as an unsigned integer. */
1688typedef X86PGUINT const *PCX86PGUINT;
1689
1690/** Number of entries in a 32-bit PT/PD. */
1691#define X86_PG_ENTRIES 1024
1692
1693
1694/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1695typedef uint64_t X86PGPAEUINT;
1696/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1697typedef X86PGPAEUINT *PX86PGPAEUINT;
1698/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1699typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1700
1701/** Number of entries in a PAE PT/PD. */
1702#define X86_PG_PAE_ENTRIES 512
1703/** Number of entries in a PAE PDPT. */
1704#define X86_PG_PAE_PDPE_ENTRIES 4
1705
1706/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1707#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1708/** Number of entries in an AMD64 PDPT.
1709 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1710#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1711
1712/** The size of a default page. */
1713#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1714/** The page shift of a default page. */
1715#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1716/** The default page offset mask. */
1717#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1718/** The default page base mask for virtual addresses. */
1719#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1720/** The default page base mask for virtual addresses - 32bit version. */
1721#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1722
1723/** The size of a 4KB page. */
1724#define X86_PAGE_4K_SIZE _4K
1725/** The page shift of a 4KB page. */
1726#define X86_PAGE_4K_SHIFT 12
1727/** The 4KB page offset mask. */
1728#define X86_PAGE_4K_OFFSET_MASK 0xfff
1729/** The 4KB page base mask for virtual addresses. */
1730#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1731/** The 4KB page base mask for virtual addresses - 32bit version. */
1732#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1733
1734/** The size of a 2MB page. */
1735#define X86_PAGE_2M_SIZE _2M
1736/** The page shift of a 2MB page. */
1737#define X86_PAGE_2M_SHIFT 21
1738/** The 2MB page offset mask. */
1739#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1740/** The 2MB page base mask for virtual addresses. */
1741#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1742/** The 2MB page base mask for virtual addresses - 32bit version. */
1743#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1744
1745/** The size of a 4MB page. */
1746#define X86_PAGE_4M_SIZE _4M
1747/** The page shift of a 4MB page. */
1748#define X86_PAGE_4M_SHIFT 22
1749/** The 4MB page offset mask. */
1750#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1751/** The 4MB page base mask for virtual addresses. */
1752#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1753/** The 4MB page base mask for virtual addresses - 32bit version. */
1754#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1755
1756/** The size of a 1GB page. */
1757#define X86_PAGE_1G_SIZE _1G
1758/** The page shift of a 1GB page. */
1759#define X86_PAGE_1G_SHIFT 30
1760/** The 1GB page offset mask. */
1761#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1762/** The 1GB page base mask for virtual addresses. */
1763#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1764
1765/**
1766 * Check if the given address is canonical.
1767 */
1768#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1769
1770
1771/** @name Page Table Entry
1772 * @{
1773 */
1774/** Bit 0 - P - Present bit. */
1775#define X86_PTE_BIT_P 0
1776/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1777#define X86_PTE_BIT_RW 1
1778/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1779#define X86_PTE_BIT_US 2
1780/** Bit 3 - PWT - Page level write thru bit. */
1781#define X86_PTE_BIT_PWT 3
1782/** Bit 4 - PCD - Page level cache disable bit. */
1783#define X86_PTE_BIT_PCD 4
1784/** Bit 5 - A - Access bit. */
1785#define X86_PTE_BIT_A 5
1786/** Bit 6 - D - Dirty bit. */
1787#define X86_PTE_BIT_D 6
1788/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1789#define X86_PTE_BIT_PAT 7
1790/** Bit 8 - G - Global flag. */
1791#define X86_PTE_BIT_G 8
1792/** Bits 63 - NX - PAE/LM - No execution flag. */
1793#define X86_PTE_PAE_BIT_NX 63
1794
1795/** Bit 0 - P - Present bit mask. */
1796#define X86_PTE_P RT_BIT_32(0)
1797/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1798#define X86_PTE_RW RT_BIT_32(1)
1799/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1800#define X86_PTE_US RT_BIT_32(2)
1801/** Bit 3 - PWT - Page level write thru bit mask. */
1802#define X86_PTE_PWT RT_BIT_32(3)
1803/** Bit 4 - PCD - Page level cache disable bit mask. */
1804#define X86_PTE_PCD RT_BIT_32(4)
1805/** Bit 5 - A - Access bit mask. */
1806#define X86_PTE_A RT_BIT_32(5)
1807/** Bit 6 - D - Dirty bit mask. */
1808#define X86_PTE_D RT_BIT_32(6)
1809/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1810#define X86_PTE_PAT RT_BIT_32(7)
1811/** Bit 8 - G - Global bit mask. */
1812#define X86_PTE_G RT_BIT_32(8)
1813
1814/** Bits 9-11 - - Available for use to system software. */
1815#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1816/** Bits 12-31 - - Physical Page number of the next level. */
1817#define X86_PTE_PG_MASK ( 0xfffff000 )
1818
1819/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1820#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1821/** Bits 63 - NX - PAE/LM - No execution flag. */
1822#define X86_PTE_PAE_NX RT_BIT_64(63)
1823/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1824#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1825/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1826#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1827/** No bits - - LM - MBZ bits when NX is active. */
1828#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1829/** Bits 63 - - LM - MBZ bits when no NX. */
1830#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1831
1832/**
1833 * Page table entry.
1834 */
1835typedef struct X86PTEBITS
1836{
1837 /** Flags whether(=1) or not the page is present. */
1838 uint32_t u1Present : 1;
1839 /** Read(=0) / Write(=1) flag. */
1840 uint32_t u1Write : 1;
1841 /** User(=1) / Supervisor (=0) flag. */
1842 uint32_t u1User : 1;
1843 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1844 uint32_t u1WriteThru : 1;
1845 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1846 uint32_t u1CacheDisable : 1;
1847 /** Accessed flag.
1848 * Indicates that the page have been read or written to. */
1849 uint32_t u1Accessed : 1;
1850 /** Dirty flag.
1851 * Indicates that the page has been written to. */
1852 uint32_t u1Dirty : 1;
1853 /** Reserved / If PAT enabled, bit 2 of the index. */
1854 uint32_t u1PAT : 1;
1855 /** Global flag. (Ignored in all but final level.) */
1856 uint32_t u1Global : 1;
1857 /** Available for use to system software. */
1858 uint32_t u3Available : 3;
1859 /** Physical Page number of the next level. */
1860 uint32_t u20PageNo : 20;
1861} X86PTEBITS;
1862#ifndef VBOX_FOR_DTRACE_LIB
1863AssertCompileSize(X86PTEBITS, 4);
1864#endif
1865/** Pointer to a page table entry. */
1866typedef X86PTEBITS *PX86PTEBITS;
1867/** Pointer to a const page table entry. */
1868typedef const X86PTEBITS *PCX86PTEBITS;
1869
1870/**
1871 * Page table entry.
1872 */
1873typedef union X86PTE
1874{
1875 /** Unsigned integer view */
1876 X86PGUINT u;
1877 /** Bit field view. */
1878 X86PTEBITS n;
1879 /** 32-bit view. */
1880 uint32_t au32[1];
1881 /** 16-bit view. */
1882 uint16_t au16[2];
1883 /** 8-bit view. */
1884 uint8_t au8[4];
1885} X86PTE;
1886#ifndef VBOX_FOR_DTRACE_LIB
1887AssertCompileSize(X86PTE, 4);
1888#endif
1889/** Pointer to a page table entry. */
1890typedef X86PTE *PX86PTE;
1891/** Pointer to a const page table entry. */
1892typedef const X86PTE *PCX86PTE;
1893
1894
1895/**
1896 * PAE page table entry.
1897 */
1898typedef struct X86PTEPAEBITS
1899{
1900 /** Flags whether(=1) or not the page is present. */
1901 uint32_t u1Present : 1;
1902 /** Read(=0) / Write(=1) flag. */
1903 uint32_t u1Write : 1;
1904 /** User(=1) / Supervisor(=0) flag. */
1905 uint32_t u1User : 1;
1906 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1907 uint32_t u1WriteThru : 1;
1908 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1909 uint32_t u1CacheDisable : 1;
1910 /** Accessed flag.
1911 * Indicates that the page have been read or written to. */
1912 uint32_t u1Accessed : 1;
1913 /** Dirty flag.
1914 * Indicates that the page has been written to. */
1915 uint32_t u1Dirty : 1;
1916 /** Reserved / If PAT enabled, bit 2 of the index. */
1917 uint32_t u1PAT : 1;
1918 /** Global flag. (Ignored in all but final level.) */
1919 uint32_t u1Global : 1;
1920 /** Available for use to system software. */
1921 uint32_t u3Available : 3;
1922 /** Physical Page number of the next level - Low Part. Don't use this. */
1923 uint32_t u20PageNoLow : 20;
1924 /** Physical Page number of the next level - High Part. Don't use this. */
1925 uint32_t u20PageNoHigh : 20;
1926 /** MBZ bits */
1927 uint32_t u11Reserved : 11;
1928 /** No Execute flag. */
1929 uint32_t u1NoExecute : 1;
1930} X86PTEPAEBITS;
1931#ifndef VBOX_FOR_DTRACE_LIB
1932AssertCompileSize(X86PTEPAEBITS, 8);
1933#endif
1934/** Pointer to a page table entry. */
1935typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1936/** Pointer to a page table entry. */
1937typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1938
1939/**
1940 * PAE Page table entry.
1941 */
1942typedef union X86PTEPAE
1943{
1944 /** Unsigned integer view */
1945 X86PGPAEUINT u;
1946 /** Bit field view. */
1947 X86PTEPAEBITS n;
1948 /** 32-bit view. */
1949 uint32_t au32[2];
1950 /** 16-bit view. */
1951 uint16_t au16[4];
1952 /** 8-bit view. */
1953 uint8_t au8[8];
1954} X86PTEPAE;
1955#ifndef VBOX_FOR_DTRACE_LIB
1956AssertCompileSize(X86PTEPAE, 8);
1957#endif
1958/** Pointer to a PAE page table entry. */
1959typedef X86PTEPAE *PX86PTEPAE;
1960/** Pointer to a const PAE page table entry. */
1961typedef const X86PTEPAE *PCX86PTEPAE;
1962/** @} */
1963
1964/**
1965 * Page table.
1966 */
1967typedef struct X86PT
1968{
1969 /** PTE Array. */
1970 X86PTE a[X86_PG_ENTRIES];
1971} X86PT;
1972#ifndef VBOX_FOR_DTRACE_LIB
1973AssertCompileSize(X86PT, 4096);
1974#endif
1975/** Pointer to a page table. */
1976typedef X86PT *PX86PT;
1977/** Pointer to a const page table. */
1978typedef const X86PT *PCX86PT;
1979
1980/** The page shift to get the PT index. */
1981#define X86_PT_SHIFT 12
1982/** The PT index mask (apply to a shifted page address). */
1983#define X86_PT_MASK 0x3ff
1984
1985
1986/**
1987 * Page directory.
1988 */
1989typedef struct X86PTPAE
1990{
1991 /** PTE Array. */
1992 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1993} X86PTPAE;
1994#ifndef VBOX_FOR_DTRACE_LIB
1995AssertCompileSize(X86PTPAE, 4096);
1996#endif
1997/** Pointer to a page table. */
1998typedef X86PTPAE *PX86PTPAE;
1999/** Pointer to a const page table. */
2000typedef const X86PTPAE *PCX86PTPAE;
2001
2002/** The page shift to get the PA PTE index. */
2003#define X86_PT_PAE_SHIFT 12
2004/** The PAE PT index mask (apply to a shifted page address). */
2005#define X86_PT_PAE_MASK 0x1ff
2006
2007
2008/** @name 4KB Page Directory Entry
2009 * @{
2010 */
2011/** Bit 0 - P - Present bit. */
2012#define X86_PDE_P RT_BIT_32(0)
2013/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2014#define X86_PDE_RW RT_BIT_32(1)
2015/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2016#define X86_PDE_US RT_BIT_32(2)
2017/** Bit 3 - PWT - Page level write thru bit. */
2018#define X86_PDE_PWT RT_BIT_32(3)
2019/** Bit 4 - PCD - Page level cache disable bit. */
2020#define X86_PDE_PCD RT_BIT_32(4)
2021/** Bit 5 - A - Access bit. */
2022#define X86_PDE_A RT_BIT_32(5)
2023/** Bit 7 - PS - Page size attribute.
2024 * Clear mean 4KB pages, set means large pages (2/4MB). */
2025#define X86_PDE_PS RT_BIT_32(7)
2026/** Bits 9-11 - - Available for use to system software. */
2027#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2028/** Bits 12-31 - - Physical Page number of the next level. */
2029#define X86_PDE_PG_MASK ( 0xfffff000 )
2030
2031/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2032#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2033/** Bits 63 - NX - PAE/LM - No execution flag. */
2034#define X86_PDE_PAE_NX RT_BIT_64(63)
2035/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2036#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2037/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2038#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2039/** Bit 7 - - LM - MBZ bits when NX is active. */
2040#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2041/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2042#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2043
2044/**
2045 * Page directory entry.
2046 */
2047typedef struct X86PDEBITS
2048{
2049 /** Flags whether(=1) or not the page is present. */
2050 uint32_t u1Present : 1;
2051 /** Read(=0) / Write(=1) flag. */
2052 uint32_t u1Write : 1;
2053 /** User(=1) / Supervisor (=0) flag. */
2054 uint32_t u1User : 1;
2055 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2056 uint32_t u1WriteThru : 1;
2057 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2058 uint32_t u1CacheDisable : 1;
2059 /** Accessed flag.
2060 * Indicates that the page has been read or written to. */
2061 uint32_t u1Accessed : 1;
2062 /** Reserved / Ignored (dirty bit). */
2063 uint32_t u1Reserved0 : 1;
2064 /** Size bit if PSE is enabled - in any event it's 0. */
2065 uint32_t u1Size : 1;
2066 /** Reserved / Ignored (global bit). */
2067 uint32_t u1Reserved1 : 1;
2068 /** Available for use to system software. */
2069 uint32_t u3Available : 3;
2070 /** Physical Page number of the next level. */
2071 uint32_t u20PageNo : 20;
2072} X86PDEBITS;
2073#ifndef VBOX_FOR_DTRACE_LIB
2074AssertCompileSize(X86PDEBITS, 4);
2075#endif
2076/** Pointer to a page directory entry. */
2077typedef X86PDEBITS *PX86PDEBITS;
2078/** Pointer to a const page directory entry. */
2079typedef const X86PDEBITS *PCX86PDEBITS;
2080
2081
2082/**
2083 * PAE page directory entry.
2084 */
2085typedef struct X86PDEPAEBITS
2086{
2087 /** Flags whether(=1) or not the page is present. */
2088 uint32_t u1Present : 1;
2089 /** Read(=0) / Write(=1) flag. */
2090 uint32_t u1Write : 1;
2091 /** User(=1) / Supervisor (=0) flag. */
2092 uint32_t u1User : 1;
2093 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2094 uint32_t u1WriteThru : 1;
2095 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2096 uint32_t u1CacheDisable : 1;
2097 /** Accessed flag.
2098 * Indicates that the page has been read or written to. */
2099 uint32_t u1Accessed : 1;
2100 /** Reserved / Ignored (dirty bit). */
2101 uint32_t u1Reserved0 : 1;
2102 /** Size bit if PSE is enabled - in any event it's 0. */
2103 uint32_t u1Size : 1;
2104 /** Reserved / Ignored (global bit). / */
2105 uint32_t u1Reserved1 : 1;
2106 /** Available for use to system software. */
2107 uint32_t u3Available : 3;
2108 /** Physical Page number of the next level - Low Part. Don't use! */
2109 uint32_t u20PageNoLow : 20;
2110 /** Physical Page number of the next level - High Part. Don't use! */
2111 uint32_t u20PageNoHigh : 20;
2112 /** MBZ bits */
2113 uint32_t u11Reserved : 11;
2114 /** No Execute flag. */
2115 uint32_t u1NoExecute : 1;
2116} X86PDEPAEBITS;
2117#ifndef VBOX_FOR_DTRACE_LIB
2118AssertCompileSize(X86PDEPAEBITS, 8);
2119#endif
2120/** Pointer to a page directory entry. */
2121typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2122/** Pointer to a const page directory entry. */
2123typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2124
2125/** @} */
2126
2127
2128/** @name 2/4MB Page Directory Entry
2129 * @{
2130 */
2131/** Bit 0 - P - Present bit. */
2132#define X86_PDE4M_P RT_BIT_32(0)
2133/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2134#define X86_PDE4M_RW RT_BIT_32(1)
2135/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2136#define X86_PDE4M_US RT_BIT_32(2)
2137/** Bit 3 - PWT - Page level write thru bit. */
2138#define X86_PDE4M_PWT RT_BIT_32(3)
2139/** Bit 4 - PCD - Page level cache disable bit. */
2140#define X86_PDE4M_PCD RT_BIT_32(4)
2141/** Bit 5 - A - Access bit. */
2142#define X86_PDE4M_A RT_BIT_32(5)
2143/** Bit 6 - D - Dirty bit. */
2144#define X86_PDE4M_D RT_BIT_32(6)
2145/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2146#define X86_PDE4M_PS RT_BIT_32(7)
2147/** Bit 8 - G - Global flag. */
2148#define X86_PDE4M_G RT_BIT_32(8)
2149/** Bits 9-11 - AVL - Available for use to system software. */
2150#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2151/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2152#define X86_PDE4M_PAT RT_BIT_32(12)
2153/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2154#define X86_PDE4M_PAT_SHIFT (12 - 7)
2155/** Bits 22-31 - - Physical Page number. */
2156#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2157/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2158#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2159/** The number of bits to the high part of the page number. */
2160#define X86_PDE4M_PG_HIGH_SHIFT 19
2161/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2162#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2163
2164/** Bits 21-51 - - PAE/LM - Physical Page number.
2165 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2166#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2167/** Bits 63 - NX - PAE/LM - No execution flag. */
2168#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2169/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2170#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2171/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2172#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2173/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2174#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2175/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2176#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2177
2178/**
2179 * 4MB page directory entry.
2180 */
2181typedef struct X86PDE4MBITS
2182{
2183 /** Flags whether(=1) or not the page is present. */
2184 uint32_t u1Present : 1;
2185 /** Read(=0) / Write(=1) flag. */
2186 uint32_t u1Write : 1;
2187 /** User(=1) / Supervisor (=0) flag. */
2188 uint32_t u1User : 1;
2189 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2190 uint32_t u1WriteThru : 1;
2191 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2192 uint32_t u1CacheDisable : 1;
2193 /** Accessed flag.
2194 * Indicates that the page have been read or written to. */
2195 uint32_t u1Accessed : 1;
2196 /** Dirty flag.
2197 * Indicates that the page has been written to. */
2198 uint32_t u1Dirty : 1;
2199 /** Page size flag - always 1 for 4MB entries. */
2200 uint32_t u1Size : 1;
2201 /** Global flag. */
2202 uint32_t u1Global : 1;
2203 /** Available for use to system software. */
2204 uint32_t u3Available : 3;
2205 /** Reserved / If PAT enabled, bit 2 of the index. */
2206 uint32_t u1PAT : 1;
2207 /** Bits 32-39 of the page number on AMD64.
2208 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2209 uint32_t u8PageNoHigh : 8;
2210 /** Reserved. */
2211 uint32_t u1Reserved : 1;
2212 /** Physical Page number of the page. */
2213 uint32_t u10PageNo : 10;
2214} X86PDE4MBITS;
2215#ifndef VBOX_FOR_DTRACE_LIB
2216AssertCompileSize(X86PDE4MBITS, 4);
2217#endif
2218/** Pointer to a page table entry. */
2219typedef X86PDE4MBITS *PX86PDE4MBITS;
2220/** Pointer to a const page table entry. */
2221typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2222
2223
2224/**
2225 * 2MB PAE page directory entry.
2226 */
2227typedef struct X86PDE2MPAEBITS
2228{
2229 /** Flags whether(=1) or not the page is present. */
2230 uint32_t u1Present : 1;
2231 /** Read(=0) / Write(=1) flag. */
2232 uint32_t u1Write : 1;
2233 /** User(=1) / Supervisor(=0) flag. */
2234 uint32_t u1User : 1;
2235 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2236 uint32_t u1WriteThru : 1;
2237 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2238 uint32_t u1CacheDisable : 1;
2239 /** Accessed flag.
2240 * Indicates that the page have been read or written to. */
2241 uint32_t u1Accessed : 1;
2242 /** Dirty flag.
2243 * Indicates that the page has been written to. */
2244 uint32_t u1Dirty : 1;
2245 /** Page size flag - always 1 for 2MB entries. */
2246 uint32_t u1Size : 1;
2247 /** Global flag. */
2248 uint32_t u1Global : 1;
2249 /** Available for use to system software. */
2250 uint32_t u3Available : 3;
2251 /** Reserved / If PAT enabled, bit 2 of the index. */
2252 uint32_t u1PAT : 1;
2253 /** Reserved. */
2254 uint32_t u9Reserved : 9;
2255 /** Physical Page number of the next level - Low part. Don't use! */
2256 uint32_t u10PageNoLow : 10;
2257 /** Physical Page number of the next level - High part. Don't use! */
2258 uint32_t u20PageNoHigh : 20;
2259 /** MBZ bits */
2260 uint32_t u11Reserved : 11;
2261 /** No Execute flag. */
2262 uint32_t u1NoExecute : 1;
2263} X86PDE2MPAEBITS;
2264#ifndef VBOX_FOR_DTRACE_LIB
2265AssertCompileSize(X86PDE2MPAEBITS, 8);
2266#endif
2267/** Pointer to a 2MB PAE page table entry. */
2268typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2269/** Pointer to a 2MB PAE page table entry. */
2270typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2271
2272/** @} */
2273
2274/**
2275 * Page directory entry.
2276 */
2277typedef union X86PDE
2278{
2279 /** Unsigned integer view. */
2280 X86PGUINT u;
2281 /** Normal view. */
2282 X86PDEBITS n;
2283 /** 4MB view (big). */
2284 X86PDE4MBITS b;
2285 /** 8 bit unsigned integer view. */
2286 uint8_t au8[4];
2287 /** 16 bit unsigned integer view. */
2288 uint16_t au16[2];
2289 /** 32 bit unsigned integer view. */
2290 uint32_t au32[1];
2291} X86PDE;
2292#ifndef VBOX_FOR_DTRACE_LIB
2293AssertCompileSize(X86PDE, 4);
2294#endif
2295/** Pointer to a page directory entry. */
2296typedef X86PDE *PX86PDE;
2297/** Pointer to a const page directory entry. */
2298typedef const X86PDE *PCX86PDE;
2299
2300/**
2301 * PAE page directory entry.
2302 */
2303typedef union X86PDEPAE
2304{
2305 /** Unsigned integer view. */
2306 X86PGPAEUINT u;
2307 /** Normal view. */
2308 X86PDEPAEBITS n;
2309 /** 2MB page view (big). */
2310 X86PDE2MPAEBITS b;
2311 /** 8 bit unsigned integer view. */
2312 uint8_t au8[8];
2313 /** 16 bit unsigned integer view. */
2314 uint16_t au16[4];
2315 /** 32 bit unsigned integer view. */
2316 uint32_t au32[2];
2317} X86PDEPAE;
2318#ifndef VBOX_FOR_DTRACE_LIB
2319AssertCompileSize(X86PDEPAE, 8);
2320#endif
2321/** Pointer to a page directory entry. */
2322typedef X86PDEPAE *PX86PDEPAE;
2323/** Pointer to a const page directory entry. */
2324typedef const X86PDEPAE *PCX86PDEPAE;
2325
2326/**
2327 * Page directory.
2328 */
2329typedef struct X86PD
2330{
2331 /** PDE Array. */
2332 X86PDE a[X86_PG_ENTRIES];
2333} X86PD;
2334#ifndef VBOX_FOR_DTRACE_LIB
2335AssertCompileSize(X86PD, 4096);
2336#endif
2337/** Pointer to a page directory. */
2338typedef X86PD *PX86PD;
2339/** Pointer to a const page directory. */
2340typedef const X86PD *PCX86PD;
2341
2342/** The page shift to get the PD index. */
2343#define X86_PD_SHIFT 22
2344/** The PD index mask (apply to a shifted page address). */
2345#define X86_PD_MASK 0x3ff
2346
2347
2348/**
2349 * PAE page directory.
2350 */
2351typedef struct X86PDPAE
2352{
2353 /** PDE Array. */
2354 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2355} X86PDPAE;
2356#ifndef VBOX_FOR_DTRACE_LIB
2357AssertCompileSize(X86PDPAE, 4096);
2358#endif
2359/** Pointer to a PAE page directory. */
2360typedef X86PDPAE *PX86PDPAE;
2361/** Pointer to a const PAE page directory. */
2362typedef const X86PDPAE *PCX86PDPAE;
2363
2364/** The page shift to get the PAE PD index. */
2365#define X86_PD_PAE_SHIFT 21
2366/** The PAE PD index mask (apply to a shifted page address). */
2367#define X86_PD_PAE_MASK 0x1ff
2368
2369
2370/** @name Page Directory Pointer Table Entry (PAE)
2371 * @{
2372 */
2373/** Bit 0 - P - Present bit. */
2374#define X86_PDPE_P RT_BIT_32(0)
2375/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2376#define X86_PDPE_RW RT_BIT_32(1)
2377/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2378#define X86_PDPE_US RT_BIT_32(2)
2379/** Bit 3 - PWT - Page level write thru bit. */
2380#define X86_PDPE_PWT RT_BIT_32(3)
2381/** Bit 4 - PCD - Page level cache disable bit. */
2382#define X86_PDPE_PCD RT_BIT_32(4)
2383/** Bit 5 - A - Access bit. Long Mode only. */
2384#define X86_PDPE_A RT_BIT_32(5)
2385/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2386#define X86_PDPE_LM_PS RT_BIT_32(7)
2387/** Bits 9-11 - - Available for use to system software. */
2388#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2389/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2390#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2391/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2392#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2393/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2394#define X86_PDPE_LM_NX RT_BIT_64(63)
2395/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2396#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2397/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2398#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2399/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2400#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2401/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2402#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2403
2404
2405/**
2406 * Page directory pointer table entry.
2407 */
2408typedef struct X86PDPEBITS
2409{
2410 /** Flags whether(=1) or not the page is present. */
2411 uint32_t u1Present : 1;
2412 /** Chunk of reserved bits. */
2413 uint32_t u2Reserved : 2;
2414 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2415 uint32_t u1WriteThru : 1;
2416 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2417 uint32_t u1CacheDisable : 1;
2418 /** Chunk of reserved bits. */
2419 uint32_t u4Reserved : 4;
2420 /** Available for use to system software. */
2421 uint32_t u3Available : 3;
2422 /** Physical Page number of the next level - Low Part. Don't use! */
2423 uint32_t u20PageNoLow : 20;
2424 /** Physical Page number of the next level - High Part. Don't use! */
2425 uint32_t u20PageNoHigh : 20;
2426 /** MBZ bits */
2427 uint32_t u12Reserved : 12;
2428} X86PDPEBITS;
2429#ifndef VBOX_FOR_DTRACE_LIB
2430AssertCompileSize(X86PDPEBITS, 8);
2431#endif
2432/** Pointer to a page directory pointer table entry. */
2433typedef X86PDPEBITS *PX86PTPEBITS;
2434/** Pointer to a const page directory pointer table entry. */
2435typedef const X86PDPEBITS *PCX86PTPEBITS;
2436
2437/**
2438 * Page directory pointer table entry. AMD64 version
2439 */
2440typedef struct X86PDPEAMD64BITS
2441{
2442 /** Flags whether(=1) or not the page is present. */
2443 uint32_t u1Present : 1;
2444 /** Read(=0) / Write(=1) flag. */
2445 uint32_t u1Write : 1;
2446 /** User(=1) / Supervisor (=0) flag. */
2447 uint32_t u1User : 1;
2448 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2449 uint32_t u1WriteThru : 1;
2450 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2451 uint32_t u1CacheDisable : 1;
2452 /** Accessed flag.
2453 * Indicates that the page have been read or written to. */
2454 uint32_t u1Accessed : 1;
2455 /** Chunk of reserved bits. */
2456 uint32_t u3Reserved : 3;
2457 /** Available for use to system software. */
2458 uint32_t u3Available : 3;
2459 /** Physical Page number of the next level - Low Part. Don't use! */
2460 uint32_t u20PageNoLow : 20;
2461 /** Physical Page number of the next level - High Part. Don't use! */
2462 uint32_t u20PageNoHigh : 20;
2463 /** MBZ bits */
2464 uint32_t u11Reserved : 11;
2465 /** No Execute flag. */
2466 uint32_t u1NoExecute : 1;
2467} X86PDPEAMD64BITS;
2468#ifndef VBOX_FOR_DTRACE_LIB
2469AssertCompileSize(X86PDPEAMD64BITS, 8);
2470#endif
2471/** Pointer to a page directory pointer table entry. */
2472typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2473/** Pointer to a const page directory pointer table entry. */
2474typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2475
2476/**
2477 * Page directory pointer table entry for 1GB page. (AMD64 only)
2478 */
2479typedef struct X86PDPE1GB
2480{
2481 /** 0: Flags whether(=1) or not the page is present. */
2482 uint32_t u1Present : 1;
2483 /** 1: Read(=0) / Write(=1) flag. */
2484 uint32_t u1Write : 1;
2485 /** 2: User(=1) / Supervisor (=0) flag. */
2486 uint32_t u1User : 1;
2487 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2488 uint32_t u1WriteThru : 1;
2489 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2490 uint32_t u1CacheDisable : 1;
2491 /** 5: Accessed flag.
2492 * Indicates that the page have been read or written to. */
2493 uint32_t u1Accessed : 1;
2494 /** 6: Dirty flag for 1GB pages. */
2495 uint32_t u1Dirty : 1;
2496 /** 7: Indicates 1GB page if set. */
2497 uint32_t u1Size : 1;
2498 /** 8: Global 1GB page. */
2499 uint32_t u1Global: 1;
2500 /** 9-11: Available for use to system software. */
2501 uint32_t u3Available : 3;
2502 /** 12: PAT bit for 1GB page. */
2503 uint32_t u1PAT : 1;
2504 /** 13-29: MBZ bits. */
2505 uint32_t u17Reserved : 17;
2506 /** 30-31: Physical page number - Low Part. Don't use! */
2507 uint32_t u2PageNoLow : 2;
2508 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2509 uint32_t u20PageNoHigh : 20;
2510 /** 52-62: MBZ bits */
2511 uint32_t u11Reserved : 11;
2512 /** 63: No Execute flag. */
2513 uint32_t u1NoExecute : 1;
2514} X86PDPE1GB;
2515#ifndef VBOX_FOR_DTRACE_LIB
2516AssertCompileSize(X86PDPE1GB, 8);
2517#endif
2518/** Pointer to a page directory pointer table entry for a 1GB page. */
2519typedef X86PDPE1GB *PX86PDPE1GB;
2520/** Pointer to a const page directory pointer table entry for a 1GB page. */
2521typedef const X86PDPE1GB *PCX86PDPE1GB;
2522
2523/**
2524 * Page directory pointer table entry.
2525 */
2526typedef union X86PDPE
2527{
2528 /** Unsigned integer view. */
2529 X86PGPAEUINT u;
2530 /** Normal view. */
2531 X86PDPEBITS n;
2532 /** AMD64 view. */
2533 X86PDPEAMD64BITS lm;
2534 /** AMD64 big view. */
2535 X86PDPE1GB b;
2536 /** 8 bit unsigned integer view. */
2537 uint8_t au8[8];
2538 /** 16 bit unsigned integer view. */
2539 uint16_t au16[4];
2540 /** 32 bit unsigned integer view. */
2541 uint32_t au32[2];
2542} X86PDPE;
2543#ifndef VBOX_FOR_DTRACE_LIB
2544AssertCompileSize(X86PDPE, 8);
2545#endif
2546/** Pointer to a page directory pointer table entry. */
2547typedef X86PDPE *PX86PDPE;
2548/** Pointer to a const page directory pointer table entry. */
2549typedef const X86PDPE *PCX86PDPE;
2550
2551
2552/**
2553 * Page directory pointer table.
2554 */
2555typedef struct X86PDPT
2556{
2557 /** PDE Array. */
2558 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2559} X86PDPT;
2560#ifndef VBOX_FOR_DTRACE_LIB
2561AssertCompileSize(X86PDPT, 4096);
2562#endif
2563/** Pointer to a page directory pointer table. */
2564typedef X86PDPT *PX86PDPT;
2565/** Pointer to a const page directory pointer table. */
2566typedef const X86PDPT *PCX86PDPT;
2567
2568/** The page shift to get the PDPT index. */
2569#define X86_PDPT_SHIFT 30
2570/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2571#define X86_PDPT_MASK_PAE 0x3
2572/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2573#define X86_PDPT_MASK_AMD64 0x1ff
2574
2575/** @} */
2576
2577
2578/** @name Page Map Level-4 Entry (Long Mode PAE)
2579 * @{
2580 */
2581/** Bit 0 - P - Present bit. */
2582#define X86_PML4E_P RT_BIT_32(0)
2583/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2584#define X86_PML4E_RW RT_BIT_32(1)
2585/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2586#define X86_PML4E_US RT_BIT_32(2)
2587/** Bit 3 - PWT - Page level write thru bit. */
2588#define X86_PML4E_PWT RT_BIT_32(3)
2589/** Bit 4 - PCD - Page level cache disable bit. */
2590#define X86_PML4E_PCD RT_BIT_32(4)
2591/** Bit 5 - A - Access bit. */
2592#define X86_PML4E_A RT_BIT_32(5)
2593/** Bits 9-11 - - Available for use to system software. */
2594#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2595/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2596#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2597/** Bits 8, 7 - - MBZ bits when NX is active. */
2598#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2599/** Bits 63, 7 - - MBZ bits when no NX. */
2600#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2601/** Bits 63 - NX - PAE - No execution flag. */
2602#define X86_PML4E_NX RT_BIT_64(63)
2603
2604/**
2605 * Page Map Level-4 Entry
2606 */
2607typedef struct X86PML4EBITS
2608{
2609 /** Flags whether(=1) or not the page is present. */
2610 uint32_t u1Present : 1;
2611 /** Read(=0) / Write(=1) flag. */
2612 uint32_t u1Write : 1;
2613 /** User(=1) / Supervisor (=0) flag. */
2614 uint32_t u1User : 1;
2615 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2616 uint32_t u1WriteThru : 1;
2617 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2618 uint32_t u1CacheDisable : 1;
2619 /** Accessed flag.
2620 * Indicates that the page have been read or written to. */
2621 uint32_t u1Accessed : 1;
2622 /** Chunk of reserved bits. */
2623 uint32_t u3Reserved : 3;
2624 /** Available for use to system software. */
2625 uint32_t u3Available : 3;
2626 /** Physical Page number of the next level - Low Part. Don't use! */
2627 uint32_t u20PageNoLow : 20;
2628 /** Physical Page number of the next level - High Part. Don't use! */
2629 uint32_t u20PageNoHigh : 20;
2630 /** MBZ bits */
2631 uint32_t u11Reserved : 11;
2632 /** No Execute flag. */
2633 uint32_t u1NoExecute : 1;
2634} X86PML4EBITS;
2635#ifndef VBOX_FOR_DTRACE_LIB
2636AssertCompileSize(X86PML4EBITS, 8);
2637#endif
2638/** Pointer to a page map level-4 entry. */
2639typedef X86PML4EBITS *PX86PML4EBITS;
2640/** Pointer to a const page map level-4 entry. */
2641typedef const X86PML4EBITS *PCX86PML4EBITS;
2642
2643/**
2644 * Page Map Level-4 Entry.
2645 */
2646typedef union X86PML4E
2647{
2648 /** Unsigned integer view. */
2649 X86PGPAEUINT u;
2650 /** Normal view. */
2651 X86PML4EBITS n;
2652 /** 8 bit unsigned integer view. */
2653 uint8_t au8[8];
2654 /** 16 bit unsigned integer view. */
2655 uint16_t au16[4];
2656 /** 32 bit unsigned integer view. */
2657 uint32_t au32[2];
2658} X86PML4E;
2659#ifndef VBOX_FOR_DTRACE_LIB
2660AssertCompileSize(X86PML4E, 8);
2661#endif
2662/** Pointer to a page map level-4 entry. */
2663typedef X86PML4E *PX86PML4E;
2664/** Pointer to a const page map level-4 entry. */
2665typedef const X86PML4E *PCX86PML4E;
2666
2667
2668/**
2669 * Page Map Level-4.
2670 */
2671typedef struct X86PML4
2672{
2673 /** PDE Array. */
2674 X86PML4E a[X86_PG_PAE_ENTRIES];
2675} X86PML4;
2676#ifndef VBOX_FOR_DTRACE_LIB
2677AssertCompileSize(X86PML4, 4096);
2678#endif
2679/** Pointer to a page map level-4. */
2680typedef X86PML4 *PX86PML4;
2681/** Pointer to a const page map level-4. */
2682typedef const X86PML4 *PCX86PML4;
2683
2684/** The page shift to get the PML4 index. */
2685#define X86_PML4_SHIFT 39
2686/** The PML4 index mask (apply to a shifted page address). */
2687#define X86_PML4_MASK 0x1ff
2688
2689/** @} */
2690
2691/** @} */
2692
2693/**
2694 * Intel PCID invalidation types.
2695 */
2696/** Individual address invalidation. */
2697#define X86_INVPCID_TYPE_INDV_ADDR 0
2698/** Single-context invalidation. */
2699#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2700/** All-context including globals invalidation. */
2701#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2702/** All-context excluding globals invalidation. */
2703#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2704/** The maximum valid invalidation type value. */
2705#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2706
2707/**
2708 * 32-bit protected mode FSTENV image.
2709 */
2710typedef struct X86FSTENV32P
2711{
2712 uint16_t FCW;
2713 uint16_t padding1;
2714 uint16_t FSW;
2715 uint16_t padding2;
2716 uint16_t FTW;
2717 uint16_t padding3;
2718 uint32_t FPUIP;
2719 uint16_t FPUCS;
2720 uint16_t FOP;
2721 uint32_t FPUDP;
2722 uint16_t FPUDS;
2723 uint16_t padding4;
2724} X86FSTENV32P;
2725/** Pointer to a 32-bit protected mode FSTENV image. */
2726typedef X86FSTENV32P *PX86FSTENV32P;
2727/** Pointer to a const 32-bit protected mode FSTENV image. */
2728typedef X86FSTENV32P const *PCX86FSTENV32P;
2729
2730
2731/**
2732 * 80-bit MMX/FPU register type.
2733 */
2734typedef struct X86FPUMMX
2735{
2736 uint8_t reg[10];
2737} X86FPUMMX;
2738#ifndef VBOX_FOR_DTRACE_LIB
2739AssertCompileSize(X86FPUMMX, 10);
2740#endif
2741/** Pointer to a 80-bit MMX/FPU register type. */
2742typedef X86FPUMMX *PX86FPUMMX;
2743/** Pointer to a const 80-bit MMX/FPU register type. */
2744typedef const X86FPUMMX *PCX86FPUMMX;
2745
2746/** FPU (x87) register. */
2747typedef union X86FPUREG
2748{
2749 /** MMX view. */
2750 uint64_t mmx;
2751 /** FPU view - todo. */
2752 X86FPUMMX fpu;
2753 /** Extended precision floating point view. */
2754 RTFLOAT80U r80;
2755 /** Extended precision floating point view v2 */
2756 RTFLOAT80U2 r80Ex;
2757 /** 8-bit view. */
2758 uint8_t au8[16];
2759 /** 16-bit view. */
2760 uint16_t au16[8];
2761 /** 32-bit view. */
2762 uint32_t au32[4];
2763 /** 64-bit view. */
2764 uint64_t au64[2];
2765 /** 128-bit view. (yeah, very helpful) */
2766 uint128_t au128[1];
2767} X86FPUREG;
2768#ifndef VBOX_FOR_DTRACE_LIB
2769AssertCompileSize(X86FPUREG, 16);
2770#endif
2771/** Pointer to a FPU register. */
2772typedef X86FPUREG *PX86FPUREG;
2773/** Pointer to a const FPU register. */
2774typedef X86FPUREG const *PCX86FPUREG;
2775
2776/**
2777 * XMM register union.
2778 */
2779typedef union X86XMMREG
2780{
2781 /** XMM Register view. */
2782 uint128_t xmm;
2783 /** 8-bit view. */
2784 uint8_t au8[16];
2785 /** 16-bit view. */
2786 uint16_t au16[8];
2787 /** 32-bit view. */
2788 uint32_t au32[4];
2789 /** 64-bit view. */
2790 uint64_t au64[2];
2791 /** 128-bit view. (yeah, very helpful) */
2792 uint128_t au128[1];
2793#ifndef VBOX_FOR_DTRACE_LIB
2794 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2795 RTUINT128U uXmm;
2796#endif
2797} X86XMMREG;
2798#ifndef VBOX_FOR_DTRACE_LIB
2799AssertCompileSize(X86XMMREG, 16);
2800#endif
2801/** Pointer to an XMM register state. */
2802typedef X86XMMREG *PX86XMMREG;
2803/** Pointer to a const XMM register state. */
2804typedef X86XMMREG const *PCX86XMMREG;
2805
2806/**
2807 * YMM register union.
2808 */
2809typedef union X86YMMREG
2810{
2811 /** 8-bit view. */
2812 uint8_t au8[32];
2813 /** 16-bit view. */
2814 uint16_t au16[16];
2815 /** 32-bit view. */
2816 uint32_t au32[8];
2817 /** 64-bit view. */
2818 uint64_t au64[4];
2819 /** 128-bit view. (yeah, very helpful) */
2820 uint128_t au128[2];
2821 /** XMM sub register view. */
2822 X86XMMREG aXmm[2];
2823} X86YMMREG;
2824#ifndef VBOX_FOR_DTRACE_LIB
2825AssertCompileSize(X86YMMREG, 32);
2826#endif
2827/** Pointer to an YMM register state. */
2828typedef X86YMMREG *PX86YMMREG;
2829/** Pointer to a const YMM register state. */
2830typedef X86YMMREG const *PCX86YMMREG;
2831
2832/**
2833 * ZMM register union.
2834 */
2835typedef union X86ZMMREG
2836{
2837 /** 8-bit view. */
2838 uint8_t au8[64];
2839 /** 16-bit view. */
2840 uint16_t au16[32];
2841 /** 32-bit view. */
2842 uint32_t au32[16];
2843 /** 64-bit view. */
2844 uint64_t au64[8];
2845 /** 128-bit view. (yeah, very helpful) */
2846 uint128_t au128[4];
2847 /** XMM sub register view. */
2848 X86XMMREG aXmm[4];
2849 /** YMM sub register view. */
2850 X86YMMREG aYmm[2];
2851} X86ZMMREG;
2852#ifndef VBOX_FOR_DTRACE_LIB
2853AssertCompileSize(X86ZMMREG, 64);
2854#endif
2855/** Pointer to an ZMM register state. */
2856typedef X86ZMMREG *PX86ZMMREG;
2857/** Pointer to a const ZMM register state. */
2858typedef X86ZMMREG const *PCX86ZMMREG;
2859
2860
2861/**
2862 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2863 * @todo verify this...
2864 */
2865#pragma pack(1)
2866typedef struct X86FPUSTATE
2867{
2868 /** 0x00 - Control word. */
2869 uint16_t FCW;
2870 /** 0x02 - Alignment word */
2871 uint16_t Dummy1;
2872 /** 0x04 - Status word. */
2873 uint16_t FSW;
2874 /** 0x06 - Alignment word */
2875 uint16_t Dummy2;
2876 /** 0x08 - Tag word */
2877 uint16_t FTW;
2878 /** 0x0a - Alignment word */
2879 uint16_t Dummy3;
2880
2881 /** 0x0c - Instruction pointer. */
2882 uint32_t FPUIP;
2883 /** 0x10 - Code selector. */
2884 uint16_t CS;
2885 /** 0x12 - Opcode. */
2886 uint16_t FOP;
2887 /** 0x14 - FOO. */
2888 uint32_t FPUOO;
2889 /** 0x18 - FOS. */
2890 uint32_t FPUOS;
2891 /** 0x1c - FPU register. */
2892 X86FPUREG regs[8];
2893} X86FPUSTATE;
2894#pragma pack()
2895/** Pointer to a FPU state. */
2896typedef X86FPUSTATE *PX86FPUSTATE;
2897/** Pointer to a const FPU state. */
2898typedef const X86FPUSTATE *PCX86FPUSTATE;
2899
2900/**
2901 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2902 */
2903#pragma pack(1)
2904typedef struct X86FXSTATE
2905{
2906 /** 0x00 - Control word. */
2907 uint16_t FCW;
2908 /** 0x02 - Status word. */
2909 uint16_t FSW;
2910 /** 0x04 - Tag word. (The upper byte is always zero.) */
2911 uint16_t FTW;
2912 /** 0x06 - Opcode. */
2913 uint16_t FOP;
2914 /** 0x08 - Instruction pointer. */
2915 uint32_t FPUIP;
2916 /** 0x0c - Code selector. */
2917 uint16_t CS;
2918 uint16_t Rsrvd1;
2919 /** 0x10 - Data pointer. */
2920 uint32_t FPUDP;
2921 /** 0x14 - Data segment */
2922 uint16_t DS;
2923 /** 0x16 */
2924 uint16_t Rsrvd2;
2925 /** 0x18 */
2926 uint32_t MXCSR;
2927 /** 0x1c */
2928 uint32_t MXCSR_MASK;
2929 /** 0x20 - FPU registers. */
2930 X86FPUREG aRegs[8];
2931 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2932 X86XMMREG aXMM[16];
2933 /* - offset 416 - */
2934 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2935 /* - offset 464 - Software usable reserved bits. */
2936 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2937} X86FXSTATE;
2938#pragma pack()
2939/** Pointer to a FPU Extended state. */
2940typedef X86FXSTATE *PX86FXSTATE;
2941/** Pointer to a const FPU Extended state. */
2942typedef const X86FXSTATE *PCX86FXSTATE;
2943
2944/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2945 * magic. Don't forget to update x86.mac if you change this! */
2946#define X86_OFF_FXSTATE_RSVD 0x1d0
2947/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2948 * forget to update x86.mac if you change this!
2949 * @todo r=bird: This has nothing what-so-ever to do here.... */
2950#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2951#ifndef VBOX_FOR_DTRACE_LIB
2952AssertCompileSize(X86FXSTATE, 512);
2953AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2954#endif
2955
2956/** @name FPU status word flags.
2957 * @{ */
2958/** Exception Flag: Invalid operation. */
2959#define X86_FSW_IE RT_BIT_32(0)
2960/** Exception Flag: Denormalized operand. */
2961#define X86_FSW_DE RT_BIT_32(1)
2962/** Exception Flag: Zero divide. */
2963#define X86_FSW_ZE RT_BIT_32(2)
2964/** Exception Flag: Overflow. */
2965#define X86_FSW_OE RT_BIT_32(3)
2966/** Exception Flag: Underflow. */
2967#define X86_FSW_UE RT_BIT_32(4)
2968/** Exception Flag: Precision. */
2969#define X86_FSW_PE RT_BIT_32(5)
2970/** Stack fault. */
2971#define X86_FSW_SF RT_BIT_32(6)
2972/** Error summary status. */
2973#define X86_FSW_ES RT_BIT_32(7)
2974/** Mask of exceptions flags, excluding the summary bit. */
2975#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2976/** Mask of exceptions flags, including the summary bit. */
2977#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2978/** Condition code 0. */
2979#define X86_FSW_C0 RT_BIT_32(8)
2980/** Condition code 1. */
2981#define X86_FSW_C1 RT_BIT_32(9)
2982/** Condition code 2. */
2983#define X86_FSW_C2 RT_BIT_32(10)
2984/** Top of the stack mask. */
2985#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2986/** TOP shift value. */
2987#define X86_FSW_TOP_SHIFT 11
2988/** Mask for getting TOP value after shifting it right. */
2989#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2990/** Get the TOP value. */
2991#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2992/** Condition code 3. */
2993#define X86_FSW_C3 RT_BIT_32(14)
2994/** Mask of exceptions flags, including the summary bit. */
2995#define X86_FSW_C_MASK UINT16_C(0x4700)
2996/** FPU busy. */
2997#define X86_FSW_B RT_BIT_32(15)
2998/** @} */
2999
3000
3001/** @name FPU control word flags.
3002 * @{ */
3003/** Exception Mask: Invalid operation. */
3004#define X86_FCW_IM RT_BIT_32(0)
3005/** Exception Mask: Denormalized operand. */
3006#define X86_FCW_DM RT_BIT_32(1)
3007/** Exception Mask: Zero divide. */
3008#define X86_FCW_ZM RT_BIT_32(2)
3009/** Exception Mask: Overflow. */
3010#define X86_FCW_OM RT_BIT_32(3)
3011/** Exception Mask: Underflow. */
3012#define X86_FCW_UM RT_BIT_32(4)
3013/** Exception Mask: Precision. */
3014#define X86_FCW_PM RT_BIT_32(5)
3015/** Mask all exceptions, the value typically loaded (by for instance fninit).
3016 * @remarks This includes reserved bit 6. */
3017#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3018/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3019#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3020/** Precision control mask. */
3021#define X86_FCW_PC_MASK UINT16_C(0x0300)
3022/** Precision control: 24-bit. */
3023#define X86_FCW_PC_24 UINT16_C(0x0000)
3024/** Precision control: Reserved. */
3025#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3026/** Precision control: 53-bit. */
3027#define X86_FCW_PC_53 UINT16_C(0x0200)
3028/** Precision control: 64-bit. */
3029#define X86_FCW_PC_64 UINT16_C(0x0300)
3030/** Rounding control mask. */
3031#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3032/** Rounding control: To nearest. */
3033#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3034/** Rounding control: Down. */
3035#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3036/** Rounding control: Up. */
3037#define X86_FCW_RC_UP UINT16_C(0x0800)
3038/** Rounding control: Towards zero. */
3039#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3040/** Bits which should be zero, apparently. */
3041#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3042/** @} */
3043
3044/** @name SSE MXCSR
3045 * @{ */
3046/** Exception Flag: Invalid operation. */
3047#define X86_MXCSR_IE RT_BIT_32(0)
3048/** Exception Flag: Denormalized operand. */
3049#define X86_MXCSR_DE RT_BIT_32(1)
3050/** Exception Flag: Zero divide. */
3051#define X86_MXCSR_ZE RT_BIT_32(2)
3052/** Exception Flag: Overflow. */
3053#define X86_MXCSR_OE RT_BIT_32(3)
3054/** Exception Flag: Underflow. */
3055#define X86_MXCSR_UE RT_BIT_32(4)
3056/** Exception Flag: Precision. */
3057#define X86_MXCSR_PE RT_BIT_32(5)
3058
3059/** Denormals are zero. */
3060#define X86_MXCSR_DAZ RT_BIT_32(6)
3061
3062/** Exception Mask: Invalid operation. */
3063#define X86_MXCSR_IM RT_BIT_32(7)
3064/** Exception Mask: Denormalized operand. */
3065#define X86_MXCSR_DM RT_BIT_32(8)
3066/** Exception Mask: Zero divide. */
3067#define X86_MXCSR_ZM RT_BIT_32(9)
3068/** Exception Mask: Overflow. */
3069#define X86_MXCSR_OM RT_BIT_32(10)
3070/** Exception Mask: Underflow. */
3071#define X86_MXCSR_UM RT_BIT_32(11)
3072/** Exception Mask: Precision. */
3073#define X86_MXCSR_PM RT_BIT_32(12)
3074
3075/** Rounding control mask. */
3076#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3077/** Rounding control: To nearest. */
3078#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3079/** Rounding control: Down. */
3080#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3081/** Rounding control: Up. */
3082#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3083/** Rounding control: Towards zero. */
3084#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3085
3086/** Flush-to-zero for masked underflow. */
3087#define X86_MXCSR_FZ RT_BIT_32(15)
3088
3089/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3090#define X86_MXCSR_MM RT_BIT_32(17)
3091/** @} */
3092
3093/**
3094 * XSAVE header.
3095 */
3096typedef struct X86XSAVEHDR
3097{
3098 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3099 uint64_t bmXState;
3100 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3101 uint64_t bmXComp;
3102 /** Reserved for furture extensions, probably MBZ. */
3103 uint64_t au64Reserved[6];
3104} X86XSAVEHDR;
3105#ifndef VBOX_FOR_DTRACE_LIB
3106AssertCompileSize(X86XSAVEHDR, 64);
3107#endif
3108/** Pointer to an XSAVE header. */
3109typedef X86XSAVEHDR *PX86XSAVEHDR;
3110/** Pointer to a const XSAVE header. */
3111typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3112
3113
3114/**
3115 * The high 128-bit YMM register state (XSAVE_C_YMM).
3116 * (The lower 128-bits being in X86FXSTATE.)
3117 */
3118typedef struct X86XSAVEYMMHI
3119{
3120 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3121 X86XMMREG aYmmHi[16];
3122} X86XSAVEYMMHI;
3123#ifndef VBOX_FOR_DTRACE_LIB
3124AssertCompileSize(X86XSAVEYMMHI, 256);
3125#endif
3126/** Pointer to a high 128-bit YMM register state. */
3127typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3128/** Pointer to a const high 128-bit YMM register state. */
3129typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3130
3131/**
3132 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3133 */
3134typedef struct X86XSAVEBNDREGS
3135{
3136 /** Array of registers (BND0...BND3). */
3137 struct
3138 {
3139 /** Lower bound. */
3140 uint64_t uLowerBound;
3141 /** Upper bound. */
3142 uint64_t uUpperBound;
3143 } aRegs[4];
3144} X86XSAVEBNDREGS;
3145#ifndef VBOX_FOR_DTRACE_LIB
3146AssertCompileSize(X86XSAVEBNDREGS, 64);
3147#endif
3148/** Pointer to a MPX bound register state. */
3149typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3150/** Pointer to a const MPX bound register state. */
3151typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3152
3153/**
3154 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3155 */
3156typedef struct X86XSAVEBNDCFG
3157{
3158 uint64_t fConfig;
3159 uint64_t fStatus;
3160} X86XSAVEBNDCFG;
3161#ifndef VBOX_FOR_DTRACE_LIB
3162AssertCompileSize(X86XSAVEBNDCFG, 16);
3163#endif
3164/** Pointer to a MPX bound config and status register state. */
3165typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3166/** Pointer to a const MPX bound config and status register state. */
3167typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3168
3169/**
3170 * AVX-512 opmask state (XSAVE_C_OPMASK).
3171 */
3172typedef struct X86XSAVEOPMASK
3173{
3174 /** The K0..K7 values. */
3175 uint64_t aKRegs[8];
3176} X86XSAVEOPMASK;
3177#ifndef VBOX_FOR_DTRACE_LIB
3178AssertCompileSize(X86XSAVEOPMASK, 64);
3179#endif
3180/** Pointer to a AVX-512 opmask state. */
3181typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3182/** Pointer to a const AVX-512 opmask state. */
3183typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3184
3185/**
3186 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3187 */
3188typedef struct X86XSAVEZMMHI256
3189{
3190 /** Upper 256-bits of ZMM0-15. */
3191 X86YMMREG aHi256Regs[16];
3192} X86XSAVEZMMHI256;
3193#ifndef VBOX_FOR_DTRACE_LIB
3194AssertCompileSize(X86XSAVEZMMHI256, 512);
3195#endif
3196/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3197typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3198/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3199typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3200
3201/**
3202 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3203 */
3204typedef struct X86XSAVEZMM16HI
3205{
3206 /** ZMM16 thru ZMM31. */
3207 X86ZMMREG aRegs[16];
3208} X86XSAVEZMM16HI;
3209#ifndef VBOX_FOR_DTRACE_LIB
3210AssertCompileSize(X86XSAVEZMM16HI, 1024);
3211#endif
3212/** Pointer to a state comprising ZMM16-32. */
3213typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3214/** Pointer to a const state comprising ZMM16-32. */
3215typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3216
3217/**
3218 * AMD Light weight profiling state (XSAVE_C_LWP).
3219 *
3220 * We probably won't play with this as AMD seems to be dropping from their "zen"
3221 * processor micro architecture.
3222 */
3223typedef struct X86XSAVELWP
3224{
3225 /** Details when needed. */
3226 uint64_t auLater[128/8];
3227} X86XSAVELWP;
3228#ifndef VBOX_FOR_DTRACE_LIB
3229AssertCompileSize(X86XSAVELWP, 128);
3230#endif
3231
3232
3233/**
3234 * x86 FPU/SSE/AVX/XXXX state.
3235 *
3236 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3237 * changes to this structure.
3238 */
3239typedef struct X86XSAVEAREA
3240{
3241 /** The x87 and SSE region (or legacy region if you like). */
3242 X86FXSTATE x87;
3243 /** The XSAVE header. */
3244 X86XSAVEHDR Hdr;
3245 /** Beyond the header, there isn't really a fixed layout, but we can
3246 generally assume the YMM (AVX) register extensions are present and
3247 follows immediately. */
3248 union
3249 {
3250 /** The high 128-bit AVX registers for easy access by IEM.
3251 * @note This ASSUMES they will always be here... */
3252 X86XSAVEYMMHI YmmHi;
3253
3254 /** This is a typical layout on intel CPUs (good for debuggers). */
3255 struct
3256 {
3257 X86XSAVEYMMHI YmmHi;
3258 X86XSAVEBNDREGS BndRegs;
3259 X86XSAVEBNDCFG BndCfg;
3260 uint8_t abFudgeToMatchDocs[0xB0];
3261 X86XSAVEOPMASK Opmask;
3262 X86XSAVEZMMHI256 ZmmHi256;
3263 X86XSAVEZMM16HI Zmm16Hi;
3264 } Intel;
3265
3266 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3267 struct
3268 {
3269 X86XSAVEYMMHI YmmHi;
3270 X86XSAVELWP Lwp;
3271 } AmdBd;
3272
3273 /** To enbling static deployments that have a reasonable chance of working for
3274 * the next 3-6 CPU generations without running short on space, we allocate a
3275 * lot of extra space here, making the structure a round 8KB in size. This
3276 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3277 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3278 uint8_t ab[8192 - 512 - 64];
3279 } u;
3280} X86XSAVEAREA;
3281#ifndef VBOX_FOR_DTRACE_LIB
3282AssertCompileSize(X86XSAVEAREA, 8192);
3283AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3284AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3285AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3286AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3287AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3288AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3289AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3290AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3291#endif
3292/** Pointer to a XSAVE area. */
3293typedef X86XSAVEAREA *PX86XSAVEAREA;
3294/** Pointer to a const XSAVE area. */
3295typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3296
3297
3298/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3299 * @{ */
3300/** Bit 0 - x87 - Legacy FPU state (bit number) */
3301#define XSAVE_C_X87_BIT 0
3302/** Bit 0 - x87 - Legacy FPU state. */
3303#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3304/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3305#define XSAVE_C_SSE_BIT 1
3306/** Bit 1 - SSE - 128-bit SSE state. */
3307#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3308/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3309#define XSAVE_C_YMM_BIT 2
3310/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3311#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3312/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3313#define XSAVE_C_BNDREGS_BIT 3
3314/** Bit 3 - BNDREGS - MPX bound register state. */
3315#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3316/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3317#define XSAVE_C_BNDCSR_BIT 4
3318/** Bit 4 - BNDCSR - MPX bound config and status state. */
3319#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3320/** Bit 5 - Opmask - opmask state (bit number). */
3321#define XSAVE_C_OPMASK_BIT 5
3322/** Bit 5 - Opmask - opmask state. */
3323#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3324/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3325#define XSAVE_C_ZMM_HI256_BIT 6
3326/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3327#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3328/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3329#define XSAVE_C_ZMM_16HI_BIT 7
3330/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3331#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3332/** Bit 9 - PKRU - Protection-key state (bit number). */
3333#define XSAVE_C_PKRU_BIT 9
3334/** Bit 9 - PKRU - Protection-key state. */
3335#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3336/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3337#define XSAVE_C_LWP_BIT 62
3338/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3339#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3340/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3341#define XSAVE_C_X_BIT 63
3342/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3343#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3344/** @} */
3345
3346
3347
3348/** @name Selector Descriptor
3349 * @{
3350 */
3351
3352#ifndef VBOX_FOR_DTRACE_LIB
3353/**
3354 * Descriptor attributes (as seen by VT-x).
3355 */
3356typedef struct X86DESCATTRBITS
3357{
3358 /** 00 - Segment Type. */
3359 unsigned u4Type : 4;
3360 /** 04 - Descriptor Type. System(=0) or code/data selector */
3361 unsigned u1DescType : 1;
3362 /** 05 - Descriptor Privilege level. */
3363 unsigned u2Dpl : 2;
3364 /** 07 - Flags selector present(=1) or not. */
3365 unsigned u1Present : 1;
3366 /** 08 - Segment limit 16-19. */
3367 unsigned u4LimitHigh : 4;
3368 /** 0c - Available for system software. */
3369 unsigned u1Available : 1;
3370 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3371 unsigned u1Long : 1;
3372 /** 0e - This flags meaning depends on the segment type. Try make sense out
3373 * of the intel manual yourself. */
3374 unsigned u1DefBig : 1;
3375 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3376 * clear byte. */
3377 unsigned u1Granularity : 1;
3378 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3379 unsigned u1Unusable : 1;
3380} X86DESCATTRBITS;
3381#endif /* !VBOX_FOR_DTRACE_LIB */
3382
3383/** @name X86DESCATTR masks
3384 * @{ */
3385#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3386#define X86DESCATTR_DT UINT32_C(0x00000010)
3387#define X86DESCATTR_DPL UINT32_C(0x00000060)
3388#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3389#define X86DESCATTR_P UINT32_C(0x00000080)
3390#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3391#define X86DESCATTR_AVL UINT32_C(0x00001000)
3392#define X86DESCATTR_L UINT32_C(0x00002000)
3393#define X86DESCATTR_D UINT32_C(0x00004000)
3394#define X86DESCATTR_G UINT32_C(0x00008000)
3395#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3396/** @} */
3397
3398#pragma pack(1)
3399typedef union X86DESCATTR
3400{
3401 /** Unsigned integer view. */
3402 uint32_t u;
3403#ifndef VBOX_FOR_DTRACE_LIB
3404 /** Normal view. */
3405 X86DESCATTRBITS n;
3406#endif
3407} X86DESCATTR;
3408#pragma pack()
3409/** Pointer to descriptor attributes. */
3410typedef X86DESCATTR *PX86DESCATTR;
3411/** Pointer to const descriptor attributes. */
3412typedef const X86DESCATTR *PCX86DESCATTR;
3413
3414#ifndef VBOX_FOR_DTRACE_LIB
3415
3416/**
3417 * Generic descriptor table entry
3418 */
3419#pragma pack(1)
3420typedef struct X86DESCGENERIC
3421{
3422 /** 00 - Limit - Low word. */
3423 unsigned u16LimitLow : 16;
3424 /** 10 - Base address - low word.
3425 * Don't try set this to 24 because MSC is doing stupid things then. */
3426 unsigned u16BaseLow : 16;
3427 /** 20 - Base address - first 8 bits of high word. */
3428 unsigned u8BaseHigh1 : 8;
3429 /** 28 - Segment Type. */
3430 unsigned u4Type : 4;
3431 /** 2c - Descriptor Type. System(=0) or code/data selector */
3432 unsigned u1DescType : 1;
3433 /** 2d - Descriptor Privilege level. */
3434 unsigned u2Dpl : 2;
3435 /** 2f - Flags selector present(=1) or not. */
3436 unsigned u1Present : 1;
3437 /** 30 - Segment limit 16-19. */
3438 unsigned u4LimitHigh : 4;
3439 /** 34 - Available for system software. */
3440 unsigned u1Available : 1;
3441 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3442 unsigned u1Long : 1;
3443 /** 36 - This flags meaning depends on the segment type. Try make sense out
3444 * of the intel manual yourself. */
3445 unsigned u1DefBig : 1;
3446 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3447 * clear byte. */
3448 unsigned u1Granularity : 1;
3449 /** 38 - Base address - highest 8 bits. */
3450 unsigned u8BaseHigh2 : 8;
3451} X86DESCGENERIC;
3452#pragma pack()
3453/** Pointer to a generic descriptor entry. */
3454typedef X86DESCGENERIC *PX86DESCGENERIC;
3455/** Pointer to a const generic descriptor entry. */
3456typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3457
3458/** @name Bit offsets of X86DESCGENERIC members.
3459 * @{*/
3460#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3461#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3462#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3463#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3464#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3465#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3466#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3467#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3468#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3469#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3470#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3471#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3472#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3473/** @} */
3474
3475
3476/** @name LAR mask
3477 * @{ */
3478#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3479#define X86LAR_F_DT UINT16_C( 0x1000)
3480#define X86LAR_F_DPL UINT16_C( 0x6000)
3481#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3482#define X86LAR_F_P UINT16_C( 0x8000)
3483#define X86LAR_F_AVL UINT32_C(0x00100000)
3484#define X86LAR_F_L UINT32_C(0x00200000)
3485#define X86LAR_F_D UINT32_C(0x00400000)
3486#define X86LAR_F_G UINT32_C(0x00800000)
3487/** @} */
3488
3489
3490/**
3491 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3492 */
3493typedef struct X86DESCGATE
3494{
3495 /** 00 - Target code segment offset - Low word.
3496 * Ignored if task-gate. */
3497 unsigned u16OffsetLow : 16;
3498 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3499 * TSS selector if task-gate. */
3500 unsigned u16Sel : 16;
3501 /** 20 - Number of parameters for a call-gate.
3502 * Ignored if interrupt-, trap- or task-gate. */
3503 unsigned u5ParmCount : 5;
3504 /** 25 - Reserved / ignored. */
3505 unsigned u3Reserved : 3;
3506 /** 28 - Segment Type. */
3507 unsigned u4Type : 4;
3508 /** 2c - Descriptor Type (0 = system). */
3509 unsigned u1DescType : 1;
3510 /** 2d - Descriptor Privilege level. */
3511 unsigned u2Dpl : 2;
3512 /** 2f - Flags selector present(=1) or not. */
3513 unsigned u1Present : 1;
3514 /** 30 - Target code segment offset - High word.
3515 * Ignored if task-gate. */
3516 unsigned u16OffsetHigh : 16;
3517} X86DESCGATE;
3518/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3519typedef X86DESCGATE *PX86DESCGATE;
3520/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3521typedef const X86DESCGATE *PCX86DESCGATE;
3522
3523#endif /* VBOX_FOR_DTRACE_LIB */
3524
3525/**
3526 * Descriptor table entry.
3527 */
3528#pragma pack(1)
3529typedef union X86DESC
3530{
3531#ifndef VBOX_FOR_DTRACE_LIB
3532 /** Generic descriptor view. */
3533 X86DESCGENERIC Gen;
3534 /** Gate descriptor view. */
3535 X86DESCGATE Gate;
3536#endif
3537
3538 /** 8 bit unsigned integer view. */
3539 uint8_t au8[8];
3540 /** 16 bit unsigned integer view. */
3541 uint16_t au16[4];
3542 /** 32 bit unsigned integer view. */
3543 uint32_t au32[2];
3544 /** 64 bit unsigned integer view. */
3545 uint64_t au64[1];
3546 /** Unsigned integer view. */
3547 uint64_t u;
3548} X86DESC;
3549#ifndef VBOX_FOR_DTRACE_LIB
3550AssertCompileSize(X86DESC, 8);
3551#endif
3552#pragma pack()
3553/** Pointer to descriptor table entry. */
3554typedef X86DESC *PX86DESC;
3555/** Pointer to const descriptor table entry. */
3556typedef const X86DESC *PCX86DESC;
3557
3558/** @def X86DESC_BASE
3559 * Return the base address of a descriptor.
3560 */
3561#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3562 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3563 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3564 | ( (a_pDesc)->Gen.u16BaseLow ) )
3565
3566/** @def X86DESC_LIMIT
3567 * Return the limit of a descriptor.
3568 */
3569#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3570 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3571 | ( (a_pDesc)->Gen.u16LimitLow ) )
3572
3573/** @def X86DESC_LIMIT_G
3574 * Return the limit of a descriptor with the granularity bit taken into account.
3575 * @returns Selector limit (uint32_t).
3576 * @param a_pDesc Pointer to the descriptor.
3577 */
3578#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3579 ( (a_pDesc)->Gen.u1Granularity \
3580 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3581 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3582 )
3583
3584/** @def X86DESC_GET_HID_ATTR
3585 * Get the descriptor attributes for the hidden register.
3586 */
3587#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3588 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3589
3590#ifndef VBOX_FOR_DTRACE_LIB
3591
3592/**
3593 * 64 bits generic descriptor table entry
3594 * Note: most of these bits have no meaning in long mode.
3595 */
3596#pragma pack(1)
3597typedef struct X86DESC64GENERIC
3598{
3599 /** Limit - Low word - *IGNORED*. */
3600 uint32_t u16LimitLow : 16;
3601 /** Base address - low word. - *IGNORED*
3602 * Don't try set this to 24 because MSC is doing stupid things then. */
3603 uint32_t u16BaseLow : 16;
3604 /** Base address - first 8 bits of high word. - *IGNORED* */
3605 uint32_t u8BaseHigh1 : 8;
3606 /** Segment Type. */
3607 uint32_t u4Type : 4;
3608 /** Descriptor Type. System(=0) or code/data selector */
3609 uint32_t u1DescType : 1;
3610 /** Descriptor Privilege level. */
3611 uint32_t u2Dpl : 2;
3612 /** Flags selector present(=1) or not. */
3613 uint32_t u1Present : 1;
3614 /** Segment limit 16-19. - *IGNORED* */
3615 uint32_t u4LimitHigh : 4;
3616 /** Available for system software. - *IGNORED* */
3617 uint32_t u1Available : 1;
3618 /** Long mode flag. */
3619 uint32_t u1Long : 1;
3620 /** This flags meaning depends on the segment type. Try make sense out
3621 * of the intel manual yourself. */
3622 uint32_t u1DefBig : 1;
3623 /** Granularity of the limit. If set 4KB granularity is used, if
3624 * clear byte. - *IGNORED* */
3625 uint32_t u1Granularity : 1;
3626 /** Base address - highest 8 bits. - *IGNORED* */
3627 uint32_t u8BaseHigh2 : 8;
3628 /** Base address - bits 63-32. */
3629 uint32_t u32BaseHigh3 : 32;
3630 uint32_t u8Reserved : 8;
3631 uint32_t u5Zeros : 5;
3632 uint32_t u19Reserved : 19;
3633} X86DESC64GENERIC;
3634#pragma pack()
3635/** Pointer to a generic descriptor entry. */
3636typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3637/** Pointer to a const generic descriptor entry. */
3638typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3639
3640/**
3641 * System descriptor table entry (64 bits)
3642 *
3643 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3644 */
3645#pragma pack(1)
3646typedef struct X86DESC64SYSTEM
3647{
3648 /** Limit - Low word. */
3649 uint32_t u16LimitLow : 16;
3650 /** Base address - low word.
3651 * Don't try set this to 24 because MSC is doing stupid things then. */
3652 uint32_t u16BaseLow : 16;
3653 /** Base address - first 8 bits of high word. */
3654 uint32_t u8BaseHigh1 : 8;
3655 /** Segment Type. */
3656 uint32_t u4Type : 4;
3657 /** Descriptor Type. System(=0) or code/data selector */
3658 uint32_t u1DescType : 1;
3659 /** Descriptor Privilege level. */
3660 uint32_t u2Dpl : 2;
3661 /** Flags selector present(=1) or not. */
3662 uint32_t u1Present : 1;
3663 /** Segment limit 16-19. */
3664 uint32_t u4LimitHigh : 4;
3665 /** Available for system software. */
3666 uint32_t u1Available : 1;
3667 /** Reserved - 0. */
3668 uint32_t u1Reserved : 1;
3669 /** This flags meaning depends on the segment type. Try make sense out
3670 * of the intel manual yourself. */
3671 uint32_t u1DefBig : 1;
3672 /** Granularity of the limit. If set 4KB granularity is used, if
3673 * clear byte. */
3674 uint32_t u1Granularity : 1;
3675 /** Base address - bits 31-24. */
3676 uint32_t u8BaseHigh2 : 8;
3677 /** Base address - bits 63-32. */
3678 uint32_t u32BaseHigh3 : 32;
3679 uint32_t u8Reserved : 8;
3680 uint32_t u5Zeros : 5;
3681 uint32_t u19Reserved : 19;
3682} X86DESC64SYSTEM;
3683#pragma pack()
3684/** Pointer to a system descriptor entry. */
3685typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3686/** Pointer to a const system descriptor entry. */
3687typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3688
3689/**
3690 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3691 */
3692typedef struct X86DESC64GATE
3693{
3694 /** Target code segment offset - Low word. */
3695 uint32_t u16OffsetLow : 16;
3696 /** Target code segment selector. */
3697 uint32_t u16Sel : 16;
3698 /** Interrupt stack table for interrupt- and trap-gates.
3699 * Ignored by call-gates. */
3700 uint32_t u3IST : 3;
3701 /** Reserved / ignored. */
3702 uint32_t u5Reserved : 5;
3703 /** Segment Type. */
3704 uint32_t u4Type : 4;
3705 /** Descriptor Type (0 = system). */
3706 uint32_t u1DescType : 1;
3707 /** Descriptor Privilege level. */
3708 uint32_t u2Dpl : 2;
3709 /** Flags selector present(=1) or not. */
3710 uint32_t u1Present : 1;
3711 /** Target code segment offset - High word.
3712 * Ignored if task-gate. */
3713 uint32_t u16OffsetHigh : 16;
3714 /** Target code segment offset - Top dword.
3715 * Ignored if task-gate. */
3716 uint32_t u32OffsetTop : 32;
3717 /** Reserved / ignored / must be zero.
3718 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3719 uint32_t u32Reserved : 32;
3720} X86DESC64GATE;
3721AssertCompileSize(X86DESC64GATE, 16);
3722/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3723typedef X86DESC64GATE *PX86DESC64GATE;
3724/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3725typedef const X86DESC64GATE *PCX86DESC64GATE;
3726
3727#endif /* VBOX_FOR_DTRACE_LIB */
3728
3729/**
3730 * Descriptor table entry.
3731 */
3732#pragma pack(1)
3733typedef union X86DESC64
3734{
3735#ifndef VBOX_FOR_DTRACE_LIB
3736 /** Generic descriptor view. */
3737 X86DESC64GENERIC Gen;
3738 /** System descriptor view. */
3739 X86DESC64SYSTEM System;
3740 /** Gate descriptor view. */
3741 X86DESC64GATE Gate;
3742#endif
3743
3744 /** 8 bit unsigned integer view. */
3745 uint8_t au8[16];
3746 /** 16 bit unsigned integer view. */
3747 uint16_t au16[8];
3748 /** 32 bit unsigned integer view. */
3749 uint32_t au32[4];
3750 /** 64 bit unsigned integer view. */
3751 uint64_t au64[2];
3752} X86DESC64;
3753#ifndef VBOX_FOR_DTRACE_LIB
3754AssertCompileSize(X86DESC64, 16);
3755#endif
3756#pragma pack()
3757/** Pointer to descriptor table entry. */
3758typedef X86DESC64 *PX86DESC64;
3759/** Pointer to const descriptor table entry. */
3760typedef const X86DESC64 *PCX86DESC64;
3761
3762/** @def X86DESC64_BASE
3763 * Return the base of a 64-bit descriptor.
3764 */
3765#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3766 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3767 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3768 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3769 | ( (a_pDesc)->Gen.u16BaseLow ) )
3770
3771
3772
3773/** @name Host system descriptor table entry - Use with care!
3774 * @{ */
3775/** Host system descriptor table entry. */
3776#if HC_ARCH_BITS == 64
3777typedef X86DESC64 X86DESCHC;
3778#else
3779typedef X86DESC X86DESCHC;
3780#endif
3781/** Pointer to a host system descriptor table entry. */
3782#if HC_ARCH_BITS == 64
3783typedef PX86DESC64 PX86DESCHC;
3784#else
3785typedef PX86DESC PX86DESCHC;
3786#endif
3787/** Pointer to a const host system descriptor table entry. */
3788#if HC_ARCH_BITS == 64
3789typedef PCX86DESC64 PCX86DESCHC;
3790#else
3791typedef PCX86DESC PCX86DESCHC;
3792#endif
3793/** @} */
3794
3795
3796/** @name Selector Descriptor Types.
3797 * @{
3798 */
3799
3800/** @name Non-System Selector Types.
3801 * @{ */
3802/** Code(=set)/Data(=clear) bit. */
3803#define X86_SEL_TYPE_CODE 8
3804/** Memory(=set)/System(=clear) bit. */
3805#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3806/** Accessed bit. */
3807#define X86_SEL_TYPE_ACCESSED 1
3808/** Expand down bit (for data selectors only). */
3809#define X86_SEL_TYPE_DOWN 4
3810/** Conforming bit (for code selectors only). */
3811#define X86_SEL_TYPE_CONF 4
3812/** Write bit (for data selectors only). */
3813#define X86_SEL_TYPE_WRITE 2
3814/** Read bit (for code selectors only). */
3815#define X86_SEL_TYPE_READ 2
3816/** The bit number of the code segment read bit (relative to u4Type). */
3817#define X86_SEL_TYPE_READ_BIT 1
3818
3819/** Read only selector type. */
3820#define X86_SEL_TYPE_RO 0
3821/** Accessed read only selector type. */
3822#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3823/** Read write selector type. */
3824#define X86_SEL_TYPE_RW 2
3825/** Accessed read write selector type. */
3826#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3827/** Expand down read only selector type. */
3828#define X86_SEL_TYPE_RO_DOWN 4
3829/** Accessed expand down read only selector type. */
3830#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3831/** Expand down read write selector type. */
3832#define X86_SEL_TYPE_RW_DOWN 6
3833/** Accessed expand down read write selector type. */
3834#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3835/** Execute only selector type. */
3836#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3837/** Accessed execute only selector type. */
3838#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3839/** Execute and read selector type. */
3840#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3841/** Accessed execute and read selector type. */
3842#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3843/** Conforming execute only selector type. */
3844#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3845/** Accessed Conforming execute only selector type. */
3846#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3847/** Conforming execute and write selector type. */
3848#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3849/** Accessed Conforming execute and write selector type. */
3850#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3851/** @} */
3852
3853
3854/** @name System Selector Types.
3855 * @{ */
3856/** The TSS busy bit mask. */
3857#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3858
3859/** Undefined system selector type. */
3860#define X86_SEL_TYPE_SYS_UNDEFINED 0
3861/** 286 TSS selector. */
3862#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3863/** LDT selector. */
3864#define X86_SEL_TYPE_SYS_LDT 2
3865/** 286 TSS selector - Busy. */
3866#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3867/** 286 Callgate selector. */
3868#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3869/** Taskgate selector. */
3870#define X86_SEL_TYPE_SYS_TASK_GATE 5
3871/** 286 Interrupt gate selector. */
3872#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3873/** 286 Trapgate selector. */
3874#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3875/** Undefined system selector. */
3876#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3877/** 386 TSS selector. */
3878#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3879/** Undefined system selector. */
3880#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3881/** 386 TSS selector - Busy. */
3882#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3883/** 386 Callgate selector. */
3884#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3885/** Undefined system selector. */
3886#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3887/** 386 Interruptgate selector. */
3888#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3889/** 386 Trapgate selector. */
3890#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3891/** @} */
3892
3893/** @name AMD64 System Selector Types.
3894 * @{ */
3895/** LDT selector. */
3896#define AMD64_SEL_TYPE_SYS_LDT 2
3897/** TSS selector - Busy. */
3898#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3899/** TSS selector - Busy. */
3900#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3901/** Callgate selector. */
3902#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3903/** Interruptgate selector. */
3904#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3905/** Trapgate selector. */
3906#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3907/** @} */
3908
3909/** @} */
3910
3911
3912/** @name Descriptor Table Entry Flag Masks.
3913 * These are for the 2nd 32-bit word of a descriptor.
3914 * @{ */
3915/** Bits 8-11 - TYPE - Descriptor type mask. */
3916#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3917/** Bit 12 - S - System (=0) or Code/Data (=1). */
3918#define X86_DESC_S RT_BIT_32(12)
3919/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3920#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3921/** Bit 15 - P - Present. */
3922#define X86_DESC_P RT_BIT_32(15)
3923/** Bit 20 - AVL - Available for system software. */
3924#define X86_DESC_AVL RT_BIT_32(20)
3925/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3926#define X86_DESC_DB RT_BIT_32(22)
3927/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3928 * used, if clear byte. */
3929#define X86_DESC_G RT_BIT_32(23)
3930/** @} */
3931
3932/** @} */
3933
3934
3935/** @name Task Segments.
3936 * @{
3937 */
3938
3939/**
3940 * The minimum TSS descriptor limit for 286 tasks.
3941 */
3942#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3943
3944/**
3945 * The minimum TSS descriptor segment limit for 386 tasks.
3946 */
3947#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3948
3949/**
3950 * 16-bit Task Segment (TSS).
3951 */
3952#pragma pack(1)
3953typedef struct X86TSS16
3954{
3955 /** Back link to previous task. (static) */
3956 RTSEL selPrev;
3957 /** Ring-0 stack pointer. (static) */
3958 uint16_t sp0;
3959 /** Ring-0 stack segment. (static) */
3960 RTSEL ss0;
3961 /** Ring-1 stack pointer. (static) */
3962 uint16_t sp1;
3963 /** Ring-1 stack segment. (static) */
3964 RTSEL ss1;
3965 /** Ring-2 stack pointer. (static) */
3966 uint16_t sp2;
3967 /** Ring-2 stack segment. (static) */
3968 RTSEL ss2;
3969 /** IP before task switch. */
3970 uint16_t ip;
3971 /** FLAGS before task switch. */
3972 uint16_t flags;
3973 /** AX before task switch. */
3974 uint16_t ax;
3975 /** CX before task switch. */
3976 uint16_t cx;
3977 /** DX before task switch. */
3978 uint16_t dx;
3979 /** BX before task switch. */
3980 uint16_t bx;
3981 /** SP before task switch. */
3982 uint16_t sp;
3983 /** BP before task switch. */
3984 uint16_t bp;
3985 /** SI before task switch. */
3986 uint16_t si;
3987 /** DI before task switch. */
3988 uint16_t di;
3989 /** ES before task switch. */
3990 RTSEL es;
3991 /** CS before task switch. */
3992 RTSEL cs;
3993 /** SS before task switch. */
3994 RTSEL ss;
3995 /** DS before task switch. */
3996 RTSEL ds;
3997 /** LDTR before task switch. */
3998 RTSEL selLdt;
3999} X86TSS16;
4000#ifndef VBOX_FOR_DTRACE_LIB
4001AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4002#endif
4003#pragma pack()
4004/** Pointer to a 16-bit task segment. */
4005typedef X86TSS16 *PX86TSS16;
4006/** Pointer to a const 16-bit task segment. */
4007typedef const X86TSS16 *PCX86TSS16;
4008
4009
4010/**
4011 * 32-bit Task Segment (TSS).
4012 */
4013#pragma pack(1)
4014typedef struct X86TSS32
4015{
4016 /** Back link to previous task. (static) */
4017 RTSEL selPrev;
4018 uint16_t padding1;
4019 /** Ring-0 stack pointer. (static) */
4020 uint32_t esp0;
4021 /** Ring-0 stack segment. (static) */
4022 RTSEL ss0;
4023 uint16_t padding_ss0;
4024 /** Ring-1 stack pointer. (static) */
4025 uint32_t esp1;
4026 /** Ring-1 stack segment. (static) */
4027 RTSEL ss1;
4028 uint16_t padding_ss1;
4029 /** Ring-2 stack pointer. (static) */
4030 uint32_t esp2;
4031 /** Ring-2 stack segment. (static) */
4032 RTSEL ss2;
4033 uint16_t padding_ss2;
4034 /** Page directory for the task. (static) */
4035 uint32_t cr3;
4036 /** EIP before task switch. */
4037 uint32_t eip;
4038 /** EFLAGS before task switch. */
4039 uint32_t eflags;
4040 /** EAX before task switch. */
4041 uint32_t eax;
4042 /** ECX before task switch. */
4043 uint32_t ecx;
4044 /** EDX before task switch. */
4045 uint32_t edx;
4046 /** EBX before task switch. */
4047 uint32_t ebx;
4048 /** ESP before task switch. */
4049 uint32_t esp;
4050 /** EBP before task switch. */
4051 uint32_t ebp;
4052 /** ESI before task switch. */
4053 uint32_t esi;
4054 /** EDI before task switch. */
4055 uint32_t edi;
4056 /** ES before task switch. */
4057 RTSEL es;
4058 uint16_t padding_es;
4059 /** CS before task switch. */
4060 RTSEL cs;
4061 uint16_t padding_cs;
4062 /** SS before task switch. */
4063 RTSEL ss;
4064 uint16_t padding_ss;
4065 /** DS before task switch. */
4066 RTSEL ds;
4067 uint16_t padding_ds;
4068 /** FS before task switch. */
4069 RTSEL fs;
4070 uint16_t padding_fs;
4071 /** GS before task switch. */
4072 RTSEL gs;
4073 uint16_t padding_gs;
4074 /** LDTR before task switch. */
4075 RTSEL selLdt;
4076 uint16_t padding_ldt;
4077 /** Debug trap flag */
4078 uint16_t fDebugTrap;
4079 /** Offset relative to the TSS of the start of the I/O Bitmap
4080 * and the end of the interrupt redirection bitmap. */
4081 uint16_t offIoBitmap;
4082} X86TSS32;
4083#pragma pack()
4084/** Pointer to task segment. */
4085typedef X86TSS32 *PX86TSS32;
4086/** Pointer to const task segment. */
4087typedef const X86TSS32 *PCX86TSS32;
4088#ifndef VBOX_FOR_DTRACE_LIB
4089AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4090AssertCompileMemberOffset(X86TSS32, cr3, 28);
4091AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4092#endif
4093
4094/**
4095 * 64-bit Task segment.
4096 */
4097#pragma pack(1)
4098typedef struct X86TSS64
4099{
4100 /** Reserved. */
4101 uint32_t u32Reserved;
4102 /** Ring-0 stack pointer. (static) */
4103 uint64_t rsp0;
4104 /** Ring-1 stack pointer. (static) */
4105 uint64_t rsp1;
4106 /** Ring-2 stack pointer. (static) */
4107 uint64_t rsp2;
4108 /** Reserved. */
4109 uint32_t u32Reserved2[2];
4110 /* IST */
4111 uint64_t ist1;
4112 uint64_t ist2;
4113 uint64_t ist3;
4114 uint64_t ist4;
4115 uint64_t ist5;
4116 uint64_t ist6;
4117 uint64_t ist7;
4118 /* Reserved. */
4119 uint16_t u16Reserved[5];
4120 /** Offset relative to the TSS of the start of the I/O Bitmap
4121 * and the end of the interrupt redirection bitmap. */
4122 uint16_t offIoBitmap;
4123} X86TSS64;
4124#pragma pack()
4125/** Pointer to a 64-bit task segment. */
4126typedef X86TSS64 *PX86TSS64;
4127/** Pointer to a const 64-bit task segment. */
4128typedef const X86TSS64 *PCX86TSS64;
4129#ifndef VBOX_FOR_DTRACE_LIB
4130AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4131#endif
4132
4133/** @} */
4134
4135
4136/** @name Selectors.
4137 * @{
4138 */
4139
4140/**
4141 * The shift used to convert a selector from and to index an index (C).
4142 */
4143#define X86_SEL_SHIFT 3
4144
4145/**
4146 * The mask used to mask off the table indicator and RPL of an selector.
4147 */
4148#define X86_SEL_MASK 0xfff8U
4149
4150/**
4151 * The mask used to mask off the RPL of an selector.
4152 * This is suitable for checking for NULL selectors.
4153 */
4154#define X86_SEL_MASK_OFF_RPL 0xfffcU
4155
4156/**
4157 * The bit indicating that a selector is in the LDT and not in the GDT.
4158 */
4159#define X86_SEL_LDT 0x0004U
4160
4161/**
4162 * The bit mask for getting the RPL of a selector.
4163 */
4164#define X86_SEL_RPL 0x0003U
4165
4166/**
4167 * The mask covering both RPL and LDT.
4168 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4169 * checks.
4170 */
4171#define X86_SEL_RPL_LDT 0x0007U
4172
4173/** @} */
4174
4175
4176/**
4177 * x86 Exceptions/Faults/Traps.
4178 */
4179typedef enum X86XCPT
4180{
4181 /** \#DE - Divide error. */
4182 X86_XCPT_DE = 0x00,
4183 /** \#DB - Debug event (single step, DRx, ..) */
4184 X86_XCPT_DB = 0x01,
4185 /** NMI - Non-Maskable Interrupt */
4186 X86_XCPT_NMI = 0x02,
4187 /** \#BP - Breakpoint (INT3). */
4188 X86_XCPT_BP = 0x03,
4189 /** \#OF - Overflow (INTO). */
4190 X86_XCPT_OF = 0x04,
4191 /** \#BR - Bound range exceeded (BOUND). */
4192 X86_XCPT_BR = 0x05,
4193 /** \#UD - Undefined opcode. */
4194 X86_XCPT_UD = 0x06,
4195 /** \#NM - Device not available (math coprocessor device). */
4196 X86_XCPT_NM = 0x07,
4197 /** \#DF - Double fault. */
4198 X86_XCPT_DF = 0x08,
4199 /** ??? - Coprocessor segment overrun (obsolete). */
4200 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4201 /** \#TS - Taskswitch (TSS). */
4202 X86_XCPT_TS = 0x0a,
4203 /** \#NP - Segment no present. */
4204 X86_XCPT_NP = 0x0b,
4205 /** \#SS - Stack segment fault. */
4206 X86_XCPT_SS = 0x0c,
4207 /** \#GP - General protection fault. */
4208 X86_XCPT_GP = 0x0d,
4209 /** \#PF - Page fault. */
4210 X86_XCPT_PF = 0x0e,
4211 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4212 /** \#MF - Math fault (FPU). */
4213 X86_XCPT_MF = 0x10,
4214 /** \#AC - Alignment check. */
4215 X86_XCPT_AC = 0x11,
4216 /** \#MC - Machine check. */
4217 X86_XCPT_MC = 0x12,
4218 /** \#XF - SIMD Floating-Pointer Exception. */
4219 X86_XCPT_XF = 0x13,
4220 /** \#VE - Virtualization Exception. */
4221 X86_XCPT_VE = 0x14,
4222 /** \#SX - Security Exception. */
4223 X86_XCPT_SX = 0x1e
4224} X86XCPT;
4225/** Pointer to a x86 exception code. */
4226typedef X86XCPT *PX86XCPT;
4227/** Pointer to a const x86 exception code. */
4228typedef const X86XCPT *PCX86XCPT;
4229/** The last valid (currently reserved) exception value. */
4230#define X86_XCPT_LAST 0x1f
4231
4232
4233/** @name Trap Error Codes
4234 * @{
4235 */
4236/** External indicator. */
4237#define X86_TRAP_ERR_EXTERNAL 1
4238/** IDT indicator. */
4239#define X86_TRAP_ERR_IDT 2
4240/** Descriptor table indicator - If set LDT, if clear GDT. */
4241#define X86_TRAP_ERR_TI 4
4242/** Mask for getting the selector. */
4243#define X86_TRAP_ERR_SEL_MASK 0xfff8
4244/** Shift for getting the selector table index (C type index). */
4245#define X86_TRAP_ERR_SEL_SHIFT 3
4246/** @} */
4247
4248
4249/** @name \#PF Trap Error Codes
4250 * @{
4251 */
4252/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4253#define X86_TRAP_PF_P RT_BIT_32(0)
4254/** Bit 1 - R/W - Read (clear) or write (set) access. */
4255#define X86_TRAP_PF_RW RT_BIT_32(1)
4256/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4257#define X86_TRAP_PF_US RT_BIT_32(2)
4258/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4259#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4260/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4261#define X86_TRAP_PF_ID RT_BIT_32(4)
4262/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4263#define X86_TRAP_PF_PK RT_BIT_32(5)
4264/** @} */
4265
4266#pragma pack(1)
4267/**
4268 * 16-bit IDTR.
4269 */
4270typedef struct X86IDTR16
4271{
4272 /** Offset. */
4273 uint16_t offSel;
4274 /** Selector. */
4275 uint16_t uSel;
4276} X86IDTR16, *PX86IDTR16;
4277#pragma pack()
4278
4279#pragma pack(1)
4280/**
4281 * 32-bit IDTR/GDTR.
4282 */
4283typedef struct X86XDTR32
4284{
4285 /** Size of the descriptor table. */
4286 uint16_t cb;
4287 /** Address of the descriptor table. */
4288#ifndef VBOX_FOR_DTRACE_LIB
4289 uint32_t uAddr;
4290#else
4291 uint16_t au16Addr[2];
4292#endif
4293} X86XDTR32, *PX86XDTR32;
4294#pragma pack()
4295
4296#pragma pack(1)
4297/**
4298 * 64-bit IDTR/GDTR.
4299 */
4300typedef struct X86XDTR64
4301{
4302 /** Size of the descriptor table. */
4303 uint16_t cb;
4304 /** Address of the descriptor table. */
4305#ifndef VBOX_FOR_DTRACE_LIB
4306 uint64_t uAddr;
4307#else
4308 uint16_t au16Addr[4];
4309#endif
4310} X86XDTR64, *PX86XDTR64;
4311#pragma pack()
4312
4313
4314/** @name ModR/M
4315 * @{ */
4316#define X86_MODRM_RM_MASK UINT8_C(0x07)
4317#define X86_MODRM_REG_MASK UINT8_C(0x38)
4318#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4319#define X86_MODRM_REG_SHIFT 3
4320#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4321#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4322#define X86_MODRM_MOD_SHIFT 6
4323#ifndef VBOX_FOR_DTRACE_LIB
4324AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4325AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4326AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4327/** @def X86_MODRM_MAKE
4328 * @param a_Mod The mod value (0..3).
4329 * @param a_Reg The register value (0..7).
4330 * @param a_RegMem The register or memory value (0..7). */
4331# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4332#endif
4333/** @} */
4334
4335/** @name SIB
4336 * @{ */
4337#define X86_SIB_BASE_MASK UINT8_C(0x07)
4338#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4339#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4340#define X86_SIB_INDEX_SHIFT 3
4341#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4342#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4343#define X86_SIB_SCALE_SHIFT 6
4344#ifndef VBOX_FOR_DTRACE_LIB
4345AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4346AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4347AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4348#endif
4349/** @} */
4350
4351/** @name General register indexes.
4352 * @{ */
4353#define X86_GREG_xAX 0
4354#define X86_GREG_xCX 1
4355#define X86_GREG_xDX 2
4356#define X86_GREG_xBX 3
4357#define X86_GREG_xSP 4
4358#define X86_GREG_xBP 5
4359#define X86_GREG_xSI 6
4360#define X86_GREG_xDI 7
4361#define X86_GREG_x8 8
4362#define X86_GREG_x9 9
4363#define X86_GREG_x10 10
4364#define X86_GREG_x11 11
4365#define X86_GREG_x12 12
4366#define X86_GREG_x13 13
4367#define X86_GREG_x14 14
4368#define X86_GREG_x15 15
4369/** @} */
4370/** General register count. */
4371#define X86_GREG_COUNT 16
4372
4373/** @name X86_SREG_XXX - Segment register indexes.
4374 * @{ */
4375#define X86_SREG_ES 0
4376#define X86_SREG_CS 1
4377#define X86_SREG_SS 2
4378#define X86_SREG_DS 3
4379#define X86_SREG_FS 4
4380#define X86_SREG_GS 5
4381/** @} */
4382/** Segment register count. */
4383#define X86_SREG_COUNT 6
4384
4385
4386/** @name X86_OP_XXX - Prefixes
4387 * @{ */
4388#define X86_OP_PRF_CS UINT8_C(0x2e)
4389#define X86_OP_PRF_SS UINT8_C(0x36)
4390#define X86_OP_PRF_DS UINT8_C(0x3e)
4391#define X86_OP_PRF_ES UINT8_C(0x26)
4392#define X86_OP_PRF_FS UINT8_C(0x64)
4393#define X86_OP_PRF_GS UINT8_C(0x65)
4394#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4395#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4396#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4397#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4398#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4399#define X86_OP_REX_B UINT8_C(0x41)
4400#define X86_OP_REX_X UINT8_C(0x42)
4401#define X86_OP_REX_R UINT8_C(0x44)
4402#define X86_OP_REX_W UINT8_C(0x48)
4403/** @} */
4404
4405
4406/** @} */
4407
4408#endif /* !IPRT_INCLUDED_x86_h */
4409
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