VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 78632

Last change on this file since 78632 was 78632, checked in by vboxsync, 5 years ago

Forward ported 130474,130475,130477,130479. bugref:9453
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File size: 165.8 KB
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2019 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403/** @} */
404
405
406/** @name CPUID Feature information.
407 * CPUID query with EAX=1.
408 * @{
409 */
410/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
411#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
412/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
413#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
414/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
415#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
416/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
417#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
418/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
419#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
420/** ECX Bit 5 - VMX - Virtual Machine Technology. */
421#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
422/** ECX Bit 6 - SMX - Safer Mode Extensions. */
423#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
424/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
425#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
426/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
427#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
428/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
429#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
430/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
431#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
432/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
433 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
434#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
435/** ECX Bit 12 - FMA. */
436#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
437/** ECX Bit 13 - CX16 - CMPXCHG16B. */
438#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
439/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
440#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
441/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
442#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
443/** ECX Bit 17 - PCID - Process-context identifiers. */
444#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
445/** ECX Bit 18 - DCA - Direct Cache Access. */
446#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
447/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
448#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
449/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
450#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
451/** ECX Bit 21 - x2APIC support. */
452#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
453/** ECX Bit 22 - MOVBE instruction. */
454#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
455/** ECX Bit 23 - POPCNT instruction. */
456#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
457/** ECX Bir 24 - TSC-Deadline. */
458#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
459/** ECX Bit 25 - AES instructions. */
460#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
461/** ECX Bit 26 - XSAVE instruction. */
462#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
463/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
464#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
465/** ECX Bit 28 - AVX. */
466#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
467/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
468#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
469/** ECX Bit 30 - RDRAND instruction. */
470#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
471/** ECX Bit 31 - Hypervisor Present (software only). */
472#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
473
474
475/** Bit 0 - FPU - x87 FPU on Chip. */
476#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
477/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
478#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
479/** Bit 2 - DE - Debugging extensions. */
480#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
481/** Bit 3 - PSE - Page Size Extension. */
482#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
483#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
484/** Bit 4 - TSC - Time Stamp Counter. */
485#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
486/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
487#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
488/** Bit 6 - PAE - Physical Address Extension. */
489#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
490#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
491/** Bit 7 - MCE - Machine Check Exception. */
492#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
493/** Bit 8 - CX8 - CMPXCHG8B instruction. */
494#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
495/** Bit 9 - APIC - APIC On-Chip. */
496#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
497/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
498#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
499/** Bit 12 - MTRR - Memory Type Range Registers. */
500#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
501/** Bit 13 - PGE - PTE Global Bit. */
502#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
503/** Bit 14 - MCA - Machine Check Architecture. */
504#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
505/** Bit 15 - CMOV - Conditional Move Instructions. */
506#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
507/** Bit 16 - PAT - Page Attribute Table. */
508#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
509/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
510#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
511/** Bit 18 - PSN - Processor Serial Number. */
512#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
513/** Bit 19 - CLFSH - CLFLUSH Instruction. */
514#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
515/** Bit 21 - DS - Debug Store. */
516#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
517/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
518#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
519/** Bit 23 - MMX - Intel MMX Technology. */
520#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
521/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
522#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
523/** Bit 25 - SSE - SSE Support. */
524#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
525/** Bit 26 - SSE2 - SSE2 Support. */
526#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
527/** Bit 27 - SS - Self Snoop. */
528#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
529/** Bit 28 - HTT - Hyper-Threading Technology. */
530#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
531/** Bit 29 - TM - Therm. Monitor. */
532#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
533/** Bit 31 - PBE - Pending Break Enabled. */
534#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
535/** @} */
536
537/** @name CPUID mwait/monitor information.
538 * CPUID query with EAX=5.
539 * @{
540 */
541/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
542#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
543/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
544#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
545/** @} */
546
547
548/** @name CPUID Structured Extended Feature information.
549 * CPUID query with EAX=7.
550 * @{
551 */
552/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
553#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
554/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
555#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
556/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
557#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
558/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
559#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
560/** EBX Bit 4 - HLE - Hardware Lock Elision. */
561#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
562/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
563#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
564/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
565#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
566/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
567#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
568/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
569#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
570/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
571#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
572/** EBX Bit 10 - INVPCID - Supports INVPCID. */
573#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
574/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
575#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
576/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
577#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
578/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
579#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
580/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
581#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
582/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
583#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
584/** EBX Bit 16 - AVX512F - Supports AVX512F. */
585#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
586/** EBX Bit 18 - RDSEED - Supports RDSEED. */
587#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
588/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
589#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
590/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
591#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
592/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
593#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
594/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
595#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
596/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
597#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
598/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
599#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
600/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
601#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
602/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
603#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
604
605/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
606#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
607/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
608#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
609/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
610#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
611/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
612#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
613/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
614#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
615/** ECX Bit 22 - RDPID - Support pread process ID. */
616#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
617/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
618#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
619
620/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
621#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
622/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
623 * IBPB command in IA32_PRED_CMD. */
624#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
625/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
626#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
627/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
628#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
629/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
630#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
631
632/** @} */
633
634
635/** @name CPUID Extended Feature information.
636 * CPUID query with EAX=0x80000001.
637 * @{
638 */
639/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
640#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
641
642/** EDX Bit 11 - SYSCALL/SYSRET. */
643#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
644/** EDX Bit 20 - No-Execute/Execute-Disable. */
645#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
646/** EDX Bit 26 - 1 GB large page. */
647#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
648/** EDX Bit 27 - RDTSCP. */
649#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
650/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
651#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
652/** @}*/
653
654/** @name CPUID AMD Feature information.
655 * CPUID query with EAX=0x80000001.
656 * @{
657 */
658/** Bit 0 - FPU - x87 FPU on Chip. */
659#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
660/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
661#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
662/** Bit 2 - DE - Debugging extensions. */
663#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
664/** Bit 3 - PSE - Page Size Extension. */
665#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
666/** Bit 4 - TSC - Time Stamp Counter. */
667#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
668/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
669#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
670/** Bit 6 - PAE - Physical Address Extension. */
671#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
672/** Bit 7 - MCE - Machine Check Exception. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
674/** Bit 8 - CX8 - CMPXCHG8B instruction. */
675#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
676/** Bit 9 - APIC - APIC On-Chip. */
677#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
678/** Bit 12 - MTRR - Memory Type Range Registers. */
679#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
680/** Bit 13 - PGE - PTE Global Bit. */
681#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
682/** Bit 14 - MCA - Machine Check Architecture. */
683#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
684/** Bit 15 - CMOV - Conditional Move Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
686/** Bit 16 - PAT - Page Attribute Table. */
687#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
688/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
689#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
690/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
691#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
692/** Bit 23 - MMX - Intel MMX Technology. */
693#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
694/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
695#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
696/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
697#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
698/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
699#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
700/** Bit 31 - 3DNOW - AMD 3DNow. */
701#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
702
703/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
704#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
705/** Bit 2 - SVM - AMD VM extensions. */
706#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
707/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
708#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
709/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
710#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
711/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
712#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
713/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
714#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
715/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
716#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
717/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
718#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
719/** Bit 9 - OSVW - AMD OS visible workaround. */
720#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
721/** Bit 10 - IBS - Instruct based sampling. */
722#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
723/** Bit 11 - XOP - Extended operation support (see APM6). */
724#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
725/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
726#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
727/** Bit 13 - WDT - AMD Watchdog timer support. */
728#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
729/** Bit 15 - LWP - Lightweight profiling support. */
730#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
731/** Bit 16 - FMA4 - Four operand FMA instruction support. */
732#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
733/** Bit 19 - NodeId - Indicates support for
734 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
735#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
736/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
737#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
738/** Bit 22 - TopologyExtensions - . */
739#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
740/** @} */
741
742
743/** @name CPUID AMD Feature information.
744 * CPUID query with EAX=0x80000007.
745 * @{
746 */
747/** Bit 0 - TS - Temperature Sensor. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
749/** Bit 1 - FID - Frequency ID Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
751/** Bit 2 - VID - Voltage ID Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
753/** Bit 3 - TTP - THERMTRIP. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
755/** Bit 4 - TM - Hardware Thermal Control. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
757/** Bit 5 - STC - Software Thermal Control. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
759/** Bit 6 - MC - 100 Mhz Multiplier Control. */
760#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
761/** Bit 7 - HWPSTATE - Hardware P-State Control. */
762#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
763/** Bit 8 - TSCINVAR - TSC Invariant. */
764#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
765/** Bit 9 - CPB - TSC Invariant. */
766#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
767/** Bit 10 - EffFreqRO - MPERF/APERF. */
768#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
769/** Bit 11 - PFI - Processor feedback interface (see EAX). */
770#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
771/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
772#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
773/** @} */
774
775
776/** @name CPUID AMD extended feature extensions ID (EBX).
777 * CPUID query with EAX=0x80000008.
778 * @{
779 */
780/** Bit 0 - CLZERO - Clear zero instruction. */
781#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
782/** Bit 1 - IRPerf - Instructions retired count support. */
783#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
784/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
785#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
786/* AMD pipeline length: 9 feature bits ;-) */
787/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
788#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
789/** @} */
790
791
792/** @name CPUID AMD SVM Feature information.
793 * CPUID query with EAX=0x8000000a.
794 * @{
795 */
796/** Bit 0 - NP - Nested Paging supported. */
797#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
798/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
799#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
800/** Bit 2 - SVML - SVM locking bit supported. */
801#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
802/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
803#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
804/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
805#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
806/** Bit 5 - VmcbClean - Support VMCB clean bits. */
807#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
808/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
809 * VMCB.TLB_Control is supported. */
810#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
811/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
812#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
813/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
814#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
815/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
816 * intercept filter cycle count threshold. */
817#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
818/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
819#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
820/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
821#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
822/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
823#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
824/** @} */
825
826
827/** @name CR0
828 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
829 * reserved flags.
830 * @{ */
831/** Bit 0 - PE - Protection Enabled */
832#define X86_CR0_PE RT_BIT_32(0)
833#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
834/** Bit 1 - MP - Monitor Coprocessor */
835#define X86_CR0_MP RT_BIT_32(1)
836#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
837/** Bit 2 - EM - Emulation. */
838#define X86_CR0_EM RT_BIT_32(2)
839#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
840/** Bit 3 - TS - Task Switch. */
841#define X86_CR0_TS RT_BIT_32(3)
842#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
843/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
844#define X86_CR0_ET RT_BIT_32(4)
845#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
846/** Bit 5 - NE - Numeric error (486+). */
847#define X86_CR0_NE RT_BIT_32(5)
848#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
849/** Bit 16 - WP - Write Protect (486+). */
850#define X86_CR0_WP RT_BIT_32(16)
851#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
852/** Bit 18 - AM - Alignment Mask (486+). */
853#define X86_CR0_AM RT_BIT_32(18)
854#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
855/** Bit 29 - NW - Not Write-though (486+). */
856#define X86_CR0_NW RT_BIT_32(29)
857#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
858/** Bit 30 - WP - Cache Disable (486+). */
859#define X86_CR0_CD RT_BIT_32(30)
860#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
861/** Bit 31 - PG - Paging. */
862#define X86_CR0_PG RT_BIT_32(31)
863#define X86_CR0_PAGING RT_BIT_32(31)
864#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
865/** @} */
866
867
868/** @name CR3
869 * @{ */
870/** Bit 3 - PWT - Page-level Writes Transparent. */
871#define X86_CR3_PWT RT_BIT_32(3)
872/** Bit 4 - PCD - Page-level Cache Disable. */
873#define X86_CR3_PCD RT_BIT_32(4)
874/** Bits 12-31 - - Page directory page number. */
875#define X86_CR3_PAGE_MASK (0xfffff000)
876/** Bits 5-31 - - PAE Page directory page number. */
877#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
878/** Bits 12-51 - - AMD64 Page directory page number. */
879#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
880/** @} */
881
882
883/** @name CR4
884 * @{ */
885/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
886#define X86_CR4_VME RT_BIT_32(0)
887/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
888#define X86_CR4_PVI RT_BIT_32(1)
889/** Bit 2 - TSD - Time Stamp Disable. */
890#define X86_CR4_TSD RT_BIT_32(2)
891/** Bit 3 - DE - Debugging Extensions. */
892#define X86_CR4_DE RT_BIT_32(3)
893/** Bit 4 - PSE - Page Size Extension. */
894#define X86_CR4_PSE RT_BIT_32(4)
895/** Bit 5 - PAE - Physical Address Extension. */
896#define X86_CR4_PAE RT_BIT_32(5)
897/** Bit 6 - MCE - Machine-Check Enable. */
898#define X86_CR4_MCE RT_BIT_32(6)
899/** Bit 7 - PGE - Page Global Enable. */
900#define X86_CR4_PGE RT_BIT_32(7)
901/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
902#define X86_CR4_PCE RT_BIT_32(8)
903/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
904#define X86_CR4_OSFXSR RT_BIT_32(9)
905/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
906#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
907/** Bit 13 - VMXE - VMX mode is enabled. */
908#define X86_CR4_VMXE RT_BIT_32(13)
909/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
910#define X86_CR4_SMXE RT_BIT_32(14)
911/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
912#define X86_CR4_FSGSBASE RT_BIT_32(16)
913/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
914#define X86_CR4_PCIDE RT_BIT_32(17)
915/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
916 * extended states. */
917#define X86_CR4_OSXSAVE RT_BIT_32(18)
918/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
919#define X86_CR4_SMEP RT_BIT_32(20)
920/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
921#define X86_CR4_SMAP RT_BIT_32(21)
922/** Bit 22 - PKE - Protection Key Enable. */
923#define X86_CR4_PKE RT_BIT_32(22)
924/** @} */
925
926
927/** @name DR6
928 * @{ */
929/** Bit 0 - B0 - Breakpoint 0 condition detected. */
930#define X86_DR6_B0 RT_BIT_32(0)
931/** Bit 1 - B1 - Breakpoint 1 condition detected. */
932#define X86_DR6_B1 RT_BIT_32(1)
933/** Bit 2 - B2 - Breakpoint 2 condition detected. */
934#define X86_DR6_B2 RT_BIT_32(2)
935/** Bit 3 - B3 - Breakpoint 3 condition detected. */
936#define X86_DR6_B3 RT_BIT_32(3)
937/** Mask of all the Bx bits. */
938#define X86_DR6_B_MASK UINT64_C(0x0000000f)
939/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
940#define X86_DR6_BD RT_BIT_32(13)
941/** Bit 14 - BS - Single step */
942#define X86_DR6_BS RT_BIT_32(14)
943/** Bit 15 - BT - Task switch. (TSS T bit.) */
944#define X86_DR6_BT RT_BIT_32(15)
945/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
946#define X86_DR6_RTM RT_BIT_32(16)
947/** Value of DR6 after powerup/reset. */
948#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
949/** Bits which must be 1s in DR6. */
950#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
951/** Bits which must be 1s in DR6, when RTM is supported. */
952#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
953/** Bits which must be 0s in DR6. */
954#define X86_DR6_RAZ_MASK RT_BIT_64(12)
955/** Bits which must be 0s on writes to DR6. */
956#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
957/** @} */
958
959/** Get the DR6.Bx bit for a the given breakpoint. */
960#define X86_DR6_B(iBp) RT_BIT_64(iBp)
961
962
963/** @name DR7
964 * @{ */
965/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
966#define X86_DR7_L0 RT_BIT_32(0)
967/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
968#define X86_DR7_G0 RT_BIT_32(1)
969/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
970#define X86_DR7_L1 RT_BIT_32(2)
971/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
972#define X86_DR7_G1 RT_BIT_32(3)
973/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
974#define X86_DR7_L2 RT_BIT_32(4)
975/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
976#define X86_DR7_G2 RT_BIT_32(5)
977/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
978#define X86_DR7_L3 RT_BIT_32(6)
979/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
980#define X86_DR7_G3 RT_BIT_32(7)
981/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
982#define X86_DR7_LE RT_BIT_32(8)
983/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
984#define X86_DR7_GE RT_BIT_32(9)
985
986/** L0, L1, L2, and L3. */
987#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
988/** L0, L1, L2, and L3. */
989#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
990
991/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
992 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
993#define X86_DR7_RTM RT_BIT_32(11)
994/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
995 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
996 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
997 * instruction is executed.
998 * @see http://www.rcollins.org/secrets/DR7.html */
999#define X86_DR7_ICE_IR RT_BIT_32(12)
1000/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1001 * any DR register is accessed. */
1002#define X86_DR7_GD RT_BIT_32(13)
1003/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1004 * Pentium. */
1005#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1006/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1007#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1008/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1009#define X86_DR7_RW0_MASK (3 << 16)
1010/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1011#define X86_DR7_LEN0_MASK (3 << 18)
1012/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1013#define X86_DR7_RW1_MASK (3 << 20)
1014/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1015#define X86_DR7_LEN1_MASK (3 << 22)
1016/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1017#define X86_DR7_RW2_MASK (3 << 24)
1018/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1019#define X86_DR7_LEN2_MASK (3 << 26)
1020/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1021#define X86_DR7_RW3_MASK (3 << 28)
1022/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1023#define X86_DR7_LEN3_MASK (3 << 30)
1024
1025/** Bits which reads as 1s. */
1026#define X86_DR7_RA1_MASK RT_BIT_32(10)
1027/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1028#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1029/** Bits which must be 0s when writing to DR7. */
1030#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1031
1032/** Calcs the L bit of Nth breakpoint.
1033 * @param iBp The breakpoint number [0..3].
1034 */
1035#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1036
1037/** Calcs the G bit of Nth breakpoint.
1038 * @param iBp The breakpoint number [0..3].
1039 */
1040#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1041
1042/** Calcs the L and G bits of Nth breakpoint.
1043 * @param iBp The breakpoint number [0..3].
1044 */
1045#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1046
1047/** @name Read/Write values.
1048 * @{ */
1049/** Break on instruction fetch only. */
1050#define X86_DR7_RW_EO UINT32_C(0)
1051/** Break on write only. */
1052#define X86_DR7_RW_WO UINT32_C(1)
1053/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1054#define X86_DR7_RW_IO UINT32_C(2)
1055/** Break on read or write (but not instruction fetches). */
1056#define X86_DR7_RW_RW UINT32_C(3)
1057/** @} */
1058
1059/** Shifts a X86_DR7_RW_* value to its right place.
1060 * @param iBp The breakpoint number [0..3].
1061 * @param fRw One of the X86_DR7_RW_* value.
1062 */
1063#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1064
1065/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1066 * one of the X86_DR7_RW_XXX constants).
1067 *
1068 * @returns X86_DR7_RW_XXX
1069 * @param uDR7 DR7 value
1070 * @param iBp The breakpoint number [0..3].
1071 */
1072#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1073
1074/** R/W0, R/W1, R/W2, and R/W3. */
1075#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1076
1077#ifndef VBOX_FOR_DTRACE_LIB
1078/** Checks if there are any I/O breakpoint types configured in the RW
1079 * registers. Does NOT check if these are enabled, sorry. */
1080# define X86_DR7_ANY_RW_IO(uDR7) \
1081 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1082 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1083AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1084AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1085AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1086AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1087AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1088AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1089AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1090AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1091AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1092#endif /* !VBOX_FOR_DTRACE_LIB */
1093
1094/** @name Length values.
1095 * @{ */
1096#define X86_DR7_LEN_BYTE UINT32_C(0)
1097#define X86_DR7_LEN_WORD UINT32_C(1)
1098#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1099#define X86_DR7_LEN_DWORD UINT32_C(3)
1100/** @} */
1101
1102/** Shifts a X86_DR7_LEN_* value to its right place.
1103 * @param iBp The breakpoint number [0..3].
1104 * @param cb One of the X86_DR7_LEN_* values.
1105 */
1106#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1107
1108/** Fetch the breakpoint length bits from the DR7 value.
1109 * @param uDR7 DR7 value
1110 * @param iBp The breakpoint number [0..3].
1111 */
1112#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1113
1114/** Mask used to check if any breakpoints are enabled. */
1115#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1116
1117/** LEN0, LEN1, LEN2, and LEN3. */
1118#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1119/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1120#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1121
1122/** Value of DR7 after powerup/reset. */
1123#define X86_DR7_INIT_VAL 0x400
1124/** @} */
1125
1126
1127/** @name Machine Specific Registers
1128 * @{
1129 */
1130/** Machine check address register (P5). */
1131#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1132/** Machine check type register (P5). */
1133#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1134/** Time Stamp Counter. */
1135#define MSR_IA32_TSC 0x10
1136#define MSR_IA32_CESR UINT32_C(0x00000011)
1137#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1138#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1139
1140#define MSR_IA32_PLATFORM_ID 0x17
1141
1142#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1143# define MSR_IA32_APICBASE 0x1b
1144/** Local APIC enabled. */
1145# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1146/** X2APIC enabled (requires the EN bit to be set). */
1147# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1148/** The processor is the boot strap processor (BSP). */
1149# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1150/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1151 * width. */
1152# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1153/** The default physical base address of the APIC. */
1154# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1155/** Gets the physical base address from the MSR. */
1156# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1157#endif
1158
1159/** Undocumented intel MSR for reporting thread and core counts.
1160 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1161 * first 16 bits is the thread count. The next 16 bits the core count, except
1162 * on Westmere where it seems it's only the next 4 bits for some reason. */
1163#define MSR_CORE_THREAD_COUNT 0x35
1164
1165/** CPU Feature control. */
1166#define MSR_IA32_FEATURE_CONTROL 0x3A
1167/** Feature control - Lock MSR from writes (R/W0). */
1168#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1169/** Feature control - Enable VMX inside SMX operation (R/WL). */
1170#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1171/** Feature control - Enable VMX outside SMX operation (R/WL). */
1172#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1173/** Feature control - SENTER local functions enable (R/WL). */
1174#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1175#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1176#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1177#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1178#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1179#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1180#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1181/** Feature control - SENTER global enable (R/WL). */
1182#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1183/** Feature control - SGX launch control enable (R/WL). */
1184#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1185/** Feature control - SGX global enable (R/WL). */
1186#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1187/** Feature control - LMCE on (R/WL). */
1188#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1189
1190/** Per-processor TSC adjust MSR. */
1191#define MSR_IA32_TSC_ADJUST 0x3B
1192
1193/** Spectre control register.
1194 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1195#define MSR_IA32_SPEC_CTRL 0x48
1196/** IBRS - Indirect branch restricted speculation. */
1197#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1198/** STIBP - Single thread indirect branch predictors. */
1199#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1200
1201/** Prediction command register.
1202 * Write only, logical processor scope, no state since write only. */
1203#define MSR_IA32_PRED_CMD 0x49
1204/** IBPB - Indirect branch prediction barrie when written as 1. */
1205#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1206
1207/** BIOS update trigger (microcode update). */
1208#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1209
1210/** BIOS update signature (microcode). */
1211#define MSR_IA32_BIOS_SIGN_ID 0x8B
1212
1213/** SMM monitor control. */
1214#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1215/** SMM control - Valid. */
1216#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1217/** SMM control - VMXOFF unblocks SMI. */
1218#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1219/** SMM control - MSEG base physical address. */
1220#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1221
1222/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1223#define MSR_IA32_SMBASE 0x9E
1224
1225/** General performance counter no. 0. */
1226#define MSR_IA32_PMC0 0xC1
1227/** General performance counter no. 1. */
1228#define MSR_IA32_PMC1 0xC2
1229/** General performance counter no. 2. */
1230#define MSR_IA32_PMC2 0xC3
1231/** General performance counter no. 3. */
1232#define MSR_IA32_PMC3 0xC4
1233
1234/** Nehalem power control. */
1235#define MSR_IA32_PLATFORM_INFO 0xCE
1236
1237/** Get FSB clock status (Intel-specific). */
1238#define MSR_IA32_FSB_CLOCK_STS 0xCD
1239
1240/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1241#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1242
1243/** C0 Maximum Frequency Clock Count */
1244#define MSR_IA32_MPERF 0xE7
1245/** C0 Actual Frequency Clock Count */
1246#define MSR_IA32_APERF 0xE8
1247
1248/** MTRR Capabilities. */
1249#define MSR_IA32_MTRR_CAP 0xFE
1250
1251/** Architecture capabilities (bugfixes). */
1252#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1253/** CPU is no subject to meltdown problems. */
1254#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1255/** CPU has better IBRS and you can leave it on all the time. */
1256#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1257/** CPU has return stack buffer (RSB) override. */
1258#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1259/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1260 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1261#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1262/** CPU does not suffer from MDS issues. */
1263#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1264
1265/** Flush command register. */
1266#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1267/** Flush the level 1 data cache when this bit is written. */
1268#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1269
1270/** Cache control/info. */
1271#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1272
1273#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1274/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1275 * R0 SS == CS + 8
1276 * R3 CS == CS + 16
1277 * R3 SS == CS + 24
1278 */
1279#define MSR_IA32_SYSENTER_CS 0x174
1280/** SYSENTER_ESP - the R0 ESP. */
1281#define MSR_IA32_SYSENTER_ESP 0x175
1282/** SYSENTER_EIP - the R0 EIP. */
1283#define MSR_IA32_SYSENTER_EIP 0x176
1284#endif
1285
1286/** Machine Check Global Capabilities Register. */
1287#define MSR_IA32_MCG_CAP 0x179
1288/** Machine Check Global Status Register. */
1289#define MSR_IA32_MCG_STATUS 0x17A
1290/** Machine Check Global Control Register. */
1291#define MSR_IA32_MCG_CTRL 0x17B
1292
1293/** Page Attribute Table. */
1294#define MSR_IA32_CR_PAT 0x277
1295/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1296 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1297#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1298
1299/** Performance counter MSRs. (Intel only) */
1300#define MSR_IA32_PERFEVTSEL0 0x186
1301#define MSR_IA32_PERFEVTSEL1 0x187
1302/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1303 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1304 * holds a ratio that Apple takes for TSC granularity.
1305 *
1306 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1307#define MSR_FLEX_RATIO 0x194
1308/** Performance state value and starting with Intel core more.
1309 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1310#define MSR_IA32_PERF_STATUS 0x198
1311#define MSR_IA32_PERF_CTL 0x199
1312#define MSR_IA32_THERM_STATUS 0x19c
1313
1314/** Enable misc. processor features (R/W). */
1315#define MSR_IA32_MISC_ENABLE 0x1A0
1316/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1317#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1318/** Automatic Thermal Control Circuit Enable (R/W). */
1319#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1320/** Performance Monitoring Available (R). */
1321#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1322/** Branch Trace Storage Unavailable (R/O). */
1323#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1324/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1325#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1326/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1327#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1328/** If MONITOR/MWAIT is supported (R/W). */
1329#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1330/** Limit CPUID Maxval to 3 leafs (R/W). */
1331#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1332/** When set to 1, xTPR messages are disabled (R/W). */
1333#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1334/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1335#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1336
1337/** Trace/Profile Resource Control (R/W) */
1338#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1339/** Last branch record. */
1340#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1341/** Branch trace flag (single step on branches). */
1342#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1343/** Performance monitoring pin control (AMD only). */
1344#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1345#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1346#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1347#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1348/** Trace message enable (Intel only). */
1349#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1350/** Branch trace store (Intel only). */
1351#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1352/** Branch trace interrupt (Intel only). */
1353#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1354/** Branch trace off in privileged code (Intel only). */
1355#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1356/** Branch trace off in user code (Intel only). */
1357#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1358/** Freeze LBR on PMI flag (Intel only). */
1359#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1360/** Freeze PERFMON on PMI flag (Intel only). */
1361#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1362/** Freeze while SMM enabled (Intel only). */
1363#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1364/** Advanced debugging of RTM regions (Intel only). */
1365#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1366/** Debug control MSR valid bits (Intel only). */
1367#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1368 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1369 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1370 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1371 | MSR_IA32_DEBUGCTL_RTM)
1372
1373/** The number (0..3 or 0..15) of the last branch record register on P4 and
1374 * related Xeons. */
1375#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1376/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1377 * @{ */
1378#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1379#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1380#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1381#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1382/** @} */
1383
1384
1385#define IA32_MTRR_PHYSBASE0 0x200
1386#define IA32_MTRR_PHYSMASK0 0x201
1387#define IA32_MTRR_PHYSBASE1 0x202
1388#define IA32_MTRR_PHYSMASK1 0x203
1389#define IA32_MTRR_PHYSBASE2 0x204
1390#define IA32_MTRR_PHYSMASK2 0x205
1391#define IA32_MTRR_PHYSBASE3 0x206
1392#define IA32_MTRR_PHYSMASK3 0x207
1393#define IA32_MTRR_PHYSBASE4 0x208
1394#define IA32_MTRR_PHYSMASK4 0x209
1395#define IA32_MTRR_PHYSBASE5 0x20a
1396#define IA32_MTRR_PHYSMASK5 0x20b
1397#define IA32_MTRR_PHYSBASE6 0x20c
1398#define IA32_MTRR_PHYSMASK6 0x20d
1399#define IA32_MTRR_PHYSBASE7 0x20e
1400#define IA32_MTRR_PHYSMASK7 0x20f
1401#define IA32_MTRR_PHYSBASE8 0x210
1402#define IA32_MTRR_PHYSMASK8 0x211
1403#define IA32_MTRR_PHYSBASE9 0x212
1404#define IA32_MTRR_PHYSMASK9 0x213
1405
1406/** Fixed range MTRRs.
1407 * @{ */
1408#define IA32_MTRR_FIX64K_00000 0x250
1409#define IA32_MTRR_FIX16K_80000 0x258
1410#define IA32_MTRR_FIX16K_A0000 0x259
1411#define IA32_MTRR_FIX4K_C0000 0x268
1412#define IA32_MTRR_FIX4K_C8000 0x269
1413#define IA32_MTRR_FIX4K_D0000 0x26a
1414#define IA32_MTRR_FIX4K_D8000 0x26b
1415#define IA32_MTRR_FIX4K_E0000 0x26c
1416#define IA32_MTRR_FIX4K_E8000 0x26d
1417#define IA32_MTRR_FIX4K_F0000 0x26e
1418#define IA32_MTRR_FIX4K_F8000 0x26f
1419/** @} */
1420
1421/** MTRR Default Range. */
1422#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1423
1424/** Global performance counter control facilities (Intel only). */
1425#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1426#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1427#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1428
1429/** Precise Event Based sampling (Intel only). */
1430#define MSR_IA32_PEBS_ENABLE 0x3F1
1431
1432#define MSR_IA32_MC0_CTL 0x400
1433#define MSR_IA32_MC0_STATUS 0x401
1434
1435/** Basic VMX information. */
1436#define MSR_IA32_VMX_BASIC 0x480
1437/** Allowed settings for pin-based VM execution controls. */
1438#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1439/** Allowed settings for proc-based VM execution controls. */
1440#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1441/** Allowed settings for the VM-exit controls. */
1442#define MSR_IA32_VMX_EXIT_CTLS 0x483
1443/** Allowed settings for the VM-entry controls. */
1444#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1445/** Misc VMX info. */
1446#define MSR_IA32_VMX_MISC 0x485
1447/** Fixed cleared bits in CR0. */
1448#define MSR_IA32_VMX_CR0_FIXED0 0x486
1449/** Fixed set bits in CR0. */
1450#define MSR_IA32_VMX_CR0_FIXED1 0x487
1451/** Fixed cleared bits in CR4. */
1452#define MSR_IA32_VMX_CR4_FIXED0 0x488
1453/** Fixed set bits in CR4. */
1454#define MSR_IA32_VMX_CR4_FIXED1 0x489
1455/** Information for enumerating fields in the VMCS. */
1456#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1457/** Allowed settings for secondary proc-based VM execution controls */
1458#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1459/** EPT capabilities. */
1460#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1461/** Allowed settings of all pin-based VM execution controls. */
1462#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1463/** Allowed settings of all proc-based VM execution controls. */
1464#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1465/** Allowed settings of all VMX exit controls. */
1466#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1467/** Allowed settings of all VMX entry controls. */
1468#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1469/** Allowed settings for the VM-function controls. */
1470#define MSR_IA32_VMX_VMFUNC 0x491
1471
1472/** Intel PT - Enable and control for trace packet generation. */
1473#define MSR_IA32_RTIT_CTL 0x570
1474
1475/** DS Save Area (R/W). */
1476#define MSR_IA32_DS_AREA 0x600
1477/** Running Average Power Limit (RAPL) power units. */
1478#define MSR_RAPL_POWER_UNIT 0x606
1479
1480/** X2APIC MSR range start. */
1481#define MSR_IA32_X2APIC_START 0x800
1482/** X2APIC MSR - APIC ID Register. */
1483#define MSR_IA32_X2APIC_ID 0x802
1484/** X2APIC MSR - APIC Version Register. */
1485#define MSR_IA32_X2APIC_VERSION 0x803
1486/** X2APIC MSR - Task Priority Register. */
1487#define MSR_IA32_X2APIC_TPR 0x808
1488/** X2APIC MSR - Processor Priority register. */
1489#define MSR_IA32_X2APIC_PPR 0x80A
1490/** X2APIC MSR - End Of Interrupt register. */
1491#define MSR_IA32_X2APIC_EOI 0x80B
1492/** X2APIC MSR - Logical Destination Register. */
1493#define MSR_IA32_X2APIC_LDR 0x80D
1494/** X2APIC MSR - Spurious Interrupt Vector Register. */
1495#define MSR_IA32_X2APIC_SVR 0x80F
1496/** X2APIC MSR - In-service Register (bits 31:0). */
1497#define MSR_IA32_X2APIC_ISR0 0x810
1498/** X2APIC MSR - In-service Register (bits 63:32). */
1499#define MSR_IA32_X2APIC_ISR1 0x811
1500/** X2APIC MSR - In-service Register (bits 95:64). */
1501#define MSR_IA32_X2APIC_ISR2 0x812
1502/** X2APIC MSR - In-service Register (bits 127:96). */
1503#define MSR_IA32_X2APIC_ISR3 0x813
1504/** X2APIC MSR - In-service Register (bits 159:128). */
1505#define MSR_IA32_X2APIC_ISR4 0x814
1506/** X2APIC MSR - In-service Register (bits 191:160). */
1507#define MSR_IA32_X2APIC_ISR5 0x815
1508/** X2APIC MSR - In-service Register (bits 223:192). */
1509#define MSR_IA32_X2APIC_ISR6 0x816
1510/** X2APIC MSR - In-service Register (bits 255:224). */
1511#define MSR_IA32_X2APIC_ISR7 0x817
1512/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1513#define MSR_IA32_X2APIC_TMR0 0x818
1514/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1515#define MSR_IA32_X2APIC_TMR1 0x819
1516/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1517#define MSR_IA32_X2APIC_TMR2 0x81A
1518/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1519#define MSR_IA32_X2APIC_TMR3 0x81B
1520/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1521#define MSR_IA32_X2APIC_TMR4 0x81C
1522/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1523#define MSR_IA32_X2APIC_TMR5 0x81D
1524/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1525#define MSR_IA32_X2APIC_TMR6 0x81E
1526/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1527#define MSR_IA32_X2APIC_TMR7 0x81F
1528/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1529#define MSR_IA32_X2APIC_IRR0 0x820
1530/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1531#define MSR_IA32_X2APIC_IRR1 0x821
1532/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1533#define MSR_IA32_X2APIC_IRR2 0x822
1534/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1535#define MSR_IA32_X2APIC_IRR3 0x823
1536/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1537#define MSR_IA32_X2APIC_IRR4 0x824
1538/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1539#define MSR_IA32_X2APIC_IRR5 0x825
1540/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1541#define MSR_IA32_X2APIC_IRR6 0x826
1542/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1543#define MSR_IA32_X2APIC_IRR7 0x827
1544/** X2APIC MSR - Error Status Register. */
1545#define MSR_IA32_X2APIC_ESR 0x828
1546/** X2APIC MSR - LVT CMCI Register. */
1547#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1548/** X2APIC MSR - Interrupt Command Register. */
1549#define MSR_IA32_X2APIC_ICR 0x830
1550/** X2APIC MSR - LVT Timer Register. */
1551#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1552/** X2APIC MSR - LVT Thermal Sensor Register. */
1553#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1554/** X2APIC MSR - LVT Performance Counter Register. */
1555#define MSR_IA32_X2APIC_LVT_PERF 0x834
1556/** X2APIC MSR - LVT LINT0 Register. */
1557#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1558/** X2APIC MSR - LVT LINT1 Register. */
1559#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1560/** X2APIC MSR - LVT Error Register . */
1561#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1562/** X2APIC MSR - Timer Initial Count Register. */
1563#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1564/** X2APIC MSR - Timer Current Count Register. */
1565#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1566/** X2APIC MSR - Timer Divide Configuration Register. */
1567#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1568/** X2APIC MSR - Self IPI. */
1569#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1570/** X2APIC MSR range end. */
1571#define MSR_IA32_X2APIC_END 0xBFF
1572/** X2APIC MSR - LVT start range. */
1573#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1574/** X2APIC MSR - LVT end range (inclusive). */
1575#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1576
1577/** K6 EFER - Extended Feature Enable Register. */
1578#define MSR_K6_EFER UINT32_C(0xc0000080)
1579/** @todo document EFER */
1580/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1581#define MSR_K6_EFER_SCE RT_BIT_32(0)
1582/** Bit 8 - LME - Long mode enabled. (R/W) */
1583#define MSR_K6_EFER_LME RT_BIT_32(8)
1584#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1585/** Bit 10 - LMA - Long mode active. (R) */
1586#define MSR_K6_EFER_LMA RT_BIT_32(10)
1587#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1588/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1589#define MSR_K6_EFER_NXE RT_BIT_32(11)
1590#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1591/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1592#define MSR_K6_EFER_SVME RT_BIT_32(12)
1593/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1594#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1595/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1596#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1597/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1598#define MSR_K6_EFER_TCE RT_BIT_32(15)
1599/** K6 STAR - SYSCALL/RET targets. */
1600#define MSR_K6_STAR UINT32_C(0xc0000081)
1601/** Shift value for getting the SYSRET CS and SS value. */
1602#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1603/** Shift value for getting the SYSCALL CS and SS value. */
1604#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1605/** Selector mask for use after shifting. */
1606#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1607/** The mask which give the SYSCALL EIP. */
1608#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1609/** K6 WHCR - Write Handling Control Register. */
1610#define MSR_K6_WHCR UINT32_C(0xc0000082)
1611/** K6 UWCCR - UC/WC Cacheability Control Register. */
1612#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1613/** K6 PSOR - Processor State Observability Register. */
1614#define MSR_K6_PSOR UINT32_C(0xc0000087)
1615/** K6 PFIR - Page Flush/Invalidate Register. */
1616#define MSR_K6_PFIR UINT32_C(0xc0000088)
1617
1618/** Performance counter MSRs. (AMD only) */
1619#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1620#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1621#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1622#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1623#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1624#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1625#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1626#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1627
1628/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1629#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1630/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1631#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1632/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1633#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1634/** K8 FS.base - The 64-bit base FS register. */
1635#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1636/** K8 GS.base - The 64-bit base GS register. */
1637#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1638/** K8 KernelGSbase - Used with SWAPGS. */
1639#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1640/** K8 TSC_AUX - Used with RDTSCP. */
1641#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1642#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1643#define MSR_K8_HWCR UINT32_C(0xc0010015)
1644#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1645#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1646#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1647#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1648#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1649#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1650/** North bridge config? See BIOS & Kernel dev guides for
1651 * details. */
1652#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1653
1654/** Hypertransport interrupt pending register.
1655 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1656#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1657
1658/** SVM Control. */
1659#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1660/** Disables HDT (Hardware Debug Tool) and certain internal debug
1661 * features. */
1662#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1663/** If set, non-intercepted INIT signals are converted to \#SX
1664 * exceptions. */
1665#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1666/** Disables A20 masking. */
1667#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1668/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1669#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1670/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1671 * clear, EFER.SVME can be written normally. */
1672#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1673
1674#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1675#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1676/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1677 * host state during world switch. */
1678#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1679
1680/** @} */
1681
1682
1683/** @name Page Table / Directory / Directory Pointers / L4.
1684 * @{
1685 */
1686
1687/** Page table/directory entry as an unsigned integer. */
1688typedef uint32_t X86PGUINT;
1689/** Pointer to a page table/directory table entry as an unsigned integer. */
1690typedef X86PGUINT *PX86PGUINT;
1691/** Pointer to an const page table/directory table entry as an unsigned integer. */
1692typedef X86PGUINT const *PCX86PGUINT;
1693
1694/** Number of entries in a 32-bit PT/PD. */
1695#define X86_PG_ENTRIES 1024
1696
1697
1698/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1699typedef uint64_t X86PGPAEUINT;
1700/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1701typedef X86PGPAEUINT *PX86PGPAEUINT;
1702/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1703typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1704
1705/** Number of entries in a PAE PT/PD. */
1706#define X86_PG_PAE_ENTRIES 512
1707/** Number of entries in a PAE PDPT. */
1708#define X86_PG_PAE_PDPE_ENTRIES 4
1709
1710/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1711#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1712/** Number of entries in an AMD64 PDPT.
1713 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1714#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1715
1716/** The size of a default page. */
1717#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1718/** The page shift of a default page. */
1719#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1720/** The default page offset mask. */
1721#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1722/** The default page base mask for virtual addresses. */
1723#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1724/** The default page base mask for virtual addresses - 32bit version. */
1725#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1726
1727/** The size of a 4KB page. */
1728#define X86_PAGE_4K_SIZE _4K
1729/** The page shift of a 4KB page. */
1730#define X86_PAGE_4K_SHIFT 12
1731/** The 4KB page offset mask. */
1732#define X86_PAGE_4K_OFFSET_MASK 0xfff
1733/** The 4KB page base mask for virtual addresses. */
1734#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1735/** The 4KB page base mask for virtual addresses - 32bit version. */
1736#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1737
1738/** The size of a 2MB page. */
1739#define X86_PAGE_2M_SIZE _2M
1740/** The page shift of a 2MB page. */
1741#define X86_PAGE_2M_SHIFT 21
1742/** The 2MB page offset mask. */
1743#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1744/** The 2MB page base mask for virtual addresses. */
1745#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1746/** The 2MB page base mask for virtual addresses - 32bit version. */
1747#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1748
1749/** The size of a 4MB page. */
1750#define X86_PAGE_4M_SIZE _4M
1751/** The page shift of a 4MB page. */
1752#define X86_PAGE_4M_SHIFT 22
1753/** The 4MB page offset mask. */
1754#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1755/** The 4MB page base mask for virtual addresses. */
1756#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1757/** The 4MB page base mask for virtual addresses - 32bit version. */
1758#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1759
1760/** The size of a 1GB page. */
1761#define X86_PAGE_1G_SIZE _1G
1762/** The page shift of a 1GB page. */
1763#define X86_PAGE_1G_SHIFT 30
1764/** The 1GB page offset mask. */
1765#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1766/** The 1GB page base mask for virtual addresses. */
1767#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1768
1769/**
1770 * Check if the given address is canonical.
1771 */
1772#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1773
1774
1775/** @name Page Table Entry
1776 * @{
1777 */
1778/** Bit 0 - P - Present bit. */
1779#define X86_PTE_BIT_P 0
1780/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1781#define X86_PTE_BIT_RW 1
1782/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1783#define X86_PTE_BIT_US 2
1784/** Bit 3 - PWT - Page level write thru bit. */
1785#define X86_PTE_BIT_PWT 3
1786/** Bit 4 - PCD - Page level cache disable bit. */
1787#define X86_PTE_BIT_PCD 4
1788/** Bit 5 - A - Access bit. */
1789#define X86_PTE_BIT_A 5
1790/** Bit 6 - D - Dirty bit. */
1791#define X86_PTE_BIT_D 6
1792/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1793#define X86_PTE_BIT_PAT 7
1794/** Bit 8 - G - Global flag. */
1795#define X86_PTE_BIT_G 8
1796/** Bits 63 - NX - PAE/LM - No execution flag. */
1797#define X86_PTE_PAE_BIT_NX 63
1798
1799/** Bit 0 - P - Present bit mask. */
1800#define X86_PTE_P RT_BIT_32(0)
1801/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1802#define X86_PTE_RW RT_BIT_32(1)
1803/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1804#define X86_PTE_US RT_BIT_32(2)
1805/** Bit 3 - PWT - Page level write thru bit mask. */
1806#define X86_PTE_PWT RT_BIT_32(3)
1807/** Bit 4 - PCD - Page level cache disable bit mask. */
1808#define X86_PTE_PCD RT_BIT_32(4)
1809/** Bit 5 - A - Access bit mask. */
1810#define X86_PTE_A RT_BIT_32(5)
1811/** Bit 6 - D - Dirty bit mask. */
1812#define X86_PTE_D RT_BIT_32(6)
1813/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1814#define X86_PTE_PAT RT_BIT_32(7)
1815/** Bit 8 - G - Global bit mask. */
1816#define X86_PTE_G RT_BIT_32(8)
1817
1818/** Bits 9-11 - - Available for use to system software. */
1819#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1820/** Bits 12-31 - - Physical Page number of the next level. */
1821#define X86_PTE_PG_MASK ( 0xfffff000 )
1822
1823/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1824#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1825/** Bits 63 - NX - PAE/LM - No execution flag. */
1826#define X86_PTE_PAE_NX RT_BIT_64(63)
1827/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1828#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1829/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1830#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1831/** No bits - - LM - MBZ bits when NX is active. */
1832#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1833/** Bits 63 - - LM - MBZ bits when no NX. */
1834#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1835
1836/**
1837 * Page table entry.
1838 */
1839typedef struct X86PTEBITS
1840{
1841 /** Flags whether(=1) or not the page is present. */
1842 uint32_t u1Present : 1;
1843 /** Read(=0) / Write(=1) flag. */
1844 uint32_t u1Write : 1;
1845 /** User(=1) / Supervisor (=0) flag. */
1846 uint32_t u1User : 1;
1847 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1848 uint32_t u1WriteThru : 1;
1849 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1850 uint32_t u1CacheDisable : 1;
1851 /** Accessed flag.
1852 * Indicates that the page have been read or written to. */
1853 uint32_t u1Accessed : 1;
1854 /** Dirty flag.
1855 * Indicates that the page has been written to. */
1856 uint32_t u1Dirty : 1;
1857 /** Reserved / If PAT enabled, bit 2 of the index. */
1858 uint32_t u1PAT : 1;
1859 /** Global flag. (Ignored in all but final level.) */
1860 uint32_t u1Global : 1;
1861 /** Available for use to system software. */
1862 uint32_t u3Available : 3;
1863 /** Physical Page number of the next level. */
1864 uint32_t u20PageNo : 20;
1865} X86PTEBITS;
1866#ifndef VBOX_FOR_DTRACE_LIB
1867AssertCompileSize(X86PTEBITS, 4);
1868#endif
1869/** Pointer to a page table entry. */
1870typedef X86PTEBITS *PX86PTEBITS;
1871/** Pointer to a const page table entry. */
1872typedef const X86PTEBITS *PCX86PTEBITS;
1873
1874/**
1875 * Page table entry.
1876 */
1877typedef union X86PTE
1878{
1879 /** Unsigned integer view */
1880 X86PGUINT u;
1881 /** Bit field view. */
1882 X86PTEBITS n;
1883 /** 32-bit view. */
1884 uint32_t au32[1];
1885 /** 16-bit view. */
1886 uint16_t au16[2];
1887 /** 8-bit view. */
1888 uint8_t au8[4];
1889} X86PTE;
1890#ifndef VBOX_FOR_DTRACE_LIB
1891AssertCompileSize(X86PTE, 4);
1892#endif
1893/** Pointer to a page table entry. */
1894typedef X86PTE *PX86PTE;
1895/** Pointer to a const page table entry. */
1896typedef const X86PTE *PCX86PTE;
1897
1898
1899/**
1900 * PAE page table entry.
1901 */
1902typedef struct X86PTEPAEBITS
1903{
1904 /** Flags whether(=1) or not the page is present. */
1905 uint32_t u1Present : 1;
1906 /** Read(=0) / Write(=1) flag. */
1907 uint32_t u1Write : 1;
1908 /** User(=1) / Supervisor(=0) flag. */
1909 uint32_t u1User : 1;
1910 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1911 uint32_t u1WriteThru : 1;
1912 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1913 uint32_t u1CacheDisable : 1;
1914 /** Accessed flag.
1915 * Indicates that the page have been read or written to. */
1916 uint32_t u1Accessed : 1;
1917 /** Dirty flag.
1918 * Indicates that the page has been written to. */
1919 uint32_t u1Dirty : 1;
1920 /** Reserved / If PAT enabled, bit 2 of the index. */
1921 uint32_t u1PAT : 1;
1922 /** Global flag. (Ignored in all but final level.) */
1923 uint32_t u1Global : 1;
1924 /** Available for use to system software. */
1925 uint32_t u3Available : 3;
1926 /** Physical Page number of the next level - Low Part. Don't use this. */
1927 uint32_t u20PageNoLow : 20;
1928 /** Physical Page number of the next level - High Part. Don't use this. */
1929 uint32_t u20PageNoHigh : 20;
1930 /** MBZ bits */
1931 uint32_t u11Reserved : 11;
1932 /** No Execute flag. */
1933 uint32_t u1NoExecute : 1;
1934} X86PTEPAEBITS;
1935#ifndef VBOX_FOR_DTRACE_LIB
1936AssertCompileSize(X86PTEPAEBITS, 8);
1937#endif
1938/** Pointer to a page table entry. */
1939typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1940/** Pointer to a page table entry. */
1941typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1942
1943/**
1944 * PAE Page table entry.
1945 */
1946typedef union X86PTEPAE
1947{
1948 /** Unsigned integer view */
1949 X86PGPAEUINT u;
1950 /** Bit field view. */
1951 X86PTEPAEBITS n;
1952 /** 32-bit view. */
1953 uint32_t au32[2];
1954 /** 16-bit view. */
1955 uint16_t au16[4];
1956 /** 8-bit view. */
1957 uint8_t au8[8];
1958} X86PTEPAE;
1959#ifndef VBOX_FOR_DTRACE_LIB
1960AssertCompileSize(X86PTEPAE, 8);
1961#endif
1962/** Pointer to a PAE page table entry. */
1963typedef X86PTEPAE *PX86PTEPAE;
1964/** Pointer to a const PAE page table entry. */
1965typedef const X86PTEPAE *PCX86PTEPAE;
1966/** @} */
1967
1968/**
1969 * Page table.
1970 */
1971typedef struct X86PT
1972{
1973 /** PTE Array. */
1974 X86PTE a[X86_PG_ENTRIES];
1975} X86PT;
1976#ifndef VBOX_FOR_DTRACE_LIB
1977AssertCompileSize(X86PT, 4096);
1978#endif
1979/** Pointer to a page table. */
1980typedef X86PT *PX86PT;
1981/** Pointer to a const page table. */
1982typedef const X86PT *PCX86PT;
1983
1984/** The page shift to get the PT index. */
1985#define X86_PT_SHIFT 12
1986/** The PT index mask (apply to a shifted page address). */
1987#define X86_PT_MASK 0x3ff
1988
1989
1990/**
1991 * Page directory.
1992 */
1993typedef struct X86PTPAE
1994{
1995 /** PTE Array. */
1996 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1997} X86PTPAE;
1998#ifndef VBOX_FOR_DTRACE_LIB
1999AssertCompileSize(X86PTPAE, 4096);
2000#endif
2001/** Pointer to a page table. */
2002typedef X86PTPAE *PX86PTPAE;
2003/** Pointer to a const page table. */
2004typedef const X86PTPAE *PCX86PTPAE;
2005
2006/** The page shift to get the PA PTE index. */
2007#define X86_PT_PAE_SHIFT 12
2008/** The PAE PT index mask (apply to a shifted page address). */
2009#define X86_PT_PAE_MASK 0x1ff
2010
2011
2012/** @name 4KB Page Directory Entry
2013 * @{
2014 */
2015/** Bit 0 - P - Present bit. */
2016#define X86_PDE_P RT_BIT_32(0)
2017/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2018#define X86_PDE_RW RT_BIT_32(1)
2019/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2020#define X86_PDE_US RT_BIT_32(2)
2021/** Bit 3 - PWT - Page level write thru bit. */
2022#define X86_PDE_PWT RT_BIT_32(3)
2023/** Bit 4 - PCD - Page level cache disable bit. */
2024#define X86_PDE_PCD RT_BIT_32(4)
2025/** Bit 5 - A - Access bit. */
2026#define X86_PDE_A RT_BIT_32(5)
2027/** Bit 7 - PS - Page size attribute.
2028 * Clear mean 4KB pages, set means large pages (2/4MB). */
2029#define X86_PDE_PS RT_BIT_32(7)
2030/** Bits 9-11 - - Available for use to system software. */
2031#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2032/** Bits 12-31 - - Physical Page number of the next level. */
2033#define X86_PDE_PG_MASK ( 0xfffff000 )
2034
2035/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2036#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2037/** Bits 63 - NX - PAE/LM - No execution flag. */
2038#define X86_PDE_PAE_NX RT_BIT_64(63)
2039/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2040#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2041/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2042#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2043/** Bit 7 - - LM - MBZ bits when NX is active. */
2044#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2045/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2046#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2047
2048/**
2049 * Page directory entry.
2050 */
2051typedef struct X86PDEBITS
2052{
2053 /** Flags whether(=1) or not the page is present. */
2054 uint32_t u1Present : 1;
2055 /** Read(=0) / Write(=1) flag. */
2056 uint32_t u1Write : 1;
2057 /** User(=1) / Supervisor (=0) flag. */
2058 uint32_t u1User : 1;
2059 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2060 uint32_t u1WriteThru : 1;
2061 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2062 uint32_t u1CacheDisable : 1;
2063 /** Accessed flag.
2064 * Indicates that the page has been read or written to. */
2065 uint32_t u1Accessed : 1;
2066 /** Reserved / Ignored (dirty bit). */
2067 uint32_t u1Reserved0 : 1;
2068 /** Size bit if PSE is enabled - in any event it's 0. */
2069 uint32_t u1Size : 1;
2070 /** Reserved / Ignored (global bit). */
2071 uint32_t u1Reserved1 : 1;
2072 /** Available for use to system software. */
2073 uint32_t u3Available : 3;
2074 /** Physical Page number of the next level. */
2075 uint32_t u20PageNo : 20;
2076} X86PDEBITS;
2077#ifndef VBOX_FOR_DTRACE_LIB
2078AssertCompileSize(X86PDEBITS, 4);
2079#endif
2080/** Pointer to a page directory entry. */
2081typedef X86PDEBITS *PX86PDEBITS;
2082/** Pointer to a const page directory entry. */
2083typedef const X86PDEBITS *PCX86PDEBITS;
2084
2085
2086/**
2087 * PAE page directory entry.
2088 */
2089typedef struct X86PDEPAEBITS
2090{
2091 /** Flags whether(=1) or not the page is present. */
2092 uint32_t u1Present : 1;
2093 /** Read(=0) / Write(=1) flag. */
2094 uint32_t u1Write : 1;
2095 /** User(=1) / Supervisor (=0) flag. */
2096 uint32_t u1User : 1;
2097 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2098 uint32_t u1WriteThru : 1;
2099 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2100 uint32_t u1CacheDisable : 1;
2101 /** Accessed flag.
2102 * Indicates that the page has been read or written to. */
2103 uint32_t u1Accessed : 1;
2104 /** Reserved / Ignored (dirty bit). */
2105 uint32_t u1Reserved0 : 1;
2106 /** Size bit if PSE is enabled - in any event it's 0. */
2107 uint32_t u1Size : 1;
2108 /** Reserved / Ignored (global bit). / */
2109 uint32_t u1Reserved1 : 1;
2110 /** Available for use to system software. */
2111 uint32_t u3Available : 3;
2112 /** Physical Page number of the next level - Low Part. Don't use! */
2113 uint32_t u20PageNoLow : 20;
2114 /** Physical Page number of the next level - High Part. Don't use! */
2115 uint32_t u20PageNoHigh : 20;
2116 /** MBZ bits */
2117 uint32_t u11Reserved : 11;
2118 /** No Execute flag. */
2119 uint32_t u1NoExecute : 1;
2120} X86PDEPAEBITS;
2121#ifndef VBOX_FOR_DTRACE_LIB
2122AssertCompileSize(X86PDEPAEBITS, 8);
2123#endif
2124/** Pointer to a page directory entry. */
2125typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2126/** Pointer to a const page directory entry. */
2127typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2128
2129/** @} */
2130
2131
2132/** @name 2/4MB Page Directory Entry
2133 * @{
2134 */
2135/** Bit 0 - P - Present bit. */
2136#define X86_PDE4M_P RT_BIT_32(0)
2137/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2138#define X86_PDE4M_RW RT_BIT_32(1)
2139/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2140#define X86_PDE4M_US RT_BIT_32(2)
2141/** Bit 3 - PWT - Page level write thru bit. */
2142#define X86_PDE4M_PWT RT_BIT_32(3)
2143/** Bit 4 - PCD - Page level cache disable bit. */
2144#define X86_PDE4M_PCD RT_BIT_32(4)
2145/** Bit 5 - A - Access bit. */
2146#define X86_PDE4M_A RT_BIT_32(5)
2147/** Bit 6 - D - Dirty bit. */
2148#define X86_PDE4M_D RT_BIT_32(6)
2149/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2150#define X86_PDE4M_PS RT_BIT_32(7)
2151/** Bit 8 - G - Global flag. */
2152#define X86_PDE4M_G RT_BIT_32(8)
2153/** Bits 9-11 - AVL - Available for use to system software. */
2154#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2155/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2156#define X86_PDE4M_PAT RT_BIT_32(12)
2157/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2158#define X86_PDE4M_PAT_SHIFT (12 - 7)
2159/** Bits 22-31 - - Physical Page number. */
2160#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2161/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2162#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2163/** The number of bits to the high part of the page number. */
2164#define X86_PDE4M_PG_HIGH_SHIFT 19
2165/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2166#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2167
2168/** Bits 21-51 - - PAE/LM - Physical Page number.
2169 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2170#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2171/** Bits 63 - NX - PAE/LM - No execution flag. */
2172#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2173/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2174#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2175/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2176#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2177/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2178#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2179/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2180#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2181
2182/**
2183 * 4MB page directory entry.
2184 */
2185typedef struct X86PDE4MBITS
2186{
2187 /** Flags whether(=1) or not the page is present. */
2188 uint32_t u1Present : 1;
2189 /** Read(=0) / Write(=1) flag. */
2190 uint32_t u1Write : 1;
2191 /** User(=1) / Supervisor (=0) flag. */
2192 uint32_t u1User : 1;
2193 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2194 uint32_t u1WriteThru : 1;
2195 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2196 uint32_t u1CacheDisable : 1;
2197 /** Accessed flag.
2198 * Indicates that the page have been read or written to. */
2199 uint32_t u1Accessed : 1;
2200 /** Dirty flag.
2201 * Indicates that the page has been written to. */
2202 uint32_t u1Dirty : 1;
2203 /** Page size flag - always 1 for 4MB entries. */
2204 uint32_t u1Size : 1;
2205 /** Global flag. */
2206 uint32_t u1Global : 1;
2207 /** Available for use to system software. */
2208 uint32_t u3Available : 3;
2209 /** Reserved / If PAT enabled, bit 2 of the index. */
2210 uint32_t u1PAT : 1;
2211 /** Bits 32-39 of the page number on AMD64.
2212 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2213 uint32_t u8PageNoHigh : 8;
2214 /** Reserved. */
2215 uint32_t u1Reserved : 1;
2216 /** Physical Page number of the page. */
2217 uint32_t u10PageNo : 10;
2218} X86PDE4MBITS;
2219#ifndef VBOX_FOR_DTRACE_LIB
2220AssertCompileSize(X86PDE4MBITS, 4);
2221#endif
2222/** Pointer to a page table entry. */
2223typedef X86PDE4MBITS *PX86PDE4MBITS;
2224/** Pointer to a const page table entry. */
2225typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2226
2227
2228/**
2229 * 2MB PAE page directory entry.
2230 */
2231typedef struct X86PDE2MPAEBITS
2232{
2233 /** Flags whether(=1) or not the page is present. */
2234 uint32_t u1Present : 1;
2235 /** Read(=0) / Write(=1) flag. */
2236 uint32_t u1Write : 1;
2237 /** User(=1) / Supervisor(=0) flag. */
2238 uint32_t u1User : 1;
2239 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2240 uint32_t u1WriteThru : 1;
2241 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2242 uint32_t u1CacheDisable : 1;
2243 /** Accessed flag.
2244 * Indicates that the page have been read or written to. */
2245 uint32_t u1Accessed : 1;
2246 /** Dirty flag.
2247 * Indicates that the page has been written to. */
2248 uint32_t u1Dirty : 1;
2249 /** Page size flag - always 1 for 2MB entries. */
2250 uint32_t u1Size : 1;
2251 /** Global flag. */
2252 uint32_t u1Global : 1;
2253 /** Available for use to system software. */
2254 uint32_t u3Available : 3;
2255 /** Reserved / If PAT enabled, bit 2 of the index. */
2256 uint32_t u1PAT : 1;
2257 /** Reserved. */
2258 uint32_t u9Reserved : 9;
2259 /** Physical Page number of the next level - Low part. Don't use! */
2260 uint32_t u10PageNoLow : 10;
2261 /** Physical Page number of the next level - High part. Don't use! */
2262 uint32_t u20PageNoHigh : 20;
2263 /** MBZ bits */
2264 uint32_t u11Reserved : 11;
2265 /** No Execute flag. */
2266 uint32_t u1NoExecute : 1;
2267} X86PDE2MPAEBITS;
2268#ifndef VBOX_FOR_DTRACE_LIB
2269AssertCompileSize(X86PDE2MPAEBITS, 8);
2270#endif
2271/** Pointer to a 2MB PAE page table entry. */
2272typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2273/** Pointer to a 2MB PAE page table entry. */
2274typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2275
2276/** @} */
2277
2278/**
2279 * Page directory entry.
2280 */
2281typedef union X86PDE
2282{
2283 /** Unsigned integer view. */
2284 X86PGUINT u;
2285 /** Normal view. */
2286 X86PDEBITS n;
2287 /** 4MB view (big). */
2288 X86PDE4MBITS b;
2289 /** 8 bit unsigned integer view. */
2290 uint8_t au8[4];
2291 /** 16 bit unsigned integer view. */
2292 uint16_t au16[2];
2293 /** 32 bit unsigned integer view. */
2294 uint32_t au32[1];
2295} X86PDE;
2296#ifndef VBOX_FOR_DTRACE_LIB
2297AssertCompileSize(X86PDE, 4);
2298#endif
2299/** Pointer to a page directory entry. */
2300typedef X86PDE *PX86PDE;
2301/** Pointer to a const page directory entry. */
2302typedef const X86PDE *PCX86PDE;
2303
2304/**
2305 * PAE page directory entry.
2306 */
2307typedef union X86PDEPAE
2308{
2309 /** Unsigned integer view. */
2310 X86PGPAEUINT u;
2311 /** Normal view. */
2312 X86PDEPAEBITS n;
2313 /** 2MB page view (big). */
2314 X86PDE2MPAEBITS b;
2315 /** 8 bit unsigned integer view. */
2316 uint8_t au8[8];
2317 /** 16 bit unsigned integer view. */
2318 uint16_t au16[4];
2319 /** 32 bit unsigned integer view. */
2320 uint32_t au32[2];
2321} X86PDEPAE;
2322#ifndef VBOX_FOR_DTRACE_LIB
2323AssertCompileSize(X86PDEPAE, 8);
2324#endif
2325/** Pointer to a page directory entry. */
2326typedef X86PDEPAE *PX86PDEPAE;
2327/** Pointer to a const page directory entry. */
2328typedef const X86PDEPAE *PCX86PDEPAE;
2329
2330/**
2331 * Page directory.
2332 */
2333typedef struct X86PD
2334{
2335 /** PDE Array. */
2336 X86PDE a[X86_PG_ENTRIES];
2337} X86PD;
2338#ifndef VBOX_FOR_DTRACE_LIB
2339AssertCompileSize(X86PD, 4096);
2340#endif
2341/** Pointer to a page directory. */
2342typedef X86PD *PX86PD;
2343/** Pointer to a const page directory. */
2344typedef const X86PD *PCX86PD;
2345
2346/** The page shift to get the PD index. */
2347#define X86_PD_SHIFT 22
2348/** The PD index mask (apply to a shifted page address). */
2349#define X86_PD_MASK 0x3ff
2350
2351
2352/**
2353 * PAE page directory.
2354 */
2355typedef struct X86PDPAE
2356{
2357 /** PDE Array. */
2358 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2359} X86PDPAE;
2360#ifndef VBOX_FOR_DTRACE_LIB
2361AssertCompileSize(X86PDPAE, 4096);
2362#endif
2363/** Pointer to a PAE page directory. */
2364typedef X86PDPAE *PX86PDPAE;
2365/** Pointer to a const PAE page directory. */
2366typedef const X86PDPAE *PCX86PDPAE;
2367
2368/** The page shift to get the PAE PD index. */
2369#define X86_PD_PAE_SHIFT 21
2370/** The PAE PD index mask (apply to a shifted page address). */
2371#define X86_PD_PAE_MASK 0x1ff
2372
2373
2374/** @name Page Directory Pointer Table Entry (PAE)
2375 * @{
2376 */
2377/** Bit 0 - P - Present bit. */
2378#define X86_PDPE_P RT_BIT_32(0)
2379/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2380#define X86_PDPE_RW RT_BIT_32(1)
2381/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2382#define X86_PDPE_US RT_BIT_32(2)
2383/** Bit 3 - PWT - Page level write thru bit. */
2384#define X86_PDPE_PWT RT_BIT_32(3)
2385/** Bit 4 - PCD - Page level cache disable bit. */
2386#define X86_PDPE_PCD RT_BIT_32(4)
2387/** Bit 5 - A - Access bit. Long Mode only. */
2388#define X86_PDPE_A RT_BIT_32(5)
2389/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2390#define X86_PDPE_LM_PS RT_BIT_32(7)
2391/** Bits 9-11 - - Available for use to system software. */
2392#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2393/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2394#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2395/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2396#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2397/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2398#define X86_PDPE_LM_NX RT_BIT_64(63)
2399/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2400#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2401/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2402#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2403/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2404#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2405/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2406#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2407
2408
2409/**
2410 * Page directory pointer table entry.
2411 */
2412typedef struct X86PDPEBITS
2413{
2414 /** Flags whether(=1) or not the page is present. */
2415 uint32_t u1Present : 1;
2416 /** Chunk of reserved bits. */
2417 uint32_t u2Reserved : 2;
2418 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2419 uint32_t u1WriteThru : 1;
2420 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2421 uint32_t u1CacheDisable : 1;
2422 /** Chunk of reserved bits. */
2423 uint32_t u4Reserved : 4;
2424 /** Available for use to system software. */
2425 uint32_t u3Available : 3;
2426 /** Physical Page number of the next level - Low Part. Don't use! */
2427 uint32_t u20PageNoLow : 20;
2428 /** Physical Page number of the next level - High Part. Don't use! */
2429 uint32_t u20PageNoHigh : 20;
2430 /** MBZ bits */
2431 uint32_t u12Reserved : 12;
2432} X86PDPEBITS;
2433#ifndef VBOX_FOR_DTRACE_LIB
2434AssertCompileSize(X86PDPEBITS, 8);
2435#endif
2436/** Pointer to a page directory pointer table entry. */
2437typedef X86PDPEBITS *PX86PTPEBITS;
2438/** Pointer to a const page directory pointer table entry. */
2439typedef const X86PDPEBITS *PCX86PTPEBITS;
2440
2441/**
2442 * Page directory pointer table entry. AMD64 version
2443 */
2444typedef struct X86PDPEAMD64BITS
2445{
2446 /** Flags whether(=1) or not the page is present. */
2447 uint32_t u1Present : 1;
2448 /** Read(=0) / Write(=1) flag. */
2449 uint32_t u1Write : 1;
2450 /** User(=1) / Supervisor (=0) flag. */
2451 uint32_t u1User : 1;
2452 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2453 uint32_t u1WriteThru : 1;
2454 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2455 uint32_t u1CacheDisable : 1;
2456 /** Accessed flag.
2457 * Indicates that the page have been read or written to. */
2458 uint32_t u1Accessed : 1;
2459 /** Chunk of reserved bits. */
2460 uint32_t u3Reserved : 3;
2461 /** Available for use to system software. */
2462 uint32_t u3Available : 3;
2463 /** Physical Page number of the next level - Low Part. Don't use! */
2464 uint32_t u20PageNoLow : 20;
2465 /** Physical Page number of the next level - High Part. Don't use! */
2466 uint32_t u20PageNoHigh : 20;
2467 /** MBZ bits */
2468 uint32_t u11Reserved : 11;
2469 /** No Execute flag. */
2470 uint32_t u1NoExecute : 1;
2471} X86PDPEAMD64BITS;
2472#ifndef VBOX_FOR_DTRACE_LIB
2473AssertCompileSize(X86PDPEAMD64BITS, 8);
2474#endif
2475/** Pointer to a page directory pointer table entry. */
2476typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2477/** Pointer to a const page directory pointer table entry. */
2478typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2479
2480/**
2481 * Page directory pointer table entry for 1GB page. (AMD64 only)
2482 */
2483typedef struct X86PDPE1GB
2484{
2485 /** 0: Flags whether(=1) or not the page is present. */
2486 uint32_t u1Present : 1;
2487 /** 1: Read(=0) / Write(=1) flag. */
2488 uint32_t u1Write : 1;
2489 /** 2: User(=1) / Supervisor (=0) flag. */
2490 uint32_t u1User : 1;
2491 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2492 uint32_t u1WriteThru : 1;
2493 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2494 uint32_t u1CacheDisable : 1;
2495 /** 5: Accessed flag.
2496 * Indicates that the page have been read or written to. */
2497 uint32_t u1Accessed : 1;
2498 /** 6: Dirty flag for 1GB pages. */
2499 uint32_t u1Dirty : 1;
2500 /** 7: Indicates 1GB page if set. */
2501 uint32_t u1Size : 1;
2502 /** 8: Global 1GB page. */
2503 uint32_t u1Global: 1;
2504 /** 9-11: Available for use to system software. */
2505 uint32_t u3Available : 3;
2506 /** 12: PAT bit for 1GB page. */
2507 uint32_t u1PAT : 1;
2508 /** 13-29: MBZ bits. */
2509 uint32_t u17Reserved : 17;
2510 /** 30-31: Physical page number - Low Part. Don't use! */
2511 uint32_t u2PageNoLow : 2;
2512 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2513 uint32_t u20PageNoHigh : 20;
2514 /** 52-62: MBZ bits */
2515 uint32_t u11Reserved : 11;
2516 /** 63: No Execute flag. */
2517 uint32_t u1NoExecute : 1;
2518} X86PDPE1GB;
2519#ifndef VBOX_FOR_DTRACE_LIB
2520AssertCompileSize(X86PDPE1GB, 8);
2521#endif
2522/** Pointer to a page directory pointer table entry for a 1GB page. */
2523typedef X86PDPE1GB *PX86PDPE1GB;
2524/** Pointer to a const page directory pointer table entry for a 1GB page. */
2525typedef const X86PDPE1GB *PCX86PDPE1GB;
2526
2527/**
2528 * Page directory pointer table entry.
2529 */
2530typedef union X86PDPE
2531{
2532 /** Unsigned integer view. */
2533 X86PGPAEUINT u;
2534 /** Normal view. */
2535 X86PDPEBITS n;
2536 /** AMD64 view. */
2537 X86PDPEAMD64BITS lm;
2538 /** AMD64 big view. */
2539 X86PDPE1GB b;
2540 /** 8 bit unsigned integer view. */
2541 uint8_t au8[8];
2542 /** 16 bit unsigned integer view. */
2543 uint16_t au16[4];
2544 /** 32 bit unsigned integer view. */
2545 uint32_t au32[2];
2546} X86PDPE;
2547#ifndef VBOX_FOR_DTRACE_LIB
2548AssertCompileSize(X86PDPE, 8);
2549#endif
2550/** Pointer to a page directory pointer table entry. */
2551typedef X86PDPE *PX86PDPE;
2552/** Pointer to a const page directory pointer table entry. */
2553typedef const X86PDPE *PCX86PDPE;
2554
2555
2556/**
2557 * Page directory pointer table.
2558 */
2559typedef struct X86PDPT
2560{
2561 /** PDE Array. */
2562 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2563} X86PDPT;
2564#ifndef VBOX_FOR_DTRACE_LIB
2565AssertCompileSize(X86PDPT, 4096);
2566#endif
2567/** Pointer to a page directory pointer table. */
2568typedef X86PDPT *PX86PDPT;
2569/** Pointer to a const page directory pointer table. */
2570typedef const X86PDPT *PCX86PDPT;
2571
2572/** The page shift to get the PDPT index. */
2573#define X86_PDPT_SHIFT 30
2574/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2575#define X86_PDPT_MASK_PAE 0x3
2576/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2577#define X86_PDPT_MASK_AMD64 0x1ff
2578
2579/** @} */
2580
2581
2582/** @name Page Map Level-4 Entry (Long Mode PAE)
2583 * @{
2584 */
2585/** Bit 0 - P - Present bit. */
2586#define X86_PML4E_P RT_BIT_32(0)
2587/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2588#define X86_PML4E_RW RT_BIT_32(1)
2589/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2590#define X86_PML4E_US RT_BIT_32(2)
2591/** Bit 3 - PWT - Page level write thru bit. */
2592#define X86_PML4E_PWT RT_BIT_32(3)
2593/** Bit 4 - PCD - Page level cache disable bit. */
2594#define X86_PML4E_PCD RT_BIT_32(4)
2595/** Bit 5 - A - Access bit. */
2596#define X86_PML4E_A RT_BIT_32(5)
2597/** Bits 9-11 - - Available for use to system software. */
2598#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2599/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2600#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2601/** Bits 8, 7 - - MBZ bits when NX is active. */
2602#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2603/** Bits 63, 7 - - MBZ bits when no NX. */
2604#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2605/** Bits 63 - NX - PAE - No execution flag. */
2606#define X86_PML4E_NX RT_BIT_64(63)
2607
2608/**
2609 * Page Map Level-4 Entry
2610 */
2611typedef struct X86PML4EBITS
2612{
2613 /** Flags whether(=1) or not the page is present. */
2614 uint32_t u1Present : 1;
2615 /** Read(=0) / Write(=1) flag. */
2616 uint32_t u1Write : 1;
2617 /** User(=1) / Supervisor (=0) flag. */
2618 uint32_t u1User : 1;
2619 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2620 uint32_t u1WriteThru : 1;
2621 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2622 uint32_t u1CacheDisable : 1;
2623 /** Accessed flag.
2624 * Indicates that the page have been read or written to. */
2625 uint32_t u1Accessed : 1;
2626 /** Chunk of reserved bits. */
2627 uint32_t u3Reserved : 3;
2628 /** Available for use to system software. */
2629 uint32_t u3Available : 3;
2630 /** Physical Page number of the next level - Low Part. Don't use! */
2631 uint32_t u20PageNoLow : 20;
2632 /** Physical Page number of the next level - High Part. Don't use! */
2633 uint32_t u20PageNoHigh : 20;
2634 /** MBZ bits */
2635 uint32_t u11Reserved : 11;
2636 /** No Execute flag. */
2637 uint32_t u1NoExecute : 1;
2638} X86PML4EBITS;
2639#ifndef VBOX_FOR_DTRACE_LIB
2640AssertCompileSize(X86PML4EBITS, 8);
2641#endif
2642/** Pointer to a page map level-4 entry. */
2643typedef X86PML4EBITS *PX86PML4EBITS;
2644/** Pointer to a const page map level-4 entry. */
2645typedef const X86PML4EBITS *PCX86PML4EBITS;
2646
2647/**
2648 * Page Map Level-4 Entry.
2649 */
2650typedef union X86PML4E
2651{
2652 /** Unsigned integer view. */
2653 X86PGPAEUINT u;
2654 /** Normal view. */
2655 X86PML4EBITS n;
2656 /** 8 bit unsigned integer view. */
2657 uint8_t au8[8];
2658 /** 16 bit unsigned integer view. */
2659 uint16_t au16[4];
2660 /** 32 bit unsigned integer view. */
2661 uint32_t au32[2];
2662} X86PML4E;
2663#ifndef VBOX_FOR_DTRACE_LIB
2664AssertCompileSize(X86PML4E, 8);
2665#endif
2666/** Pointer to a page map level-4 entry. */
2667typedef X86PML4E *PX86PML4E;
2668/** Pointer to a const page map level-4 entry. */
2669typedef const X86PML4E *PCX86PML4E;
2670
2671
2672/**
2673 * Page Map Level-4.
2674 */
2675typedef struct X86PML4
2676{
2677 /** PDE Array. */
2678 X86PML4E a[X86_PG_PAE_ENTRIES];
2679} X86PML4;
2680#ifndef VBOX_FOR_DTRACE_LIB
2681AssertCompileSize(X86PML4, 4096);
2682#endif
2683/** Pointer to a page map level-4. */
2684typedef X86PML4 *PX86PML4;
2685/** Pointer to a const page map level-4. */
2686typedef const X86PML4 *PCX86PML4;
2687
2688/** The page shift to get the PML4 index. */
2689#define X86_PML4_SHIFT 39
2690/** The PML4 index mask (apply to a shifted page address). */
2691#define X86_PML4_MASK 0x1ff
2692
2693/** @} */
2694
2695/** @} */
2696
2697/**
2698 * Intel PCID invalidation types.
2699 */
2700/** Individual address invalidation. */
2701#define X86_INVPCID_TYPE_INDV_ADDR 0
2702/** Single-context invalidation. */
2703#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2704/** All-context including globals invalidation. */
2705#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2706/** All-context excluding globals invalidation. */
2707#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2708/** The maximum valid invalidation type value. */
2709#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2710
2711/**
2712 * 32-bit protected mode FSTENV image.
2713 */
2714typedef struct X86FSTENV32P
2715{
2716 uint16_t FCW;
2717 uint16_t padding1;
2718 uint16_t FSW;
2719 uint16_t padding2;
2720 uint16_t FTW;
2721 uint16_t padding3;
2722 uint32_t FPUIP;
2723 uint16_t FPUCS;
2724 uint16_t FOP;
2725 uint32_t FPUDP;
2726 uint16_t FPUDS;
2727 uint16_t padding4;
2728} X86FSTENV32P;
2729/** Pointer to a 32-bit protected mode FSTENV image. */
2730typedef X86FSTENV32P *PX86FSTENV32P;
2731/** Pointer to a const 32-bit protected mode FSTENV image. */
2732typedef X86FSTENV32P const *PCX86FSTENV32P;
2733
2734
2735/**
2736 * 80-bit MMX/FPU register type.
2737 */
2738typedef struct X86FPUMMX
2739{
2740 uint8_t reg[10];
2741} X86FPUMMX;
2742#ifndef VBOX_FOR_DTRACE_LIB
2743AssertCompileSize(X86FPUMMX, 10);
2744#endif
2745/** Pointer to a 80-bit MMX/FPU register type. */
2746typedef X86FPUMMX *PX86FPUMMX;
2747/** Pointer to a const 80-bit MMX/FPU register type. */
2748typedef const X86FPUMMX *PCX86FPUMMX;
2749
2750/** FPU (x87) register. */
2751typedef union X86FPUREG
2752{
2753 /** MMX view. */
2754 uint64_t mmx;
2755 /** FPU view - todo. */
2756 X86FPUMMX fpu;
2757 /** Extended precision floating point view. */
2758 RTFLOAT80U r80;
2759 /** Extended precision floating point view v2 */
2760 RTFLOAT80U2 r80Ex;
2761 /** 8-bit view. */
2762 uint8_t au8[16];
2763 /** 16-bit view. */
2764 uint16_t au16[8];
2765 /** 32-bit view. */
2766 uint32_t au32[4];
2767 /** 64-bit view. */
2768 uint64_t au64[2];
2769 /** 128-bit view. (yeah, very helpful) */
2770 uint128_t au128[1];
2771} X86FPUREG;
2772#ifndef VBOX_FOR_DTRACE_LIB
2773AssertCompileSize(X86FPUREG, 16);
2774#endif
2775/** Pointer to a FPU register. */
2776typedef X86FPUREG *PX86FPUREG;
2777/** Pointer to a const FPU register. */
2778typedef X86FPUREG const *PCX86FPUREG;
2779
2780/**
2781 * XMM register union.
2782 */
2783typedef union X86XMMREG
2784{
2785 /** XMM Register view. */
2786 uint128_t xmm;
2787 /** 8-bit view. */
2788 uint8_t au8[16];
2789 /** 16-bit view. */
2790 uint16_t au16[8];
2791 /** 32-bit view. */
2792 uint32_t au32[4];
2793 /** 64-bit view. */
2794 uint64_t au64[2];
2795 /** 128-bit view. (yeah, very helpful) */
2796 uint128_t au128[1];
2797#ifndef VBOX_FOR_DTRACE_LIB
2798 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2799 RTUINT128U uXmm;
2800#endif
2801} X86XMMREG;
2802#ifndef VBOX_FOR_DTRACE_LIB
2803AssertCompileSize(X86XMMREG, 16);
2804#endif
2805/** Pointer to an XMM register state. */
2806typedef X86XMMREG *PX86XMMREG;
2807/** Pointer to a const XMM register state. */
2808typedef X86XMMREG const *PCX86XMMREG;
2809
2810/**
2811 * YMM register union.
2812 */
2813typedef union X86YMMREG
2814{
2815 /** 8-bit view. */
2816 uint8_t au8[32];
2817 /** 16-bit view. */
2818 uint16_t au16[16];
2819 /** 32-bit view. */
2820 uint32_t au32[8];
2821 /** 64-bit view. */
2822 uint64_t au64[4];
2823 /** 128-bit view. (yeah, very helpful) */
2824 uint128_t au128[2];
2825 /** XMM sub register view. */
2826 X86XMMREG aXmm[2];
2827} X86YMMREG;
2828#ifndef VBOX_FOR_DTRACE_LIB
2829AssertCompileSize(X86YMMREG, 32);
2830#endif
2831/** Pointer to an YMM register state. */
2832typedef X86YMMREG *PX86YMMREG;
2833/** Pointer to a const YMM register state. */
2834typedef X86YMMREG const *PCX86YMMREG;
2835
2836/**
2837 * ZMM register union.
2838 */
2839typedef union X86ZMMREG
2840{
2841 /** 8-bit view. */
2842 uint8_t au8[64];
2843 /** 16-bit view. */
2844 uint16_t au16[32];
2845 /** 32-bit view. */
2846 uint32_t au32[16];
2847 /** 64-bit view. */
2848 uint64_t au64[8];
2849 /** 128-bit view. (yeah, very helpful) */
2850 uint128_t au128[4];
2851 /** XMM sub register view. */
2852 X86XMMREG aXmm[4];
2853 /** YMM sub register view. */
2854 X86YMMREG aYmm[2];
2855} X86ZMMREG;
2856#ifndef VBOX_FOR_DTRACE_LIB
2857AssertCompileSize(X86ZMMREG, 64);
2858#endif
2859/** Pointer to an ZMM register state. */
2860typedef X86ZMMREG *PX86ZMMREG;
2861/** Pointer to a const ZMM register state. */
2862typedef X86ZMMREG const *PCX86ZMMREG;
2863
2864
2865/**
2866 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2867 * @todo verify this...
2868 */
2869#pragma pack(1)
2870typedef struct X86FPUSTATE
2871{
2872 /** 0x00 - Control word. */
2873 uint16_t FCW;
2874 /** 0x02 - Alignment word */
2875 uint16_t Dummy1;
2876 /** 0x04 - Status word. */
2877 uint16_t FSW;
2878 /** 0x06 - Alignment word */
2879 uint16_t Dummy2;
2880 /** 0x08 - Tag word */
2881 uint16_t FTW;
2882 /** 0x0a - Alignment word */
2883 uint16_t Dummy3;
2884
2885 /** 0x0c - Instruction pointer. */
2886 uint32_t FPUIP;
2887 /** 0x10 - Code selector. */
2888 uint16_t CS;
2889 /** 0x12 - Opcode. */
2890 uint16_t FOP;
2891 /** 0x14 - FOO. */
2892 uint32_t FPUOO;
2893 /** 0x18 - FOS. */
2894 uint32_t FPUOS;
2895 /** 0x1c - FPU register. */
2896 X86FPUREG regs[8];
2897} X86FPUSTATE;
2898#pragma pack()
2899/** Pointer to a FPU state. */
2900typedef X86FPUSTATE *PX86FPUSTATE;
2901/** Pointer to a const FPU state. */
2902typedef const X86FPUSTATE *PCX86FPUSTATE;
2903
2904/**
2905 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2906 */
2907#pragma pack(1)
2908typedef struct X86FXSTATE
2909{
2910 /** 0x00 - Control word. */
2911 uint16_t FCW;
2912 /** 0x02 - Status word. */
2913 uint16_t FSW;
2914 /** 0x04 - Tag word. (The upper byte is always zero.) */
2915 uint16_t FTW;
2916 /** 0x06 - Opcode. */
2917 uint16_t FOP;
2918 /** 0x08 - Instruction pointer. */
2919 uint32_t FPUIP;
2920 /** 0x0c - Code selector. */
2921 uint16_t CS;
2922 uint16_t Rsrvd1;
2923 /** 0x10 - Data pointer. */
2924 uint32_t FPUDP;
2925 /** 0x14 - Data segment */
2926 uint16_t DS;
2927 /** 0x16 */
2928 uint16_t Rsrvd2;
2929 /** 0x18 */
2930 uint32_t MXCSR;
2931 /** 0x1c */
2932 uint32_t MXCSR_MASK;
2933 /** 0x20 - FPU registers. */
2934 X86FPUREG aRegs[8];
2935 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2936 X86XMMREG aXMM[16];
2937 /* - offset 416 - */
2938 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2939 /* - offset 464 - Software usable reserved bits. */
2940 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2941} X86FXSTATE;
2942#pragma pack()
2943/** Pointer to a FPU Extended state. */
2944typedef X86FXSTATE *PX86FXSTATE;
2945/** Pointer to a const FPU Extended state. */
2946typedef const X86FXSTATE *PCX86FXSTATE;
2947
2948/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2949 * magic. Don't forget to update x86.mac if you change this! */
2950#define X86_OFF_FXSTATE_RSVD 0x1d0
2951/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2952 * forget to update x86.mac if you change this!
2953 * @todo r=bird: This has nothing what-so-ever to do here.... */
2954#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2955#ifndef VBOX_FOR_DTRACE_LIB
2956AssertCompileSize(X86FXSTATE, 512);
2957AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2958#endif
2959
2960/** @name FPU status word flags.
2961 * @{ */
2962/** Exception Flag: Invalid operation. */
2963#define X86_FSW_IE RT_BIT_32(0)
2964/** Exception Flag: Denormalized operand. */
2965#define X86_FSW_DE RT_BIT_32(1)
2966/** Exception Flag: Zero divide. */
2967#define X86_FSW_ZE RT_BIT_32(2)
2968/** Exception Flag: Overflow. */
2969#define X86_FSW_OE RT_BIT_32(3)
2970/** Exception Flag: Underflow. */
2971#define X86_FSW_UE RT_BIT_32(4)
2972/** Exception Flag: Precision. */
2973#define X86_FSW_PE RT_BIT_32(5)
2974/** Stack fault. */
2975#define X86_FSW_SF RT_BIT_32(6)
2976/** Error summary status. */
2977#define X86_FSW_ES RT_BIT_32(7)
2978/** Mask of exceptions flags, excluding the summary bit. */
2979#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2980/** Mask of exceptions flags, including the summary bit. */
2981#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2982/** Condition code 0. */
2983#define X86_FSW_C0 RT_BIT_32(8)
2984/** Condition code 1. */
2985#define X86_FSW_C1 RT_BIT_32(9)
2986/** Condition code 2. */
2987#define X86_FSW_C2 RT_BIT_32(10)
2988/** Top of the stack mask. */
2989#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2990/** TOP shift value. */
2991#define X86_FSW_TOP_SHIFT 11
2992/** Mask for getting TOP value after shifting it right. */
2993#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2994/** Get the TOP value. */
2995#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2996/** Condition code 3. */
2997#define X86_FSW_C3 RT_BIT_32(14)
2998/** Mask of exceptions flags, including the summary bit. */
2999#define X86_FSW_C_MASK UINT16_C(0x4700)
3000/** FPU busy. */
3001#define X86_FSW_B RT_BIT_32(15)
3002/** @} */
3003
3004
3005/** @name FPU control word flags.
3006 * @{ */
3007/** Exception Mask: Invalid operation. */
3008#define X86_FCW_IM RT_BIT_32(0)
3009/** Exception Mask: Denormalized operand. */
3010#define X86_FCW_DM RT_BIT_32(1)
3011/** Exception Mask: Zero divide. */
3012#define X86_FCW_ZM RT_BIT_32(2)
3013/** Exception Mask: Overflow. */
3014#define X86_FCW_OM RT_BIT_32(3)
3015/** Exception Mask: Underflow. */
3016#define X86_FCW_UM RT_BIT_32(4)
3017/** Exception Mask: Precision. */
3018#define X86_FCW_PM RT_BIT_32(5)
3019/** Mask all exceptions, the value typically loaded (by for instance fninit).
3020 * @remarks This includes reserved bit 6. */
3021#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3022/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3023#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3024/** Precision control mask. */
3025#define X86_FCW_PC_MASK UINT16_C(0x0300)
3026/** Precision control: 24-bit. */
3027#define X86_FCW_PC_24 UINT16_C(0x0000)
3028/** Precision control: Reserved. */
3029#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3030/** Precision control: 53-bit. */
3031#define X86_FCW_PC_53 UINT16_C(0x0200)
3032/** Precision control: 64-bit. */
3033#define X86_FCW_PC_64 UINT16_C(0x0300)
3034/** Rounding control mask. */
3035#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3036/** Rounding control: To nearest. */
3037#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3038/** Rounding control: Down. */
3039#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3040/** Rounding control: Up. */
3041#define X86_FCW_RC_UP UINT16_C(0x0800)
3042/** Rounding control: Towards zero. */
3043#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3044/** Bits which should be zero, apparently. */
3045#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3046/** @} */
3047
3048/** @name SSE MXCSR
3049 * @{ */
3050/** Exception Flag: Invalid operation. */
3051#define X86_MXCSR_IE RT_BIT_32(0)
3052/** Exception Flag: Denormalized operand. */
3053#define X86_MXCSR_DE RT_BIT_32(1)
3054/** Exception Flag: Zero divide. */
3055#define X86_MXCSR_ZE RT_BIT_32(2)
3056/** Exception Flag: Overflow. */
3057#define X86_MXCSR_OE RT_BIT_32(3)
3058/** Exception Flag: Underflow. */
3059#define X86_MXCSR_UE RT_BIT_32(4)
3060/** Exception Flag: Precision. */
3061#define X86_MXCSR_PE RT_BIT_32(5)
3062
3063/** Denormals are zero. */
3064#define X86_MXCSR_DAZ RT_BIT_32(6)
3065
3066/** Exception Mask: Invalid operation. */
3067#define X86_MXCSR_IM RT_BIT_32(7)
3068/** Exception Mask: Denormalized operand. */
3069#define X86_MXCSR_DM RT_BIT_32(8)
3070/** Exception Mask: Zero divide. */
3071#define X86_MXCSR_ZM RT_BIT_32(9)
3072/** Exception Mask: Overflow. */
3073#define X86_MXCSR_OM RT_BIT_32(10)
3074/** Exception Mask: Underflow. */
3075#define X86_MXCSR_UM RT_BIT_32(11)
3076/** Exception Mask: Precision. */
3077#define X86_MXCSR_PM RT_BIT_32(12)
3078
3079/** Rounding control mask. */
3080#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3081/** Rounding control: To nearest. */
3082#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3083/** Rounding control: Down. */
3084#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3085/** Rounding control: Up. */
3086#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3087/** Rounding control: Towards zero. */
3088#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3089
3090/** Flush-to-zero for masked underflow. */
3091#define X86_MXCSR_FZ RT_BIT_32(15)
3092
3093/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3094#define X86_MXCSR_MM RT_BIT_32(17)
3095/** @} */
3096
3097/**
3098 * XSAVE header.
3099 */
3100typedef struct X86XSAVEHDR
3101{
3102 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3103 uint64_t bmXState;
3104 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3105 uint64_t bmXComp;
3106 /** Reserved for furture extensions, probably MBZ. */
3107 uint64_t au64Reserved[6];
3108} X86XSAVEHDR;
3109#ifndef VBOX_FOR_DTRACE_LIB
3110AssertCompileSize(X86XSAVEHDR, 64);
3111#endif
3112/** Pointer to an XSAVE header. */
3113typedef X86XSAVEHDR *PX86XSAVEHDR;
3114/** Pointer to a const XSAVE header. */
3115typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3116
3117
3118/**
3119 * The high 128-bit YMM register state (XSAVE_C_YMM).
3120 * (The lower 128-bits being in X86FXSTATE.)
3121 */
3122typedef struct X86XSAVEYMMHI
3123{
3124 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3125 X86XMMREG aYmmHi[16];
3126} X86XSAVEYMMHI;
3127#ifndef VBOX_FOR_DTRACE_LIB
3128AssertCompileSize(X86XSAVEYMMHI, 256);
3129#endif
3130/** Pointer to a high 128-bit YMM register state. */
3131typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3132/** Pointer to a const high 128-bit YMM register state. */
3133typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3134
3135/**
3136 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3137 */
3138typedef struct X86XSAVEBNDREGS
3139{
3140 /** Array of registers (BND0...BND3). */
3141 struct
3142 {
3143 /** Lower bound. */
3144 uint64_t uLowerBound;
3145 /** Upper bound. */
3146 uint64_t uUpperBound;
3147 } aRegs[4];
3148} X86XSAVEBNDREGS;
3149#ifndef VBOX_FOR_DTRACE_LIB
3150AssertCompileSize(X86XSAVEBNDREGS, 64);
3151#endif
3152/** Pointer to a MPX bound register state. */
3153typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3154/** Pointer to a const MPX bound register state. */
3155typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3156
3157/**
3158 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3159 */
3160typedef struct X86XSAVEBNDCFG
3161{
3162 uint64_t fConfig;
3163 uint64_t fStatus;
3164} X86XSAVEBNDCFG;
3165#ifndef VBOX_FOR_DTRACE_LIB
3166AssertCompileSize(X86XSAVEBNDCFG, 16);
3167#endif
3168/** Pointer to a MPX bound config and status register state. */
3169typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3170/** Pointer to a const MPX bound config and status register state. */
3171typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3172
3173/**
3174 * AVX-512 opmask state (XSAVE_C_OPMASK).
3175 */
3176typedef struct X86XSAVEOPMASK
3177{
3178 /** The K0..K7 values. */
3179 uint64_t aKRegs[8];
3180} X86XSAVEOPMASK;
3181#ifndef VBOX_FOR_DTRACE_LIB
3182AssertCompileSize(X86XSAVEOPMASK, 64);
3183#endif
3184/** Pointer to a AVX-512 opmask state. */
3185typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3186/** Pointer to a const AVX-512 opmask state. */
3187typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3188
3189/**
3190 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3191 */
3192typedef struct X86XSAVEZMMHI256
3193{
3194 /** Upper 256-bits of ZMM0-15. */
3195 X86YMMREG aHi256Regs[16];
3196} X86XSAVEZMMHI256;
3197#ifndef VBOX_FOR_DTRACE_LIB
3198AssertCompileSize(X86XSAVEZMMHI256, 512);
3199#endif
3200/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3201typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3202/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3203typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3204
3205/**
3206 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3207 */
3208typedef struct X86XSAVEZMM16HI
3209{
3210 /** ZMM16 thru ZMM31. */
3211 X86ZMMREG aRegs[16];
3212} X86XSAVEZMM16HI;
3213#ifndef VBOX_FOR_DTRACE_LIB
3214AssertCompileSize(X86XSAVEZMM16HI, 1024);
3215#endif
3216/** Pointer to a state comprising ZMM16-32. */
3217typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3218/** Pointer to a const state comprising ZMM16-32. */
3219typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3220
3221/**
3222 * AMD Light weight profiling state (XSAVE_C_LWP).
3223 *
3224 * We probably won't play with this as AMD seems to be dropping from their "zen"
3225 * processor micro architecture.
3226 */
3227typedef struct X86XSAVELWP
3228{
3229 /** Details when needed. */
3230 uint64_t auLater[128/8];
3231} X86XSAVELWP;
3232#ifndef VBOX_FOR_DTRACE_LIB
3233AssertCompileSize(X86XSAVELWP, 128);
3234#endif
3235
3236
3237/**
3238 * x86 FPU/SSE/AVX/XXXX state.
3239 *
3240 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3241 * changes to this structure.
3242 */
3243typedef struct X86XSAVEAREA
3244{
3245 /** The x87 and SSE region (or legacy region if you like). */
3246 X86FXSTATE x87;
3247 /** The XSAVE header. */
3248 X86XSAVEHDR Hdr;
3249 /** Beyond the header, there isn't really a fixed layout, but we can
3250 generally assume the YMM (AVX) register extensions are present and
3251 follows immediately. */
3252 union
3253 {
3254 /** The high 128-bit AVX registers for easy access by IEM.
3255 * @note This ASSUMES they will always be here... */
3256 X86XSAVEYMMHI YmmHi;
3257
3258 /** This is a typical layout on intel CPUs (good for debuggers). */
3259 struct
3260 {
3261 X86XSAVEYMMHI YmmHi;
3262 X86XSAVEBNDREGS BndRegs;
3263 X86XSAVEBNDCFG BndCfg;
3264 uint8_t abFudgeToMatchDocs[0xB0];
3265 X86XSAVEOPMASK Opmask;
3266 X86XSAVEZMMHI256 ZmmHi256;
3267 X86XSAVEZMM16HI Zmm16Hi;
3268 } Intel;
3269
3270 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3271 struct
3272 {
3273 X86XSAVEYMMHI YmmHi;
3274 X86XSAVELWP Lwp;
3275 } AmdBd;
3276
3277 /** To enbling static deployments that have a reasonable chance of working for
3278 * the next 3-6 CPU generations without running short on space, we allocate a
3279 * lot of extra space here, making the structure a round 8KB in size. This
3280 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3281 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3282 uint8_t ab[8192 - 512 - 64];
3283 } u;
3284} X86XSAVEAREA;
3285#ifndef VBOX_FOR_DTRACE_LIB
3286AssertCompileSize(X86XSAVEAREA, 8192);
3287AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3288AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3289AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3290AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3291AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3292AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3293AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3294AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3295#endif
3296/** Pointer to a XSAVE area. */
3297typedef X86XSAVEAREA *PX86XSAVEAREA;
3298/** Pointer to a const XSAVE area. */
3299typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3300
3301
3302/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3303 * @{ */
3304/** Bit 0 - x87 - Legacy FPU state (bit number) */
3305#define XSAVE_C_X87_BIT 0
3306/** Bit 0 - x87 - Legacy FPU state. */
3307#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3308/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3309#define XSAVE_C_SSE_BIT 1
3310/** Bit 1 - SSE - 128-bit SSE state. */
3311#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3312/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3313#define XSAVE_C_YMM_BIT 2
3314/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3315#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3316/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3317#define XSAVE_C_BNDREGS_BIT 3
3318/** Bit 3 - BNDREGS - MPX bound register state. */
3319#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3320/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3321#define XSAVE_C_BNDCSR_BIT 4
3322/** Bit 4 - BNDCSR - MPX bound config and status state. */
3323#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3324/** Bit 5 - Opmask - opmask state (bit number). */
3325#define XSAVE_C_OPMASK_BIT 5
3326/** Bit 5 - Opmask - opmask state. */
3327#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3328/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3329#define XSAVE_C_ZMM_HI256_BIT 6
3330/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3331#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3332/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3333#define XSAVE_C_ZMM_16HI_BIT 7
3334/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3335#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3336/** Bit 9 - PKRU - Protection-key state (bit number). */
3337#define XSAVE_C_PKRU_BIT 9
3338/** Bit 9 - PKRU - Protection-key state. */
3339#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3340/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3341#define XSAVE_C_LWP_BIT 62
3342/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3343#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3344/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3345#define XSAVE_C_X_BIT 63
3346/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3347#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3348/** @} */
3349
3350
3351
3352/** @name Selector Descriptor
3353 * @{
3354 */
3355
3356#ifndef VBOX_FOR_DTRACE_LIB
3357/**
3358 * Descriptor attributes (as seen by VT-x).
3359 */
3360typedef struct X86DESCATTRBITS
3361{
3362 /** 00 - Segment Type. */
3363 unsigned u4Type : 4;
3364 /** 04 - Descriptor Type. System(=0) or code/data selector */
3365 unsigned u1DescType : 1;
3366 /** 05 - Descriptor Privilege level. */
3367 unsigned u2Dpl : 2;
3368 /** 07 - Flags selector present(=1) or not. */
3369 unsigned u1Present : 1;
3370 /** 08 - Segment limit 16-19. */
3371 unsigned u4LimitHigh : 4;
3372 /** 0c - Available for system software. */
3373 unsigned u1Available : 1;
3374 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3375 unsigned u1Long : 1;
3376 /** 0e - This flags meaning depends on the segment type. Try make sense out
3377 * of the intel manual yourself. */
3378 unsigned u1DefBig : 1;
3379 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3380 * clear byte. */
3381 unsigned u1Granularity : 1;
3382 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3383 unsigned u1Unusable : 1;
3384} X86DESCATTRBITS;
3385#endif /* !VBOX_FOR_DTRACE_LIB */
3386
3387/** @name X86DESCATTR masks
3388 * @{ */
3389#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3390#define X86DESCATTR_DT UINT32_C(0x00000010)
3391#define X86DESCATTR_DPL UINT32_C(0x00000060)
3392#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3393#define X86DESCATTR_P UINT32_C(0x00000080)
3394#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3395#define X86DESCATTR_AVL UINT32_C(0x00001000)
3396#define X86DESCATTR_L UINT32_C(0x00002000)
3397#define X86DESCATTR_D UINT32_C(0x00004000)
3398#define X86DESCATTR_G UINT32_C(0x00008000)
3399#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3400/** @} */
3401
3402#pragma pack(1)
3403typedef union X86DESCATTR
3404{
3405 /** Unsigned integer view. */
3406 uint32_t u;
3407#ifndef VBOX_FOR_DTRACE_LIB
3408 /** Normal view. */
3409 X86DESCATTRBITS n;
3410#endif
3411} X86DESCATTR;
3412#pragma pack()
3413/** Pointer to descriptor attributes. */
3414typedef X86DESCATTR *PX86DESCATTR;
3415/** Pointer to const descriptor attributes. */
3416typedef const X86DESCATTR *PCX86DESCATTR;
3417
3418#ifndef VBOX_FOR_DTRACE_LIB
3419
3420/**
3421 * Generic descriptor table entry
3422 */
3423#pragma pack(1)
3424typedef struct X86DESCGENERIC
3425{
3426 /** 00 - Limit - Low word. */
3427 unsigned u16LimitLow : 16;
3428 /** 10 - Base address - low word.
3429 * Don't try set this to 24 because MSC is doing stupid things then. */
3430 unsigned u16BaseLow : 16;
3431 /** 20 - Base address - first 8 bits of high word. */
3432 unsigned u8BaseHigh1 : 8;
3433 /** 28 - Segment Type. */
3434 unsigned u4Type : 4;
3435 /** 2c - Descriptor Type. System(=0) or code/data selector */
3436 unsigned u1DescType : 1;
3437 /** 2d - Descriptor Privilege level. */
3438 unsigned u2Dpl : 2;
3439 /** 2f - Flags selector present(=1) or not. */
3440 unsigned u1Present : 1;
3441 /** 30 - Segment limit 16-19. */
3442 unsigned u4LimitHigh : 4;
3443 /** 34 - Available for system software. */
3444 unsigned u1Available : 1;
3445 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3446 unsigned u1Long : 1;
3447 /** 36 - This flags meaning depends on the segment type. Try make sense out
3448 * of the intel manual yourself. */
3449 unsigned u1DefBig : 1;
3450 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3451 * clear byte. */
3452 unsigned u1Granularity : 1;
3453 /** 38 - Base address - highest 8 bits. */
3454 unsigned u8BaseHigh2 : 8;
3455} X86DESCGENERIC;
3456#pragma pack()
3457/** Pointer to a generic descriptor entry. */
3458typedef X86DESCGENERIC *PX86DESCGENERIC;
3459/** Pointer to a const generic descriptor entry. */
3460typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3461
3462/** @name Bit offsets of X86DESCGENERIC members.
3463 * @{*/
3464#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3465#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3466#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3467#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3468#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3469#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3470#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3471#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3472#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3473#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3474#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3475#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3476#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3477/** @} */
3478
3479
3480/** @name LAR mask
3481 * @{ */
3482#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3483#define X86LAR_F_DT UINT16_C( 0x1000)
3484#define X86LAR_F_DPL UINT16_C( 0x6000)
3485#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3486#define X86LAR_F_P UINT16_C( 0x8000)
3487#define X86LAR_F_AVL UINT32_C(0x00100000)
3488#define X86LAR_F_L UINT32_C(0x00200000)
3489#define X86LAR_F_D UINT32_C(0x00400000)
3490#define X86LAR_F_G UINT32_C(0x00800000)
3491/** @} */
3492
3493
3494/**
3495 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3496 */
3497typedef struct X86DESCGATE
3498{
3499 /** 00 - Target code segment offset - Low word.
3500 * Ignored if task-gate. */
3501 unsigned u16OffsetLow : 16;
3502 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3503 * TSS selector if task-gate. */
3504 unsigned u16Sel : 16;
3505 /** 20 - Number of parameters for a call-gate.
3506 * Ignored if interrupt-, trap- or task-gate. */
3507 unsigned u5ParmCount : 5;
3508 /** 25 - Reserved / ignored. */
3509 unsigned u3Reserved : 3;
3510 /** 28 - Segment Type. */
3511 unsigned u4Type : 4;
3512 /** 2c - Descriptor Type (0 = system). */
3513 unsigned u1DescType : 1;
3514 /** 2d - Descriptor Privilege level. */
3515 unsigned u2Dpl : 2;
3516 /** 2f - Flags selector present(=1) or not. */
3517 unsigned u1Present : 1;
3518 /** 30 - Target code segment offset - High word.
3519 * Ignored if task-gate. */
3520 unsigned u16OffsetHigh : 16;
3521} X86DESCGATE;
3522/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3523typedef X86DESCGATE *PX86DESCGATE;
3524/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3525typedef const X86DESCGATE *PCX86DESCGATE;
3526
3527#endif /* VBOX_FOR_DTRACE_LIB */
3528
3529/**
3530 * Descriptor table entry.
3531 */
3532#pragma pack(1)
3533typedef union X86DESC
3534{
3535#ifndef VBOX_FOR_DTRACE_LIB
3536 /** Generic descriptor view. */
3537 X86DESCGENERIC Gen;
3538 /** Gate descriptor view. */
3539 X86DESCGATE Gate;
3540#endif
3541
3542 /** 8 bit unsigned integer view. */
3543 uint8_t au8[8];
3544 /** 16 bit unsigned integer view. */
3545 uint16_t au16[4];
3546 /** 32 bit unsigned integer view. */
3547 uint32_t au32[2];
3548 /** 64 bit unsigned integer view. */
3549 uint64_t au64[1];
3550 /** Unsigned integer view. */
3551 uint64_t u;
3552} X86DESC;
3553#ifndef VBOX_FOR_DTRACE_LIB
3554AssertCompileSize(X86DESC, 8);
3555#endif
3556#pragma pack()
3557/** Pointer to descriptor table entry. */
3558typedef X86DESC *PX86DESC;
3559/** Pointer to const descriptor table entry. */
3560typedef const X86DESC *PCX86DESC;
3561
3562/** @def X86DESC_BASE
3563 * Return the base address of a descriptor.
3564 */
3565#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3566 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3567 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3568 | ( (a_pDesc)->Gen.u16BaseLow ) )
3569
3570/** @def X86DESC_LIMIT
3571 * Return the limit of a descriptor.
3572 */
3573#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3574 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3575 | ( (a_pDesc)->Gen.u16LimitLow ) )
3576
3577/** @def X86DESC_LIMIT_G
3578 * Return the limit of a descriptor with the granularity bit taken into account.
3579 * @returns Selector limit (uint32_t).
3580 * @param a_pDesc Pointer to the descriptor.
3581 */
3582#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3583 ( (a_pDesc)->Gen.u1Granularity \
3584 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3585 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3586 )
3587
3588/** @def X86DESC_GET_HID_ATTR
3589 * Get the descriptor attributes for the hidden register.
3590 */
3591#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3592 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3593
3594#ifndef VBOX_FOR_DTRACE_LIB
3595
3596/**
3597 * 64 bits generic descriptor table entry
3598 * Note: most of these bits have no meaning in long mode.
3599 */
3600#pragma pack(1)
3601typedef struct X86DESC64GENERIC
3602{
3603 /** Limit - Low word - *IGNORED*. */
3604 uint32_t u16LimitLow : 16;
3605 /** Base address - low word. - *IGNORED*
3606 * Don't try set this to 24 because MSC is doing stupid things then. */
3607 uint32_t u16BaseLow : 16;
3608 /** Base address - first 8 bits of high word. - *IGNORED* */
3609 uint32_t u8BaseHigh1 : 8;
3610 /** Segment Type. */
3611 uint32_t u4Type : 4;
3612 /** Descriptor Type. System(=0) or code/data selector */
3613 uint32_t u1DescType : 1;
3614 /** Descriptor Privilege level. */
3615 uint32_t u2Dpl : 2;
3616 /** Flags selector present(=1) or not. */
3617 uint32_t u1Present : 1;
3618 /** Segment limit 16-19. - *IGNORED* */
3619 uint32_t u4LimitHigh : 4;
3620 /** Available for system software. - *IGNORED* */
3621 uint32_t u1Available : 1;
3622 /** Long mode flag. */
3623 uint32_t u1Long : 1;
3624 /** This flags meaning depends on the segment type. Try make sense out
3625 * of the intel manual yourself. */
3626 uint32_t u1DefBig : 1;
3627 /** Granularity of the limit. If set 4KB granularity is used, if
3628 * clear byte. - *IGNORED* */
3629 uint32_t u1Granularity : 1;
3630 /** Base address - highest 8 bits. - *IGNORED* */
3631 uint32_t u8BaseHigh2 : 8;
3632 /** Base address - bits 63-32. */
3633 uint32_t u32BaseHigh3 : 32;
3634 uint32_t u8Reserved : 8;
3635 uint32_t u5Zeros : 5;
3636 uint32_t u19Reserved : 19;
3637} X86DESC64GENERIC;
3638#pragma pack()
3639/** Pointer to a generic descriptor entry. */
3640typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3641/** Pointer to a const generic descriptor entry. */
3642typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3643
3644/**
3645 * System descriptor table entry (64 bits)
3646 *
3647 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3648 */
3649#pragma pack(1)
3650typedef struct X86DESC64SYSTEM
3651{
3652 /** Limit - Low word. */
3653 uint32_t u16LimitLow : 16;
3654 /** Base address - low word.
3655 * Don't try set this to 24 because MSC is doing stupid things then. */
3656 uint32_t u16BaseLow : 16;
3657 /** Base address - first 8 bits of high word. */
3658 uint32_t u8BaseHigh1 : 8;
3659 /** Segment Type. */
3660 uint32_t u4Type : 4;
3661 /** Descriptor Type. System(=0) or code/data selector */
3662 uint32_t u1DescType : 1;
3663 /** Descriptor Privilege level. */
3664 uint32_t u2Dpl : 2;
3665 /** Flags selector present(=1) or not. */
3666 uint32_t u1Present : 1;
3667 /** Segment limit 16-19. */
3668 uint32_t u4LimitHigh : 4;
3669 /** Available for system software. */
3670 uint32_t u1Available : 1;
3671 /** Reserved - 0. */
3672 uint32_t u1Reserved : 1;
3673 /** This flags meaning depends on the segment type. Try make sense out
3674 * of the intel manual yourself. */
3675 uint32_t u1DefBig : 1;
3676 /** Granularity of the limit. If set 4KB granularity is used, if
3677 * clear byte. */
3678 uint32_t u1Granularity : 1;
3679 /** Base address - bits 31-24. */
3680 uint32_t u8BaseHigh2 : 8;
3681 /** Base address - bits 63-32. */
3682 uint32_t u32BaseHigh3 : 32;
3683 uint32_t u8Reserved : 8;
3684 uint32_t u5Zeros : 5;
3685 uint32_t u19Reserved : 19;
3686} X86DESC64SYSTEM;
3687#pragma pack()
3688/** Pointer to a system descriptor entry. */
3689typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3690/** Pointer to a const system descriptor entry. */
3691typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3692
3693/**
3694 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3695 */
3696typedef struct X86DESC64GATE
3697{
3698 /** Target code segment offset - Low word. */
3699 uint32_t u16OffsetLow : 16;
3700 /** Target code segment selector. */
3701 uint32_t u16Sel : 16;
3702 /** Interrupt stack table for interrupt- and trap-gates.
3703 * Ignored by call-gates. */
3704 uint32_t u3IST : 3;
3705 /** Reserved / ignored. */
3706 uint32_t u5Reserved : 5;
3707 /** Segment Type. */
3708 uint32_t u4Type : 4;
3709 /** Descriptor Type (0 = system). */
3710 uint32_t u1DescType : 1;
3711 /** Descriptor Privilege level. */
3712 uint32_t u2Dpl : 2;
3713 /** Flags selector present(=1) or not. */
3714 uint32_t u1Present : 1;
3715 /** Target code segment offset - High word.
3716 * Ignored if task-gate. */
3717 uint32_t u16OffsetHigh : 16;
3718 /** Target code segment offset - Top dword.
3719 * Ignored if task-gate. */
3720 uint32_t u32OffsetTop : 32;
3721 /** Reserved / ignored / must be zero.
3722 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3723 uint32_t u32Reserved : 32;
3724} X86DESC64GATE;
3725AssertCompileSize(X86DESC64GATE, 16);
3726/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3727typedef X86DESC64GATE *PX86DESC64GATE;
3728/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3729typedef const X86DESC64GATE *PCX86DESC64GATE;
3730
3731#endif /* VBOX_FOR_DTRACE_LIB */
3732
3733/**
3734 * Descriptor table entry.
3735 */
3736#pragma pack(1)
3737typedef union X86DESC64
3738{
3739#ifndef VBOX_FOR_DTRACE_LIB
3740 /** Generic descriptor view. */
3741 X86DESC64GENERIC Gen;
3742 /** System descriptor view. */
3743 X86DESC64SYSTEM System;
3744 /** Gate descriptor view. */
3745 X86DESC64GATE Gate;
3746#endif
3747
3748 /** 8 bit unsigned integer view. */
3749 uint8_t au8[16];
3750 /** 16 bit unsigned integer view. */
3751 uint16_t au16[8];
3752 /** 32 bit unsigned integer view. */
3753 uint32_t au32[4];
3754 /** 64 bit unsigned integer view. */
3755 uint64_t au64[2];
3756} X86DESC64;
3757#ifndef VBOX_FOR_DTRACE_LIB
3758AssertCompileSize(X86DESC64, 16);
3759#endif
3760#pragma pack()
3761/** Pointer to descriptor table entry. */
3762typedef X86DESC64 *PX86DESC64;
3763/** Pointer to const descriptor table entry. */
3764typedef const X86DESC64 *PCX86DESC64;
3765
3766/** @def X86DESC64_BASE
3767 * Return the base of a 64-bit descriptor.
3768 */
3769#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3770 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3771 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3772 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3773 | ( (a_pDesc)->Gen.u16BaseLow ) )
3774
3775
3776
3777/** @name Host system descriptor table entry - Use with care!
3778 * @{ */
3779/** Host system descriptor table entry. */
3780#if HC_ARCH_BITS == 64
3781typedef X86DESC64 X86DESCHC;
3782#else
3783typedef X86DESC X86DESCHC;
3784#endif
3785/** Pointer to a host system descriptor table entry. */
3786#if HC_ARCH_BITS == 64
3787typedef PX86DESC64 PX86DESCHC;
3788#else
3789typedef PX86DESC PX86DESCHC;
3790#endif
3791/** Pointer to a const host system descriptor table entry. */
3792#if HC_ARCH_BITS == 64
3793typedef PCX86DESC64 PCX86DESCHC;
3794#else
3795typedef PCX86DESC PCX86DESCHC;
3796#endif
3797/** @} */
3798
3799
3800/** @name Selector Descriptor Types.
3801 * @{
3802 */
3803
3804/** @name Non-System Selector Types.
3805 * @{ */
3806/** Code(=set)/Data(=clear) bit. */
3807#define X86_SEL_TYPE_CODE 8
3808/** Memory(=set)/System(=clear) bit. */
3809#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3810/** Accessed bit. */
3811#define X86_SEL_TYPE_ACCESSED 1
3812/** Expand down bit (for data selectors only). */
3813#define X86_SEL_TYPE_DOWN 4
3814/** Conforming bit (for code selectors only). */
3815#define X86_SEL_TYPE_CONF 4
3816/** Write bit (for data selectors only). */
3817#define X86_SEL_TYPE_WRITE 2
3818/** Read bit (for code selectors only). */
3819#define X86_SEL_TYPE_READ 2
3820/** The bit number of the code segment read bit (relative to u4Type). */
3821#define X86_SEL_TYPE_READ_BIT 1
3822
3823/** Read only selector type. */
3824#define X86_SEL_TYPE_RO 0
3825/** Accessed read only selector type. */
3826#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3827/** Read write selector type. */
3828#define X86_SEL_TYPE_RW 2
3829/** Accessed read write selector type. */
3830#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3831/** Expand down read only selector type. */
3832#define X86_SEL_TYPE_RO_DOWN 4
3833/** Accessed expand down read only selector type. */
3834#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3835/** Expand down read write selector type. */
3836#define X86_SEL_TYPE_RW_DOWN 6
3837/** Accessed expand down read write selector type. */
3838#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3839/** Execute only selector type. */
3840#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3841/** Accessed execute only selector type. */
3842#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3843/** Execute and read selector type. */
3844#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3845/** Accessed execute and read selector type. */
3846#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3847/** Conforming execute only selector type. */
3848#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3849/** Accessed Conforming execute only selector type. */
3850#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3851/** Conforming execute and write selector type. */
3852#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3853/** Accessed Conforming execute and write selector type. */
3854#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3855/** @} */
3856
3857
3858/** @name System Selector Types.
3859 * @{ */
3860/** The TSS busy bit mask. */
3861#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3862
3863/** Undefined system selector type. */
3864#define X86_SEL_TYPE_SYS_UNDEFINED 0
3865/** 286 TSS selector. */
3866#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3867/** LDT selector. */
3868#define X86_SEL_TYPE_SYS_LDT 2
3869/** 286 TSS selector - Busy. */
3870#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3871/** 286 Callgate selector. */
3872#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3873/** Taskgate selector. */
3874#define X86_SEL_TYPE_SYS_TASK_GATE 5
3875/** 286 Interrupt gate selector. */
3876#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3877/** 286 Trapgate selector. */
3878#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3879/** Undefined system selector. */
3880#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3881/** 386 TSS selector. */
3882#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3883/** Undefined system selector. */
3884#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3885/** 386 TSS selector - Busy. */
3886#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3887/** 386 Callgate selector. */
3888#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3889/** Undefined system selector. */
3890#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3891/** 386 Interruptgate selector. */
3892#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3893/** 386 Trapgate selector. */
3894#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3895/** @} */
3896
3897/** @name AMD64 System Selector Types.
3898 * @{ */
3899/** LDT selector. */
3900#define AMD64_SEL_TYPE_SYS_LDT 2
3901/** TSS selector - Busy. */
3902#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3903/** TSS selector - Busy. */
3904#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3905/** Callgate selector. */
3906#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3907/** Interruptgate selector. */
3908#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3909/** Trapgate selector. */
3910#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3911/** @} */
3912
3913/** @} */
3914
3915
3916/** @name Descriptor Table Entry Flag Masks.
3917 * These are for the 2nd 32-bit word of a descriptor.
3918 * @{ */
3919/** Bits 8-11 - TYPE - Descriptor type mask. */
3920#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3921/** Bit 12 - S - System (=0) or Code/Data (=1). */
3922#define X86_DESC_S RT_BIT_32(12)
3923/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3924#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3925/** Bit 15 - P - Present. */
3926#define X86_DESC_P RT_BIT_32(15)
3927/** Bit 20 - AVL - Available for system software. */
3928#define X86_DESC_AVL RT_BIT_32(20)
3929/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3930#define X86_DESC_DB RT_BIT_32(22)
3931/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3932 * used, if clear byte. */
3933#define X86_DESC_G RT_BIT_32(23)
3934/** @} */
3935
3936/** @} */
3937
3938
3939/** @name Task Segments.
3940 * @{
3941 */
3942
3943/**
3944 * The minimum TSS descriptor limit for 286 tasks.
3945 */
3946#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3947
3948/**
3949 * The minimum TSS descriptor segment limit for 386 tasks.
3950 */
3951#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3952
3953/**
3954 * 16-bit Task Segment (TSS).
3955 */
3956#pragma pack(1)
3957typedef struct X86TSS16
3958{
3959 /** Back link to previous task. (static) */
3960 RTSEL selPrev;
3961 /** Ring-0 stack pointer. (static) */
3962 uint16_t sp0;
3963 /** Ring-0 stack segment. (static) */
3964 RTSEL ss0;
3965 /** Ring-1 stack pointer. (static) */
3966 uint16_t sp1;
3967 /** Ring-1 stack segment. (static) */
3968 RTSEL ss1;
3969 /** Ring-2 stack pointer. (static) */
3970 uint16_t sp2;
3971 /** Ring-2 stack segment. (static) */
3972 RTSEL ss2;
3973 /** IP before task switch. */
3974 uint16_t ip;
3975 /** FLAGS before task switch. */
3976 uint16_t flags;
3977 /** AX before task switch. */
3978 uint16_t ax;
3979 /** CX before task switch. */
3980 uint16_t cx;
3981 /** DX before task switch. */
3982 uint16_t dx;
3983 /** BX before task switch. */
3984 uint16_t bx;
3985 /** SP before task switch. */
3986 uint16_t sp;
3987 /** BP before task switch. */
3988 uint16_t bp;
3989 /** SI before task switch. */
3990 uint16_t si;
3991 /** DI before task switch. */
3992 uint16_t di;
3993 /** ES before task switch. */
3994 RTSEL es;
3995 /** CS before task switch. */
3996 RTSEL cs;
3997 /** SS before task switch. */
3998 RTSEL ss;
3999 /** DS before task switch. */
4000 RTSEL ds;
4001 /** LDTR before task switch. */
4002 RTSEL selLdt;
4003} X86TSS16;
4004#ifndef VBOX_FOR_DTRACE_LIB
4005AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4006#endif
4007#pragma pack()
4008/** Pointer to a 16-bit task segment. */
4009typedef X86TSS16 *PX86TSS16;
4010/** Pointer to a const 16-bit task segment. */
4011typedef const X86TSS16 *PCX86TSS16;
4012
4013
4014/**
4015 * 32-bit Task Segment (TSS).
4016 */
4017#pragma pack(1)
4018typedef struct X86TSS32
4019{
4020 /** Back link to previous task. (static) */
4021 RTSEL selPrev;
4022 uint16_t padding1;
4023 /** Ring-0 stack pointer. (static) */
4024 uint32_t esp0;
4025 /** Ring-0 stack segment. (static) */
4026 RTSEL ss0;
4027 uint16_t padding_ss0;
4028 /** Ring-1 stack pointer. (static) */
4029 uint32_t esp1;
4030 /** Ring-1 stack segment. (static) */
4031 RTSEL ss1;
4032 uint16_t padding_ss1;
4033 /** Ring-2 stack pointer. (static) */
4034 uint32_t esp2;
4035 /** Ring-2 stack segment. (static) */
4036 RTSEL ss2;
4037 uint16_t padding_ss2;
4038 /** Page directory for the task. (static) */
4039 uint32_t cr3;
4040 /** EIP before task switch. */
4041 uint32_t eip;
4042 /** EFLAGS before task switch. */
4043 uint32_t eflags;
4044 /** EAX before task switch. */
4045 uint32_t eax;
4046 /** ECX before task switch. */
4047 uint32_t ecx;
4048 /** EDX before task switch. */
4049 uint32_t edx;
4050 /** EBX before task switch. */
4051 uint32_t ebx;
4052 /** ESP before task switch. */
4053 uint32_t esp;
4054 /** EBP before task switch. */
4055 uint32_t ebp;
4056 /** ESI before task switch. */
4057 uint32_t esi;
4058 /** EDI before task switch. */
4059 uint32_t edi;
4060 /** ES before task switch. */
4061 RTSEL es;
4062 uint16_t padding_es;
4063 /** CS before task switch. */
4064 RTSEL cs;
4065 uint16_t padding_cs;
4066 /** SS before task switch. */
4067 RTSEL ss;
4068 uint16_t padding_ss;
4069 /** DS before task switch. */
4070 RTSEL ds;
4071 uint16_t padding_ds;
4072 /** FS before task switch. */
4073 RTSEL fs;
4074 uint16_t padding_fs;
4075 /** GS before task switch. */
4076 RTSEL gs;
4077 uint16_t padding_gs;
4078 /** LDTR before task switch. */
4079 RTSEL selLdt;
4080 uint16_t padding_ldt;
4081 /** Debug trap flag */
4082 uint16_t fDebugTrap;
4083 /** Offset relative to the TSS of the start of the I/O Bitmap
4084 * and the end of the interrupt redirection bitmap. */
4085 uint16_t offIoBitmap;
4086} X86TSS32;
4087#pragma pack()
4088/** Pointer to task segment. */
4089typedef X86TSS32 *PX86TSS32;
4090/** Pointer to const task segment. */
4091typedef const X86TSS32 *PCX86TSS32;
4092#ifndef VBOX_FOR_DTRACE_LIB
4093AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4094AssertCompileMemberOffset(X86TSS32, cr3, 28);
4095AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4096#endif
4097
4098/**
4099 * 64-bit Task segment.
4100 */
4101#pragma pack(1)
4102typedef struct X86TSS64
4103{
4104 /** Reserved. */
4105 uint32_t u32Reserved;
4106 /** Ring-0 stack pointer. (static) */
4107 uint64_t rsp0;
4108 /** Ring-1 stack pointer. (static) */
4109 uint64_t rsp1;
4110 /** Ring-2 stack pointer. (static) */
4111 uint64_t rsp2;
4112 /** Reserved. */
4113 uint32_t u32Reserved2[2];
4114 /* IST */
4115 uint64_t ist1;
4116 uint64_t ist2;
4117 uint64_t ist3;
4118 uint64_t ist4;
4119 uint64_t ist5;
4120 uint64_t ist6;
4121 uint64_t ist7;
4122 /* Reserved. */
4123 uint16_t u16Reserved[5];
4124 /** Offset relative to the TSS of the start of the I/O Bitmap
4125 * and the end of the interrupt redirection bitmap. */
4126 uint16_t offIoBitmap;
4127} X86TSS64;
4128#pragma pack()
4129/** Pointer to a 64-bit task segment. */
4130typedef X86TSS64 *PX86TSS64;
4131/** Pointer to a const 64-bit task segment. */
4132typedef const X86TSS64 *PCX86TSS64;
4133#ifndef VBOX_FOR_DTRACE_LIB
4134AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4135#endif
4136
4137/** @} */
4138
4139
4140/** @name Selectors.
4141 * @{
4142 */
4143
4144/**
4145 * The shift used to convert a selector from and to index an index (C).
4146 */
4147#define X86_SEL_SHIFT 3
4148
4149/**
4150 * The mask used to mask off the table indicator and RPL of an selector.
4151 */
4152#define X86_SEL_MASK 0xfff8U
4153
4154/**
4155 * The mask used to mask off the RPL of an selector.
4156 * This is suitable for checking for NULL selectors.
4157 */
4158#define X86_SEL_MASK_OFF_RPL 0xfffcU
4159
4160/**
4161 * The bit indicating that a selector is in the LDT and not in the GDT.
4162 */
4163#define X86_SEL_LDT 0x0004U
4164
4165/**
4166 * The bit mask for getting the RPL of a selector.
4167 */
4168#define X86_SEL_RPL 0x0003U
4169
4170/**
4171 * The mask covering both RPL and LDT.
4172 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4173 * checks.
4174 */
4175#define X86_SEL_RPL_LDT 0x0007U
4176
4177/** @} */
4178
4179
4180/**
4181 * x86 Exceptions/Faults/Traps.
4182 */
4183typedef enum X86XCPT
4184{
4185 /** \#DE - Divide error. */
4186 X86_XCPT_DE = 0x00,
4187 /** \#DB - Debug event (single step, DRx, ..) */
4188 X86_XCPT_DB = 0x01,
4189 /** NMI - Non-Maskable Interrupt */
4190 X86_XCPT_NMI = 0x02,
4191 /** \#BP - Breakpoint (INT3). */
4192 X86_XCPT_BP = 0x03,
4193 /** \#OF - Overflow (INTO). */
4194 X86_XCPT_OF = 0x04,
4195 /** \#BR - Bound range exceeded (BOUND). */
4196 X86_XCPT_BR = 0x05,
4197 /** \#UD - Undefined opcode. */
4198 X86_XCPT_UD = 0x06,
4199 /** \#NM - Device not available (math coprocessor device). */
4200 X86_XCPT_NM = 0x07,
4201 /** \#DF - Double fault. */
4202 X86_XCPT_DF = 0x08,
4203 /** ??? - Coprocessor segment overrun (obsolete). */
4204 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4205 /** \#TS - Taskswitch (TSS). */
4206 X86_XCPT_TS = 0x0a,
4207 /** \#NP - Segment no present. */
4208 X86_XCPT_NP = 0x0b,
4209 /** \#SS - Stack segment fault. */
4210 X86_XCPT_SS = 0x0c,
4211 /** \#GP - General protection fault. */
4212 X86_XCPT_GP = 0x0d,
4213 /** \#PF - Page fault. */
4214 X86_XCPT_PF = 0x0e,
4215 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4216 /** \#MF - Math fault (FPU). */
4217 X86_XCPT_MF = 0x10,
4218 /** \#AC - Alignment check. */
4219 X86_XCPT_AC = 0x11,
4220 /** \#MC - Machine check. */
4221 X86_XCPT_MC = 0x12,
4222 /** \#XF - SIMD Floating-Pointer Exception. */
4223 X86_XCPT_XF = 0x13,
4224 /** \#VE - Virtualization Exception. */
4225 X86_XCPT_VE = 0x14,
4226 /** \#SX - Security Exception. */
4227 X86_XCPT_SX = 0x1e
4228} X86XCPT;
4229/** Pointer to a x86 exception code. */
4230typedef X86XCPT *PX86XCPT;
4231/** Pointer to a const x86 exception code. */
4232typedef const X86XCPT *PCX86XCPT;
4233/** The last valid (currently reserved) exception value. */
4234#define X86_XCPT_LAST 0x1f
4235
4236
4237/** @name Trap Error Codes
4238 * @{
4239 */
4240/** External indicator. */
4241#define X86_TRAP_ERR_EXTERNAL 1
4242/** IDT indicator. */
4243#define X86_TRAP_ERR_IDT 2
4244/** Descriptor table indicator - If set LDT, if clear GDT. */
4245#define X86_TRAP_ERR_TI 4
4246/** Mask for getting the selector. */
4247#define X86_TRAP_ERR_SEL_MASK 0xfff8
4248/** Shift for getting the selector table index (C type index). */
4249#define X86_TRAP_ERR_SEL_SHIFT 3
4250/** @} */
4251
4252
4253/** @name \#PF Trap Error Codes
4254 * @{
4255 */
4256/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4257#define X86_TRAP_PF_P RT_BIT_32(0)
4258/** Bit 1 - R/W - Read (clear) or write (set) access. */
4259#define X86_TRAP_PF_RW RT_BIT_32(1)
4260/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4261#define X86_TRAP_PF_US RT_BIT_32(2)
4262/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4263#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4264/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4265#define X86_TRAP_PF_ID RT_BIT_32(4)
4266/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4267#define X86_TRAP_PF_PK RT_BIT_32(5)
4268/** @} */
4269
4270#pragma pack(1)
4271/**
4272 * 16-bit IDTR.
4273 */
4274typedef struct X86IDTR16
4275{
4276 /** Offset. */
4277 uint16_t offSel;
4278 /** Selector. */
4279 uint16_t uSel;
4280} X86IDTR16, *PX86IDTR16;
4281#pragma pack()
4282
4283#pragma pack(1)
4284/**
4285 * 32-bit IDTR/GDTR.
4286 */
4287typedef struct X86XDTR32
4288{
4289 /** Size of the descriptor table. */
4290 uint16_t cb;
4291 /** Address of the descriptor table. */
4292#ifndef VBOX_FOR_DTRACE_LIB
4293 uint32_t uAddr;
4294#else
4295 uint16_t au16Addr[2];
4296#endif
4297} X86XDTR32, *PX86XDTR32;
4298#pragma pack()
4299
4300#pragma pack(1)
4301/**
4302 * 64-bit IDTR/GDTR.
4303 */
4304typedef struct X86XDTR64
4305{
4306 /** Size of the descriptor table. */
4307 uint16_t cb;
4308 /** Address of the descriptor table. */
4309#ifndef VBOX_FOR_DTRACE_LIB
4310 uint64_t uAddr;
4311#else
4312 uint16_t au16Addr[4];
4313#endif
4314} X86XDTR64, *PX86XDTR64;
4315#pragma pack()
4316
4317
4318/** @name ModR/M
4319 * @{ */
4320#define X86_MODRM_RM_MASK UINT8_C(0x07)
4321#define X86_MODRM_REG_MASK UINT8_C(0x38)
4322#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4323#define X86_MODRM_REG_SHIFT 3
4324#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4325#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4326#define X86_MODRM_MOD_SHIFT 6
4327#ifndef VBOX_FOR_DTRACE_LIB
4328AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4329AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4330AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4331/** @def X86_MODRM_MAKE
4332 * @param a_Mod The mod value (0..3).
4333 * @param a_Reg The register value (0..7).
4334 * @param a_RegMem The register or memory value (0..7). */
4335# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4336#endif
4337/** @} */
4338
4339/** @name SIB
4340 * @{ */
4341#define X86_SIB_BASE_MASK UINT8_C(0x07)
4342#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4343#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4344#define X86_SIB_INDEX_SHIFT 3
4345#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4346#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4347#define X86_SIB_SCALE_SHIFT 6
4348#ifndef VBOX_FOR_DTRACE_LIB
4349AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4350AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4351AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4352#endif
4353/** @} */
4354
4355/** @name General register indexes.
4356 * @{ */
4357#define X86_GREG_xAX 0
4358#define X86_GREG_xCX 1
4359#define X86_GREG_xDX 2
4360#define X86_GREG_xBX 3
4361#define X86_GREG_xSP 4
4362#define X86_GREG_xBP 5
4363#define X86_GREG_xSI 6
4364#define X86_GREG_xDI 7
4365#define X86_GREG_x8 8
4366#define X86_GREG_x9 9
4367#define X86_GREG_x10 10
4368#define X86_GREG_x11 11
4369#define X86_GREG_x12 12
4370#define X86_GREG_x13 13
4371#define X86_GREG_x14 14
4372#define X86_GREG_x15 15
4373/** @} */
4374/** General register count. */
4375#define X86_GREG_COUNT 16
4376
4377/** @name X86_SREG_XXX - Segment register indexes.
4378 * @{ */
4379#define X86_SREG_ES 0
4380#define X86_SREG_CS 1
4381#define X86_SREG_SS 2
4382#define X86_SREG_DS 3
4383#define X86_SREG_FS 4
4384#define X86_SREG_GS 5
4385/** @} */
4386/** Segment register count. */
4387#define X86_SREG_COUNT 6
4388
4389
4390/** @name X86_OP_XXX - Prefixes
4391 * @{ */
4392#define X86_OP_PRF_CS UINT8_C(0x2e)
4393#define X86_OP_PRF_SS UINT8_C(0x36)
4394#define X86_OP_PRF_DS UINT8_C(0x3e)
4395#define X86_OP_PRF_ES UINT8_C(0x26)
4396#define X86_OP_PRF_FS UINT8_C(0x64)
4397#define X86_OP_PRF_GS UINT8_C(0x65)
4398#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4399#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4400#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4401#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4402#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4403#define X86_OP_REX_B UINT8_C(0x41)
4404#define X86_OP_REX_X UINT8_C(0x42)
4405#define X86_OP_REX_R UINT8_C(0x44)
4406#define X86_OP_REX_W UINT8_C(0x48)
4407/** @} */
4408
4409
4410/** @} */
4411
4412#endif /* !IPRT_INCLUDED_x86_h */
4413
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