/* $Id: bs3-cpu-instr-4.c32 105684 2024-08-15 11:33:35Z vboxsync $ */ /** @file * BS3Kit - bs3-cpu-instr-4 - SSE, AVX FPU instructions, C code template. */ /* * Copyright (C) 2024 Oracle and/or its affiliates. * * This file is part of VirtualBox base platform packages, as * available from https://www.virtualbox.org. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, in version 3 of the * License. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see . * * The contents of this file may alternatively be used under the terms * of the Common Development and Distribution License Version 1.0 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included * in the VirtualBox distribution, in which case the provisions of the * CDDL are applicable instead of those of the GPL. * * You may elect to license modified versions of this file under the * terms and conditions of either the GPL or the CDDL or both. * * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0 */ /********************************************************************************************************************************* * Header Files * *********************************************************************************************************************************/ #include #include "bs3-cpu-instr-4-asm-auto.h" #include #include /********************************************************************************************************************************* * Defined Constants And Macros * *********************************************************************************************************************************/ /** Converts an execution mode (BS3_MODE_XXX) into an index into an array * initialized by BS3CPUINSTR4_TEST1_MODES_INIT etc. */ #define BS3CPUINSTR4_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2) /** Maximum length for the names of all SIMD FP exception flags combined. */ #define FP_XCPT_FLAGS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ") /** Maximum length for the names of all SIMD FP exception masks combined. */ #define FP_XCPT_MASKS_NAMES_MAXLEN sizeof(" IE DE ZE OE UE PE ") /** Maximum length for the names of all SIMD FP exception other bits combined. */ #define FP_XCPT_OTHERS_NAMES_MAXLEN sizeof(" DAZ FZ MM RC=NEAREST ") /* * Single-precision (32 bits) floating-point defines. */ /** The max exponent value for a single-precision floating-point normal. */ #define FP32_EXP_NORM_MAX 254 /** The min exponent value for a single-precision floating-point normal. */ #define FP32_EXP_NORM_MIN 1 /** The max fraction value for a single-precision floating-point normal. */ #define FP32_FRAC_NORM_MAX 0x7fffff /** The min fraction value for a single-precision floating-point normal. */ #define FP32_FRAC_NORM_MIN 0 /** The exponent bias for the single-precision floating-point format. */ #define FP32_EXP_BIAS RTFLOAT32U_EXP_BIAS /** Fraction width (in bits) for the single-precision floating-point format. */ #define FP32_FRAC_BITS RTFLOAT32U_FRACTION_BITS /** The max exponent value for a single-precision floating-point integer without * losing precision. */ #define FP32_EXP_SAFE_INT_MAX FP32_EXP_BIAS + FP32_FRAC_BITS /** The min exponent value for a single-precision floating-point integer without * losing precision. */ #define FP32_EXP_SAFE_INT_MIN 1 /** The max fraction value for a double-precision floating-point denormal. */ #define FP32_FRAC_DENORM_MAX 0x7fffff /** The min fraction value for a double-precision floating-point denormal. */ #define FP32_FRAC_DENORM_MIN 1 #define FP32_NORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_NORM_MAX) #define FP32_NORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN) #define FP32_0(a_Sign) RTFLOAT32U_INIT_ZERO(a_Sign) #define FP32_1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0, RTFLOAT32U_EXP_BIAS) #define FP32_V(a_Sign, a_Frac, a_Exp) RTFLOAT32U_INIT_C(a_Sign, a_Frac, a_Exp) #define FP32_INF(a_Sign) RTFLOAT32U_INIT_INF(a_Sign) #define FP32_QNAN(a_Sign) RTFLOAT32U_INIT_QNAN(a_Sign) #define FP32_QNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val) #define FP32_SNAN(a_Sign) RTFLOAT32U_INIT_SNAN(a_Sign) #define FP32_SNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_SNAN_EX(a_Sign, a_Val) /* * Single-precision floating normals. * Fraction - 23 bits, all usable. * Exponent - 8 bits, least significant bit MBZ. */ #define FP32_FRAC_V0 0x401ac0 #define FP32_FRAC_V1 0x5fcabd #define FP32_FRAC_V2 0x7e117a #define FP32_FRAC_V3 0x5b5b5b #define FP32_FRAC_V4 0x1e0f1f #define FP32_FRAC_V5 0x012345 #define FP32_FRAC_V6 0x330b3b #define FP32_FRAC_V7 0x4ebeb4 #define FP32_EXP_V0 0x78 #define FP32_EXP_V1 0xbc #define FP32_EXP_V2 0x7e #define FP32_EXP_V3 0x9a #define FP32_EXP_V4 0x32 #define FP32_EXP_V5 0x56 #define FP32_EXP_V6 0x90 #define FP32_EXP_V7 0x30 AssertCompile(!(FP32_EXP_V0 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V1 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V2 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V3 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V4 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V5 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V6 & RT_BIT(0))); AssertCompile(!(FP32_EXP_V7 & RT_BIT(0))); #define FP32_NORM_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V0, FP32_EXP_V0) #define FP32_NORM_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V1, FP32_EXP_V1) #define FP32_NORM_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V2, FP32_EXP_V2) #define FP32_NORM_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V3, FP32_EXP_V3) #define FP32_NORM_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V4, FP32_EXP_V4) #define FP32_NORM_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V5, FP32_EXP_V5) #define FP32_NORM_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V6, FP32_EXP_V6) #define FP32_NORM_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_V7, FP32_EXP_V7) /* The maximum integer value (all 23 + 1 implied bit of the fraction part set) without losing precision. */ #define FP32_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX) /* The minimum integer value without losing precision. */ #define FP32_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_SAFE_INT_MIN) /* * Single-precision floating-point denormals. */ /** The maximum denormal value. */ #define FP32_DENORM_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MAX, 0) /** The maximum denormal value. */ #define FP32_DENORM_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_DENORM_MIN, 0) /* * Single-precision random values (incl. potentially invalid values). * We don't care what the exact values are as these are meant to populate * unmodified parts of operands and be compared bitwise. */ #define FP32_RAND_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7bacda, 0x55) #define FP32_RAND_V1(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7010f0, 0xc0) #define FP32_RAND_V2(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x4ffcbe, 0xf1) #define FP32_RAND_V3(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x2fd7c8, 0x1f) #define FP32_RAND_V4(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x5b5b5b, 0x09) #define FP32_RAND_V5(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x3d2d1d, 0x99) #define FP32_RAND_V6(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x123456, 0x5e) #define FP32_RAND_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x05432f, 0xd7) /* * Double-precision (64 bits) floating-point defines. */ /** The max exponent value for a double-precision floating-point normal. */ #define FP64_EXP_NORM_MAX 2046 /** The min exponent value for a double-precision floating-point normal. */ #define FP64_EXP_NORM_MIN 1 /** The max fraction value for a double-precision floating-point normal. */ #define FP64_FRAC_NORM_MAX 0xfffffffffffff /** The min fraction value for a double-precision floating-point normal. */ #define FP64_FRAC_NORM_MIN 0 /** The exponent bias for the double-precision floating-point format. */ #define FP64_EXP_BIAS RTFLOAT64U_EXP_BIAS /** Fraction width (in bits) for the double-precision floating-point format. */ #define FP64_FRAC_BITS RTFLOAT64U_FRACTION_BITS /** The max exponent value for a double-precision floating-point integer without * losing precision. */ #define FP64_EXP_SAFE_INT_MAX FP64_EXP_BIAS + FP64_FRAC_BITS /** The min exponent value for a double-precision floating-point integer without * losing precision. */ #define FP64_EXP_SAFE_INT_MIN 1 /** The max fraction value for a double-precision floating-point denormal. */ #define FP64_FRAC_DENORM_MAX 0xfffffffffffff /** The min fraction value for a double-precision floating-point denormal. */ #define FP64_FRAC_DENORM_MIN 1 #define FP64_NORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX) #define FP64_NORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_NORM_MIN) #define FP64_0(a_Sign) RTFLOAT64U_INIT_ZERO(a_Sign) #define FP64_1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0, RTFLOAT64U_EXP_BIAS) #define FP64_V(a_Sign, a_Frac, a_Exp) RTFLOAT64U_INIT_C(a_Sign, a_Frac, a_Exp) #define FP64_INF(a_Sign) RTFLOAT64U_INIT_INF(a_Sign) #define FP64_QNAN(a_Sign) RTFLOAT64U_INIT_QNAN(a_Sign) #define FP64_QNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val) #define FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign) #define FP64_SNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val) /* * Double-precision random values (incl. potentially invalid values). * We don't care what the exact values are as these are meant to populate * unmodified parts of operands and be compared bitwise. */ #define FP64_RAND_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xab07eb7bcebce, 0x777) #define FP64_RAND_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x2fa17e10b3c7c, 0x6b6) #define FP64_RAND_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xceb1703cbe310, 0x100) #define FP64_RAND_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x7134abcdef10f, 0x70f) /* * Double-precision floating-point normals. * Fraction - 52 bits, all usable. * Exponent - 11 bits, least significant bit MBZ. */ #define FP64_FRAC_V0 0xacc01adec0de5 #define FP64_FRAC_V1 0xf10a7ab1ec01a #define FP64_FRAC_V2 0xca5cadea1b1ed #define FP64_FRAC_V3 0xb5b5b5b5b5b5b #define FP64_EXP_V0 0x30c #define FP64_EXP_V1 0x4bc #define FP64_EXP_V2 0x3ae #define FP64_EXP_V3 0x7fe AssertCompile(!(FP64_EXP_V0 & RT_BIT(0))); AssertCompile(!(FP64_EXP_V1 & RT_BIT(0))); AssertCompile(!(FP64_EXP_V2 & RT_BIT(0))); AssertCompile(!(FP64_EXP_V3 & RT_BIT(0))); #define FP64_NORM_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V0, FP64_EXP_V0) #define FP64_NORM_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V1, FP64_EXP_V1) #define FP64_NORM_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V2, FP64_EXP_V2) #define FP64_NORM_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_V3, FP64_EXP_V3) /* The maximum integer value (all 52 + 1 implied bit of the fraction part set) without losing precision. */ #define FP64_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX) /* The minimum integer value without losing precision. */ #define FP64_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_SAFE_INT_MIN) /* * Double-precision floating-point denormals. */ /** The maximum denormal value. */ #define FP64_DENORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MAX, 0) /** The maximum denormal value. */ #define FP64_DENORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MIN, 0) /********************************************************************************************************************************* * Structures and Typedefs * *********************************************************************************************************************************/ /** Instruction set type and operand width. */ typedef enum BS3CPUINSTRX_INSTRTYPE_T { T_INVALID, T_MMX, T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */ T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */ T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */ T_AXMMX, T_AXMMX_OR_SSE, T_SSE, T_128BITS = T_SSE, T_SSE2, T_SSE3, T_SSSE3, T_SSE4_1, T_SSE4_2, T_SSE4A, T_PCLMUL, T_SHA, T_AVX_128, T_AVX2_128, T_AVX_PCLMUL, T_AVX_256, T_256BITS = T_AVX_256, T_AVX2_256, T_MAX } BS3CPUINSTRX_INSTRTYPE_T; /** Memory or register rm variant. */ enum { RM_REG = 0, RM_MEM, RM_MEM8, /**< Memory operand is 8 bytes. Hack for movss and similar. */ RM_MEM16, /**< Memory operand is 16 bytes. Hack for movss and similar. */ RM_MEM32, /**< Memory operand is 32 bytes. Hack for movss and similar. */ RM_MEM64 /**< Memory operand is 64 bytes. Hack for movss and similar. */ }; /** * Execution environment configuration. */ typedef struct BS3CPUINSTR4_CONFIG_T { uint16_t fCr0Mp : 1; uint16_t fCr0Em : 1; uint16_t fCr0Ts : 1; uint16_t fCr4OsFxSR : 1; uint16_t fCr4OsXSave : 1; uint16_t fCr4OsXmmExcpt : 1; uint16_t fXcr0Sse : 1; uint16_t fXcr0Avx : 1; uint16_t fAligned : 1; /**< Aligned mem operands. If 0, they will be misaligned and tests w/o mem operands skipped. */ uint16_t fAlignCheck : 1; uint16_t fMxCsrMM : 1; /**< AMD only */ uint8_t bXcptSse; uint8_t bXcptAvx; } BS3CPUINSTR4_CONFIG_T; /** Pointer to an execution environment configuration. */ typedef BS3CPUINSTR4_CONFIG_T const BS3_FAR *PCBS3CPUINSTR4_CONFIG_T; /** State saved by bs3CpuInstr4ConfigReconfigure. */ typedef struct BS3CPUINSTRX_CONFIG_SAVED_T { uint32_t uCr0; uint32_t uCr4; uint32_t uEfl; uint16_t uFcw; uint16_t uFsw; uint32_t uMxCsr; } BS3CPUINSTRX_CONFIG_SAVED_T; typedef BS3CPUINSTRX_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTRX_CONFIG_SAVED_T; typedef BS3CPUINSTRX_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTRX_CONFIG_SAVED_T; /** * YMM packed single-precision floating-point register. * @todo move to x86.h? */ typedef union X86YMMFLOATPSREG { /** Packed single-precision floating-point view. */ RTFLOAT32U ar32[8]; /** 256-bit integer view. */ RTUINT256U ymm; } X86YMMFLOATPSREG; # ifndef VBOX_FOR_DTRACE_LIB AssertCompileSize(X86YMMFLOATPSREG, 32); AssertCompileSize(X86YMMFLOATPSREG, sizeof(X86YMMREG)); # endif /** Pointer to a YMM packed single-precision floating-point register. */ typedef X86YMMFLOATPSREG BS3_FAR *PX86YMMFLOATPSREG; /** Pointer to a const YMM single-precision packed floating-point register. */ typedef X86YMMFLOATPSREG const BS3_FAR *PCX86YMMFLOATPSREG; /** * YMM packed double-precision floating-point register. * @todo move to x86.h? */ typedef union X86YMMFLOATPDREG { /** Packed double-precision floating-point view. */ RTFLOAT64U ar64[4]; /** 256-bit integer view. */ RTUINT256U ymm; } X86YMMFLOATPDREG; # ifndef VBOX_FOR_DTRACE_LIB AssertCompileSize(X86YMMFLOATPDREG, 32); AssertCompileSize(X86YMMFLOATPDREG, sizeof(X86YMMREG)); # endif /** Pointer to a YMM packed floating-point register. */ typedef X86YMMFLOATPDREG BS3_FAR *PX86YMMFLOATPDREG; /** Pointer to a const YMM packed floating-point register. */ typedef X86YMMFLOATPDREG const BS3_FAR *PCX86YMMFLOATPDREG; /** * YMM scalar single-precision floating-point register. * @todo move to x86.h? */ typedef union X86YMMFLOATSSREG { /** Scalar single-precision floating-point view. */ RTFLOAT32U ar32[8]; /** 256-bit integer view. */ RTUINT256U ymm; } X86YMMFLOATSSREG; # ifndef VBOX_FOR_DTRACE_LIB AssertCompileSize(X86YMMFLOATSSREG, 32); AssertCompileSize(X86YMMFLOATSSREG, sizeof(X86YMMREG)); # endif /** Pointer to a YMM scalar single-precision floating-point register. */ typedef X86YMMFLOATSSREG BS3_FAR *PX86YMMFLOATSSREG; /** Pointer to a const YMM scalar single-precision floating-point register. */ typedef X86YMMFLOATSSREG const BS3_FAR *PCX86YMMFLOATSSREG; /** * YMM scalar double-precision floating-point register. * @todo move to x86.h? */ typedef union X86YMMFLOATSDREG { /** Scalar double-precision floating-point view. */ RTFLOAT64U ar64[4]; /** 256-bit integer view. */ RTUINT256U ymm; } X86YMMFLOATSDREG; # ifndef VBOX_FOR_DTRACE_LIB AssertCompileSize(X86YMMFLOATSDREG, 32); AssertCompileSize(X86YMMFLOATSDREG, sizeof(X86YMMREG)); # endif /** Pointer to a YMM scalar double-precision floating-point register. */ typedef X86YMMFLOATSDREG BS3_FAR *PX86YMMFLOATSDREG; /** Pointer to a const YMM scalar double-precision floating-point register. */ typedef X86YMMFLOATSDREG const BS3_FAR *PCX86YMMFLOATSDREG; /** * YMM scalar quadruple-precision floating-point register. * @todo move to x86.h? */ typedef union X86YMMFLOATSQREG { /** Scalar quadruple-precision floating point view. */ RTFLOAT128U ar128[2]; /** 256-bit integer view. */ RTUINT256U ymm; } X86YMMFLOATSQREG; # ifndef VBOX_FOR_DTRACE_LIB AssertCompileSize(X86YMMFLOATSQREG, 32); AssertCompileSize(X86YMMFLOATSQREG, sizeof(X86YMMREG)); # endif /** Pointer to a YMM scalar quadruple-precision floating-point register. */ typedef X86YMMFLOATSQREG *PX86YMMFLOATSQREG; /** Pointer to a const YMM scalar quadruple-precision floating-point register. */ typedef X86YMMFLOATSQREG const *PCX86YMMFLOATSQREG; /********************************************************************************************************************************* * Global Variables * *********************************************************************************************************************************/ static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false }; static bool g_fAmdMisalignedSse = false; static uint8_t g_enmExtCtxMethod = BS3EXTCTXMETHOD_INVALID; static bool g_fMxCsrDazSupported = false; /** Size of g_pbBuf - at least three pages. */ static uint32_t g_cbBuf; /** Buffer of g_cbBuf size. */ static uint8_t BS3_FAR *g_pbBuf; /** RW alias for the buffer memory at g_pbBuf. Set up by bs3CpuInstrXBufSetup. */ static uint8_t BS3_FAR *g_pbBufAlias; /** RW alias for the memory at g_pbBuf. */ static uint8_t BS3_FAR *g_pbBufAliasAlloc; /** Exception type \#2 test configurations, 16 & 32 bytes strictly aligned. */ static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig2[] = { /* * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to * +AVX +AVX +AMD/SSE +AMD/SSE * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */ { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */ { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */ { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */ { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */ { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_GP, X86_XCPT_DB }, /* #11 */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */ }; /** Exception type \#3 test configurations (< 16-byte memory argument). */ static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig3[] = { /* * X87 SSE SSE SSE AVX SSE AVX AVX SSE AVX AMD/SSE <-- applies to * +AVX +AVX +AMD/SSE +AMD/SSE * CR0 CR0 CR0 CR4 CR4 CR4 XCR0 XCR0 MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX, fAligned, AC/AM, MM, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ { 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ { 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #2 */ { 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #3 */ { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM }, /* #4 */ { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_NM }, /* #5 */ { 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_DB }, /* #6 */ { 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD }, /* #9 */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */ /* [Avx]:AC */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */ { 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */ }; /** * Returns the name of an X86 exception given the vector. * * @returns Name of the exception. * @param uVector The exception vector. */ static const char BS3_FAR *bs3CpuInstr4XcptName(uint8_t uVector) { switch (uVector) { case X86_XCPT_DE: return "#DE"; case X86_XCPT_DB: return "#DB"; case X86_XCPT_NMI: return "#NMI"; case X86_XCPT_BP: return "#BP"; case X86_XCPT_OF: return "#OF"; case X86_XCPT_BR: return "#BR"; case X86_XCPT_UD: return "#UD"; case X86_XCPT_NM: return "#NM"; case X86_XCPT_DF: return "#DF"; case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN"; case X86_XCPT_TS: return "#TS"; case X86_XCPT_NP: return "#NP"; case X86_XCPT_SS: return "#SS"; case X86_XCPT_GP: return "#GP"; case X86_XCPT_PF: return "#PF"; case X86_XCPT_MF: return "#MF"; case X86_XCPT_AC: return "#AC"; case X86_XCPT_MC: return "#MC"; case X86_XCPT_XF: return "#XF"; case X86_XCPT_VE: return "#VE"; case X86_XCPT_CP: return "#CP"; case X86_XCPT_VC: return "#VC"; case X86_XCPT_SX: return "#SX"; } return "UNKNOWN"; } DECL_FORCE_INLINE(bool) bs3CpuInstr4IsSse(uint8_t enmType) { return enmType >= T_SSE && enmType < T_AVX_128; } DECL_FORCE_INLINE(bool) bs3CpuInstr4IsAvx(uint8_t enmType) { return enmType >= T_AVX_128; } DECL_FORCE_INLINE(uint8_t) bs3CpuInstr4GetOperandSize(uint8_t enmType) { return enmType < T_128BITS ? 64/8 : enmType < T_256BITS ? 128/8 : 256/8; } /** * Gets the names of floating-point exception flags that are set for a given MXCSR. * * @returns Names of floating-point exception flags that are set. * @param pszBuf Where to store the floating-point exception flags. * @param cchBuf The size of the buffer. * @param uMxCsr The MXCSR value. */ static size_t bs3CpuInstr4GetXcptFlags(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr) { BS3_ASSERT(cchBuf >= FP_XCPT_FLAGS_NAMES_MAXLEN); return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IE ? " IE" : "", uMxCsr & X86_MXCSR_DE ? " DE" : "", uMxCsr & X86_MXCSR_ZE ? " ZE" : "", uMxCsr & X86_MXCSR_OE ? " OE" : "", uMxCsr & X86_MXCSR_UE ? " UE" : "", uMxCsr & X86_MXCSR_PE ? " PE" : ""); } /** * Gets the names of floating-point exception mask that are set for a given MXCSR. * * @returns Names of floating-point exception flags that are set. * @param pszBuf Where to store the floating-point exception flags. * @param cchBuf The size of the buffer. * @param uMxCsr The MXCSR value. */ static size_t bs3CpuInstr4GetXcptMasks(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr) { BS3_ASSERT(cchBuf >= FP_XCPT_MASKS_NAMES_MAXLEN); return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", uMxCsr & X86_MXCSR_IM ? " IM" : "", uMxCsr & X86_MXCSR_DM ? " DM" : "", uMxCsr & X86_MXCSR_ZM ? " ZM" : "", uMxCsr & X86_MXCSR_OM ? " OM" : "", uMxCsr & X86_MXCSR_UM ? " UM" : "", uMxCsr & X86_MXCSR_PM ? " PM" : ""); } /** * Gets the names of floating-point bits other than flags and masks that are set for * a given MXCSR. * * @returns Names of floating-point exception flags that are set. * @param pszBuf Where to store the floating-point exception flags. * @param cchBuf The size of the buffer. * @param uMxCsr The MXCSR value. */ static size_t bs3CpuInstr4GetXcptOthers(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t uMxCsr) { uint32_t const fMxCsrRc = uMxCsr & X86_MXCSR_RC_MASK; BS3_ASSERT(cchBuf >= FP_XCPT_OTHERS_NAMES_MAXLEN); return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s", uMxCsr & X86_MXCSR_DAZ ? " DAZ" : "", uMxCsr & X86_MXCSR_FZ ? " FZ" : "", uMxCsr & X86_MXCSR_MM ? " MM" : "", fMxCsrRc == X86_MXCSR_RC_NEAREST ? " RC=NEAREST" : fMxCsrRc == X86_MXCSR_RC_DOWN ? " RC=DOWN" : fMxCsrRc == X86_MXCSR_RC_UP ? " RC=UP" : fMxCsrRc == X86_MXCSR_RC_ZERO ? " RC=ZERO" : ""); } /** * Reconfigures the execution environment according to @a pConfig. * * Call bs3CpuInstrXConfigRestore to undo the changes. * * @returns true on success, false if the configuration cannot be applied. In * the latter case, no context changes are made. * @param pSavedCfg Where to save state we modify. * @param pCtx The register context to modify. * @param pExtCtx The extended register context to modify. * @param pConfig The configuration to apply. * @param bMode The target mode. */ static bool bs3CpuInstr4ConfigReconfigure(PBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx, PCBS3CPUINSTR4_CONFIG_T pConfig, uint8_t bMode) { /* * Save context bits we may change here */ pSavedCfg->uCr0 = pCtx->cr0.u32; pSavedCfg->uCr4 = pCtx->cr4.u32; pSavedCfg->uEfl = pCtx->rflags.u32; pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx); pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx); pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx); /* * Can we make these changes? */ if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse) return false; /* * Modify the test context. */ if (pConfig->fCr0Mp) pCtx->cr0.u32 |= X86_CR0_MP; else pCtx->cr0.u32 &= ~X86_CR0_MP; if (pConfig->fCr0Em) pCtx->cr0.u32 |= X86_CR0_EM; else pCtx->cr0.u32 &= ~X86_CR0_EM; if (pConfig->fCr0Ts) pCtx->cr0.u32 |= X86_CR0_TS; else pCtx->cr0.u32 &= ~X86_CR0_TS; if (pConfig->fCr4OsFxSR) pCtx->cr4.u32 |= X86_CR4_OSFXSR; else pCtx->cr4.u32 &= ~X86_CR4_OSFXSR; if (pConfig->fCr4OsXmmExcpt && g_afTypeSupports[T_SSE]) pCtx->cr4.u32 |= X86_CR4_OSXMMEEXCPT; else pCtx->cr4.u32 &= ~X86_CR4_OSXMMEEXCPT; if (pConfig->fCr4OsFxSR) pCtx->cr4.u32 |= X86_CR4_OSFXSR; else pCtx->cr4.u32 &= ~X86_CR4_OSFXSR; if (pConfig->fCr4OsXSave) pCtx->cr4.u32 |= X86_CR4_OSXSAVE; else pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE; if (pConfig->fXcr0Sse) pExtCtx->fXcr0Saved |= XSAVE_C_SSE; else pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE; if (pConfig->fXcr0Avx && g_afTypeSupports[T_AVX_256]) pExtCtx->fXcr0Saved |= XSAVE_C_YMM; else pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM; if (pConfig->fAlignCheck) { pCtx->rflags.u32 |= X86_EFL_AC; pCtx->cr0.u32 |= X86_CR0_AM; } else { pCtx->rflags.u32 &= ~X86_EFL_AC; pCtx->cr0.u32 &= ~X86_CR0_AM; } /** @todo Can we remove this? x87 FPU and SIMD are independent. */ Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B)); if (pConfig->fMxCsrMM) Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM); else Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM); return true; } /** * Undoes changes made by bs3CpuInstr4ConfigReconfigure. */ static void bs3CpuInstrXConfigRestore(PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx) { pCtx->cr0.u32 = pSavedCfg->uCr0; pCtx->cr4.u32 = pSavedCfg->uCr4; pCtx->rflags.u32 = pSavedCfg->uEfl; pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal; Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw); Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw); Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr); } /** * Allocates three extended CPU contexts and initializes the first one * with random data. * @returns First extended context, initialized with randomish data. NULL on * failure (complained). * @param ppExtCtx2 Where to return the 2nd context. */ static PBS3EXTCTX bs3CpuInstrXAllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2) { /* Allocate extended context structures. */ uint64_t fFlags; uint16_t cb = Bs3ExtCtxGetSize(&fFlags); PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2); PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb); if (pExtCtx1) { Bs3ExtCtxInit(pExtCtx1, cb, fFlags); /** @todo populate with semi-random stuff. */ Bs3ExtCtxInit(pExtCtx2, cb, fFlags); *ppExtCtx2 = pExtCtx2; return pExtCtx1; } Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2); *ppExtCtx2 = NULL; return NULL; } /** * Frees the extended CPU contexts allocated by bs3CpuInstrXAllocExtCtxs. * * @param pExtCtx1 The first extended context. * @param pExtCtx2 The second extended context. */ static void bs3CpuInstrXFreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2) { RT_NOREF_PV(pExtCtx2); Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2); } /** * Sets up SSE and AVX bits relevant for FPU instructions. */ static void bs3CpuInstr4SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx) { /* CR0: */ uint32_t cr0 = Bs3RegGetCr0(); cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM); cr0 |= X86_CR0_NE; Bs3RegSetCr0(cr0); /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */ pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM); pCtx->cr0.u32 |= X86_CR0_NE; /* CR4: */ BS3_ASSERT( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE || pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE); { uint32_t cr4 = Bs3RegGetCr4(); if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE) { cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE; Bs3RegSetCr4(cr4); Bs3RegSetXcr0(pExtCtx->fXcr0Nominal); } else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE) { cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT; Bs3RegSetCr4(cr4); } pCtx->cr4.u32 = cr4; } } /** * Configures the buffer with electric fences in paged modes. * * @returns Adjusted buffer pointer. * @param pbBuf The buffer pointer. * @param pcbBuf Pointer to the buffer size (input & output). * @param bMode The testing target mode. */ DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode) { if (BS3_MODE_IS_PAGED(bMode)) { int rc; uint32_t cbBuf = *pcbBuf; Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P); Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P); pbBuf += X86_PAGE_SIZE; cbBuf -= X86_PAGE_SIZE * 2; *pcbBuf = cbBuf; g_pbBufAlias = g_pbBufAliasAlloc; rc = Bs3PagingAlias((uintptr_t)g_pbBufAlias, (uintptr_t)pbBuf, cbBuf + X86_PAGE_SIZE, /* must include the tail guard pg */ X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW); if (RT_FAILURE(rc)) Bs3TestFailedF("Bs3PagingAlias failed on %p/%p LB %#x: %d", g_pbBufAlias, pbBuf, cbBuf, rc); } else g_pbBufAlias = pbBuf; return pbBuf; } /** * Undoes what bs3CpuInstrXBufSetup did. * * @param pbBuf The buffer pointer. * @param cbBuf The buffer size. * @param bMode The testing target mode. */ DECLINLINE(void) bs3CpuInstrXBufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode) { if (BS3_MODE_IS_PAGED(bMode)) { Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0); Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0); } } /** * Gets a buffer of a @a cbMemOp sized operand according to the given * configuration and alignment restrictions. * * @returns Pointer to the buffer. * @param pbBuf The buffer pointer. * @param cbBuf The buffer size. * @param cbMemOp The operand size. * @param cbAlign The operand alignment restriction. * @param pConfig The configuration. * @param fPageFault The \#PF test setting. */ DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstrXBufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign, PCBS3CPUINSTR4_CONFIG_T pConfig, unsigned fPageFault) { /* All allocations are at the tail end of the buffer, so that we've got a guard page following the operand. When asked to consistenly trigger a #PF, we slide the buffer into that guard page. */ if (fPageFault) cbBuf += X86_PAGE_SIZE; if (pConfig->fAligned) { if (!pConfig->fAlignCheck) return &pbBuf[cbBuf - cbMemOp]; return &pbBuf[cbBuf - cbMemOp - cbAlign]; } return &pbBuf[cbBuf - cbMemOp - 1]; } /** * Determines the size of memory operands. */ DECLINLINE(uint8_t) bs3CpuInstrXMemOpSize(uint8_t cbOperand, uint8_t enmRm) { if (enmRm <= RM_MEM) return cbOperand; if (enmRm == RM_MEM8) return sizeof(uint8_t); if (enmRm == RM_MEM16) return sizeof(uint16_t); if (enmRm == RM_MEM32) return sizeof(uint32_t); if (enmRm == RM_MEM64) return sizeof(uint64_t); BS3_ASSERT(0); return cbOperand; } /* * Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly * skips a large fraction of the micro-tests. It is sufficiently random * that over a large number of runs, all micro-tests will be hit. * * This improves the runtime of the worst case (`#define ALL_TESTS' on a * debug build, run with '--execute-all-in-iem') from ~9000 to ~800 seconds * (on an Intel Core i7-10700, fwiw). * * To activate this 'developer's speed-testing mode', turn on * `#define BS3_SKIPIT_DO_SKIP' here. * * BS3_SKIPIT_AVG_SKIP governs approximately how many micro-tests are * skipped in a row; e.g. the default of 26 means about every 27th * micro-test is run during a particular test run. (This is not 27x * faster due to other activities which are not skipped!) Note this is * only an average; the actual skips are random. * * You can also modify bs3CpuInstrX_SkipIt() to focus on specific sub-tests, * using its (currently ignored) `bRing, iCfg, iTest, iVal, iVariant' args * (to enable this: turn on `#define BS3_SKIPIT_DO_ARGS': which costs about * 3% performance). * * Note! The skipping is not compatible with testing the native recompiler as * it requires the test code to be run a number of times before it kicks * in and does the native recompilation (currently around 16 times). */ #define BS3_SKIPIT_AVG_SKIP 26 #define BS3_SKIPIT_REPORT_COUNT 150000 #undef BS3_SKIPIT_DO_SKIP #undef BS3_SKIPIT_DO_ARGS #ifndef BS3_SKIPIT_DO_SKIP # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) (false) #else # include # include DECLINLINE(uint32_t) bs3CpuInstrX_SimpleRand(void) { /* * A simple Lehmer linear congruential pseudo-random number * generator using the constants suggested by Park & Miller: * * modulus = 2^31 - 1 (INT32_MAX) * multiplier = 7^5 (16807) * * It produces numbers in the range [1..INT32_MAX-1] and is * more chaotic in the higher bits. * * Note! Runtime/common/rand/randparkmiller.cpp is also use this algorithm, * though the zero handling is different. */ static uint32_t s_uSeedMemory = 0; uint32_t uVal = s_uSeedMemory; if (!uVal) uVal = (uint32_t)ASMReadTSC(); uVal = ASMModU64ByU32RetU32(ASMMult2xU32RetU64(uVal, 16807), INT32_MAX); s_uSeedMemory = uVal; return uVal; } static unsigned g_cSeen, g_cSkipped; static void bs3CpuInstrX_ShowTallies(void) { Bs3TestPrintf("Micro-tests %d: tested %d / skipped %d\n", g_cSeen, g_cSeen - g_cSkipped, g_cSkipped); } # ifdef BS3_SKIPIT_DO_ARGS # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt(bRing, iCfg, iTest, iVal, iVariant) static bool bs3CpuInstrX_SkipIt(uint8_t bRing, unsigned iCfg, unsigned iTest, unsigned iVal, unsigned iVariant) # else # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt() static bool bs3CpuInstrX_SkipIt(void) # endif { static unsigned s_uTimes = 0; bool fSkip; /* Cache calls to the relatively expensive random routine */ if (!s_uTimes) s_uTimes = bs3CpuInstrX_SimpleRand() % (BS3_SKIPIT_AVG_SKIP * 2 + 1) + 1; fSkip = --s_uTimes > 0; if (fSkip) ++g_cSkipped; if (++g_cSeen % BS3_SKIPIT_REPORT_COUNT == 0) bs3CpuInstrX_ShowTallies(); return fSkip; } #endif /* BS3_SKIPIT_DO_SKIP */ /* * Test type #1. * Generic YMM registers. */ typedef struct BS3CPUINSTR4_TEST1_VALUES_T { X86YMMREG uSrc2; /**< Second source operand. */ X86YMMREG uSrc1; /**< uDstIn for SSE */ X86YMMREG uDstOut; /**< Destination output. */ uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ uint8_t afPadding[2]; /**< Alignment padding. */ } BS3CPUINSTR4_TEST1_VALUES_T; /* * Test type #1. * Packed single-precision. */ typedef struct BS3CPUINSTR4_TEST1_VALUES_PS_T { X86YMMFLOATPSREG uSrc2; /**< Second source operand. */ X86YMMFLOATPSREG uSrc1; /**< uDstIn for SSE */ X86YMMFLOATPSREG uDstOut; /**< Destination output. */ uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ uint8_t afPadding[2]; /**< Alignment padding. */ } BS3CPUINSTR4_TEST1_VALUES_PS_T; AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); /* * Test type #1. * Packed double-precision. */ typedef struct BS3CPUINSTR4_TEST1_VALUES_PD_T { X86YMMFLOATPDREG uSrc2; /**< Second source operand. */ X86YMMFLOATPDREG uSrc1; /**< uDstIn for SSE */ X86YMMFLOATPDREG uDstOut; /**< Destination output. */ uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ uint8_t afPadding[2]; /**< Alignment padding. */ } BS3CPUINSTR4_TEST1_VALUES_PD_T; AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); /* * Test type #1. * Scalar single-precision. */ typedef struct BS3CPUINSTR4_TEST1_VALUES_SS_T { X86YMMFLOATSSREG uSrc2; /**< Second source operand. */ X86YMMFLOATSSREG uSrc1; /**< uDstIn for SSE */ X86YMMFLOATSSREG uDstOut; /**< Destination output. */ uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ uint8_t afPadding[2]; /**< Alignment padding. */ } BS3CPUINSTR4_TEST1_VALUES_SS_T; AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); /* * Test type #1. * Scalar double-precision. */ typedef struct BS3CPUINSTR4_TEST1_VALUES_SD_T { X86YMMFLOATSDREG uSrc2; /**< Second source operand. */ X86YMMFLOATSDREG uSrc1; /**< uDstIn for SSE */ X86YMMFLOATSDREG uDstOut; /**< Destination output. */ uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ uint8_t afPadding[2]; /**< Alignment padding. */ } BS3CPUINSTR4_TEST1_VALUES_SD_T; AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); /* * Test type #1. * Scalar quadruple-precision. */ typedef struct BS3CPUINSTR4_TEST1_VALUES_SQ_T { X86YMMFLOATSQREG uSrc2; /**< Second source operand. */ X86YMMFLOATSQREG uSrc1; /**< uDstIn for SSE */ X86YMMFLOATSQREG uDstOut; /**< Destination output. */ uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ uint8_t afPadding[2]; /**< Alignment padding. */ } BS3CPUINSTR4_TEST1_VALUES_SQ_T; AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SQ_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); typedef struct BS3CPUINSTR4_TEST1_T { FPFNBS3FAR pfnWorker; /**< Test function worker. */ uint8_t bAvxMisalignXcpt; /**< AVX misalignment exception. */ uint8_t enmRm; /**< R/M type. */ uint8_t enmType; /**< CPU instruction type (see T_XXX). */ uint8_t iRegDst; /**< Index of destination register, UINT8_MAX if N/A. */ uint8_t iRegSrc1; /**< Index of first source register, UINT8_MAX if N/A. */ uint8_t iRegSrc2; /**< Index of second source register, UINT8_MAX if N/A. */ uint8_t cValues; /**< Number of test values in @c paValues. */ BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *paValues; /**< Test values. */ } BS3CPUINSTR4_TEST1_T; typedef struct BS3CPUINSTR4_TEST1_MODE_T { BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR4_TEST1_MODE_T; /** Initializer for a BS3CPUINSTR4_TEST1_MODE_T array (three entries). */ #define BS3CPUINSTR4_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } typedef struct BS3CPUINSTR4_TEST1_CTX_T { BS3CPUINSTR4_CONFIG_T const BS3_FAR *pConfig; /**< The test execution environment configuration. */ BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest; /**< The instruction being tested. */ unsigned iVal; /**< Which iteration of the test value is this. */ const char BS3_FAR *pszMode; /**< The testing mode (e.g. real, protected, paged and permutations). */ PBS3TRAPFRAME pTrapFrame; /**< The exception (trap) frame. */ PBS3REGCTX pCtx; /**< The general-purpose register context. */ PBS3EXTCTX pExtCtx; /**< The extended (FPU) register context. */ PBS3EXTCTX pExtCtxOut; /**< The output extended (FPU) register context. */ uint8_t BS3_FAR *puMemOp; /**< The memory operand buffer. */ uint8_t BS3_FAR *puMemOpAlias; /**< The memory operand alias buffer for comparing result. */ uint8_t cbMemOp; /**< Size of the memory operand (and alias) buffer in bytes. */ uint8_t cbOperand; /**< Size of the instruction operand (8 for MMX, 16 for SSE etc). */ uint8_t cbInstr; /**< Size of the instruction opcode. */ uint8_t bXcptExpect; /**< The expected exception while/after executing the instruction. */ uint16_t idTestStep; /**< The test iteration step. */ } BS3CPUINSTR4_TEST1_CTX_T; /** Pointer to a test 1 context. */ typedef BS3CPUINSTR4_TEST1_CTX_T BS3_FAR *PBS3CPUINSTR4_TEST1_CTX_T; /** * Worker for bs3CpuInstr4_WorkerTestType1. */ static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx, PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg) { BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = pTestCtx->pTest; BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal]; PBS3TRAPFRAME pTrapFrame = pTestCtx->pTrapFrame; PBS3REGCTX pCtx = pTestCtx->pCtx; PBS3EXTCTX pExtCtx = pTestCtx->pExtCtx; PBS3EXTCTX pExtCtxOut = pTestCtx->pExtCtxOut; uint8_t BS3_FAR *puMemOp = pTestCtx->puMemOp; uint8_t BS3_FAR *puMemOpAlias = pTestCtx->puMemOpAlias; uint8_t cbMemOp = pTestCtx->cbMemOp; uint8_t const cbOperand = pTestCtx->cbOperand; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)pTestCtx->pTest->pfnWorker)[-1]; uint8_t bXcptExpect = pTestCtx->bXcptExpect; uint8_t const bFpXcpt = pTestCtx->pConfig->fCr4OsXmmExcpt ? X86_XCPT_XF : X86_XCPT_UD; bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType); uint32_t uMxCsr; X86YMMREG MemOpExpect; uint16_t cErrors; uint32_t uExpectedMxCsr; bool fFpXcptExpected; /* * An exception may be raised based on the test value (128 vs 256 bits). * In addition, we allow setting the exception flags (and mask) prior to * executing the instruction, so we cannot use the exception flags to figure * out if an exception will be raised. Hence, the input values provide us * explicitly whether an exception is expected for 128 and 256-bit variants. */ if (pTestCtx->cbOperand > 16) { uExpectedMxCsr = pValues->u256ExpectedMxCsr; fFpXcptExpected = pValues->f256FpXcptExpected; } else { uExpectedMxCsr = pValues->u128ExpectedMxCsr; fFpXcptExpected = pValues->f128FpXcptExpected; } /* * Set up the context and some expectations. */ /* Destination. */ Bs3MemZero(&MemOpExpect, sizeof(MemOpExpect)); if (pTest->iRegDst == UINT8_MAX) { BS3_ASSERT(pTest->enmRm >= RM_MEM); Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp); if (bXcptExpect == X86_XCPT_DB) MemOpExpect.ymm = pValues->uDstOut.ymm; else Bs3MemSet(&MemOpExpect, 0xcc, sizeof(MemOpExpect)); } /* Source #1 (/ destination for SSE). */ if (pTest->iRegSrc1 == UINT8_MAX) { BS3_ASSERT(pTest->enmRm >= RM_MEM); Bs3MemCpy(puMemOpAlias, &pValues->uSrc1, cbMemOp); if (pTest->iRegDst == UINT8_MAX) BS3_ASSERT(fSseInstr); else MemOpExpect.ymm = pValues->uSrc1.ymm; } else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm, 32); /* Source #2. */ if (pTest->iRegSrc2 == UINT8_MAX) { BS3_ASSERT(pTest->enmRm >= RM_MEM); BS3_ASSERT(pTest->iRegDst != UINT8_MAX && pTest->iRegSrc1 != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &pValues->uSrc2, cbMemOp); MemOpExpect.ymm = pValues->uSrc2.ymm; } else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm, 32); /* Memory pointer. */ if (pTest->enmRm >= RM_MEM) { BS3_ASSERT( pTest->iRegDst == UINT8_MAX || pTest->iRegSrc1 == UINT8_MAX || pTest->iRegSrc2 == UINT8_MAX); Bs3RegCtxSetGrpSegFromCurPtr(pCtx, &pCtx->rbx, &pCtx->fs, puMemOp); } /* Setup MXCSR for the current test. */ uMxCsr = (pSavedCfg->uMxCsr & X86_MXCSR_MM) | pValues->uMxCsr; BS3_ASSERT(!(uMxCsr & X86_MXCSR_MM)); BS3_ASSERT(!(uMxCsr & X86_MXCSR_DAZ) || g_fMxCsrDazSupported); Bs3ExtCtxSetMxCsr(pExtCtx, uMxCsr); /* * Prepare globals and execute. */ g_uBs3TrapEipHint = pCtx->rip.u32; if ( bXcptExpect == X86_XCPT_DB && !fFpXcptExpected) g_uBs3TrapEipHint += cbInstr + 1; Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut); /* * Check the result. * * If a floating-point exception is expected, the destination is not updated by the instruction. * In the case of SSE instructions, updating the destination here will work because it is the same * as the source, but for AVX++ it won't because the destination is different and would contain 0s. */ cErrors = Bs3TestSubErrorCount(); if ( bXcptExpect == X86_XCPT_DB && !fFpXcptExpected && pTest->iRegDst != UINT8_MAX) { if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm, cbOperand); } #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; #endif if (bXcptExpect == X86_XCPT_DB) Bs3ExtCtxSetMxCsr(pExtCtx, uExpectedMxCsr | (pSavedCfg->uMxCsr & X86_MXCSR_MM)); Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pTestCtx->pszMode, pTestCtx->idTestStep); if (bXcptExpect == X86_XCPT_DB) { uint32_t const uGotMxCsr = Bs3ExtCtxGetMxCsr(pExtCtxOut) & ~X86_MXCSR_MM; /* Check if the SIMD FP exception flags and mask (or lack of) are as expected. */ if (uGotMxCsr != uExpectedMxCsr) { char szExpectFlags[FP_XCPT_FLAGS_NAMES_MAXLEN]; char szExpectMasks[FP_XCPT_MASKS_NAMES_MAXLEN]; char szExpectOthers[FP_XCPT_OTHERS_NAMES_MAXLEN]; char szGotFlags[FP_XCPT_FLAGS_NAMES_MAXLEN]; char szGotMasks[FP_XCPT_MASKS_NAMES_MAXLEN]; char szGotOthers[FP_XCPT_OTHERS_NAMES_MAXLEN]; bs3CpuInstr4GetXcptFlags(&szExpectFlags[0], sizeof(szExpectFlags), uExpectedMxCsr); bs3CpuInstr4GetXcptMasks(&szExpectMasks[0], sizeof(szExpectMasks), uExpectedMxCsr); bs3CpuInstr4GetXcptOthers(&szExpectOthers[0], sizeof(szExpectOthers), uExpectedMxCsr); bs3CpuInstr4GetXcptFlags(&szGotFlags[0], sizeof(szGotFlags), uGotMxCsr); bs3CpuInstr4GetXcptMasks(&szGotMasks[0], sizeof(szGotMasks), uGotMxCsr); bs3CpuInstr4GetXcptOthers(&szGotOthers[0], sizeof(szGotOthers), uGotMxCsr); Bs3TestFailedF("Expected MXCSR %#RX32 (%s%s%s ) got MXCSR %#RX32 (%s%s%s )", uExpectedMxCsr, szExpectFlags, szExpectMasks, szExpectOthers, uGotMxCsr, szGotFlags, szGotMasks, szGotOthers); } /* Check if the SIMD FP exception (or lack of) is as expected. */ if (fFpXcptExpected) { if (pTrapFrame->bXcpt == bFpXcpt) { /* likely */ } else Bs3TestFailedF("Expected floating-point xcpt %s, got %s", bs3CpuInstr4XcptName(bFpXcpt), bs3CpuInstr4XcptName(pTrapFrame->bXcpt)); } else if (pTrapFrame->bXcpt == X86_XCPT_DB) { /* likely */ } else Bs3TestFailedF("Expected no xcpt, got %s", bs3CpuInstr4XcptName(pTrapFrame->bXcpt)); } /* Check if non-FP exception is as expected. */ else if (pTrapFrame->bXcpt != bXcptExpect) Bs3TestFailedF("Expected xcpt %s, got %s", bs3CpuInstr4XcptName(bXcptExpect), bs3CpuInstr4XcptName(pTrapFrame->bXcpt)); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (pCtx->rflags.u32 & X86_EFL_AC)) { if (pTrapFrame->Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", pTrapFrame->bXcpt); pTrapFrame->Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_PF) pCtx->cr2.u = (uintptr_t)puMemOp; Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, bXcptExpect == X86_XCPT_DB && !fFpXcptExpected ? cbInstr + 1 : 0, 0 /*cbSpAdjust*/, (bXcptExpect == X86_XCPT_DB && !fFpXcptExpected) || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pTestCtx->pszMode, pTestCtx->idTestStep); pCtx->cr2.u = 0; if ( pTest->enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &MemOpExpect, cbMemOp) != 0) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &MemOpExpect, cbMemOp, puMemOpAlias); return cErrors; } /** * Test type #1 worker. */ static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstrXAllocExtCtxs(&pExtCtxOut); if (pExtCtx) { /* likely */ } else return 0; if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT) { /* likely */ } else { Bs3TestPrintf("Skipped due to ancient FPU state format\n"); return 0; } /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ pbBuf = bs3CpuInstrXBufSetup(pbBuf, &cbBuf, bMode); Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTRX_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr4ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = &paTests[iTest]; unsigned const cValues = pTest->cValues; bool const fSseInstr = bs3CpuInstr4IsSse(pTest->enmType); bool const fAvxInstr = bs3CpuInstr4IsAvx(pTest->enmType); uint8_t const cbOperand = bs3CpuInstr4GetOperandSize(pTest->enmType); uint8_t const cbMemOp = bs3CpuInstrXMemOpSize(cbOperand, pTest->enmRm); uint8_t const cbAlign = cbMemOp; uint8_t BS3_FAR *puMemOp = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); uint8_t *puMemOpAlias = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t bXcptExpect = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; /* If testing unaligned memory accesses (or #PF), skip register-only tests. This allows setting bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ( (pTest->enmRm == RM_REG || pTest->enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3. */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = pTest->bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, pTest->pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) { for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; BS3CPUINSTR4_TEST1_CTX_T TestCtx; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* * If the hardware does not support DAZ bit skip test values that set it. */ if ( !g_fMxCsrDazSupported && (pTest->paValues[iVal].uMxCsr & X86_MXCSR_DAZ)) continue; /* * Setup the test instruction context and pass it to the worker. * A few of these can be figured out by the worker but initializing * it outside the inner most loop is more optimal. */ TestCtx.pConfig = &paConfigs[iCfg]; TestCtx.pTest = pTest; TestCtx.iVal = iVal; TestCtx.pszMode = pszMode; TestCtx.pTrapFrame = &TrapFrame; TestCtx.pCtx = &Ctx; TestCtx.pExtCtx = pExtCtx; TestCtx.pExtCtxOut = pExtCtxOut; TestCtx.puMemOp = (uint8_t *)puMemOp; TestCtx.puMemOpAlias = puMemOpAlias; TestCtx.cbMemOp = cbMemOp; TestCtx.cbOperand = cbOperand; TestCtx.bXcptExpect = bXcptExpect; TestCtx.idTestStep = idTestStep; cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, %s %u-bit)", Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal, bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), fSseInstr ? "SSE" : "AVX", cbOperand * 8); else Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, puMemOp=%p, EFLAGS=%#RX32, %s %u-bit)", Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal, bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), puMemOp, TrapFrame.Ctx.rflags.u32, fSseInstr ? "SSE" : "AVX", cbOperand * 8); Bs3TestPrintf("\n"); } } } } bs3CpuInstrXConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstrXBufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * [V]ADDPS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addps(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_IM, /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } }, { /* => */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /* * Overflow, Precision. */ /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_OE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } }, { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } }, { /* => */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_NORM_MAX(1), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_PE, /*256:out */ X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.25*/ } }, { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/ } }, { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_0(0) } }, { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_1(1) /*- 1.00*/, FP32_0(0) } }, { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1), FP32_0(0) } }, { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_1(0), FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } }, { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_0(0), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_0(0), FP32_1(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_0(1), FP32_0(0) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(1), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), } }, { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), } }, { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0) } }, { /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Denormals. */ /*26*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /** @todo More Denormals. */ /* * Invalids. */ /*32*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_addps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]ADDPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addpd(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, { /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* * Infinity. */ /* 5*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(0), FP64_INF(1) } }, { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } }, { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_0(1), FP64_0(0), FP64_INF(1) } }, { /*src1 */ { FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_0(1), FP64_0(0), FP64_INF(0) } }, { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/, FP64_0(1), FP64_0(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ false, false }, /* * Overflow, Precision. */ /*10*/{ { /*src2 */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } }, { /*src1 */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_OE, /*256:out */ X86_MXCSR_OE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_OE, /*256:out */ X86_MXCSR_OE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, { /* => */ { FP64_INF(0), FP64_V(1, 0, 2), FP64_0(0), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } }, { /* => */ { FP64_V(1, 0, 2), FP64_INF(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, /** @todo Why does the below on cause PE?! */ { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/* 1.75*/, FP64_NORM_MAX(0), FP64_0(0), FP64_V(0, 0, 0x3fd)/*0.25*/ } }, { /*src1 */ { FP64_V(1, 0, 0x07d)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0, 0x3fe)/*0.50*/ } }, { /* => */ { FP64_V(0, 0xbffffffffffff, 0x3ff)/* 1.50*/, FP64_0(1), FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE, /*xcpt? */ false, false }, /* * Normals. */ /*17*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } }, { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } }, { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /* * Denormals. */ /*24*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */ /* * Invalids. */ /*27*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]ADDSS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addss(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_QNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, { /* => */ { FP32_QNAN(1), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /* * Overflow, Precision. */ /*12*/{ { /*src2 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_OE, /*256:out */ X86_MXCSR_OE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_NORM_MAX(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_1(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_1(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, /* * Denormals. */ /*27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, /*mxcsr:in */ X86_MXCSR_DE, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*xcpt? */ true, true }, /** @todo More denormals etc. */ /* * Invalids. */ /* QNan, QNan (Masked). */ /*30*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* QNan, SNan (Masked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, QNan (Masked). */ { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, SNan (Masked). */ { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, /* QNan, Norm FP (Masked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, Norm FP (Masked). */ { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, /* QNan, QNan (Unmasked). */ /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, /* QNan, SNan (Unmasked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* SNan, QNan (Unmasked). */ { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* SNan, SNan (Unmasked). */ /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, /* QNan, Norm FP (Unmasked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, /* SNan, Norm FP (Unmasked). */ /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_addss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); } /* * [V]ADDSD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addsd(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, { /* => */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_INF(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_INF(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /* * Overflow, Precision. */ /*12*/{ { /*src2 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_OE, /*256:out */ X86_MXCSR_OE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*18*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_SNAN(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_SNAN(1) } }, { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_SNAN(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, } }, { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, } }, { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, { /* => */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, { /* => */ { FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, { /*src1 */ { FP64_1(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, { /* => */ { FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, { /* => */ { FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /* * Denormals. */ /*29*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN(0) } }, { /*src1 */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, { /* => */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_SNAN(1), FP64_INF(0), FP64_SNAN(0) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, { /* => */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /** @todo More Denormals. */ /* * Invalids. */ /* QNan, QNan (Masked). */ /*32*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* QNan, SNan (Masked). */ { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, QNan (Masked). */ { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, SNan (Masked). */ { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* QNan, Norm FP (Masked). */ { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, Norm FP (Masked). */ { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, /* QNan, QNan (Unmasked). */ /*46*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, /* QNan, SNan (Unmasked). */ { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* SNan, QNan (Unmasked). */ { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* SNan, SNan (Unmasked). */ /*55*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, /* QNan, Norm FP (Unmasked). */ { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, /* SNan, Norm FP (Unmasked). */ /*59*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_addsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); } /* * [V]HADDPS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddps(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } }, { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_IM, /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_QNAN(1), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* * Overflow, Precision. */ /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_OE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(1), FP32_INF(1), FP32_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1) } }, { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0), FP32_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, { /* => */ { FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ false, false }, /* * Normals. */ /*18*/{ { /*src2 */ { FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_V(0, 0, 0x7d)/*0.25*/ } }, { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x600000, 0x7f)/*1.75*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V4(1), FP32_NORM_V4(0), FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V2(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_V3(0), FP32_NORM_V3(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/* 7.00*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_0(0), FP32_V(0, 0x534000, 0x86)/*211.25*/ } }, { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(1, 0x1ea980, 0x8f)/* -81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/*7*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_1(1) } }, { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_1(1) } }, { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_NORM_V3(1), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_0(0), FP32_1(0) } }, { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V3(1), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_NORM_V1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(0), FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0), FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0) } }, { /*src1 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } }, { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } }, { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } }, { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, 2), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* * Denormals. */ /*26*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), } }, /*mxcsr:in */ X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_DAZ, /*256:out */ X86_MXCSR_DAZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /** @todo Denormals; Rounding, FZ etc. */ /* * Invalids. */ /*32*/{ { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]HADDPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddpd(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_IM, /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_QNAN(1), FP64_INF(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_QNAN(1), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(0), FP64_0(0) } }, { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_0(0) } }, { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_QNAN(1), FP64_INF(1), FP64_QNAN(0) } }, { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_INF(1), FP64_QNAN(0) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* * Overflow, Precision. */ /*11*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_OE, /*xcpt? */ false, true }, { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, { /* => */ { FP64_INF(1), FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1), FP64_INF(0), } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, { /* => */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, { /* => */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_V(0, 0, 2), FP64_NORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE, /*xcpt? */ false, true }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ false, false }, /* * Normals. */ /*20*/{ { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_V2(1), FP64_NORM_V2(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_V1(1) } }, { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/* 55*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/ } }, { /*src1 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0, 0x408)/*512*/, FP64_V(0, 0xd6f3458800000, 0x41c)/* 987654321*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/ } }, { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/, FP64_V(0, 0xd6f3426800000, 0x41c)/* 987654221*/, FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_NORM_V2(1), FP64_NORM_V2(0) } }, { /*src1 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.50*/, FP64_NORM_V0(1), FP64_NORM_V0(0) } }, { /* => */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_NORM_V3(1), FP64_NORM_V3(0) } }, { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_V1(1) } }, { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } }, { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2), FP64_V(1, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } }, { /*src1 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0), FP64_NORM_V0(1) } }, { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /* * Denormals. */ /*26*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, { /*src1 */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_DE, /*xcpt? */ false, true }, /* * Invalids. */ /*31*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0), } }, { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1), } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_haddpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]SUBPS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subps(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_XCPT_FLAGS, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /*src1 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } }, { /* => */ { FP32_INF(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /* * Overflow, Precision. */ /*12*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_PE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } }, { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, 2), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } }, { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } }, { /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*20*/{ { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_0(0), FP32_0(1), FP32_V(0, 0x400000, 0x7e)/* 0.75*/ } }, { /*src1 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_0(0), FP32_0(0), FP32_0(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(0), FP32_0(1), FP32_V(0, 0, 0x7e)/* 0.50*/ } }, { /* => */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_0(1), FP32_0(1), FP32_V(1, 0, 0x7d)/*-0.25*/ } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x2514d6, 0x93)/* 1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_0(0) } }, { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(1, 0x7c9000, 0x88)/* -1010.25*/, FP32_1(0) /* 1.00*/, FP32_0(0) } }, { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_0(0), FP32_V(1, 0x780000, 0x84)/*-62*/, FP32_V(1, 0x253468, 0x93)/*-1353357.00*/, FP32_V(1, 0x524000, 0x86)/*210.25*/, FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/* 12345678*/, FP32_0(0), FP32_1(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_1(0), FP32_1(0) } }, { /* => */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_V(0, 0x3c614e, 0x97)/* 24691356*/, FP32_0(1), FP32_1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_0(1), FP32_0(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_0(1), FP32_0(0) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(0), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(0) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } }, { /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } }, { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, 2), FP32_V(1, 0, 2), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* * Denormals. */ /*28*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */ /* * Invalids. */ /*34*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_subps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]SUBPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subpd(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_INF(1) } }, { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } }, { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, { /* => */ { FP64_QNAN(1), FP64_INF(1), FP64_INF(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_QNAN(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, true }, { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } }, { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, { /* => */ { FP64_INF(0), FP64_INF(0), FP64_0(1), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /* * Overflow, Precision. */ /*12*/{ { /*src2 */ { FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_PE, /*256:out */ X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_PE, /*xcpt? */ false, true }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } }, { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } }, { /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*21*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/ } }, { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0, 0x409)/*1024*/ } }, { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(1, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(1, 0, 0x408)/* 512*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } }, { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_1(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_NORM_SAFE_INT_MAX(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0) } }, { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, { /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } }, { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } }, { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, 2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* * Denormals. */ /*28*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /** @todo More denormals. */ /* * Invalids. */ /*31*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V0) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) , FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_subpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]SUBSS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subss(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /* => */ { FP32_0(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM), /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE, /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_QNAN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, { /* => */ { FP32_INF(0), FP32_0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* * Overflow, Precision. */ /*12*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ X86_MXCSR_PE, /*xcpt? */ false, true }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } }, { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*21*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } }, { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*xcpt? */ false, false }, /* * Denormals. */ /*27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_subss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); } /* * [V]SUBSD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_subsd(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 6*/{ { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_INF(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* * Overflow, Precision. */ /*14*/{ { /*src2 */ { FP64_NORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_PE, /*256:out */ X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V3(1) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } }, { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_PE, /*256:out */ X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ true, true }, /* * Normals. */ /*23*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(0), FP64_NORM_V2(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, { /*src1 */ { FP64_NORM_MIN(0), FP64_NORM_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, { /* => */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(0), FP64_RAND_V0(0), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(1, 0xd6f3458800000, 0x41c)/*-987654321*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, { /* => */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* * Denormals. */ /*34*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, { /* => */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /** @todo More Denormals. */ /** @todo Invalids, Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_subsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_subsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_subsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vsubsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_subsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); } /* * [V]MULPS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulps(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_NORM_V2(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } }, { /* => */ { FP32_INF(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, #if 0 /* * Normals. */ /*12*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.250*/, FP32_V(0, 0x600000, 0x7f)/* 1.7500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7d)/*0.250*/ } }, { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.500*/, FP32_V(1, 0, 0x7d)/*-0.2500*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.500*/ } }, { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/*0.125*/, FP32_V(1, 0x600000, 0x7d)/*-0.4375*/, FP32_0(0), FP32_0(0), FP32_V(0, 0, 0x7c)/*0.125*/ } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN, /*flags */ 0, 0 }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } }, { /*src1 */ { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } }, { /* => */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(1), FP32_NORM_V3(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ 0, 0 }, { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_V(0, 0x0ba000, 0x86)/* 139.625000*/, FP32_V(0, 0x200000, 0x7e)/*0.625000*/, FP32_V(0, 0x22fae4, 0x93)/*1335132.50*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x3d400, 0x86)/*131.828125*/ } }, { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_V(0, 0x265000, 0x87)/* 332.625000*/, FP32_V(0, 0, 0x7c)/*0.125000*/, FP32_V(0, 0x200000, 0x80)/* 2.50*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_1(1) /* -1.000000*/ } }, { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x356ac4, 0x8e)/*46442.765625*/, FP32_V(0, 0x200000, 0x7b)/*0.078125*/, FP32_V(0, 0x4bb99d, 0x94)/*3337831.25*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(1, 0x3d400, 0x86)/*-131.828125*/ } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ 0, 0 }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_1(0) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO, /*flags */ 0, 0 }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2) } }, { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_1(0) } }, { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO, /*flags */ 0, 0 }, /** @todo More Normals. */ /* * Denormals. */ /*17*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_DE, X86_MXCSR_DE }, { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_DE, X86_MXCSR_DE }, { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } }, { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } }, { /* => */ { FP32_0(1), FP32_0(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST, /*flags */ 0, 0 }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V4(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_0(0), FP32_0(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_0(0), FP32_0(0) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP, /*flags */ 0, 0 }, /** @todo More Denormals. */ /* * Overflow, Precision. */ /*21*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V7(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_NORM_V7(0), FP32_INF(0), FP32_INF(0) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE }, { { /*src2 */ { FP32_NORM_V5(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_1(0), FP32_0(0) } }, { /*src1 */ { FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } }, { /* => */ { FP32_NORM_V5(0), FP32_INF(0), FP32_INF(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_V6(0), FP32_0(0) } }, /*mask */ X86_MXCSR_OM | X86_MXCSR_PM, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_V7(0), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_1(0), FP32_NORM_MAX(0) } }, { /* => */ { FP32_INF(0), FP32_0(0), FP32_1(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_NORM_V7(0), FP32_INF(0) } }, /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE }, { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_V5(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } }, { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0) } }, { /* => */ { FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_V5(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0) } }, /*mask */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO, /*flags */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE }, { { /*src2 */ { FP32_NORM_V6(0), FP32_1(1), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_1(0), FP32_NORM_V6(1), FP32_1(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /* => */ { FP32_NORM_V6(0), FP32_NORM_V6(0), FP32_0(0), FP32_1(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO, /*flags */ 0, X86_MXCSR_OE | X86_MXCSR_PE }, { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO, /*flags */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE }, /** @todo More Overflow, Precision. */ /* * Invalids. */ /*27*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ 0, 0 }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ 0, 0 }, { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mask */ X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN, /*flags */ 0, 0 }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_UP, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_DOWN, /*flags */ 0, 0 }, { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, /*mask */ ~X86_MXCSR_XCPT_MASK, /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO, /*flags */ X86_MXCSR_IE, X86_MXCSR_IE }, /** @todo Underflow, Precision; Rounding, FZ etc. */ #endif }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_mulps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]MULPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulpd(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } }, { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 7*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(1), FP64_0(0) } }, { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } }, { /* => */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } }, { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } }, { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } }, { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(0), FP64_INF(0) } }, { /*src1 */ { FP64_1(0), FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } }, { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_NORM_V3(0), FP64_INF(1) } }, { /*src1 */ { FP64_1(1), FP64_NORM_V3(1), FP64_INF(1), FP64_NORM_V1(1) } }, { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /* * Normals. */ /*13*/{ { /*src2 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/ } }, { /*src1 */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } }, { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } }, { /*src1 */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } }, { /* => */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } }, { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } }, { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } }, { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /** @todo More Normals. */ /* * Denormals. */ /*18*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE, /*xcpt? */ false, true }, { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0), FP64_1(0) } }, { /*src1 */ { FP64_1(0), FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(1), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP64_1(0), FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, { /*src1 */ { FP64_NORM_V0(0), FP64_1(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, /*xcpt? */ true, true }, /* * Overflow, Precision. */ /*26*/{ { /*src2 */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_NORM_MAX(0) } }, { /* => */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } }, { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_1(0), FP64_1(0) } }, { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_NORM_V3(1), FP64_1(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0) } }, { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, { /* => */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } }, /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } }, { /*src1 */ { FP64_1(0), FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, { /* => */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } }, { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, /* * Invalids. */ /*33*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c16, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c32, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_mulpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM1_YMM2_YMM3_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM8_YMM9_YMM10_icebp_c64, X86_XCPT_GP, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); } /* * [V]MULSS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_mulss(uint8_t bMode) { static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] = { /* * Zero. */ /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } }, { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_0(1), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_0(0), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } }, { /* => */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_1(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* * Infinity. */ /* 8*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_1(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, { /* => */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, { /*src1 */ { FP32_1(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ, /*256:out */ X86_MXCSR_FZ, /*xcpt? */ false, false }, { { /*src2 */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, { /* => */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* * Normals. */ /*15*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, { /*src1 */ { FP32_1(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, { /*src1 */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, { /* => */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, { /*src1 */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V6(0), FP32_RAND_V1(1) } }, { /* => */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V1(1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } }, { /*src1 */ { FP32_1(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } }, { /* => */ { FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, { /*src1 */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, { /* => */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } }, { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /** @todo More Normals. */ /* * Denormals. */ /*24*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_DE, /*256:out */ X86_MXCSR_DE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } }, { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } }, { /* => */ { FP32_0(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_DENORM_MIN(0), FP32_1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } }, { /* => */ { FP32_0(0), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, /** @todo More Denormals. */ /* * Invalids. */ /* QNan, QNan (Masked). */ /*28*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* QNan, SNan (Masked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, QNan (Masked). */ { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, SNan (Masked). */ { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, /* QNan, Norm FP (Masked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, /*256:out */ X86_MXCSR_XCPT_MASK, /*xcpt? */ false, false }, /* SNan, Norm FP (Masked). */ { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, /*xcpt? */ false, false }, /* QNan, QNan (Unmasked). */ /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ 0, /*256:out */ 0, /*xcpt? */ false, false }, /* QNan, SNan (Unmasked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ 0, /*128:out */ X86_MXCSR_IE, /*256:out */ X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* SNan, QNan (Unmasked). */ { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, /*xcpt? */ false, false }, /* SNan, SNan (Unmasked). */ /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, /*mxcsr:in */ X86_MXCSR_FZ, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, /*xcpt? */ true, true }, /* QNan, Norm FP (Unmasked). */ { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, /*xcpt? */ false, false }, /* SNan, Norm FP (Unmasked). */ /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, /*xcpt? */ true, true }, /** @todo Underflow, Precision; Rounding, FZ etc. */ }; static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { { bs3CpuInstr4_mulss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulss_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vmulss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_mulss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); } /** * The 32-bit protected mode main function. * * The tests a driven by 32-bit test drivers, even for real-mode tests (though * we'll switch between PE32 and RM for each test step we perform). Given that * we test SSE and AVX here, we don't need to worry about 286 or 8086. * * Some extra steps needs to be taken to properly handle extended state in LM64 * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm). */ BS3_DECL(void) Main_pe32() { static const BS3TESTMODEBYONEENTRY g_aTests[] = { #if 1 /*ndef DEBUG_bird*/ # define ALL_TESTS #endif #if defined(ALL_TESTS) { "[v]addps", bs3CpuInstr4_v_addps, 0 }, { "[v]addpd", bs3CpuInstr4_v_addpd, 0 }, { "[v]addss", bs3CpuInstr4_v_addss, 0 }, { "[v]addsd", bs3CpuInstr4_v_addsd, 0 }, { "[v]haddps", bs3CpuInstr4_v_haddps, 0 }, { "[v]haddpd", bs3CpuInstr4_v_haddpd, 0 }, { "[v]subps", bs3CpuInstr4_v_subps, 0 }, { "[v]subpd", bs3CpuInstr4_v_subpd, 0 }, { "[v]subss", bs3CpuInstr4_v_subss, 0 }, { "[v]subsd", bs3CpuInstr4_v_subsd, 0 }, { "[v]mulps", bs3CpuInstr4_v_mulps, 0 }, { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 }, { "[v]mulss", bs3CpuInstr4_v_mulss, 0 }, #endif }; Bs3TestInit("bs3-cpu-instr-4"); /* * Initialize globals. */ if (g_uBs3CpuDetected & BS3CPU_F_CPUID) { uint32_t fEbx, fEcx, fEdx; ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx); g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX); g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE); g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2); g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3); g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE); g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2); g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3); g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3); g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1); g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2); g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL); g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL) && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); if (ASMCpuId_EAX(0) >= 7) { ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL); g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA); } if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES) { ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx); g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX); g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A); g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE); } g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE]; /* * Figure out FPU save/restore method and support for DAZ bit. */ { /** @todo Add bs3kit API to just get the ext ctx method without needing to * alloc/free a context. Replicating the logic in the bs3kit here, though * doable, runs a risk of not updating this when the other logic is * changed. */ uint64_t fFlags; uint16_t const cbExtCtx = Bs3ExtCtxGetSize(&fFlags); PBS3EXTCTX pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cbExtCtx); if (pExtCtx) { Bs3ExtCtxInit(pExtCtx, cbExtCtx, fFlags); g_enmExtCtxMethod = pExtCtx->enmMethod; if ( ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_XSAVE && (pExtCtx->Ctx.x.x87.MXCSR_MASK & X86_MXCSR_DAZ))) || ( (g_enmExtCtxMethod == BS3EXTCTXMETHOD_FXSAVE) && (pExtCtx->Ctx.x87.MXCSR_MASK & X86_MXCSR_DAZ))) g_fMxCsrDazSupported = true; } else Bs3TestFailedF("Failed to allocate %u bytes for extended CPU context (tiled addressable)\n", cbExtCtx); } /* * Allocate a buffer for testing. */ g_cbBuf = X86_PAGE_SIZE * 4; g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf); if (g_pbBuf) { g_pbBufAliasAlloc = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_TILED, g_cbBuf); if (g_pbBufAliasAlloc) { /* * Do the tests. */ Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY); #ifdef BS3_SKIPIT_DO_SKIP bs3CpuInstrX_ShowTallies(); #endif } else Bs3TestFailed("Failed to allocate 16K alias buffer (tiled addressable)"); } else Bs3TestFailed("Failed to allocate 16K buffer (real mode addressable)"); } Bs3TestTerm(); }