Changeset 103955 in vbox
- Timestamp:
- Mar 20, 2024 1:09:35 PM (8 months ago)
- Location:
- trunk
- Files:
-
- 4 edited
-
include/VBox/disopcode-x86-amd64.h (modified) (1 diff)
-
src/VBox/VMM/VMMAll/IEMAllInstPython.py (modified) (2 diffs)
-
src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h (modified) (11 diffs)
-
src/VBox/VMM/include/IEMInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/disopcode-x86-amd64.h
r103927 r103955 1455 1455 #define OP_PARM_Eq (OP_PARM_E+OP_PARM_q) 1456 1456 #define OP_PARM_Eq_WO OP_PARM_Eq /**< Annotates write only operand. */ 1457 #define OP_PARM_Ey_WO OP_PARM_Ey /**< Annotates write only operand. */ 1457 1458 #define OP_PARM_Gv_RO OP_PARM_Gv /**< Annotates read only first operand (default is readwrite). */ 1458 1459 #define OP_PARM_HssHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:32]. */ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r103953 r103955 243 243 'Ev': ( 'IDX_UseModRM', 'rm', '%Ev', 'Ev', 'RM', ), 244 244 'Ey': ( 'IDX_UseModRM', 'rm', '%Ey', 'Ey', 'RM', ), 245 'Ey_WO': ( 'IDX_UseModRM', 'rm', '%Ey', 'Ey', 'RM', ), 245 246 'Qd': ( 'IDX_UseModRM', 'rm', '%Qd', 'Qd', 'RM', ), 246 247 'Qq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', 'RM', ), … … 613 614 'vex_l_ignored': '', ##< VEX.L is ignored. 614 615 'vex_v_zero': '', ##< VEX.V must be 0. (generate sub-table?) 616 'vex_w_zero': '', ##< REX.W/VEX.W must be 0. 617 'vex_w_one': '', ##< REX.W/VEX.W must be 1. 618 'rex_w_zero': '', ##< REX.W/VEX.W must be 0. 619 'rex_w_one': '', ##< REX.W/VEX.W must be 1. 615 620 'lock_allowed': '', ##< Lock prefix allowed. 616 621 }; -
trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h
r103931 r103955 587 587 FNIEMOP_DEF(iemOp_vpextrw_Ew_Vdq_Ib) 588 588 { 589 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRW, vpextrw, Ew_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO); 589 /** @todo testcase: check that this ignores VEX.W. */ 590 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRW, vpextrw, Ew_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO | IEMOPHINT_IGNORES_REXW); 590 591 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 591 592 if (IEM_IS_MODRM_REG_MODE(bRm)) … … 636 637 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) 637 638 { 638 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRQ, vpextrq, Eq_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO ); /** @todo */639 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRQ, vpextrq, Eq_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ONE); 639 640 if (IEM_IS_MODRM_REG_MODE(bRm)) 640 641 { … … 681 682 * @opdone 682 683 */ 683 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRD, vpextrd, Ey , Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); /** @todo */684 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRD, vpextrd, Ey_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ZERO); 684 685 if (IEM_IS_MODRM_REG_MODE(bRm)) 685 686 { … … 1179 1180 * 1180 1181 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit. 1182 * Additionally, both VEX.W and VEX.L must be zero. 1181 1183 */ 1182 1184 FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl) … … 1193 1195 IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0); 1194 1196 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); 1197 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 1198 IEM_MC_PREPARE_AVX_USAGE(); 1199 1200 IEM_MC_LOCAL(RTUINT256U, uSrc1); 1201 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); 1202 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1203 1204 IEM_MC_LOCAL(RTUINT256U, uSrc2); 1205 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); 1206 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 1207 1208 IEM_MC_LOCAL(RTUINT256U, uSrc3); 1209 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3); 1210 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4)); 1211 1195 1212 IEM_MC_LOCAL(RTUINT256U, uDst); 1196 IEM_MC_LOCAL(RTUINT256U, uSrc1);1197 IEM_MC_LOCAL(RTUINT256U, uSrc2);1198 IEM_MC_LOCAL(RTUINT256U, uSrc3);1199 1213 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); 1200 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); 1201 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); 1202 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3); 1203 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 1204 IEM_MC_PREPARE_AVX_USAGE(); 1205 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1206 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 1207 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */ 1214 1208 1215 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3); 1216 1209 1217 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1210 1218 IEM_MC_ADVANCE_RIP_AND_FINISH(); … … 1215 1223 IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); 1216 1224 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); 1217 IEM_MC_ ARG(PRTUINT128U, puDst, 0);1218 IEM_MC_ ARG(PCRTUINT128U, puSrc1, 1);1219 IEM_MC_ARG(P CRTUINT128U, puSrc2, 2);1220 IEM_MC_ ARG(PCRTUINT128U, puSrc3, 3);1221 IEM_MC_ MAYBE_RAISE_AVX_RELATED_XCPT();1222 IEM_MC_ PREPARE_AVX_USAGE();1223 IEM_MC_ REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));1224 IEM_MC_REF_XREG_U128_CONST(puSrc 1, IEM_GET_EFFECTIVE_VVVV(pVCpu));1225 IEM_MC_ REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));1226 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */1225 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 1226 IEM_MC_PREPARE_AVX_USAGE(); 1227 IEM_MC_ARG(PRTUINT128U, puDst, 0); 1228 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1229 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); 1230 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1231 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); 1232 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 1233 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3); 1234 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4)); 1227 1235 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3); 1228 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));1236 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1229 1237 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1230 1238 IEM_MC_END(); … … 1239 1247 { 1240 1248 IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0); 1241 IEM_MC_LOCAL(RTUINT256U, uDst);1242 IEM_MC_LOCAL(RTUINT256U, uSrc1);1243 IEM_MC_LOCAL(RTUINT256U, uSrc2);1244 IEM_MC_LOCAL(RTUINT256U, uSrc3);1245 1249 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 1246 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);1247 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);1248 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);1249 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);1250 1250 1251 1251 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); … … 1256 1256 IEM_MC_PREPARE_AVX_USAGE(); 1257 1257 1258 IEM_MC_LOCAL(RTUINT256U, uSrc2); 1259 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); 1258 1260 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1259 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1260 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1261 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */ 1261 1262 IEM_MC_LOCAL(RTUINT256U, uSrc1); 1263 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); 1264 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1265 1266 IEM_MC_LOCAL(RTUINT256U, uSrc3); 1267 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3); 1268 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4)); 1269 1270 IEM_MC_LOCAL(RTUINT256U, uDst); 1271 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); 1272 1262 1273 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3); 1263 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1264 1274 1275 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1265 1276 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1266 1277 IEM_MC_END(); … … 1269 1280 { 1270 1281 IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0); 1271 IEM_MC_LOCAL(RTUINT128U, uSrc2); 1272 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 1273 IEM_MC_ARG(PRTUINT128U, puDst, 0); 1274 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); 1275 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); 1276 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3); 1277 1282 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 1278 1283 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 1279 1284 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4); … … 1283 1288 IEM_MC_PREPARE_AVX_USAGE(); 1284 1289 1290 IEM_MC_LOCAL(RTUINT128U, uSrc2); 1291 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); 1285 1292 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1293 1294 IEM_MC_ARG(PRTUINT128U, puDst, 0); 1286 1295 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1296 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); 1287 1297 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); 1288 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */ 1298 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3); 1299 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4)); 1289 1300 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3); 1290 1301 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); … … 1301 1312 FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx) 1302 1313 { 1303 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo1314 IEMOP_MNEMONIC4(VEX_RVMR, VPBLENDVB, vpblendvb, Vx_WO, Hx, Wx, Lx, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ZERO); 1304 1315 IEMOPBLENDOP_INIT_VARS(vpblendvb); 1305 1316 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback)); -
trunk/src/VBox/VMM/include/IEMInternal.h
r103951 r103955 2389 2389 /** The VEX.V value must be zero. */ 2390 2390 #define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15) 2391 /** The REX.W/VEX.V value must be zero. */ 2392 #define IEMOPHINT_REX_W_ZERO RT_BIT_32(16) 2393 #define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO 2394 /** The REX.W/VEX.V value must be one. */ 2395 #define IEMOPHINT_REX_W_ONE RT_BIT_32(17) 2396 #define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE 2391 2397 2392 2398 /** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
Note:
See TracChangeset
for help on using the changeset viewer.
