1 | /*
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2 | * Software MMU support
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3 | *
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4 | * Copyright (c) 2003 Fabrice Bellard
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5 | *
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6 | * This library is free software; you can redistribute it and/or
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7 | * modify it under the terms of the GNU Lesser General Public
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8 | * License as published by the Free Software Foundation; either
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9 | * version 2 of the License, or (at your option) any later version.
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10 | *
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11 | * This library is distributed in the hope that it will be useful,
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | * Lesser General Public License for more details.
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15 | *
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16 | * You should have received a copy of the GNU Lesser General Public
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17 | * License along with this library; if not, write to the Free Software
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18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | */
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20 |
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21 | /*
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22 | * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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23 | * other than GPL or LGPL is available it will apply instead, Sun elects to use only
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24 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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25 | * a choice of LGPL license versions is made available with the language indicating
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26 | * that LGPLv2 or any later version may be used, or where a choice of which version
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27 | * of the LGPL is applied is otherwise unspecified.
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28 | */
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29 | #define DATA_SIZE (1 << SHIFT)
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30 |
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31 | #if DATA_SIZE == 8
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32 | #define SUFFIX q
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33 | #define USUFFIX q
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34 | #define DATA_TYPE uint64_t
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35 | #define DATA_TYPE_PROMOTED uint64_t
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36 | #elif DATA_SIZE == 4
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37 | #define SUFFIX l
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38 | #define USUFFIX l
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39 | #define DATA_TYPE uint32_t
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40 | #ifdef VBOX
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41 | #define DATA_TYPE_PROMOTED RTCCUINTREG
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42 | #endif
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43 | #elif DATA_SIZE == 2
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44 | #define SUFFIX w
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45 | #define USUFFIX uw
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46 | #define DATA_TYPE uint16_t
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47 | #ifdef VBOX
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48 | #define DATA_TYPE_PROMOTED RTCCUINTREG
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49 | #endif
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50 | #elif DATA_SIZE == 1
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51 | #define SUFFIX b
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52 | #define USUFFIX ub
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53 | #define DATA_TYPE uint8_t
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54 | #ifdef VBOX
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55 | #define DATA_TYPE_PROMOTED RTCCUINTREG
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56 | #endif
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57 | #else
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58 | #error unsupported data size
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59 | #endif
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60 |
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61 | #ifdef SOFTMMU_CODE_ACCESS
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62 | #define READ_ACCESS_TYPE 2
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63 | #define ADDR_READ addr_code
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64 | #else
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65 | #define READ_ACCESS_TYPE 0
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66 | #define ADDR_READ addr_read
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67 | #endif
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68 |
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69 | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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70 | int mmu_idx,
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71 | void *retaddr);
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72 | #ifndef VBOX
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73 | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
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74 | target_ulong addr,
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75 | void *retaddr)
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76 | #else
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77 | DECLINLINE(DATA_TYPE) glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
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78 | target_ulong addr,
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79 | void *retaddr)
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80 | #endif
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81 | {
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82 | DATA_TYPE res;
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83 | int index;
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84 | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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85 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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86 | env->mem_io_pc = (unsigned long)retaddr;
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87 | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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88 | && !can_do_io(env)) {
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89 | cpu_io_recompile(env, retaddr);
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90 | }
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91 |
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92 | #if SHIFT <= 2
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93 | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
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94 | #else
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95 | #ifdef TARGET_WORDS_BIGENDIAN
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96 | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
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97 | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
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98 | #else
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99 | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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100 | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
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101 | #endif
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102 | #endif /* SHIFT > 2 */
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103 | #ifdef USE_KQEMU
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104 | env->last_io_time = cpu_get_time_fast();
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105 | #endif
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106 | return res;
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107 | }
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108 |
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109 | /* handle all cases except unaligned access which span two pages */
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110 | #ifndef VBOX
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111 | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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112 | int mmu_idx)
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113 | #else
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114 | /* Load helpers invoked from generated code, and TCG makes an assumption
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115 | that valid value takes the whole register, why gcc after 4.3 may
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116 | use only lower part of register for smaller types. So force promoution. */
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117 | DATA_TYPE_PROMOTED REGPARM
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118 | glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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119 | int mmu_idx)
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120 | #endif
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121 | {
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122 | DATA_TYPE res;
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123 | int index;
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124 | target_ulong tlb_addr;
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125 | target_phys_addr_t addend;
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126 | void *retaddr;
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127 |
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128 | /* test if there is match for unaligned or IO access */
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129 | /* XXX: could done more in memory macro in a non portable way */
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130 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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131 | redo:
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132 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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133 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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134 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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135 | /* IO access */
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136 | if ((addr & (DATA_SIZE - 1)) != 0)
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137 | goto do_unaligned_access;
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138 | retaddr = GETPC();
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139 | addend = env->iotlb[mmu_idx][index];
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140 | res = glue(io_read, SUFFIX)(addend, addr, retaddr);
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141 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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142 | /* slow unaligned access (it spans two pages or IO) */
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143 | do_unaligned_access:
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144 | retaddr = GETPC();
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145 | #ifdef ALIGNED_ONLY
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146 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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147 | #endif
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148 | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
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149 | mmu_idx, retaddr);
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150 | } else {
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151 | /* unaligned/aligned access in the same page */
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152 | #ifdef ALIGNED_ONLY
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153 | if ((addr & (DATA_SIZE - 1)) != 0) {
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154 | retaddr = GETPC();
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155 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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156 | }
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157 | #endif
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158 | addend = env->tlb_table[mmu_idx][index].addend;
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159 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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160 | }
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161 | } else {
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162 | /* the page is not in the TLB : fill it */
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163 | retaddr = GETPC();
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164 | #ifdef ALIGNED_ONLY
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165 | if ((addr & (DATA_SIZE - 1)) != 0)
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166 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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167 | #endif
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168 | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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169 | goto redo;
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170 | }
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171 | return res;
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172 | }
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173 |
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174 | /* handle all unaligned cases */
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175 | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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176 | int mmu_idx,
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177 | void *retaddr)
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178 | {
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179 | DATA_TYPE res, res1, res2;
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180 | int index, shift;
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181 | target_phys_addr_t addend;
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182 | target_ulong tlb_addr, addr1, addr2;
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183 |
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184 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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185 | redo:
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186 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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187 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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188 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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189 | /* IO access */
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190 | if ((addr & (DATA_SIZE - 1)) != 0)
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191 | goto do_unaligned_access;
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192 | retaddr = GETPC();
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193 | addend = env->iotlb[mmu_idx][index];
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194 | res = glue(io_read, SUFFIX)(addend, addr, retaddr);
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195 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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196 | do_unaligned_access:
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197 | /* slow unaligned access (it spans two pages) */
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198 | addr1 = addr & ~(DATA_SIZE - 1);
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199 | addr2 = addr1 + DATA_SIZE;
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200 | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
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201 | mmu_idx, retaddr);
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202 | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
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203 | mmu_idx, retaddr);
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204 | shift = (addr & (DATA_SIZE - 1)) * 8;
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205 | #ifdef TARGET_WORDS_BIGENDIAN
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206 | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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207 | #else
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208 | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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209 | #endif
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210 | res = (DATA_TYPE)res;
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211 | } else {
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212 | /* unaligned/aligned access in the same page */
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213 | addend = env->tlb_table[mmu_idx][index].addend;
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214 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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215 | }
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216 | } else {
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217 | /* the page is not in the TLB : fill it */
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218 | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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219 | goto redo;
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220 | }
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221 | return res;
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222 | }
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223 |
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224 | #ifndef SOFTMMU_CODE_ACCESS
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225 |
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226 | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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227 | DATA_TYPE val,
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228 | int mmu_idx,
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229 | void *retaddr);
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230 |
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231 | #ifndef VBOX
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232 | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
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233 | DATA_TYPE val,
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234 | target_ulong addr,
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235 | void *retaddr)
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236 | #else
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237 | DECLINLINE(void) glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
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238 | DATA_TYPE val,
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239 | target_ulong addr,
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240 | void *retaddr)
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241 | #endif
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242 | {
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243 | int index;
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244 | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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245 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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246 | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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247 | && !can_do_io(env)) {
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248 | cpu_io_recompile(env, retaddr);
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249 | }
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250 |
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251 | env->mem_io_vaddr = addr;
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252 | env->mem_io_pc = (unsigned long)retaddr;
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253 | #if SHIFT <= 2
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254 | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
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255 | #else
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256 | #ifdef TARGET_WORDS_BIGENDIAN
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257 | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
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258 | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
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259 | #else
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260 | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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261 | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
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262 | #endif
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263 | #endif /* SHIFT > 2 */
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264 | #ifdef USE_KQEMU
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265 | env->last_io_time = cpu_get_time_fast();
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266 | #endif
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267 | }
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268 |
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269 | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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270 | DATA_TYPE val,
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271 | int mmu_idx)
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272 | {
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273 | target_phys_addr_t addend;
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274 | target_ulong tlb_addr;
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275 | void *retaddr;
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276 | int index;
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277 |
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278 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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279 | redo:
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280 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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281 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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282 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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283 | /* IO access */
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284 | if ((addr & (DATA_SIZE - 1)) != 0)
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285 | goto do_unaligned_access;
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286 | retaddr = GETPC();
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287 | addend = env->iotlb[mmu_idx][index];
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288 | glue(io_write, SUFFIX)(addend, val, addr, retaddr);
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289 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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290 | do_unaligned_access:
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291 | retaddr = GETPC();
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292 | #ifdef ALIGNED_ONLY
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293 | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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294 | #endif
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295 | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
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296 | mmu_idx, retaddr);
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297 | } else {
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298 | /* aligned/unaligned access in the same page */
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299 | #ifdef ALIGNED_ONLY
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300 | if ((addr & (DATA_SIZE - 1)) != 0) {
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301 | retaddr = GETPC();
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302 | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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303 | }
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304 | #endif
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305 | addend = env->tlb_table[mmu_idx][index].addend;
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306 | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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307 | }
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308 | } else {
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309 | /* the page is not in the TLB : fill it */
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310 | retaddr = GETPC();
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311 | #ifdef ALIGNED_ONLY
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312 | if ((addr & (DATA_SIZE - 1)) != 0)
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313 | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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314 | #endif
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315 | tlb_fill(addr, 1, mmu_idx, retaddr);
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316 | goto redo;
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317 | }
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318 | }
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319 |
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320 | /* handles all unaligned cases */
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321 | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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322 | DATA_TYPE val,
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323 | int mmu_idx,
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324 | void *retaddr)
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325 | {
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326 | target_phys_addr_t addend;
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327 | target_ulong tlb_addr;
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328 | int index, i;
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329 |
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330 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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331 | redo:
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332 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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333 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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334 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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335 | /* IO access */
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336 | if ((addr & (DATA_SIZE - 1)) != 0)
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337 | goto do_unaligned_access;
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338 | addend = env->iotlb[mmu_idx][index];
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339 | glue(io_write, SUFFIX)(addend, val, addr, retaddr);
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340 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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341 | do_unaligned_access:
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342 | /* XXX: not efficient, but simple */
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343 | /* Note: relies on the fact that tlb_fill() does not remove the
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344 | * previous page from the TLB cache. */
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345 | for(i = DATA_SIZE - 1; i >= 0; i--) {
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346 | #ifdef TARGET_WORDS_BIGENDIAN
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347 | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
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348 | mmu_idx, retaddr);
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349 | #else
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350 | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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351 | mmu_idx, retaddr);
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352 | #endif
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353 | }
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354 | } else {
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355 | /* aligned/unaligned access in the same page */
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356 | addend = env->tlb_table[mmu_idx][index].addend;
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357 | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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358 | }
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359 | } else {
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360 | /* the page is not in the TLB : fill it */
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361 | tlb_fill(addr, 1, mmu_idx, retaddr);
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362 | goto redo;
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363 | }
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364 | }
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365 |
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366 | #endif /* !defined(SOFTMMU_CODE_ACCESS) */
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367 |
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368 | #ifdef VBOX
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369 | #undef DATA_TYPE_PROMOTED
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370 | #endif
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371 | #undef READ_ACCESS_TYPE
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372 | #undef SHIFT
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373 | #undef DATA_TYPE
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374 | #undef SUFFIX
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375 | #undef USUFFIX
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376 | #undef DATA_SIZE
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377 | #undef ADDR_READ
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