VirtualBox

source: vbox/trunk/src/recompiler_new/cpu-all.h@ 16894

Last change on this file since 16894 was 15284, checked in by vboxsync, 16 years ago

PGM, REM: Virtual address in TLB - this is what I meant...
  • Property svn:eol-style set to native
File size: 36.6 KB
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1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#ifndef CPU_ALL_H
30#define CPU_ALL_H
31
32#ifdef VBOX
33# ifndef LOG_GROUP
34# define LOG_GROUP LOG_GROUP_REM
35# endif
36# include <VBox/log.h>
37# include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
38#endif
39
40#if defined(__arm__) || defined(__sparc__)
41#define WORDS_ALIGNED
42#endif
43
44/* some important defines:
45 *
46 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
47 * memory accesses.
48 *
49 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
50 * otherwise little endian.
51 *
52 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
53 *
54 * TARGET_WORDS_BIGENDIAN : same for target cpu
55 */
56
57#include "bswap.h"
58
59#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
60#define BSWAP_NEEDED
61#endif
62
63#ifdef BSWAP_NEEDED
64
65static inline uint16_t tswap16(uint16_t s)
66{
67 return bswap16(s);
68}
69
70static inline uint32_t tswap32(uint32_t s)
71{
72 return bswap32(s);
73}
74
75static inline uint64_t tswap64(uint64_t s)
76{
77 return bswap64(s);
78}
79
80static inline void tswap16s(uint16_t *s)
81{
82 *s = bswap16(*s);
83}
84
85static inline void tswap32s(uint32_t *s)
86{
87 *s = bswap32(*s);
88}
89
90static inline void tswap64s(uint64_t *s)
91{
92 *s = bswap64(*s);
93}
94
95#else
96
97#ifndef VBOX
98static inline uint16_t tswap16(uint16_t s)
99#else
100DECLINLINE(uint16_t) tswap16(uint16_t s)
101#endif
102{
103 return s;
104}
105
106#ifndef VBOX
107static inline uint32_t tswap32(uint32_t s)
108#else
109DECLINLINE(uint32_t) tswap32(uint32_t s)
110#endif
111{
112 return s;
113}
114
115#ifndef VBOX
116static inline uint64_t tswap64(uint64_t s)
117#else
118DECLINLINE(uint64_t) tswap64(uint64_t s)
119#endif
120{
121 return s;
122}
123
124#ifndef VBOX
125static inline void tswap16s(uint16_t *s)
126#else
127DECLINLINE(void) tswap16s(uint16_t *s)
128#endif
129{
130}
131
132#ifndef VBOX
133static inline void tswap32s(uint32_t *s)
134#else
135DECLINLINE(void) tswap32s(uint32_t *s)
136#endif
137{
138}
139
140#ifndef VBOX
141static inline void tswap64s(uint64_t *s)
142#else
143DECLINLINE(void) tswap64s(uint64_t *s)
144#endif
145{
146}
147
148#endif
149
150#if TARGET_LONG_SIZE == 4
151#define tswapl(s) tswap32(s)
152#define tswapls(s) tswap32s((uint32_t *)(s))
153#define bswaptls(s) bswap32s(s)
154#else
155#define tswapl(s) tswap64(s)
156#define tswapls(s) tswap64s((uint64_t *)(s))
157#define bswaptls(s) bswap64s(s)
158#endif
159
160typedef union {
161 float32 f;
162 uint32_t l;
163} CPU_FloatU;
164
165/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
166 endian ! */
167typedef union {
168 float64 d;
169#if defined(WORDS_BIGENDIAN) \
170 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
171 struct {
172 uint32_t upper;
173 uint32_t lower;
174 } l;
175#else
176 struct {
177 uint32_t lower;
178 uint32_t upper;
179 } l;
180#endif
181 uint64_t ll;
182} CPU_DoubleU;
183
184#ifdef TARGET_SPARC
185typedef union {
186 float128 q;
187#if defined(WORDS_BIGENDIAN) \
188 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
189 struct {
190 uint32_t upmost;
191 uint32_t upper;
192 uint32_t lower;
193 uint32_t lowest;
194 } l;
195 struct {
196 uint64_t upper;
197 uint64_t lower;
198 } ll;
199#else
200 struct {
201 uint32_t lowest;
202 uint32_t lower;
203 uint32_t upper;
204 uint32_t upmost;
205 } l;
206 struct {
207 uint64_t lower;
208 uint64_t upper;
209 } ll;
210#endif
211} CPU_QuadU;
212#endif
213
214/* CPU memory access without any memory or io remapping */
215
216/*
217 * the generic syntax for the memory accesses is:
218 *
219 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
220 *
221 * store: st{type}{size}{endian}_{access_type}(ptr, val)
222 *
223 * type is:
224 * (empty): integer access
225 * f : float access
226 *
227 * sign is:
228 * (empty): for floats or 32 bit size
229 * u : unsigned
230 * s : signed
231 *
232 * size is:
233 * b: 8 bits
234 * w: 16 bits
235 * l: 32 bits
236 * q: 64 bits
237 *
238 * endian is:
239 * (empty): target cpu endianness or 8 bit access
240 * r : reversed target cpu endianness (not implemented yet)
241 * be : big endian (not implemented yet)
242 * le : little endian (not implemented yet)
243 *
244 * access_type is:
245 * raw : host memory access
246 * user : user mode access using soft MMU
247 * kernel : kernel mode access using soft MMU
248 */
249
250#ifdef VBOX
251void remAbort(int rc, const char *pszTip) __attribute__((__noreturn__));
252
253#ifndef VBOX_WITH_NEW_PHYS_CODE
254void remR3GrowDynRange(unsigned long physaddr);
255#endif
256
257void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb);
258RTCCUINTREG remR3PhysReadU8(RTGCPHYS SrcGCPhys);
259RTCCINTREG remR3PhysReadS8(RTGCPHYS SrcGCPhys);
260RTCCUINTREG remR3PhysReadU16(RTGCPHYS SrcGCPhys);
261RTCCINTREG remR3PhysReadS16(RTGCPHYS SrcGCPhys);
262RTCCUINTREG remR3PhysReadU32(RTGCPHYS SrcGCPhys);
263RTCCINTREG remR3PhysReadS32(RTGCPHYS SrcGCPhys);
264uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys);
265int64_t remR3PhysReadS64(RTGCPHYS SrcGCPhys);
266void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb);
267void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val);
268void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val);
269void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val);
270void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val);
271
272#ifndef REM_PHYS_ADDR_IN_TLB
273void *remR3TlbGCPhys2Ptr(CPUState *env1, target_ulong physAddr, int fWritable);
274target_ulong remR3HCVirt2GCPhys(CPUState *env1, void *addr);
275#endif
276
277#endif /* VBOX */
278
279#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
280
281DECLINLINE(uint8_t) ldub_p(void *ptr)
282{
283 VBOX_CHECK_ADDR(ptr);
284 return remR3PhysReadU8((uintptr_t)ptr);
285}
286
287DECLINLINE(int8_t) ldsb_p(void *ptr)
288{
289 VBOX_CHECK_ADDR(ptr);
290 return remR3PhysReadS8((uintptr_t)ptr);
291}
292
293DECLINLINE(void) stb_p(void *ptr, int v)
294{
295 VBOX_CHECK_ADDR(ptr);
296 remR3PhysWriteU8((uintptr_t)ptr, v);
297}
298
299DECLINLINE(uint32_t) lduw_le_p(void *ptr)
300{
301 VBOX_CHECK_ADDR(ptr);
302 return remR3PhysReadU16((uintptr_t)ptr);
303}
304
305DECLINLINE(int32_t) ldsw_le_p(void *ptr)
306{
307 VBOX_CHECK_ADDR(ptr);
308 return remR3PhysReadS16((uintptr_t)ptr);
309}
310
311DECLINLINE(void) stw_le_p(void *ptr, int v)
312{
313 VBOX_CHECK_ADDR(ptr);
314 remR3PhysWriteU16((uintptr_t)ptr, v);
315}
316
317DECLINLINE(uint32_t) ldl_le_p(void *ptr)
318{
319 VBOX_CHECK_ADDR(ptr);
320 return remR3PhysReadU32((uintptr_t)ptr);
321}
322
323DECLINLINE(void) stl_le_p(void *ptr, int v)
324{
325 VBOX_CHECK_ADDR(ptr);
326 remR3PhysWriteU32((uintptr_t)ptr, v);
327}
328
329DECLINLINE(void) stq_le_p(void *ptr, uint64_t v)
330{
331 VBOX_CHECK_ADDR(ptr);
332 remR3PhysWriteU64((uintptr_t)ptr, v);
333}
334
335DECLINLINE(uint64_t) ldq_le_p(void *ptr)
336{
337 VBOX_CHECK_ADDR(ptr);
338 return remR3PhysReadU64((uintptr_t)ptr);
339}
340
341#undef VBOX_CHECK_ADDR
342
343/* float access */
344
345DECLINLINE(float32) ldfl_le_p(void *ptr)
346{
347 union {
348 float32 f;
349 uint32_t i;
350 } u;
351 u.i = ldl_le_p(ptr);
352 return u.f;
353}
354
355DECLINLINE(void) stfl_le_p(void *ptr, float32 v)
356{
357 union {
358 float32 f;
359 uint32_t i;
360 } u;
361 u.f = v;
362 stl_le_p(ptr, u.i);
363}
364
365DECLINLINE(float64) ldfq_le_p(void *ptr)
366{
367 CPU_DoubleU u;
368 u.l.lower = ldl_le_p(ptr);
369 u.l.upper = ldl_le_p((uint8_t*)ptr + 4);
370 return u.d;
371}
372
373DECLINLINE(void) stfq_le_p(void *ptr, float64 v)
374{
375 CPU_DoubleU u;
376 u.d = v;
377 stl_le_p(ptr, u.l.lower);
378 stl_le_p((uint8_t*)ptr + 4, u.l.upper);
379}
380
381#else /* !(VBOX && REM_PHYS_ADDR_IN_TLB) */
382
383static inline int ldub_p(void *ptr)
384{
385 return *(uint8_t *)ptr;
386}
387
388static inline int ldsb_p(void *ptr)
389{
390 return *(int8_t *)ptr;
391}
392
393static inline void stb_p(void *ptr, int v)
394{
395 *(uint8_t *)ptr = v;
396}
397
398/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
399 kernel handles unaligned load/stores may give better results, but
400 it is a system wide setting : bad */
401#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
402
403/* conservative code for little endian unaligned accesses */
404static inline int lduw_le_p(void *ptr)
405{
406#ifdef __powerpc__
407 int val;
408 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
409 return val;
410#else
411 uint8_t *p = ptr;
412 return p[0] | (p[1] << 8);
413#endif
414}
415
416static inline int ldsw_le_p(void *ptr)
417{
418#ifdef __powerpc__
419 int val;
420 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
421 return (int16_t)val;
422#else
423 uint8_t *p = ptr;
424 return (int16_t)(p[0] | (p[1] << 8));
425#endif
426}
427
428static inline int ldl_le_p(void *ptr)
429{
430#ifdef __powerpc__
431 int val;
432 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
433 return val;
434#else
435 uint8_t *p = ptr;
436 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
437#endif
438}
439
440static inline uint64_t ldq_le_p(void *ptr)
441{
442 uint8_t *p = ptr;
443 uint32_t v1, v2;
444 v1 = ldl_le_p(p);
445 v2 = ldl_le_p(p + 4);
446 return v1 | ((uint64_t)v2 << 32);
447}
448
449static inline void stw_le_p(void *ptr, int v)
450{
451#ifdef __powerpc__
452 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
453#else
454 uint8_t *p = ptr;
455 p[0] = v;
456 p[1] = v >> 8;
457#endif
458}
459
460static inline void stl_le_p(void *ptr, int v)
461{
462#ifdef __powerpc__
463 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
464#else
465 uint8_t *p = ptr;
466 p[0] = v;
467 p[1] = v >> 8;
468 p[2] = v >> 16;
469 p[3] = v >> 24;
470#endif
471}
472
473static inline void stq_le_p(void *ptr, uint64_t v)
474{
475 uint8_t *p = ptr;
476 stl_le_p(p, (uint32_t)v);
477 stl_le_p(p + 4, v >> 32);
478}
479
480/* float access */
481
482static inline float32 ldfl_le_p(void *ptr)
483{
484 union {
485 float32 f;
486 uint32_t i;
487 } u;
488 u.i = ldl_le_p(ptr);
489 return u.f;
490}
491
492static inline void stfl_le_p(void *ptr, float32 v)
493{
494 union {
495 float32 f;
496 uint32_t i;
497 } u;
498 u.f = v;
499 stl_le_p(ptr, u.i);
500}
501
502static inline float64 ldfq_le_p(void *ptr)
503{
504 CPU_DoubleU u;
505 u.l.lower = ldl_le_p(ptr);
506 u.l.upper = ldl_le_p(ptr + 4);
507 return u.d;
508}
509
510static inline void stfq_le_p(void *ptr, float64 v)
511{
512 CPU_DoubleU u;
513 u.d = v;
514 stl_le_p(ptr, u.l.lower);
515 stl_le_p(ptr + 4, u.l.upper);
516}
517
518#else
519
520static inline int lduw_le_p(void *ptr)
521{
522 return *(uint16_t *)ptr;
523}
524
525static inline int ldsw_le_p(void *ptr)
526{
527 return *(int16_t *)ptr;
528}
529
530static inline int ldl_le_p(void *ptr)
531{
532 return *(uint32_t *)ptr;
533}
534
535static inline uint64_t ldq_le_p(void *ptr)
536{
537 return *(uint64_t *)ptr;
538}
539
540static inline void stw_le_p(void *ptr, int v)
541{
542 *(uint16_t *)ptr = v;
543}
544
545static inline void stl_le_p(void *ptr, int v)
546{
547 *(uint32_t *)ptr = v;
548}
549
550static inline void stq_le_p(void *ptr, uint64_t v)
551{
552 *(uint64_t *)ptr = v;
553}
554
555/* float access */
556
557static inline float32 ldfl_le_p(void *ptr)
558{
559 return *(float32 *)ptr;
560}
561
562static inline float64 ldfq_le_p(void *ptr)
563{
564 return *(float64 *)ptr;
565}
566
567static inline void stfl_le_p(void *ptr, float32 v)
568{
569 *(float32 *)ptr = v;
570}
571
572static inline void stfq_le_p(void *ptr, float64 v)
573{
574 *(float64 *)ptr = v;
575}
576#endif
577#endif /* !VBOX */
578
579#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
580
581#ifndef VBOX
582static inline int lduw_be_p(void *ptr)
583{
584#if defined(__i386__)
585 int val;
586 asm volatile ("movzwl %1, %0\n"
587 "xchgb %b0, %h0\n"
588 : "=q" (val)
589 : "m" (*(uint16_t *)ptr));
590 return val;
591#else
592 uint8_t *b = (uint8_t *) ptr;
593 return ((b[0] << 8) | b[1]);
594#endif
595}
596#else /* VBOX */
597DECLINLINE(int) lduw_be_p(void *ptr)
598{
599#if defined(__i386__) && !defined(_MSC_VER)
600 int val;
601 asm volatile ("movzwl %1, %0\n"
602 "xchgb %b0, %h0\n"
603 : "=q" (val)
604 : "m" (*(uint16_t *)ptr));
605 return val;
606#else
607 uint8_t *b = (uint8_t *) ptr;
608 return ((b[0] << 8) | b[1]);
609#endif
610}
611#endif
612
613#ifndef VBOX
614static inline int ldsw_be_p(void *ptr)
615{
616#if defined(__i386__)
617 int val;
618 asm volatile ("movzwl %1, %0\n"
619 "xchgb %b0, %h0\n"
620 : "=q" (val)
621 : "m" (*(uint16_t *)ptr));
622 return (int16_t)val;
623#else
624 uint8_t *b = (uint8_t *) ptr;
625 return (int16_t)((b[0] << 8) | b[1]);
626#endif
627}
628#else
629DECLINLINE(int) ldsw_be_p(void *ptr)
630{
631#if defined(__i386__) && !defined(_MSC_VER)
632 int val;
633 asm volatile ("movzwl %1, %0\n"
634 "xchgb %b0, %h0\n"
635 : "=q" (val)
636 : "m" (*(uint16_t *)ptr));
637 return (int16_t)val;
638#else
639 uint8_t *b = (uint8_t *) ptr;
640 return (int16_t)((b[0] << 8) | b[1]);
641#endif
642}
643#endif
644
645#ifndef VBOX
646static inline int ldl_be_p(void *ptr)
647{
648#if defined(__i386__) || defined(__x86_64__)
649 int val;
650 asm volatile ("movl %1, %0\n"
651 "bswap %0\n"
652 : "=r" (val)
653 : "m" (*(uint32_t *)ptr));
654 return val;
655#else
656 uint8_t *b = (uint8_t *) ptr;
657 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
658#endif
659}
660#else
661DECLINLINE(int) ldl_be_p(void *ptr)
662{
663#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
664 int val;
665 asm volatile ("movl %1, %0\n"
666 "bswap %0\n"
667 : "=r" (val)
668 : "m" (*(uint32_t *)ptr));
669 return val;
670#else
671 uint8_t *b = (uint8_t *) ptr;
672 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
673#endif
674}
675#endif
676
677#ifndef VBOX
678static inline uint64_t ldq_be_p(void *ptr)
679#else
680DECLINLINE(uint64_t) ldq_be_p(void *ptr)
681#endif
682{
683 uint32_t a,b;
684 a = ldl_be_p(ptr);
685 b = ldl_be_p((uint8_t*)ptr+4);
686 return (((uint64_t)a<<32)|b);
687}
688
689#ifndef VBOX
690static inline void stw_be_p(void *ptr, int v)
691{
692#if defined(__i386__)
693 asm volatile ("xchgb %b0, %h0\n"
694 "movw %w0, %1\n"
695 : "=q" (v)
696 : "m" (*(uint16_t *)ptr), "0" (v));
697#else
698 uint8_t *d = (uint8_t *) ptr;
699 d[0] = v >> 8;
700 d[1] = v;
701#endif
702}
703#else
704DECLINLINE(void) stw_be_p(void *ptr, int v)
705{
706#if defined(__i386__) && !defined(_MSC_VER)
707 asm volatile ("xchgb %b0, %h0\n"
708 "movw %w0, %1\n"
709 : "=q" (v)
710 : "m" (*(uint16_t *)ptr), "0" (v));
711#else
712 uint8_t *d = (uint8_t *) ptr;
713 d[0] = v >> 8;
714 d[1] = v;
715#endif
716}
717
718#endif /* VBOX */
719
720#ifndef VBOX
721static inline void stl_be_p(void *ptr, int v)
722{
723#if defined(__i386__) || defined(__x86_64__)
724 asm volatile ("bswap %0\n"
725 "movl %0, %1\n"
726 : "=r" (v)
727 : "m" (*(uint32_t *)ptr), "0" (v));
728#else
729 uint8_t *d = (uint8_t *) ptr;
730 d[0] = v >> 24;
731 d[1] = v >> 16;
732 d[2] = v >> 8;
733 d[3] = v;
734#endif
735}
736#else
737DECLINLINE(void) stl_be_p(void *ptr, int v)
738{
739#if !defined(_MSC_VER) && (defined(__i386__) || defined(__x86_64__))
740 asm volatile ("bswap %0\n"
741 "movl %0, %1\n"
742 : "=r" (v)
743 : "m" (*(uint32_t *)ptr), "0" (v));
744#else
745 uint8_t *d = (uint8_t *) ptr;
746 d[0] = v >> 24;
747 d[1] = v >> 16;
748 d[2] = v >> 8;
749 d[3] = v;
750#endif
751}
752#endif /* VBOX */
753
754#ifndef VBOX
755static inline void stq_be_p(void *ptr, uint64_t v)
756#else
757DECLINLINE(void) stq_be_p(void *ptr, uint64_t v)
758#endif
759{
760 stl_be_p(ptr, v >> 32);
761 stl_be_p((uint8_t*)ptr + 4, v);
762}
763
764/* float access */
765#ifndef VBOX
766static inline float32 ldfl_be_p(void *ptr)
767#else
768DECLINLINE(float32) ldfl_be_p(void *ptr)
769#endif
770{
771 union {
772 float32 f;
773 uint32_t i;
774 } u;
775 u.i = ldl_be_p(ptr);
776 return u.f;
777}
778
779#ifndef VBOX
780static inline void stfl_be_p(void *ptr, float32 v)
781#else
782DECLINLINE(void) stfl_be_p(void *ptr, float32 v)
783#endif
784{
785 union {
786 float32 f;
787 uint32_t i;
788 } u;
789 u.f = v;
790 stl_be_p(ptr, u.i);
791}
792
793#ifndef VBOX
794static inline float64 ldfq_be_p(void *ptr)
795#else
796DECLINLINE(float64) ldfq_be_p(void *ptr)
797#endif
798{
799 CPU_DoubleU u;
800 u.l.upper = ldl_be_p(ptr);
801 u.l.lower = ldl_be_p((uint8_t*)ptr + 4);
802 return u.d;
803}
804
805#ifndef VBOX
806static inline void stfq_be_p(void *ptr, float64 v)
807#else
808DECLINLINE(void) stfq_be_p(void *ptr, float64 v)
809#endif
810{
811 CPU_DoubleU u;
812 u.d = v;
813 stl_be_p(ptr, u.l.upper);
814 stl_be_p((uint8_t*)ptr + 4, u.l.lower);
815}
816
817#else
818
819static inline int lduw_be_p(void *ptr)
820{
821 return *(uint16_t *)ptr;
822}
823
824static inline int ldsw_be_p(void *ptr)
825{
826 return *(int16_t *)ptr;
827}
828
829static inline int ldl_be_p(void *ptr)
830{
831 return *(uint32_t *)ptr;
832}
833
834static inline uint64_t ldq_be_p(void *ptr)
835{
836 return *(uint64_t *)ptr;
837}
838
839static inline void stw_be_p(void *ptr, int v)
840{
841 *(uint16_t *)ptr = v;
842}
843
844static inline void stl_be_p(void *ptr, int v)
845{
846 *(uint32_t *)ptr = v;
847}
848
849static inline void stq_be_p(void *ptr, uint64_t v)
850{
851 *(uint64_t *)ptr = v;
852}
853
854/* float access */
855
856static inline float32 ldfl_be_p(void *ptr)
857{
858 return *(float32 *)ptr;
859}
860
861static inline float64 ldfq_be_p(void *ptr)
862{
863 return *(float64 *)ptr;
864}
865
866static inline void stfl_be_p(void *ptr, float32 v)
867{
868 *(float32 *)ptr = v;
869}
870
871static inline void stfq_be_p(void *ptr, float64 v)
872{
873 *(float64 *)ptr = v;
874}
875
876#endif
877
878/* target CPU memory access functions */
879#if defined(TARGET_WORDS_BIGENDIAN)
880#define lduw_p(p) lduw_be_p(p)
881#define ldsw_p(p) ldsw_be_p(p)
882#define ldl_p(p) ldl_be_p(p)
883#define ldq_p(p) ldq_be_p(p)
884#define ldfl_p(p) ldfl_be_p(p)
885#define ldfq_p(p) ldfq_be_p(p)
886#define stw_p(p, v) stw_be_p(p, v)
887#define stl_p(p, v) stl_be_p(p, v)
888#define stq_p(p, v) stq_be_p(p, v)
889#define stfl_p(p, v) stfl_be_p(p, v)
890#define stfq_p(p, v) stfq_be_p(p, v)
891#else
892#define lduw_p(p) lduw_le_p(p)
893#define ldsw_p(p) ldsw_le_p(p)
894#define ldl_p(p) ldl_le_p(p)
895#define ldq_p(p) ldq_le_p(p)
896#define ldfl_p(p) ldfl_le_p(p)
897#define ldfq_p(p) ldfq_le_p(p)
898#define stw_p(p, v) stw_le_p(p, v)
899#define stl_p(p, v) stl_le_p(p, v)
900#define stq_p(p, v) stq_le_p(p, v)
901#define stfl_p(p, v) stfl_le_p(p, v)
902#define stfq_p(p, v) stfq_le_p(p, v)
903#endif
904
905/* MMU memory access macros */
906
907#if defined(CONFIG_USER_ONLY)
908/* On some host systems the guest address space is reserved on the host.
909 * This allows the guest address space to be offset to a convenient location.
910 */
911//#define GUEST_BASE 0x20000000
912#define GUEST_BASE 0
913
914/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
915#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
916#define h2g(x) ((target_ulong)(x - GUEST_BASE))
917#define saddr(x) g2h(x)
918#define laddr(x) g2h(x)
919
920#else /* !CONFIG_USER_ONLY */
921/* NOTE: we use double casts if pointers and target_ulong have
922 different sizes */
923#define saddr(x) (uint8_t *)(long)(x)
924#define laddr(x) (uint8_t *)(long)(x)
925#endif
926
927#define ldub_raw(p) ldub_p(laddr((p)))
928#define ldsb_raw(p) ldsb_p(laddr((p)))
929#define lduw_raw(p) lduw_p(laddr((p)))
930#define ldsw_raw(p) ldsw_p(laddr((p)))
931#define ldl_raw(p) ldl_p(laddr((p)))
932#define ldq_raw(p) ldq_p(laddr((p)))
933#define ldfl_raw(p) ldfl_p(laddr((p)))
934#define ldfq_raw(p) ldfq_p(laddr((p)))
935#define stb_raw(p, v) stb_p(saddr((p)), v)
936#define stw_raw(p, v) stw_p(saddr((p)), v)
937#define stl_raw(p, v) stl_p(saddr((p)), v)
938#define stq_raw(p, v) stq_p(saddr((p)), v)
939#define stfl_raw(p, v) stfl_p(saddr((p)), v)
940#define stfq_raw(p, v) stfq_p(saddr((p)), v)
941
942
943#if defined(CONFIG_USER_ONLY)
944
945/* if user mode, no other memory access functions */
946#define ldub(p) ldub_raw(p)
947#define ldsb(p) ldsb_raw(p)
948#define lduw(p) lduw_raw(p)
949#define ldsw(p) ldsw_raw(p)
950#define ldl(p) ldl_raw(p)
951#define ldq(p) ldq_raw(p)
952#define ldfl(p) ldfl_raw(p)
953#define ldfq(p) ldfq_raw(p)
954#define stb(p, v) stb_raw(p, v)
955#define stw(p, v) stw_raw(p, v)
956#define stl(p, v) stl_raw(p, v)
957#define stq(p, v) stq_raw(p, v)
958#define stfl(p, v) stfl_raw(p, v)
959#define stfq(p, v) stfq_raw(p, v)
960
961#define ldub_code(p) ldub_raw(p)
962#define ldsb_code(p) ldsb_raw(p)
963#define lduw_code(p) lduw_raw(p)
964#define ldsw_code(p) ldsw_raw(p)
965#define ldl_code(p) ldl_raw(p)
966
967#define ldub_kernel(p) ldub_raw(p)
968#define ldsb_kernel(p) ldsb_raw(p)
969#define lduw_kernel(p) lduw_raw(p)
970#define ldsw_kernel(p) ldsw_raw(p)
971#define ldl_kernel(p) ldl_raw(p)
972#define ldfl_kernel(p) ldfl_raw(p)
973#define ldfq_kernel(p) ldfq_raw(p)
974#define stb_kernel(p, v) stb_raw(p, v)
975#define stw_kernel(p, v) stw_raw(p, v)
976#define stl_kernel(p, v) stl_raw(p, v)
977#define stq_kernel(p, v) stq_raw(p, v)
978#define stfl_kernel(p, v) stfl_raw(p, v)
979#define stfq_kernel(p, vt) stfq_raw(p, v)
980
981#endif /* defined(CONFIG_USER_ONLY) */
982
983/* page related stuff */
984
985#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
986#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
987#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
988
989/* ??? These should be the larger of unsigned long and target_ulong. */
990extern unsigned long qemu_real_host_page_size;
991extern unsigned long qemu_host_page_bits;
992extern unsigned long qemu_host_page_size;
993extern unsigned long qemu_host_page_mask;
994
995#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
996
997/* same as PROT_xxx */
998#define PAGE_READ 0x0001
999#define PAGE_WRITE 0x0002
1000#define PAGE_EXEC 0x0004
1001#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
1002#define PAGE_VALID 0x0008
1003/* original state of the write flag (used when tracking self-modifying
1004 code */
1005#define PAGE_WRITE_ORG 0x0010
1006#define PAGE_RESERVED 0x0020
1007
1008void page_dump(FILE *f);
1009int page_get_flags(target_ulong address);
1010void page_set_flags(target_ulong start, target_ulong end, int flags);
1011int page_check_range(target_ulong start, target_ulong len, int flags);
1012void page_unprotect_range(target_ulong data, target_ulong data_size);
1013
1014#define SINGLE_CPU_DEFINES
1015#ifdef SINGLE_CPU_DEFINES
1016
1017#if defined(TARGET_I386)
1018
1019#define CPUState CPUX86State
1020#define cpu_init cpu_x86_init
1021#define cpu_exec cpu_x86_exec
1022#define cpu_gen_code cpu_x86_gen_code
1023#define cpu_signal_handler cpu_x86_signal_handler
1024
1025#elif defined(TARGET_ARM)
1026
1027#define CPUState CPUARMState
1028#define cpu_init cpu_arm_init
1029#define cpu_exec cpu_arm_exec
1030#define cpu_gen_code cpu_arm_gen_code
1031#define cpu_signal_handler cpu_arm_signal_handler
1032
1033#elif defined(TARGET_SPARC)
1034
1035#define CPUState CPUSPARCState
1036#define cpu_init cpu_sparc_init
1037#define cpu_exec cpu_sparc_exec
1038#define cpu_gen_code cpu_sparc_gen_code
1039#define cpu_signal_handler cpu_sparc_signal_handler
1040
1041#elif defined(TARGET_PPC)
1042
1043#define CPUState CPUPPCState
1044#define cpu_init cpu_ppc_init
1045#define cpu_exec cpu_ppc_exec
1046#define cpu_gen_code cpu_ppc_gen_code
1047#define cpu_signal_handler cpu_ppc_signal_handler
1048
1049#elif defined(TARGET_M68K)
1050#define CPUState CPUM68KState
1051#define cpu_init cpu_m68k_init
1052#define cpu_exec cpu_m68k_exec
1053#define cpu_gen_code cpu_m68k_gen_code
1054#define cpu_signal_handler cpu_m68k_signal_handler
1055
1056#elif defined(TARGET_MIPS)
1057#define CPUState CPUMIPSState
1058#define cpu_init cpu_mips_init
1059#define cpu_exec cpu_mips_exec
1060#define cpu_gen_code cpu_mips_gen_code
1061#define cpu_signal_handler cpu_mips_signal_handler
1062
1063#elif defined(TARGET_SH4)
1064#define CPUState CPUSH4State
1065#define cpu_init cpu_sh4_init
1066#define cpu_exec cpu_sh4_exec
1067#define cpu_gen_code cpu_sh4_gen_code
1068#define cpu_signal_handler cpu_sh4_signal_handler
1069
1070#else
1071
1072#error unsupported target CPU
1073
1074#endif
1075
1076#endif /* SINGLE_CPU_DEFINES */
1077
1078void cpu_dump_state(CPUState *env, FILE *f,
1079 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1080 int flags);
1081
1082DECLNORETURN(void) cpu_abort(CPUState *env, const char *fmt, ...);
1083extern CPUState *first_cpu;
1084extern CPUState *cpu_single_env;
1085extern int64_t qemu_icount;
1086extern int use_icount;
1087
1088#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
1089#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
1090#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
1091#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
1092#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
1093#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
1094#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
1095#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
1096#define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
1097#define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
1098
1099#ifdef VBOX
1100/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
1101#define CPU_INTERRUPT_SINGLE_INSTR 0x0400
1102/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
1103#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0800
1104/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
1105#define CPU_INTERRUPT_RC 0x1000
1106/** Exit current TB to process an external interrupt request (also in op.c!!) */
1107#define CPU_INTERRUPT_EXTERNAL_EXIT 0x2000
1108/** Exit current TB to process an external interrupt request (also in op.c!!) */
1109#define CPU_INTERRUPT_EXTERNAL_HARD 0x4000
1110/** Exit current TB to process an external interrupt request (also in op.c!!) */
1111#define CPU_INTERRUPT_EXTERNAL_TIMER 0x8000
1112/** Exit current TB to process an external interrupt request (also in op.c!!) */
1113#define CPU_INTERRUPT_EXTERNAL_DMA 0x10000
1114#endif /* VBOX */
1115void cpu_interrupt(CPUState *s, int mask);
1116void cpu_reset_interrupt(CPUState *env, int mask);
1117
1118int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type);
1119int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
1120void cpu_watchpoint_remove_all(CPUState *env);
1121int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
1122int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
1123void cpu_breakpoint_remove_all(CPUState *env);
1124
1125#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1126#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1127#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1128
1129void cpu_single_step(CPUState *env, int enabled);
1130void cpu_reset(CPUState *s);
1131
1132/* Return the physical page corresponding to a virtual one. Use it
1133 only for debugging because no protection checks are done. Return -1
1134 if no page found. */
1135target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
1136
1137#define CPU_LOG_TB_OUT_ASM (1 << 0)
1138#define CPU_LOG_TB_IN_ASM (1 << 1)
1139#define CPU_LOG_TB_OP (1 << 2)
1140#define CPU_LOG_TB_OP_OPT (1 << 3)
1141#define CPU_LOG_INT (1 << 4)
1142#define CPU_LOG_EXEC (1 << 5)
1143#define CPU_LOG_PCALL (1 << 6)
1144#define CPU_LOG_IOPORT (1 << 7)
1145#define CPU_LOG_TB_CPU (1 << 8)
1146
1147/* define log items */
1148typedef struct CPULogItem {
1149 int mask;
1150 const char *name;
1151 const char *help;
1152} CPULogItem;
1153
1154extern CPULogItem cpu_log_items[];
1155
1156void cpu_set_log(int log_flags);
1157void cpu_set_log_filename(const char *filename);
1158int cpu_str_to_log_mask(const char *str);
1159
1160/* IO ports API */
1161
1162/* NOTE: as these functions may be even used when there is an isa
1163 brige on non x86 targets, we always defined them */
1164#ifndef NO_CPU_IO_DEFS
1165void cpu_outb(CPUState *env, int addr, int val);
1166void cpu_outw(CPUState *env, int addr, int val);
1167void cpu_outl(CPUState *env, int addr, int val);
1168int cpu_inb(CPUState *env, int addr);
1169int cpu_inw(CPUState *env, int addr);
1170int cpu_inl(CPUState *env, int addr);
1171#endif
1172
1173/* address in the RAM (different from a physical address) */
1174#ifdef USE_KQEMU
1175typedef uint32_t ram_addr_t;
1176#else
1177typedef unsigned long ram_addr_t;
1178#endif
1179
1180/* memory API */
1181
1182#ifndef VBOX
1183extern int phys_ram_size;
1184extern int phys_ram_fd;
1185extern int phys_ram_size;
1186#else /* VBOX */
1187extern RTGCPHYS phys_ram_size;
1188/** This is required for bounds checking the phys_ram_dirty accesses. */
1189extern uint32_t phys_ram_dirty_size;
1190#endif /* VBOX */
1191#if !defined(VBOX)
1192extern uint8_t *phys_ram_base;
1193#endif
1194extern uint8_t *phys_ram_dirty;
1195
1196/* physical memory access */
1197
1198/* MMIO pages are identified by a combination of an IO device index and
1199 3 flags. The ROMD code stores the page ram offset in iotlb entry,
1200 so only a limited number of ids are avaiable. */
1201
1202#define IO_MEM_SHIFT 3
1203#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
1204
1205#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
1206#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
1207#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
1208#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
1209#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
1210#define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
1211#endif
1212
1213/* Acts like a ROM when read and like a device when written. */
1214#define IO_MEM_ROMD (1)
1215#define IO_MEM_SUBPAGE (2)
1216#define IO_MEM_SUBWIDTH (4)
1217
1218/* Flags stored in the low bits of the TLB virtual address. These are
1219 defined so that fast path ram access is all zeros. */
1220/* Zero if TLB entry is valid. */
1221#define TLB_INVALID_MASK (1 << 3)
1222/* Set if TLB entry references a clean RAM page. The iotlb entry will
1223 contain the page physical address. */
1224#define TLB_NOTDIRTY (1 << 4)
1225/* Set if TLB entry is an IO callback. */
1226#define TLB_MMIO (1 << 5)
1227
1228typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
1229typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
1230
1231void cpu_register_physical_memory(target_phys_addr_t start_addr,
1232 ram_addr_t size,
1233 ram_addr_t phys_offset);
1234uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
1235ram_addr_t qemu_ram_alloc(ram_addr_t);
1236void qemu_ram_free(ram_addr_t addr);
1237int cpu_register_io_memory(int io_index,
1238 CPUReadMemoryFunc **mem_read,
1239 CPUWriteMemoryFunc **mem_write,
1240 void *opaque);
1241CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
1242CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
1243
1244void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1245 int len, int is_write);
1246#ifndef VBOX
1247static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1248 uint8_t *buf, int len)
1249#else
1250DECLINLINE(void) cpu_physical_memory_read(target_phys_addr_t addr,
1251 uint8_t *buf, int len)
1252#endif
1253{
1254 cpu_physical_memory_rw(addr, buf, len, 0);
1255}
1256#ifndef VBOX
1257static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1258 const uint8_t *buf, int len)
1259#else
1260DECLINLINE(void) cpu_physical_memory_write(target_phys_addr_t addr,
1261 const uint8_t *buf, int len)
1262#endif
1263{
1264 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1265}
1266uint32_t ldub_phys(target_phys_addr_t addr);
1267uint32_t lduw_phys(target_phys_addr_t addr);
1268uint32_t ldl_phys(target_phys_addr_t addr);
1269uint64_t ldq_phys(target_phys_addr_t addr);
1270void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1271void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
1272void stb_phys(target_phys_addr_t addr, uint32_t val);
1273void stw_phys(target_phys_addr_t addr, uint32_t val);
1274void stl_phys(target_phys_addr_t addr, uint32_t val);
1275void stq_phys(target_phys_addr_t addr, uint64_t val);
1276
1277void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1278 const uint8_t *buf, int len);
1279int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1280 uint8_t *buf, int len, int is_write);
1281
1282#define VGA_DIRTY_FLAG 0x01
1283#define CODE_DIRTY_FLAG 0x02
1284#define KQEMU_DIRTY_FLAG 0x04
1285#define MIGRATION_DIRTY_FLAG 0x08
1286
1287/* read dirty bit (return 0 or 1) */
1288#ifndef VBOX
1289static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1290{
1291 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1292}
1293#else
1294DECLINLINE(int) cpu_physical_memory_is_dirty(ram_addr_t addr)
1295{
1296 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1297 {
1298 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1299 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1300 return 0;
1301 }
1302 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1303}
1304#endif
1305
1306#ifndef VBOX
1307static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1308 int dirty_flags)
1309{
1310 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1311}
1312#else
1313DECLINLINE(int) cpu_physical_memory_get_dirty(ram_addr_t addr,
1314 int dirty_flags)
1315{
1316 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1317 {
1318 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1319 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1320 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1321 }
1322 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1323}
1324#endif
1325
1326#ifndef VBOX
1327static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1328{
1329 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1330}
1331#else
1332DECLINLINE(void) cpu_physical_memory_set_dirty(ram_addr_t addr)
1333{
1334 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1335 {
1336 Log(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));
1337 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %RGp\n", (RTGCPHYS)addr));*/
1338 return;
1339 }
1340 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1341}
1342#endif
1343
1344void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1345 int dirty_flags);
1346void cpu_tlb_update_dirty(CPUState *env);
1347
1348int cpu_physical_memory_set_dirty_tracking(int enable);
1349
1350int cpu_physical_memory_get_dirty_tracking(void);
1351
1352void dump_exec_info(FILE *f,
1353 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1354
1355/*******************************************/
1356/* host CPU ticks (if available) */
1357
1358#ifdef VBOX
1359
1360DECLINLINE(int64_t) cpu_get_real_ticks(void)
1361{
1362 return ASMReadTSC();
1363}
1364
1365#elif defined(__powerpc__)
1366
1367static inline uint32_t get_tbl(void)
1368{
1369 uint32_t tbl;
1370 asm volatile("mftb %0" : "=r" (tbl));
1371 return tbl;
1372}
1373
1374static inline uint32_t get_tbu(void)
1375{
1376 uint32_t tbl;
1377 asm volatile("mftbu %0" : "=r" (tbl));
1378 return tbl;
1379}
1380
1381static inline int64_t cpu_get_real_ticks(void)
1382{
1383 uint32_t l, h, h1;
1384 /* NOTE: we test if wrapping has occurred */
1385 do {
1386 h = get_tbu();
1387 l = get_tbl();
1388 h1 = get_tbu();
1389 } while (h != h1);
1390 return ((int64_t)h << 32) | l;
1391}
1392
1393#elif defined(__i386__)
1394
1395static inline int64_t cpu_get_real_ticks(void)
1396{
1397 int64_t val;
1398 asm volatile ("rdtsc" : "=A" (val));
1399 return val;
1400}
1401
1402#elif defined(__x86_64__)
1403
1404static inline int64_t cpu_get_real_ticks(void)
1405{
1406 uint32_t low,high;
1407 int64_t val;
1408 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1409 val = high;
1410 val <<= 32;
1411 val |= low;
1412 return val;
1413}
1414
1415#elif defined(__ia64)
1416
1417static inline int64_t cpu_get_real_ticks(void)
1418{
1419 int64_t val;
1420 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1421 return val;
1422}
1423
1424#elif defined(__s390__)
1425
1426static inline int64_t cpu_get_real_ticks(void)
1427{
1428 int64_t val;
1429 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1430 return val;
1431}
1432
1433#elif defined(__sparc_v9__)
1434
1435static inline int64_t cpu_get_real_ticks (void)
1436{
1437#if defined(_LP64)
1438 uint64_t rval;
1439 asm volatile("rd %%tick,%0" : "=r"(rval));
1440 return rval;
1441#else
1442 union {
1443 uint64_t i64;
1444 struct {
1445 uint32_t high;
1446 uint32_t low;
1447 } i32;
1448 } rval;
1449 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1450 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1451 return rval.i64;
1452#endif
1453}
1454#else
1455/* The host CPU doesn't have an easily accessible cycle counter.
1456 Just return a monotonically increasing vlue. This will be totally wrong,
1457 but hopefully better than nothing. */
1458static inline int64_t cpu_get_real_ticks (void)
1459{
1460 static int64_t ticks = 0;
1461 return ticks++;
1462}
1463#endif
1464
1465/* profiling */
1466#ifdef CONFIG_PROFILER
1467static inline int64_t profile_getclock(void)
1468{
1469 return cpu_get_real_ticks();
1470}
1471
1472extern int64_t kqemu_time, kqemu_time_start;
1473extern int64_t qemu_time, qemu_time_start;
1474extern int64_t tlb_flush_time;
1475extern int64_t kqemu_exec_count;
1476extern int64_t dev_time;
1477extern int64_t kqemu_ret_int_count;
1478extern int64_t kqemu_ret_excp_count;
1479extern int64_t kqemu_ret_intr_count;
1480
1481#endif
1482
1483#ifdef VBOX
1484void tb_invalidate_virt(CPUState *env, uint32_t eip);
1485#endif /* VBOX */
1486
1487#endif /* CPU_ALL_H */
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