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source: vbox/trunk/src/recompiler/tests/test-i386.c@ 70937

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1/*
2 * x86 CPU test
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * Oracle GPL Disclaimer: For the avoidance of doubt, except that if any license choice
22 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
23 * the General Public License version 2 (GPLv2) at this time for any software where
24 * a choice of GPL license versions is made available with the language indicating
25 * that GPLv2 or any later version may be used, or where a choice of which version
26 * of the GPL is applied is otherwise unspecified.
27 */
28
29#define _GNU_SOURCE
30#include <stdlib.h>
31#include <stdio.h>
32#include <string.h>
33#include <inttypes.h>
34#include <math.h>
35#include <signal.h>
36#include <setjmp.h>
37#include <errno.h>
38#include <sys/ucontext.h>
39#include <sys/mman.h>
40
41#if !defined(__x86_64__)
42//#define TEST_VM86
43#define TEST_SEGS
44#endif
45//#define LINUX_VM86_IOPL_FIX
46//#define TEST_P4_FLAGS
47#ifdef __SSE__
48#define TEST_SSE
49#define TEST_CMOV 1
50#define TEST_FCOMI 1
51#else
52#undef TEST_SSE
53#define TEST_CMOV 1
54#define TEST_FCOMI 1
55#endif
56
57#if defined(__x86_64__)
58#define FMT64X "%016lx"
59#define FMTLX "%016lx"
60#define X86_64_ONLY(x) x
61#else
62#define FMT64X "%016" PRIx64
63#define FMTLX "%08lx"
64#define X86_64_ONLY(x)
65#endif
66
67#ifdef TEST_VM86
68#include <asm/vm86.h>
69#endif
70
71#define xglue(x, y) x ## y
72#define glue(x, y) xglue(x, y)
73#define stringify(s) tostring(s)
74#define tostring(s) #s
75
76#define CC_C 0x0001
77#define CC_P 0x0004
78#define CC_A 0x0010
79#define CC_Z 0x0040
80#define CC_S 0x0080
81#define CC_O 0x0800
82
83#define __init_call __attribute__ ((unused,__section__ ("initcall")))
84
85#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
86
87#if defined(__x86_64__)
88static inline long i2l(long v)
89{
90 return v | ((v ^ 0xabcd) << 32);
91}
92#else
93static inline long i2l(long v)
94{
95 return v;
96}
97#endif
98
99#define OP add
100#include "test-i386.h"
101
102#define OP sub
103#include "test-i386.h"
104
105#define OP xor
106#include "test-i386.h"
107
108#define OP and
109#include "test-i386.h"
110
111#define OP or
112#include "test-i386.h"
113
114#define OP cmp
115#include "test-i386.h"
116
117#define OP adc
118#define OP_CC
119#include "test-i386.h"
120
121#define OP sbb
122#define OP_CC
123#include "test-i386.h"
124
125#define OP inc
126#define OP_CC
127#define OP1
128#include "test-i386.h"
129
130#define OP dec
131#define OP_CC
132#define OP1
133#include "test-i386.h"
134
135#define OP neg
136#define OP_CC
137#define OP1
138#include "test-i386.h"
139
140#define OP not
141#define OP_CC
142#define OP1
143#include "test-i386.h"
144
145#undef CC_MASK
146#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
147
148#define OP shl
149#include "test-i386-shift.h"
150
151#define OP shr
152#include "test-i386-shift.h"
153
154#define OP sar
155#include "test-i386-shift.h"
156
157#define OP rol
158#include "test-i386-shift.h"
159
160#define OP ror
161#include "test-i386-shift.h"
162
163#define OP rcr
164#define OP_CC
165#include "test-i386-shift.h"
166
167#define OP rcl
168#define OP_CC
169#include "test-i386-shift.h"
170
171#define OP shld
172#define OP_SHIFTD
173#define OP_NOBYTE
174#include "test-i386-shift.h"
175
176#define OP shrd
177#define OP_SHIFTD
178#define OP_NOBYTE
179#include "test-i386-shift.h"
180
181/* XXX: should be more precise ? */
182#undef CC_MASK
183#define CC_MASK (CC_C)
184
185#define OP bt
186#define OP_NOBYTE
187#include "test-i386-shift.h"
188
189#define OP bts
190#define OP_NOBYTE
191#include "test-i386-shift.h"
192
193#define OP btr
194#define OP_NOBYTE
195#include "test-i386-shift.h"
196
197#define OP btc
198#define OP_NOBYTE
199#include "test-i386-shift.h"
200
201/* lea test (modrm support) */
202#define TEST_LEAQ(STR)\
203{\
204 asm("lea " STR ", %0"\
205 : "=r" (res)\
206 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
207 printf("lea %s = " FMTLX "\n", STR, res);\
208}
209
210#define TEST_LEA(STR)\
211{\
212 asm("lea " STR ", %0"\
213 : "=r" (res)\
214 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
215 printf("lea %s = " FMTLX "\n", STR, res);\
216}
217
218#define TEST_LEA16(STR)\
219{\
220 asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
221 : "=wq" (res)\
222 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
223 printf("lea %s = %08lx\n", STR, res);\
224}
225
226
227void test_lea(void)
228{
229 long eax, ebx, ecx, edx, esi, edi, res;
230 eax = i2l(0x0001);
231 ebx = i2l(0x0002);
232 ecx = i2l(0x0004);
233 edx = i2l(0x0008);
234 esi = i2l(0x0010);
235 edi = i2l(0x0020);
236
237 TEST_LEA("0x4000");
238
239 TEST_LEA("(%%eax)");
240 TEST_LEA("(%%ebx)");
241 TEST_LEA("(%%ecx)");
242 TEST_LEA("(%%edx)");
243 TEST_LEA("(%%esi)");
244 TEST_LEA("(%%edi)");
245
246 TEST_LEA("0x40(%%eax)");
247 TEST_LEA("0x40(%%ebx)");
248 TEST_LEA("0x40(%%ecx)");
249 TEST_LEA("0x40(%%edx)");
250 TEST_LEA("0x40(%%esi)");
251 TEST_LEA("0x40(%%edi)");
252
253 TEST_LEA("0x4000(%%eax)");
254 TEST_LEA("0x4000(%%ebx)");
255 TEST_LEA("0x4000(%%ecx)");
256 TEST_LEA("0x4000(%%edx)");
257 TEST_LEA("0x4000(%%esi)");
258 TEST_LEA("0x4000(%%edi)");
259
260 TEST_LEA("(%%eax, %%ecx)");
261 TEST_LEA("(%%ebx, %%edx)");
262 TEST_LEA("(%%ecx, %%ecx)");
263 TEST_LEA("(%%edx, %%ecx)");
264 TEST_LEA("(%%esi, %%ecx)");
265 TEST_LEA("(%%edi, %%ecx)");
266
267 TEST_LEA("0x40(%%eax, %%ecx)");
268 TEST_LEA("0x4000(%%ebx, %%edx)");
269
270 TEST_LEA("(%%ecx, %%ecx, 2)");
271 TEST_LEA("(%%edx, %%ecx, 4)");
272 TEST_LEA("(%%esi, %%ecx, 8)");
273
274 TEST_LEA("(,%%eax, 2)");
275 TEST_LEA("(,%%ebx, 4)");
276 TEST_LEA("(,%%ecx, 8)");
277
278 TEST_LEA("0x40(,%%eax, 2)");
279 TEST_LEA("0x40(,%%ebx, 4)");
280 TEST_LEA("0x40(,%%ecx, 8)");
281
282
283 TEST_LEA("-10(%%ecx, %%ecx, 2)");
284 TEST_LEA("-10(%%edx, %%ecx, 4)");
285 TEST_LEA("-10(%%esi, %%ecx, 8)");
286
287 TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
288 TEST_LEA("0x4000(%%edx, %%ecx, 4)");
289 TEST_LEA("0x4000(%%esi, %%ecx, 8)");
290
291#if defined(__x86_64__)
292 TEST_LEAQ("0x4000");
293 TEST_LEAQ("0x4000(%%rip)");
294
295 TEST_LEAQ("(%%rax)");
296 TEST_LEAQ("(%%rbx)");
297 TEST_LEAQ("(%%rcx)");
298 TEST_LEAQ("(%%rdx)");
299 TEST_LEAQ("(%%rsi)");
300 TEST_LEAQ("(%%rdi)");
301
302 TEST_LEAQ("0x40(%%rax)");
303 TEST_LEAQ("0x40(%%rbx)");
304 TEST_LEAQ("0x40(%%rcx)");
305 TEST_LEAQ("0x40(%%rdx)");
306 TEST_LEAQ("0x40(%%rsi)");
307 TEST_LEAQ("0x40(%%rdi)");
308
309 TEST_LEAQ("0x4000(%%rax)");
310 TEST_LEAQ("0x4000(%%rbx)");
311 TEST_LEAQ("0x4000(%%rcx)");
312 TEST_LEAQ("0x4000(%%rdx)");
313 TEST_LEAQ("0x4000(%%rsi)");
314 TEST_LEAQ("0x4000(%%rdi)");
315
316 TEST_LEAQ("(%%rax, %%rcx)");
317 TEST_LEAQ("(%%rbx, %%rdx)");
318 TEST_LEAQ("(%%rcx, %%rcx)");
319 TEST_LEAQ("(%%rdx, %%rcx)");
320 TEST_LEAQ("(%%rsi, %%rcx)");
321 TEST_LEAQ("(%%rdi, %%rcx)");
322
323 TEST_LEAQ("0x40(%%rax, %%rcx)");
324 TEST_LEAQ("0x4000(%%rbx, %%rdx)");
325
326 TEST_LEAQ("(%%rcx, %%rcx, 2)");
327 TEST_LEAQ("(%%rdx, %%rcx, 4)");
328 TEST_LEAQ("(%%rsi, %%rcx, 8)");
329
330 TEST_LEAQ("(,%%rax, 2)");
331 TEST_LEAQ("(,%%rbx, 4)");
332 TEST_LEAQ("(,%%rcx, 8)");
333
334 TEST_LEAQ("0x40(,%%rax, 2)");
335 TEST_LEAQ("0x40(,%%rbx, 4)");
336 TEST_LEAQ("0x40(,%%rcx, 8)");
337
338
339 TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
340 TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
341 TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
342
343 TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
344 TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
345 TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
346#else
347 /* limited 16 bit addressing test */
348 TEST_LEA16("0x4000");
349 TEST_LEA16("(%%bx)");
350 TEST_LEA16("(%%si)");
351 TEST_LEA16("(%%di)");
352 TEST_LEA16("0x40(%%bx)");
353 TEST_LEA16("0x40(%%si)");
354 TEST_LEA16("0x40(%%di)");
355 TEST_LEA16("0x4000(%%bx)");
356 TEST_LEA16("0x4000(%%si)");
357 TEST_LEA16("(%%bx,%%si)");
358 TEST_LEA16("(%%bx,%%di)");
359 TEST_LEA16("0x40(%%bx,%%si)");
360 TEST_LEA16("0x40(%%bx,%%di)");
361 TEST_LEA16("0x4000(%%bx,%%si)");
362 TEST_LEA16("0x4000(%%bx,%%di)");
363#endif
364}
365
366#define TEST_JCC(JCC, v1, v2)\
367{\
368 int res;\
369 asm("movl $1, %0\n\t"\
370 "cmpl %2, %1\n\t"\
371 "j" JCC " 1f\n\t"\
372 "movl $0, %0\n\t"\
373 "1:\n\t"\
374 : "=r" (res)\
375 : "r" (v1), "r" (v2));\
376 printf("%-10s %d\n", "j" JCC, res);\
377\
378 asm("movl $0, %0\n\t"\
379 "cmpl %2, %1\n\t"\
380 "set" JCC " %b0\n\t"\
381 : "=r" (res)\
382 : "r" (v1), "r" (v2));\
383 printf("%-10s %d\n", "set" JCC, res);\
384 if (TEST_CMOV) {\
385 long val = i2l(1);\
386 long res = i2l(0x12345678);\
387X86_64_ONLY(\
388 asm("cmpl %2, %1\n\t"\
389 "cmov" JCC "q %3, %0\n\t"\
390 : "=r" (res)\
391 : "r" (v1), "r" (v2), "m" (val), "0" (res));\
392 printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
393 asm("cmpl %2, %1\n\t"\
394 "cmov" JCC "l %k3, %k0\n\t"\
395 : "=r" (res)\
396 : "r" (v1), "r" (v2), "m" (val), "0" (res));\
397 printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
398 asm("cmpl %2, %1\n\t"\
399 "cmov" JCC "w %w3, %w0\n\t"\
400 : "=r" (res)\
401 : "r" (v1), "r" (v2), "r" (1), "0" (res));\
402 printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
403 } \
404}
405
406/* various jump tests */
407void test_jcc(void)
408{
409 TEST_JCC("ne", 1, 1);
410 TEST_JCC("ne", 1, 0);
411
412 TEST_JCC("e", 1, 1);
413 TEST_JCC("e", 1, 0);
414
415 TEST_JCC("l", 1, 1);
416 TEST_JCC("l", 1, 0);
417 TEST_JCC("l", 1, -1);
418
419 TEST_JCC("le", 1, 1);
420 TEST_JCC("le", 1, 0);
421 TEST_JCC("le", 1, -1);
422
423 TEST_JCC("ge", 1, 1);
424 TEST_JCC("ge", 1, 0);
425 TEST_JCC("ge", -1, 1);
426
427 TEST_JCC("g", 1, 1);
428 TEST_JCC("g", 1, 0);
429 TEST_JCC("g", 1, -1);
430
431 TEST_JCC("b", 1, 1);
432 TEST_JCC("b", 1, 0);
433 TEST_JCC("b", 1, -1);
434
435 TEST_JCC("be", 1, 1);
436 TEST_JCC("be", 1, 0);
437 TEST_JCC("be", 1, -1);
438
439 TEST_JCC("ae", 1, 1);
440 TEST_JCC("ae", 1, 0);
441 TEST_JCC("ae", 1, -1);
442
443 TEST_JCC("a", 1, 1);
444 TEST_JCC("a", 1, 0);
445 TEST_JCC("a", 1, -1);
446
447
448 TEST_JCC("p", 1, 1);
449 TEST_JCC("p", 1, 0);
450
451 TEST_JCC("np", 1, 1);
452 TEST_JCC("np", 1, 0);
453
454 TEST_JCC("o", 0x7fffffff, 0);
455 TEST_JCC("o", 0x7fffffff, -1);
456
457 TEST_JCC("no", 0x7fffffff, 0);
458 TEST_JCC("no", 0x7fffffff, -1);
459
460 TEST_JCC("s", 0, 1);
461 TEST_JCC("s", 0, -1);
462 TEST_JCC("s", 0, 0);
463
464 TEST_JCC("ns", 0, 1);
465 TEST_JCC("ns", 0, -1);
466 TEST_JCC("ns", 0, 0);
467}
468
469#define TEST_LOOP(insn) \
470{\
471 for(i = 0; i < sizeof(ecx_vals) / sizeof(long); i++) {\
472 ecx = ecx_vals[i];\
473 for(zf = 0; zf < 2; zf++) {\
474 asm("test %2, %2\n\t"\
475 "movl $1, %0\n\t"\
476 insn " 1f\n\t" \
477 "movl $0, %0\n\t"\
478 "1:\n\t"\
479 : "=a" (res)\
480 : "c" (ecx), "b" (!zf)); \
481 printf("%-10s ECX=" FMTLX " ZF=%ld r=%d\n", insn, ecx, zf, res); \
482 }\
483 }\
484}
485
486void test_loop(void)
487{
488 long ecx, zf;
489 const long ecx_vals[] = {
490 0,
491 1,
492 0x10000,
493 0x10001,
494#if defined(__x86_64__)
495 0x100000000L,
496 0x100000001L,
497#endif
498 };
499 int i, res;
500
501#if !defined(__x86_64__)
502 TEST_LOOP("jcxz");
503 TEST_LOOP("loopw");
504 TEST_LOOP("loopzw");
505 TEST_LOOP("loopnzw");
506#endif
507
508 TEST_LOOP("jecxz");
509 TEST_LOOP("loopl");
510 TEST_LOOP("loopzl");
511 TEST_LOOP("loopnzl");
512}
513
514#undef CC_MASK
515#ifdef TEST_P4_FLAGS
516#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
517#else
518#define CC_MASK (CC_O | CC_C)
519#endif
520
521#define OP mul
522#include "test-i386-muldiv.h"
523
524#define OP imul
525#include "test-i386-muldiv.h"
526
527void test_imulw2(long op0, long op1)
528{
529 long res, s1, s0, flags;
530 s0 = op0;
531 s1 = op1;
532 res = s0;
533 flags = 0;
534 asm volatile ("push %4\n\t"
535 "popf\n\t"
536 "imulw %w2, %w0\n\t"
537 "pushf\n\t"
538 "pop %1\n\t"
539 : "=q" (res), "=g" (flags)
540 : "q" (s1), "0" (res), "1" (flags));
541 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
542 "imulw", s0, s1, res, flags & CC_MASK);
543}
544
545void test_imull2(long op0, long op1)
546{
547 long res, s1, s0, flags;
548 s0 = op0;
549 s1 = op1;
550 res = s0;
551 flags = 0;
552 asm volatile ("push %4\n\t"
553 "popf\n\t"
554 "imull %k2, %k0\n\t"
555 "pushf\n\t"
556 "pop %1\n\t"
557 : "=q" (res), "=g" (flags)
558 : "q" (s1), "0" (res), "1" (flags));
559 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
560 "imull", s0, s1, res, flags & CC_MASK);
561}
562
563#if defined(__x86_64__)
564void test_imulq2(long op0, long op1)
565{
566 long res, s1, s0, flags;
567 s0 = op0;
568 s1 = op1;
569 res = s0;
570 flags = 0;
571 asm volatile ("push %4\n\t"
572 "popf\n\t"
573 "imulq %2, %0\n\t"
574 "pushf\n\t"
575 "pop %1\n\t"
576 : "=q" (res), "=g" (flags)
577 : "q" (s1), "0" (res), "1" (flags));
578 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
579 "imulq", s0, s1, res, flags & CC_MASK);
580}
581#endif
582
583#define TEST_IMUL_IM(size, rsize, op0, op1)\
584{\
585 long res, flags, s1;\
586 flags = 0;\
587 res = 0;\
588 s1 = op1;\
589 asm volatile ("push %3\n\t"\
590 "popf\n\t"\
591 "imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
592 "pushf\n\t"\
593 "pop %1\n\t"\
594 : "=r" (res), "=g" (flags)\
595 : "r" (s1), "1" (flags), "0" (res));\
596 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
597 "imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
598}
599
600
601#undef CC_MASK
602#define CC_MASK (0)
603
604#define OP div
605#include "test-i386-muldiv.h"
606
607#define OP idiv
608#include "test-i386-muldiv.h"
609
610void test_mul(void)
611{
612 test_imulb(0x1234561d, 4);
613 test_imulb(3, -4);
614 test_imulb(0x80, 0x80);
615 test_imulb(0x10, 0x10);
616
617 test_imulw(0, 0x1234001d, 45);
618 test_imulw(0, 23, -45);
619 test_imulw(0, 0x8000, 0x8000);
620 test_imulw(0, 0x100, 0x100);
621
622 test_imull(0, 0x1234001d, 45);
623 test_imull(0, 23, -45);
624 test_imull(0, 0x80000000, 0x80000000);
625 test_imull(0, 0x10000, 0x10000);
626
627 test_mulb(0x1234561d, 4);
628 test_mulb(3, -4);
629 test_mulb(0x80, 0x80);
630 test_mulb(0x10, 0x10);
631
632 test_mulw(0, 0x1234001d, 45);
633 test_mulw(0, 23, -45);
634 test_mulw(0, 0x8000, 0x8000);
635 test_mulw(0, 0x100, 0x100);
636
637 test_mull(0, 0x1234001d, 45);
638 test_mull(0, 23, -45);
639 test_mull(0, 0x80000000, 0x80000000);
640 test_mull(0, 0x10000, 0x10000);
641
642 test_imulw2(0x1234001d, 45);
643 test_imulw2(23, -45);
644 test_imulw2(0x8000, 0x8000);
645 test_imulw2(0x100, 0x100);
646
647 test_imull2(0x1234001d, 45);
648 test_imull2(23, -45);
649 test_imull2(0x80000000, 0x80000000);
650 test_imull2(0x10000, 0x10000);
651
652 TEST_IMUL_IM("w", "w", 45, 0x1234);
653 TEST_IMUL_IM("w", "w", -45, 23);
654 TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
655 TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
656
657 TEST_IMUL_IM("l", "k", 45, 0x1234);
658 TEST_IMUL_IM("l", "k", -45, 23);
659 TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
660 TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
661
662 test_idivb(0x12341678, 0x127e);
663 test_idivb(0x43210123, -5);
664 test_idivb(0x12340004, -1);
665
666 test_idivw(0, 0x12345678, 12347);
667 test_idivw(0, -23223, -45);
668 test_idivw(0, 0x12348000, -1);
669 test_idivw(0x12343, 0x12345678, 0x81238567);
670
671 test_idivl(0, 0x12345678, 12347);
672 test_idivl(0, -233223, -45);
673 test_idivl(0, 0x80000000, -1);
674 test_idivl(0x12343, 0x12345678, 0x81234567);
675
676 test_divb(0x12341678, 0x127e);
677 test_divb(0x43210123, -5);
678 test_divb(0x12340004, -1);
679
680 test_divw(0, 0x12345678, 12347);
681 test_divw(0, -23223, -45);
682 test_divw(0, 0x12348000, -1);
683 test_divw(0x12343, 0x12345678, 0x81238567);
684
685 test_divl(0, 0x12345678, 12347);
686 test_divl(0, -233223, -45);
687 test_divl(0, 0x80000000, -1);
688 test_divl(0x12343, 0x12345678, 0x81234567);
689
690#if defined(__x86_64__)
691 test_imulq(0, 0x1234001d1234001d, 45);
692 test_imulq(0, 23, -45);
693 test_imulq(0, 0x8000000000000000, 0x8000000000000000);
694 test_imulq(0, 0x100000000, 0x100000000);
695
696 test_mulq(0, 0x1234001d1234001d, 45);
697 test_mulq(0, 23, -45);
698 test_mulq(0, 0x8000000000000000, 0x8000000000000000);
699 test_mulq(0, 0x100000000, 0x100000000);
700
701 test_imulq2(0x1234001d1234001d, 45);
702 test_imulq2(23, -45);
703 test_imulq2(0x8000000000000000, 0x8000000000000000);
704 test_imulq2(0x100000000, 0x100000000);
705
706 TEST_IMUL_IM("q", "", 45, 0x12341234);
707 TEST_IMUL_IM("q", "", -45, 23);
708 TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
709 TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
710
711 test_idivq(0, 0x12345678abcdef, 12347);
712 test_idivq(0, -233223, -45);
713 test_idivq(0, 0x8000000000000000, -1);
714 test_idivq(0x12343, 0x12345678, 0x81234567);
715
716 test_divq(0, 0x12345678abcdef, 12347);
717 test_divq(0, -233223, -45);
718 test_divq(0, 0x8000000000000000, -1);
719 test_divq(0x12343, 0x12345678, 0x81234567);
720#endif
721}
722
723#define TEST_BSX(op, size, op0)\
724{\
725 long res, val, resz;\
726 val = op0;\
727 asm("xor %1, %1\n"\
728 "mov $0x12345678, %0\n"\
729 #op " %" size "2, %" size "0 ; setz %b1" \
730 : "=&r" (res), "=&q" (resz)\
731 : "r" (val));\
732 printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
733}
734
735void test_bsx(void)
736{
737 TEST_BSX(bsrw, "w", 0);
738 TEST_BSX(bsrw, "w", 0x12340128);
739 TEST_BSX(bsfw, "w", 0);
740 TEST_BSX(bsfw, "w", 0x12340128);
741 TEST_BSX(bsrl, "k", 0);
742 TEST_BSX(bsrl, "k", 0x00340128);
743 TEST_BSX(bsfl, "k", 0);
744 TEST_BSX(bsfl, "k", 0x00340128);
745#if defined(__x86_64__)
746 TEST_BSX(bsrq, "", 0);
747 TEST_BSX(bsrq, "", 0x003401281234);
748 TEST_BSX(bsfq, "", 0);
749 TEST_BSX(bsfq, "", 0x003401281234);
750#endif
751}
752
753/**********************************************/
754
755union float64u {
756 double d;
757 uint64_t l;
758};
759
760union float64u q_nan = { .l = 0xFFF8000000000000LL };
761union float64u s_nan = { .l = 0xFFF0000000000000LL };
762
763void test_fops(double a, double b)
764{
765 printf("a=%f b=%f a+b=%f\n", a, b, a + b);
766 printf("a=%f b=%f a-b=%f\n", a, b, a - b);
767 printf("a=%f b=%f a*b=%f\n", a, b, a * b);
768 printf("a=%f b=%f a/b=%f\n", a, b, a / b);
769 printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
770 printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
771 printf("a=%f sin(a)=%f\n", a, sin(a));
772 printf("a=%f cos(a)=%f\n", a, cos(a));
773 printf("a=%f tan(a)=%f\n", a, tan(a));
774 printf("a=%f log(a)=%f\n", a, log(a));
775 printf("a=%f exp(a)=%f\n", a, exp(a));
776 printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
777 /* just to test some op combining */
778 printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
779 printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
780 printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
781
782}
783
784void fpu_clear_exceptions(void)
785{
786 struct __attribute__((packed)) {
787 uint16_t fpuc;
788 uint16_t dummy1;
789 uint16_t fpus;
790 uint16_t dummy2;
791 uint16_t fptag;
792 uint16_t dummy3;
793 uint32_t ignored[4];
794 long double fpregs[8];
795 } float_env32;
796
797 asm volatile ("fnstenv %0\n" : : "m" (float_env32));
798 float_env32.fpus &= ~0x7f;
799 asm volatile ("fldenv %0\n" : : "m" (float_env32));
800}
801
802/* XXX: display exception bits when supported */
803#define FPUS_EMASK 0x0000
804//#define FPUS_EMASK 0x007f
805
806void test_fcmp(double a, double b)
807{
808 long eflags, fpus;
809
810 fpu_clear_exceptions();
811 asm("fcom %2\n"
812 "fstsw %%ax\n"
813 : "=a" (fpus)
814 : "t" (a), "u" (b));
815 printf("fcom(%f %f)=%04lx \n",
816 a, b, fpus & (0x4500 | FPUS_EMASK));
817 fpu_clear_exceptions();
818 asm("fucom %2\n"
819 "fstsw %%ax\n"
820 : "=a" (fpus)
821 : "t" (a), "u" (b));
822 printf("fucom(%f %f)=%04lx\n",
823 a, b, fpus & (0x4500 | FPUS_EMASK));
824 if (TEST_FCOMI) {
825 /* test f(u)comi instruction */
826 fpu_clear_exceptions();
827 asm("fcomi %3, %2\n"
828 "fstsw %%ax\n"
829 "pushf\n"
830 "pop %0\n"
831 : "=r" (eflags), "=a" (fpus)
832 : "t" (a), "u" (b));
833 printf("fcomi(%f %f)=%04lx %02lx\n",
834 a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
835 fpu_clear_exceptions();
836 asm("fucomi %3, %2\n"
837 "fstsw %%ax\n"
838 "pushf\n"
839 "pop %0\n"
840 : "=r" (eflags), "=a" (fpus)
841 : "t" (a), "u" (b));
842 printf("fucomi(%f %f)=%04lx %02lx\n",
843 a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
844 }
845 fpu_clear_exceptions();
846 asm volatile("fxam\n"
847 "fstsw %%ax\n"
848 : "=a" (fpus)
849 : "t" (a));
850 printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
851 fpu_clear_exceptions();
852}
853
854void test_fcvt(double a)
855{
856 float fa;
857 long double la;
858 int16_t fpuc;
859 int i;
860 int64_t lla;
861 int ia;
862 int16_t wa;
863 double ra;
864
865 fa = a;
866 la = a;
867 printf("(float)%f = %f\n", a, fa);
868 printf("(long double)%f = %Lf\n", a, la);
869 printf("a=" FMT64X "\n", *(uint64_t *)&a);
870 printf("la=" FMT64X " %04x\n", *(uint64_t *)&la,
871 *(unsigned short *)((char *)(&la) + 8));
872
873 /* test all roundings */
874 asm volatile ("fstcw %0" : "=m" (fpuc));
875 for(i=0;i<4;i++) {
876 uint16_t val16;
877 val16 = (fpuc & ~0x0c00) | (i << 10);
878 asm volatile ("fldcw %0" : : "m" (val16));
879 asm volatile ("fist %0" : "=m" (wa) : "t" (a));
880 asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
881 asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
882 asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
883 asm volatile ("fldcw %0" : : "m" (fpuc));
884 printf("(short)a = %d\n", wa);
885 printf("(int)a = %d\n", ia);
886 printf("(int64_t)a = " FMT64X "\n", lla);
887 printf("rint(a) = %f\n", ra);
888 }
889}
890
891#define TEST(N) \
892 asm("fld" #N : "=t" (a)); \
893 printf("fld" #N "= %f\n", a);
894
895void test_fconst(void)
896{
897 double a;
898 TEST(1);
899 TEST(l2t);
900 TEST(l2e);
901 TEST(pi);
902 TEST(lg2);
903 TEST(ln2);
904 TEST(z);
905}
906
907void test_fbcd(double a)
908{
909 unsigned short bcd[5];
910 double b;
911
912 asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
913 asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
914 printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
915 a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
916}
917
918#define TEST_ENV(env, save, restore)\
919{\
920 memset((env), 0xaa, sizeof(*(env)));\
921 for(i=0;i<5;i++)\
922 asm volatile ("fldl %0" : : "m" (dtab[i]));\
923 asm volatile (save " %0\n" : : "m" (*(env)));\
924 asm volatile (restore " %0\n": : "m" (*(env)));\
925 for(i=0;i<5;i++)\
926 asm volatile ("fstpl %0" : "=m" (rtab[i]));\
927 for(i=0;i<5;i++)\
928 printf("res[%d]=%f\n", i, rtab[i]);\
929 printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
930 (env)->fpuc,\
931 (env)->fpus & 0xff00,\
932 (env)->fptag);\
933}
934
935void test_fenv(void)
936{
937 struct __attribute__((packed)) {
938 uint16_t fpuc;
939 uint16_t dummy1;
940 uint16_t fpus;
941 uint16_t dummy2;
942 uint16_t fptag;
943 uint16_t dummy3;
944 uint32_t ignored[4];
945 long double fpregs[8];
946 } float_env32;
947 struct __attribute__((packed)) {
948 uint16_t fpuc;
949 uint16_t fpus;
950 uint16_t fptag;
951 uint16_t ignored[4];
952 long double fpregs[8];
953 } float_env16;
954 double dtab[8];
955 double rtab[8];
956 int i;
957
958 for(i=0;i<8;i++)
959 dtab[i] = i + 1;
960
961 TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
962 TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
963 TEST_ENV(&float_env32, "fnstenv", "fldenv");
964 TEST_ENV(&float_env32, "fnsave", "frstor");
965
966 /* test for ffree */
967 for(i=0;i<5;i++)
968 asm volatile ("fldl %0" : : "m" (dtab[i]));
969 asm volatile("ffree %st(2)");
970 asm volatile ("fnstenv %0\n" : : "m" (float_env32));
971 asm volatile ("fninit");
972 printf("fptag=%04x\n", float_env32.fptag);
973}
974
975
976#define TEST_FCMOV(a, b, eflags, CC)\
977{\
978 double res;\
979 asm("push %3\n"\
980 "popf\n"\
981 "fcmov" CC " %2, %0\n"\
982 : "=t" (res)\
983 : "0" (a), "u" (b), "g" (eflags));\
984 printf("fcmov%s eflags=0x%04lx-> %f\n", \
985 CC, (long)eflags, res);\
986}
987
988void test_fcmov(void)
989{
990 double a, b;
991 long eflags, i;
992
993 a = 1.0;
994 b = 2.0;
995 for(i = 0; i < 4; i++) {
996 eflags = 0;
997 if (i & 1)
998 eflags |= CC_C;
999 if (i & 2)
1000 eflags |= CC_Z;
1001 TEST_FCMOV(a, b, eflags, "b");
1002 TEST_FCMOV(a, b, eflags, "e");
1003 TEST_FCMOV(a, b, eflags, "be");
1004 TEST_FCMOV(a, b, eflags, "nb");
1005 TEST_FCMOV(a, b, eflags, "ne");
1006 TEST_FCMOV(a, b, eflags, "nbe");
1007 }
1008 TEST_FCMOV(a, b, 0, "u");
1009 TEST_FCMOV(a, b, CC_P, "u");
1010 TEST_FCMOV(a, b, 0, "nu");
1011 TEST_FCMOV(a, b, CC_P, "nu");
1012}
1013
1014void test_floats(void)
1015{
1016 test_fops(2, 3);
1017 test_fops(1.4, -5);
1018 test_fcmp(2, -1);
1019 test_fcmp(2, 2);
1020 test_fcmp(2, 3);
1021 test_fcmp(2, q_nan.d);
1022 test_fcmp(q_nan.d, -1);
1023 test_fcmp(-1.0/0.0, -1);
1024 test_fcmp(1.0/0.0, -1);
1025 test_fcvt(0.5);
1026 test_fcvt(-0.5);
1027 test_fcvt(1.0/7.0);
1028 test_fcvt(-1.0/9.0);
1029 test_fcvt(32768);
1030 test_fcvt(-1e20);
1031 test_fcvt(-1.0/0.0);
1032 test_fcvt(1.0/0.0);
1033 test_fcvt(q_nan.d);
1034 test_fconst();
1035 test_fbcd(1234567890123456.0);
1036 test_fbcd(-123451234567890.0);
1037 test_fenv();
1038 if (TEST_CMOV) {
1039 test_fcmov();
1040 }
1041}
1042
1043/**********************************************/
1044#if !defined(__x86_64__)
1045
1046#define TEST_BCD(op, op0, cc_in, cc_mask)\
1047{\
1048 int res, flags;\
1049 res = op0;\
1050 flags = cc_in;\
1051 asm ("push %3\n\t"\
1052 "popf\n\t"\
1053 #op "\n\t"\
1054 "pushf\n\t"\
1055 "pop %1\n\t"\
1056 : "=a" (res), "=g" (flags)\
1057 : "0" (res), "1" (flags));\
1058 printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",\
1059 #op, op0, res, cc_in, flags & cc_mask);\
1060}
1061
1062void test_bcd(void)
1063{
1064 TEST_BCD(daa, 0x12340503, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1065 TEST_BCD(daa, 0x12340506, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1066 TEST_BCD(daa, 0x12340507, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1067 TEST_BCD(daa, 0x12340559, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1068 TEST_BCD(daa, 0x12340560, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1069 TEST_BCD(daa, 0x1234059f, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1070 TEST_BCD(daa, 0x123405a0, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1071 TEST_BCD(daa, 0x12340503, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1072 TEST_BCD(daa, 0x12340506, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1073 TEST_BCD(daa, 0x12340503, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1074 TEST_BCD(daa, 0x12340506, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1075 TEST_BCD(daa, 0x12340503, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1076 TEST_BCD(daa, 0x12340506, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1077
1078 TEST_BCD(das, 0x12340503, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1079 TEST_BCD(das, 0x12340506, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1080 TEST_BCD(das, 0x12340507, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1081 TEST_BCD(das, 0x12340559, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1082 TEST_BCD(das, 0x12340560, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1083 TEST_BCD(das, 0x1234059f, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1084 TEST_BCD(das, 0x123405a0, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1085 TEST_BCD(das, 0x12340503, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1086 TEST_BCD(das, 0x12340506, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1087 TEST_BCD(das, 0x12340503, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1088 TEST_BCD(das, 0x12340506, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1089 TEST_BCD(das, 0x12340503, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1090 TEST_BCD(das, 0x12340506, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
1091
1092 TEST_BCD(aaa, 0x12340205, CC_A, (CC_C | CC_A));
1093 TEST_BCD(aaa, 0x12340306, CC_A, (CC_C | CC_A));
1094 TEST_BCD(aaa, 0x1234040a, CC_A, (CC_C | CC_A));
1095 TEST_BCD(aaa, 0x123405fa, CC_A, (CC_C | CC_A));
1096 TEST_BCD(aaa, 0x12340205, 0, (CC_C | CC_A));
1097 TEST_BCD(aaa, 0x12340306, 0, (CC_C | CC_A));
1098 TEST_BCD(aaa, 0x1234040a, 0, (CC_C | CC_A));
1099 TEST_BCD(aaa, 0x123405fa, 0, (CC_C | CC_A));
1100
1101 TEST_BCD(aas, 0x12340205, CC_A, (CC_C | CC_A));
1102 TEST_BCD(aas, 0x12340306, CC_A, (CC_C | CC_A));
1103 TEST_BCD(aas, 0x1234040a, CC_A, (CC_C | CC_A));
1104 TEST_BCD(aas, 0x123405fa, CC_A, (CC_C | CC_A));
1105 TEST_BCD(aas, 0x12340205, 0, (CC_C | CC_A));
1106 TEST_BCD(aas, 0x12340306, 0, (CC_C | CC_A));
1107 TEST_BCD(aas, 0x1234040a, 0, (CC_C | CC_A));
1108 TEST_BCD(aas, 0x123405fa, 0, (CC_C | CC_A));
1109
1110 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
1111 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
1112}
1113#endif
1114
1115#define TEST_XCHG(op, size, opconst)\
1116{\
1117 long op0, op1;\
1118 op0 = i2l(0x12345678);\
1119 op1 = i2l(0xfbca7654);\
1120 asm(#op " %" size "0, %" size "1" \
1121 : "=q" (op0), opconst (op1) \
1122 : "0" (op0));\
1123 printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
1124 #op, op0, op1);\
1125}
1126
1127#define TEST_CMPXCHG(op, size, opconst, eax)\
1128{\
1129 long op0, op1, op2;\
1130 op0 = i2l(0x12345678);\
1131 op1 = i2l(0xfbca7654);\
1132 op2 = i2l(eax);\
1133 asm(#op " %" size "0, %" size "1" \
1134 : "=q" (op0), opconst (op1) \
1135 : "0" (op0), "a" (op2));\
1136 printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
1137 #op, op2, op0, op1);\
1138}
1139
1140void test_xchg(void)
1141{
1142#if defined(__x86_64__)
1143 TEST_XCHG(xchgq, "", "+q");
1144#endif
1145 TEST_XCHG(xchgl, "k", "+q");
1146 TEST_XCHG(xchgw, "w", "+q");
1147 TEST_XCHG(xchgb, "b", "+q");
1148
1149#if defined(__x86_64__)
1150 TEST_XCHG(xchgq, "", "=m");
1151#endif
1152 TEST_XCHG(xchgl, "k", "+m");
1153 TEST_XCHG(xchgw, "w", "+m");
1154 TEST_XCHG(xchgb, "b", "+m");
1155
1156#if defined(__x86_64__)
1157 TEST_XCHG(xaddq, "", "+q");
1158#endif
1159 TEST_XCHG(xaddl, "k", "+q");
1160 TEST_XCHG(xaddw, "w", "+q");
1161 TEST_XCHG(xaddb, "b", "+q");
1162
1163 {
1164 int res;
1165 res = 0x12345678;
1166 asm("xaddl %1, %0" : "=r" (res) : "0" (res));
1167 printf("xaddl same res=%08x\n", res);
1168 }
1169
1170#if defined(__x86_64__)
1171 TEST_XCHG(xaddq, "", "+m");
1172#endif
1173 TEST_XCHG(xaddl, "k", "+m");
1174 TEST_XCHG(xaddw, "w", "+m");
1175 TEST_XCHG(xaddb, "b", "+m");
1176
1177#if defined(__x86_64__)
1178 TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfbca7654);
1179#endif
1180 TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfbca7654);
1181 TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfbca7654);
1182 TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfbca7654);
1183
1184#if defined(__x86_64__)
1185 TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfffefdfc);
1186#endif
1187 TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfffefdfc);
1188 TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfffefdfc);
1189 TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfffefdfc);
1190
1191#if defined(__x86_64__)
1192 TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfbca7654);
1193#endif
1194 TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfbca7654);
1195 TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfbca7654);
1196 TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfbca7654);
1197
1198#if defined(__x86_64__)
1199 TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfffefdfc);
1200#endif
1201 TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfffefdfc);
1202 TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfffefdfc);
1203 TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfffefdfc);
1204
1205 {
1206 uint64_t op0, op1, op2;
1207 long eax, edx;
1208 long i, eflags;
1209
1210 for(i = 0; i < 2; i++) {
1211 op0 = 0x123456789abcdLL;
1212 eax = i2l(op0 & 0xffffffff);
1213 edx = i2l(op0 >> 32);
1214 if (i == 0)
1215 op1 = 0xfbca765423456LL;
1216 else
1217 op1 = op0;
1218 op2 = 0x6532432432434LL;
1219 asm("cmpxchg8b %2\n"
1220 "pushf\n"
1221 "pop %3\n"
1222 : "=a" (eax), "=d" (edx), "=m" (op1), "=g" (eflags)
1223 : "0" (eax), "1" (edx), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
1224 printf("cmpxchg8b: eax=" FMTLX " edx=" FMTLX " op1=" FMT64X " CC=%02lx\n",
1225 eax, edx, op1, eflags & CC_Z);
1226 }
1227 }
1228}
1229
1230#ifdef TEST_SEGS
1231/**********************************************/
1232/* segmentation tests */
1233
1234#include <sys/syscall.h>
1235#include <unistd.h>
1236#include <asm/ldt.h>
1237#include <linux/version.h>
1238
1239static inline int modify_ldt(int func, void * ptr, unsigned long bytecount)
1240{
1241 return syscall(__NR_modify_ldt, func, ptr, bytecount);
1242}
1243
1244#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
1245#define modify_ldt_ldt_s user_desc
1246#endif
1247
1248#define MK_SEL(n) (((n) << 3) | 7)
1249
1250uint8_t seg_data1[4096];
1251uint8_t seg_data2[4096];
1252
1253#define TEST_LR(op, size, seg, mask)\
1254{\
1255 int res, res2;\
1256 uint16_t mseg = seg;\
1257 res = 0x12345678;\
1258 asm (op " %" size "2, %" size "0\n" \
1259 "movl $0, %1\n"\
1260 "jnz 1f\n"\
1261 "movl $1, %1\n"\
1262 "1:\n"\
1263 : "=r" (res), "=r" (res2) : "m" (mseg), "0" (res));\
1264 printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
1265}
1266
1267#define TEST_ARPL(op, size, op1, op2)\
1268{\
1269 long a, b, c; \
1270 a = (op1); \
1271 b = (op2); \
1272 asm volatile(op " %" size "3, %" size "0\n"\
1273 "movl $0,%1\n"\
1274 "jnz 1f\n"\
1275 "movl $1,%1\n"\
1276 "1:\n"\
1277 : "=r" (a), "=r" (c) : "0" (a), "r" (b)); \
1278 printf(op size " A=" FMTLX " B=" FMTLX " R=" FMTLX " z=%ld\n",\
1279 (long)(op1), (long)(op2), a, c);\
1280}
1281
1282/* NOTE: we use Linux modify_ldt syscall */
1283void test_segs(void)
1284{
1285 struct modify_ldt_ldt_s ldt;
1286 long long ldt_table[3];
1287 int res, res2;
1288 char tmp;
1289 struct {
1290 uint32_t offset;
1291 uint16_t seg;
1292 } __attribute__((packed)) segoff;
1293
1294 ldt.entry_number = 1;
1295 ldt.base_addr = (unsigned long)&seg_data1;
1296 ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1297 ldt.seg_32bit = 1;
1298 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1299 ldt.read_exec_only = 0;
1300 ldt.limit_in_pages = 1;
1301 ldt.seg_not_present = 0;
1302 ldt.useable = 1;
1303 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1304
1305 ldt.entry_number = 2;
1306 ldt.base_addr = (unsigned long)&seg_data2;
1307 ldt.limit = (sizeof(seg_data2) + 0xfff) >> 12;
1308 ldt.seg_32bit = 1;
1309 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1310 ldt.read_exec_only = 0;
1311 ldt.limit_in_pages = 1;
1312 ldt.seg_not_present = 0;
1313 ldt.useable = 1;
1314 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1315
1316 modify_ldt(0, &ldt_table, sizeof(ldt_table)); /* read ldt entries */
1317#if 0
1318 {
1319 int i;
1320 for(i=0;i<3;i++)
1321 printf("%d: %016Lx\n", i, ldt_table[i]);
1322 }
1323#endif
1324 /* do some tests with fs or gs */
1325 asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1326
1327 seg_data1[1] = 0xaa;
1328 seg_data2[1] = 0x55;
1329
1330 asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
1331 printf("FS[1] = %02x\n", res);
1332
1333 asm volatile ("pushl %%gs\n"
1334 "movl %1, %%gs\n"
1335 "gs movzbl 0x1, %0\n"
1336 "popl %%gs\n"
1337 : "=r" (res)
1338 : "r" (MK_SEL(2)));
1339 printf("GS[1] = %02x\n", res);
1340
1341 /* tests with ds/ss (implicit segment case) */
1342 tmp = 0xa5;
1343 asm volatile ("pushl %%ebp\n\t"
1344 "pushl %%ds\n\t"
1345 "movl %2, %%ds\n\t"
1346 "movl %3, %%ebp\n\t"
1347 "movzbl 0x1, %0\n\t"
1348 "movzbl (%%ebp), %1\n\t"
1349 "popl %%ds\n\t"
1350 "popl %%ebp\n\t"
1351 : "=r" (res), "=r" (res2)
1352 : "r" (MK_SEL(1)), "r" (&tmp));
1353 printf("DS[1] = %02x\n", res);
1354 printf("SS[tmp] = %02x\n", res2);
1355
1356 segoff.seg = MK_SEL(2);
1357 segoff.offset = 0xabcdef12;
1358 asm volatile("lfs %2, %0\n\t"
1359 "movl %%fs, %1\n\t"
1360 : "=r" (res), "=g" (res2)
1361 : "m" (segoff));
1362 printf("FS:reg = %04x:%08x\n", res2, res);
1363
1364 TEST_LR("larw", "w", MK_SEL(2), 0x0100);
1365 TEST_LR("larl", "", MK_SEL(2), 0x0100);
1366 TEST_LR("lslw", "w", MK_SEL(2), 0);
1367 TEST_LR("lsll", "", MK_SEL(2), 0);
1368
1369 TEST_LR("larw", "w", 0xfff8, 0);
1370 TEST_LR("larl", "", 0xfff8, 0);
1371 TEST_LR("lslw", "w", 0xfff8, 0);
1372 TEST_LR("lsll", "", 0xfff8, 0);
1373
1374 TEST_ARPL("arpl", "w", 0x12345678 | 3, 0x762123c | 1);
1375 TEST_ARPL("arpl", "w", 0x12345678 | 1, 0x762123c | 3);
1376 TEST_ARPL("arpl", "w", 0x12345678 | 1, 0x762123c | 1);
1377}
1378
1379/* 16 bit code test */
1380extern char code16_start, code16_end;
1381extern char code16_func1;
1382extern char code16_func2;
1383extern char code16_func3;
1384
1385void test_code16(void)
1386{
1387 struct modify_ldt_ldt_s ldt;
1388 int res, res2;
1389
1390 /* build a code segment */
1391 ldt.entry_number = 1;
1392 ldt.base_addr = (unsigned long)&code16_start;
1393 ldt.limit = &code16_end - &code16_start;
1394 ldt.seg_32bit = 0;
1395 ldt.contents = MODIFY_LDT_CONTENTS_CODE;
1396 ldt.read_exec_only = 0;
1397 ldt.limit_in_pages = 0;
1398 ldt.seg_not_present = 0;
1399 ldt.useable = 1;
1400 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1401
1402 /* call the first function */
1403 asm volatile ("lcall %1, %2"
1404 : "=a" (res)
1405 : "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc");
1406 printf("func1() = 0x%08x\n", res);
1407 asm volatile ("lcall %2, %3"
1408 : "=a" (res), "=c" (res2)
1409 : "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc");
1410 printf("func2() = 0x%08x spdec=%d\n", res, res2);
1411 asm volatile ("lcall %1, %2"
1412 : "=a" (res)
1413 : "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc");
1414 printf("func3() = 0x%08x\n", res);
1415}
1416#endif
1417
1418#if defined(__x86_64__)
1419asm(".globl func_lret\n"
1420 "func_lret:\n"
1421 "movl $0x87654641, %eax\n"
1422 "lretq\n");
1423#else
1424asm(".globl func_lret\n"
1425 "func_lret:\n"
1426 "movl $0x87654321, %eax\n"
1427 "lret\n"
1428
1429 ".globl func_iret\n"
1430 "func_iret:\n"
1431 "movl $0xabcd4321, %eax\n"
1432 "iret\n");
1433#endif
1434
1435extern char func_lret;
1436extern char func_iret;
1437
1438void test_misc(void)
1439{
1440 char table[256];
1441 long res, i;
1442
1443 for(i=0;i<256;i++) table[i] = 256 - i;
1444 res = 0x12345678;
1445 asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
1446 printf("xlat: EAX=" FMTLX "\n", res);
1447
1448#if defined(__x86_64__)
1449#if 0
1450 {
1451 /* XXX: see if Intel Core2 and AMD64 behavior really
1452 differ. Here we implemented the Intel way which is not
1453 compatible yet with QEMU. */
1454 static struct __attribute__((packed)) {
1455 uint64_t offset;
1456 uint16_t seg;
1457 } desc;
1458 long cs_sel;
1459
1460 asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
1461
1462 asm volatile ("push %1\n"
1463 "call func_lret\n"
1464 : "=a" (res)
1465 : "r" (cs_sel) : "memory", "cc");
1466 printf("func_lret=" FMTLX "\n", res);
1467
1468 desc.offset = (long)&func_lret;
1469 desc.seg = cs_sel;
1470
1471 asm volatile ("xor %%rax, %%rax\n"
1472 "rex64 lcall *(%%rcx)\n"
1473 : "=a" (res)
1474 : "c" (&desc)
1475 : "memory", "cc");
1476 printf("func_lret2=" FMTLX "\n", res);
1477
1478 asm volatile ("push %2\n"
1479 "mov $ 1f, %%rax\n"
1480 "push %%rax\n"
1481 "rex64 ljmp *(%%rcx)\n"
1482 "1:\n"
1483 : "=a" (res)
1484 : "c" (&desc), "b" (cs_sel)
1485 : "memory", "cc");
1486 printf("func_lret3=" FMTLX "\n", res);
1487 }
1488#endif
1489#else
1490 asm volatile ("push %%cs ; call %1"
1491 : "=a" (res)
1492 : "m" (func_lret): "memory", "cc");
1493 printf("func_lret=" FMTLX "\n", res);
1494
1495 asm volatile ("pushf ; push %%cs ; call %1"
1496 : "=a" (res)
1497 : "m" (func_iret): "memory", "cc");
1498 printf("func_iret=" FMTLX "\n", res);
1499#endif
1500
1501#if defined(__x86_64__)
1502 /* specific popl test */
1503 asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
1504 : "=g" (res));
1505 printf("popl esp=" FMTLX "\n", res);
1506#else
1507 /* specific popl test */
1508 asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
1509 : "=g" (res));
1510 printf("popl esp=" FMTLX "\n", res);
1511
1512 /* specific popw test */
1513 asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
1514 : "=g" (res));
1515 printf("popw esp=" FMTLX "\n", res);
1516#endif
1517}
1518
1519uint8_t str_buffer[4096];
1520
1521#define TEST_STRING1(OP, size, DF, REP)\
1522{\
1523 long esi, edi, eax, ecx, eflags;\
1524\
1525 esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
1526 edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
1527 eax = i2l(0x12345678);\
1528 ecx = 17;\
1529\
1530 asm volatile ("push $0\n\t"\
1531 "popf\n\t"\
1532 DF "\n\t"\
1533 REP #OP size "\n\t"\
1534 "cld\n\t"\
1535 "pushf\n\t"\
1536 "pop %4\n\t"\
1537 : "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
1538 : "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
1539 printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
1540 REP #OP size, esi, edi, eax, ecx,\
1541 (int)(eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)));\
1542}
1543
1544#define TEST_STRING(OP, REP)\
1545 TEST_STRING1(OP, "b", "", REP);\
1546 TEST_STRING1(OP, "w", "", REP);\
1547 TEST_STRING1(OP, "l", "", REP);\
1548 X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
1549 TEST_STRING1(OP, "b", "std", REP);\
1550 TEST_STRING1(OP, "w", "std", REP);\
1551 TEST_STRING1(OP, "l", "std", REP);\
1552 X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
1553
1554void test_string(void)
1555{
1556 int i;
1557 for(i = 0;i < sizeof(str_buffer); i++)
1558 str_buffer[i] = i + 0x56;
1559 TEST_STRING(stos, "");
1560 TEST_STRING(stos, "rep ");
1561 TEST_STRING(lods, ""); /* to verify stos */
1562 TEST_STRING(lods, "rep ");
1563 TEST_STRING(movs, "");
1564 TEST_STRING(movs, "rep ");
1565 TEST_STRING(lods, ""); /* to verify stos */
1566
1567 /* XXX: better tests */
1568 TEST_STRING(scas, "");
1569 TEST_STRING(scas, "repz ");
1570 TEST_STRING(scas, "repnz ");
1571 TEST_STRING(cmps, "");
1572 TEST_STRING(cmps, "repz ");
1573 TEST_STRING(cmps, "repnz ");
1574}
1575
1576#ifdef TEST_VM86
1577/* VM86 test */
1578
1579static inline void set_bit(uint8_t *a, unsigned int bit)
1580{
1581 a[bit / 8] |= (1 << (bit % 8));
1582}
1583
1584static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
1585{
1586 return (uint8_t *)((seg << 4) + (reg & 0xffff));
1587}
1588
1589static inline void pushw(struct vm86_regs *r, int val)
1590{
1591 r->esp = (r->esp & ~0xffff) | ((r->esp - 2) & 0xffff);
1592 *(uint16_t *)seg_to_linear(r->ss, r->esp) = val;
1593}
1594
1595static inline int vm86(int func, struct vm86plus_struct *v86)
1596{
1597 return syscall(__NR_vm86, func, v86);
1598}
1599
1600extern char vm86_code_start;
1601extern char vm86_code_end;
1602
1603#define VM86_CODE_CS 0x100
1604#define VM86_CODE_IP 0x100
1605
1606void test_vm86(void)
1607{
1608 struct vm86plus_struct ctx;
1609 struct vm86_regs *r;
1610 uint8_t *vm86_mem;
1611 int seg, ret;
1612
1613 vm86_mem = mmap((void *)0x00000000, 0x110000,
1614 PROT_WRITE | PROT_READ | PROT_EXEC,
1615 MAP_FIXED | MAP_ANON | MAP_PRIVATE, -1, 0);
1616 if (vm86_mem == MAP_FAILED) {
1617 printf("ERROR: could not map vm86 memory");
1618 return;
1619 }
1620 memset(&ctx, 0, sizeof(ctx));
1621
1622 /* init basic registers */
1623 r = &ctx.regs;
1624 r->eip = VM86_CODE_IP;
1625 r->esp = 0xfffe;
1626 seg = VM86_CODE_CS;
1627 r->cs = seg;
1628 r->ss = seg;
1629 r->ds = seg;
1630 r->es = seg;
1631 r->fs = seg;
1632 r->gs = seg;
1633 r->eflags = VIF_MASK;
1634
1635 /* move code to proper address. We use the same layout as a .com
1636 dos program. */
1637 memcpy(vm86_mem + (VM86_CODE_CS << 4) + VM86_CODE_IP,
1638 &vm86_code_start, &vm86_code_end - &vm86_code_start);
1639
1640 /* mark int 0x21 as being emulated */
1641 set_bit((uint8_t *)&ctx.int_revectored, 0x21);
1642
1643 for(;;) {
1644 ret = vm86(VM86_ENTER, &ctx);
1645 switch(VM86_TYPE(ret)) {
1646 case VM86_INTx:
1647 {
1648 int int_num, ah, v;
1649
1650 int_num = VM86_ARG(ret);
1651 if (int_num != 0x21)
1652 goto unknown_int;
1653 ah = (r->eax >> 8) & 0xff;
1654 switch(ah) {
1655 case 0x00: /* exit */
1656 goto the_end;
1657 case 0x02: /* write char */
1658 {
1659 uint8_t c = r->edx;
1660 putchar(c);
1661 }
1662 break;
1663 case 0x09: /* write string */
1664 {
1665 uint8_t c, *ptr;
1666 ptr = seg_to_linear(r->ds, r->edx);
1667 for(;;) {
1668 c = *ptr++;
1669 if (c == '$')
1670 break;
1671 putchar(c);
1672 }
1673 r->eax = (r->eax & ~0xff) | '$';
1674 }
1675 break;
1676 case 0xff: /* extension: write eflags number in edx */
1677 v = (int)r->edx;
1678#ifndef LINUX_VM86_IOPL_FIX
1679 v &= ~0x3000;
1680#endif
1681 printf("%08x\n", v);
1682 break;
1683 default:
1684 unknown_int:
1685 printf("unsupported int 0x%02x\n", int_num);
1686 goto the_end;
1687 }
1688 }
1689 break;
1690 case VM86_SIGNAL:
1691 /* a signal came, we just ignore that */
1692 break;
1693 case VM86_STI:
1694 break;
1695 default:
1696 printf("ERROR: unhandled vm86 return code (0x%x)\n", ret);
1697 goto the_end;
1698 }
1699 }
1700 the_end:
1701 printf("VM86 end\n");
1702 munmap(vm86_mem, 0x110000);
1703}
1704#endif
1705
1706/* exception tests */
1707#if defined(__i386__) && !defined(REG_EAX)
1708#define REG_EAX EAX
1709#define REG_EBX EBX
1710#define REG_ECX ECX
1711#define REG_EDX EDX
1712#define REG_ESI ESI
1713#define REG_EDI EDI
1714#define REG_EBP EBP
1715#define REG_ESP ESP
1716#define REG_EIP EIP
1717#define REG_EFL EFL
1718#define REG_TRAPNO TRAPNO
1719#define REG_ERR ERR
1720#endif
1721
1722#if defined(__x86_64__)
1723#define REG_EIP REG_RIP
1724#endif
1725
1726jmp_buf jmp_env;
1727int v1;
1728int tab[2];
1729
1730void sig_handler(int sig, siginfo_t *info, void *puc)
1731{
1732 struct ucontext *uc = puc;
1733
1734 printf("si_signo=%d si_errno=%d si_code=%d",
1735 info->si_signo, info->si_errno, info->si_code);
1736 printf(" si_addr=0x%08lx",
1737 (unsigned long)info->si_addr);
1738 printf("\n");
1739
1740 printf("trapno=" FMTLX " err=" FMTLX,
1741 (long)uc->uc_mcontext.gregs[REG_TRAPNO],
1742 (long)uc->uc_mcontext.gregs[REG_ERR]);
1743 printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
1744 printf("\n");
1745 longjmp(jmp_env, 1);
1746}
1747
1748void test_exceptions(void)
1749{
1750 struct sigaction act;
1751 volatile int val;
1752
1753 act.sa_sigaction = sig_handler;
1754 sigemptyset(&act.sa_mask);
1755 act.sa_flags = SA_SIGINFO | SA_NODEFER;
1756 sigaction(SIGFPE, &act, NULL);
1757 sigaction(SIGILL, &act, NULL);
1758 sigaction(SIGSEGV, &act, NULL);
1759 sigaction(SIGBUS, &act, NULL);
1760 sigaction(SIGTRAP, &act, NULL);
1761
1762 /* test division by zero reporting */
1763 printf("DIVZ exception:\n");
1764 if (setjmp(jmp_env) == 0) {
1765 /* now divide by zero */
1766 v1 = 0;
1767 v1 = 2 / v1;
1768 }
1769
1770#if !defined(__x86_64__)
1771 printf("BOUND exception:\n");
1772 if (setjmp(jmp_env) == 0) {
1773 /* bound exception */
1774 tab[0] = 1;
1775 tab[1] = 10;
1776 asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
1777 }
1778#endif
1779
1780#ifdef TEST_SEGS
1781 printf("segment exceptions:\n");
1782 if (setjmp(jmp_env) == 0) {
1783 /* load an invalid segment */
1784 asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) | 1));
1785 }
1786 if (setjmp(jmp_env) == 0) {
1787 /* null data segment is valid */
1788 asm volatile ("movl %0, %%fs" : : "r" (3));
1789 /* null stack segment */
1790 asm volatile ("movl %0, %%ss" : : "r" (3));
1791 }
1792
1793 {
1794 struct modify_ldt_ldt_s ldt;
1795 ldt.entry_number = 1;
1796 ldt.base_addr = (unsigned long)&seg_data1;
1797 ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1798 ldt.seg_32bit = 1;
1799 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1800 ldt.read_exec_only = 0;
1801 ldt.limit_in_pages = 1;
1802 ldt.seg_not_present = 1;
1803 ldt.useable = 1;
1804 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1805
1806 if (setjmp(jmp_env) == 0) {
1807 /* segment not present */
1808 asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1809 }
1810 }
1811#endif
1812
1813 /* test SEGV reporting */
1814 printf("PF exception:\n");
1815 if (setjmp(jmp_env) == 0) {
1816 val = 1;
1817 /* we add a nop to test a weird PC retrieval case */
1818 asm volatile ("nop");
1819 /* now store in an invalid address */
1820 *(char *)0x1234 = 1;
1821 }
1822
1823 /* test SEGV reporting */
1824 printf("PF exception:\n");
1825 if (setjmp(jmp_env) == 0) {
1826 val = 1;
1827 /* read from an invalid address */
1828 v1 = *(char *)0x1234;
1829 }
1830
1831 /* test illegal instruction reporting */
1832 printf("UD2 exception:\n");
1833 if (setjmp(jmp_env) == 0) {
1834 /* now execute an invalid instruction */
1835 asm volatile("ud2");
1836 }
1837 printf("lock nop exception:\n");
1838 if (setjmp(jmp_env) == 0) {
1839 /* now execute an invalid instruction */
1840 asm volatile("lock nop");
1841 }
1842
1843 printf("INT exception:\n");
1844 if (setjmp(jmp_env) == 0) {
1845 asm volatile ("int $0xfd");
1846 }
1847 if (setjmp(jmp_env) == 0) {
1848 asm volatile ("int $0x01");
1849 }
1850 if (setjmp(jmp_env) == 0) {
1851 asm volatile (".byte 0xcd, 0x03");
1852 }
1853 if (setjmp(jmp_env) == 0) {
1854 asm volatile ("int $0x04");
1855 }
1856 if (setjmp(jmp_env) == 0) {
1857 asm volatile ("int $0x05");
1858 }
1859
1860 printf("INT3 exception:\n");
1861 if (setjmp(jmp_env) == 0) {
1862 asm volatile ("int3");
1863 }
1864
1865 printf("CLI exception:\n");
1866 if (setjmp(jmp_env) == 0) {
1867 asm volatile ("cli");
1868 }
1869
1870 printf("STI exception:\n");
1871 if (setjmp(jmp_env) == 0) {
1872 asm volatile ("cli");
1873 }
1874
1875#if !defined(__x86_64__)
1876 printf("INTO exception:\n");
1877 if (setjmp(jmp_env) == 0) {
1878 /* overflow exception */
1879 asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
1880 }
1881#endif
1882
1883 printf("OUTB exception:\n");
1884 if (setjmp(jmp_env) == 0) {
1885 asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
1886 }
1887
1888 printf("INB exception:\n");
1889 if (setjmp(jmp_env) == 0) {
1890 asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
1891 }
1892
1893 printf("REP OUTSB exception:\n");
1894 if (setjmp(jmp_env) == 0) {
1895 asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
1896 }
1897
1898 printf("REP INSB exception:\n");
1899 if (setjmp(jmp_env) == 0) {
1900 asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
1901 }
1902
1903 printf("HLT exception:\n");
1904 if (setjmp(jmp_env) == 0) {
1905 asm volatile ("hlt");
1906 }
1907
1908 printf("single step exception:\n");
1909 val = 0;
1910 if (setjmp(jmp_env) == 0) {
1911 asm volatile ("pushf\n"
1912 "orl $0x00100, (%%esp)\n"
1913 "popf\n"
1914 "movl $0xabcd, %0\n"
1915 "movl $0x0, %0\n" : "=m" (val) : : "cc", "memory");
1916 }
1917 printf("val=0x%x\n", val);
1918}
1919
1920#if !defined(__x86_64__)
1921/* specific precise single step test */
1922void sig_trap_handler(int sig, siginfo_t *info, void *puc)
1923{
1924 struct ucontext *uc = puc;
1925 printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
1926}
1927
1928const uint8_t sstep_buf1[4] = { 1, 2, 3, 4};
1929uint8_t sstep_buf2[4];
1930
1931void test_single_step(void)
1932{
1933 struct sigaction act;
1934 volatile int val;
1935 int i;
1936
1937 val = 0;
1938 act.sa_sigaction = sig_trap_handler;
1939 sigemptyset(&act.sa_mask);
1940 act.sa_flags = SA_SIGINFO;
1941 sigaction(SIGTRAP, &act, NULL);
1942 asm volatile ("pushf\n"
1943 "orl $0x00100, (%%esp)\n"
1944 "popf\n"
1945 "movl $0xabcd, %0\n"
1946
1947 /* jmp test */
1948 "movl $3, %%ecx\n"
1949 "1:\n"
1950 "addl $1, %0\n"
1951 "decl %%ecx\n"
1952 "jnz 1b\n"
1953
1954 /* movsb: the single step should stop at each movsb iteration */
1955 "movl $sstep_buf1, %%esi\n"
1956 "movl $sstep_buf2, %%edi\n"
1957 "movl $0, %%ecx\n"
1958 "rep movsb\n"
1959 "movl $3, %%ecx\n"
1960 "rep movsb\n"
1961 "movl $1, %%ecx\n"
1962 "rep movsb\n"
1963
1964 /* cmpsb: the single step should stop at each cmpsb iteration */
1965 "movl $sstep_buf1, %%esi\n"
1966 "movl $sstep_buf2, %%edi\n"
1967 "movl $0, %%ecx\n"
1968 "rep cmpsb\n"
1969 "movl $4, %%ecx\n"
1970 "rep cmpsb\n"
1971
1972 /* getpid() syscall: single step should skip one
1973 instruction */
1974 "movl $20, %%eax\n"
1975 "int $0x80\n"
1976 "movl $0, %%eax\n"
1977
1978 /* when modifying SS, trace is not done on the next
1979 instruction */
1980 "movl %%ss, %%ecx\n"
1981 "movl %%ecx, %%ss\n"
1982 "addl $1, %0\n"
1983 "movl $1, %%eax\n"
1984 "movl %%ecx, %%ss\n"
1985 "jmp 1f\n"
1986 "addl $1, %0\n"
1987 "1:\n"
1988 "movl $1, %%eax\n"
1989 "pushl %%ecx\n"
1990 "popl %%ss\n"
1991 "addl $1, %0\n"
1992 "movl $1, %%eax\n"
1993
1994 "pushf\n"
1995 "andl $~0x00100, (%%esp)\n"
1996 "popf\n"
1997 : "=m" (val)
1998 :
1999 : "cc", "memory", "eax", "ecx", "esi", "edi");
2000 printf("val=%d\n", val);
2001 for(i = 0; i < 4; i++)
2002 printf("sstep_buf2[%d] = %d\n", i, sstep_buf2[i]);
2003}
2004
2005/* self modifying code test */
2006uint8_t code[] = {
2007 0xb8, 0x1, 0x00, 0x00, 0x00, /* movl $1, %eax */
2008 0xc3, /* ret */
2009};
2010
2011asm(".section \".data\"\n"
2012 "smc_code2:\n"
2013 "movl 4(%esp), %eax\n"
2014 "movl %eax, smc_patch_addr2 + 1\n"
2015 "nop\n"
2016 "nop\n"
2017 "nop\n"
2018 "nop\n"
2019 "nop\n"
2020 "nop\n"
2021 "nop\n"
2022 "nop\n"
2023 "smc_patch_addr2:\n"
2024 "movl $1, %eax\n"
2025 "ret\n"
2026 ".previous\n"
2027 );
2028
2029typedef int FuncType(void);
2030extern int smc_code2(int);
2031void test_self_modifying_code(void)
2032{
2033 int i;
2034 printf("self modifying code:\n");
2035 printf("func1 = 0x%x\n", ((FuncType *)code)());
2036 for(i = 2; i <= 4; i++) {
2037 code[1] = i;
2038 printf("func%d = 0x%x\n", i, ((FuncType *)code)());
2039 }
2040
2041 /* more difficult test : the modified code is just after the
2042 modifying instruction. It is forbidden in Intel specs, but it
2043 is used by old DOS programs */
2044 for(i = 2; i <= 4; i++) {
2045 printf("smc_code2(%d) = %d\n", i, smc_code2(i));
2046 }
2047}
2048#endif
2049
2050long enter_stack[4096];
2051
2052#if defined(__x86_64__)
2053#define RSP "%%rsp"
2054#define RBP "%%rbp"
2055#else
2056#define RSP "%%esp"
2057#define RBP "%%ebp"
2058#endif
2059
2060#define TEST_ENTER(size, stack_type, level)\
2061{\
2062 long esp_save, esp_val, ebp_val, ebp_save, i;\
2063 stack_type *ptr, *stack_end, *stack_ptr;\
2064 memset(enter_stack, 0, sizeof(enter_stack));\
2065 stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
2066 ebp_val = (long)stack_ptr;\
2067 for(i=1;i<=32;i++)\
2068 *--stack_ptr = i;\
2069 esp_val = (long)stack_ptr;\
2070 asm("mov " RSP ", %[esp_save]\n"\
2071 "mov " RBP ", %[ebp_save]\n"\
2072 "mov %[esp_val], " RSP "\n"\
2073 "mov %[ebp_val], " RBP "\n"\
2074 "enter" size " $8, $" #level "\n"\
2075 "mov " RSP ", %[esp_val]\n"\
2076 "mov " RBP ", %[ebp_val]\n"\
2077 "mov %[esp_save], " RSP "\n"\
2078 "mov %[ebp_save], " RBP "\n"\
2079 : [esp_save] "=r" (esp_save),\
2080 [ebp_save] "=r" (ebp_save),\
2081 [esp_val] "=r" (esp_val),\
2082 [ebp_val] "=r" (ebp_val)\
2083 : "[esp_val]" (esp_val),\
2084 "[ebp_val]" (ebp_val));\
2085 printf("level=%d:\n", level);\
2086 printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
2087 printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
2088 for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
2089 printf(FMTLX "\n", (long)ptr[0]);\
2090}
2091
2092static void test_enter(void)
2093{
2094#if defined(__x86_64__)
2095 TEST_ENTER("q", uint64_t, 0);
2096 TEST_ENTER("q", uint64_t, 1);
2097 TEST_ENTER("q", uint64_t, 2);
2098 TEST_ENTER("q", uint64_t, 31);
2099#else
2100 TEST_ENTER("l", uint32_t, 0);
2101 TEST_ENTER("l", uint32_t, 1);
2102 TEST_ENTER("l", uint32_t, 2);
2103 TEST_ENTER("l", uint32_t, 31);
2104#endif
2105
2106 TEST_ENTER("w", uint16_t, 0);
2107 TEST_ENTER("w", uint16_t, 1);
2108 TEST_ENTER("w", uint16_t, 2);
2109 TEST_ENTER("w", uint16_t, 31);
2110}
2111
2112#ifdef TEST_SSE
2113
2114typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
2115typedef float __m128 __attribute__ ((__mode__(__V4SF__)));
2116
2117typedef union {
2118 double d[2];
2119 float s[4];
2120 uint32_t l[4];
2121 uint64_t q[2];
2122 __m128 dq;
2123} XMMReg;
2124
2125static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
2126 { 0x456723c698694873, 0xdc515cff944a58ec },
2127 { 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
2128 { 0x007c62c2085427f8, 0x231be9e8cde7438d },
2129 { 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
2130};
2131
2132#define SSE_OP(op)\
2133{\
2134 asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2135 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2136 #op,\
2137 a.q[1], a.q[0],\
2138 b.q[1], b.q[0],\
2139 r.q[1], r.q[0]);\
2140}
2141
2142#define SSE_OP2(op)\
2143{\
2144 int i;\
2145 for(i=0;i<2;i++) {\
2146 a.q[0] = test_values[2*i][0];\
2147 a.q[1] = test_values[2*i][1];\
2148 b.q[0] = test_values[2*i+1][0];\
2149 b.q[1] = test_values[2*i+1][1];\
2150 SSE_OP(op);\
2151 }\
2152}
2153
2154#define MMX_OP2(op)\
2155{\
2156 int i;\
2157 for(i=0;i<2;i++) {\
2158 a.q[0] = test_values[2*i][0];\
2159 b.q[0] = test_values[2*i+1][0];\
2160 asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
2161 printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
2162 #op,\
2163 a.q[0],\
2164 b.q[0],\
2165 r.q[0]);\
2166 }\
2167 SSE_OP2(op);\
2168}
2169
2170#define SHUF_OP(op, ib)\
2171{\
2172 a.q[0] = test_values[0][0];\
2173 a.q[1] = test_values[0][1];\
2174 b.q[0] = test_values[1][0];\
2175 b.q[1] = test_values[1][1];\
2176 asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2177 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2178 #op,\
2179 a.q[1], a.q[0],\
2180 b.q[1], b.q[0],\
2181 ib,\
2182 r.q[1], r.q[0]);\
2183}
2184
2185#define PSHUF_OP(op, ib)\
2186{\
2187 int i;\
2188 for(i=0;i<2;i++) {\
2189 a.q[0] = test_values[2*i][0];\
2190 a.q[1] = test_values[2*i][1];\
2191 asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2192 printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2193 #op,\
2194 a.q[1], a.q[0],\
2195 ib,\
2196 r.q[1], r.q[0]);\
2197 }\
2198}
2199
2200#define SHIFT_IM(op, ib)\
2201{\
2202 int i;\
2203 for(i=0;i<2;i++) {\
2204 a.q[0] = test_values[2*i][0];\
2205 a.q[1] = test_values[2*i][1];\
2206 asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
2207 printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2208 #op,\
2209 a.q[1], a.q[0],\
2210 ib,\
2211 r.q[1], r.q[0]);\
2212 }\
2213}
2214
2215#define SHIFT_OP(op, ib)\
2216{\
2217 int i;\
2218 SHIFT_IM(op, ib);\
2219 for(i=0;i<2;i++) {\
2220 a.q[0] = test_values[2*i][0];\
2221 a.q[1] = test_values[2*i][1];\
2222 b.q[0] = ib;\
2223 b.q[1] = 0;\
2224 asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2225 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2226 #op,\
2227 a.q[1], a.q[0],\
2228 b.q[1], b.q[0],\
2229 r.q[1], r.q[0]);\
2230 }\
2231}
2232
2233#define MOVMSK(op)\
2234{\
2235 int i, reg;\
2236 for(i=0;i<2;i++) {\
2237 a.q[0] = test_values[2*i][0];\
2238 a.q[1] = test_values[2*i][1];\
2239 asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
2240 printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2241 #op,\
2242 a.q[1], a.q[0],\
2243 reg);\
2244 }\
2245}
2246
2247#define SSE_OPS(a) \
2248SSE_OP(a ## ps);\
2249SSE_OP(a ## ss);
2250
2251#define SSE_OPD(a) \
2252SSE_OP(a ## pd);\
2253SSE_OP(a ## sd);
2254
2255#define SSE_COMI(op, field)\
2256{\
2257 unsigned int eflags;\
2258 XMMReg a, b;\
2259 a.field[0] = a1;\
2260 b.field[0] = b1;\
2261 asm volatile (#op " %2, %1\n"\
2262 "pushf\n"\
2263 "pop %0\n"\
2264 : "=m" (eflags)\
2265 : "x" (a.dq), "x" (b.dq));\
2266 printf("%-9s: a=%f b=%f cc=%04x\n",\
2267 #op, a1, b1,\
2268 eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
2269}
2270
2271void test_sse_comi(double a1, double b1)
2272{
2273 SSE_COMI(ucomiss, s);
2274 SSE_COMI(ucomisd, d);
2275 SSE_COMI(comiss, s);
2276 SSE_COMI(comisd, d);
2277}
2278
2279#define CVT_OP_XMM(op)\
2280{\
2281 asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2282 printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2283 #op,\
2284 a.q[1], a.q[0],\
2285 r.q[1], r.q[0]);\
2286}
2287
2288/* Force %xmm0 usage to avoid the case where both register index are 0
2289 to test intruction decoding more extensively */
2290#define CVT_OP_XMM2MMX(op)\
2291{\
2292 asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
2293 : "%xmm0"); \
2294 asm volatile("emms\n"); \
2295 printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
2296 #op,\
2297 a.q[1], a.q[0],\
2298 r.q[0]);\
2299}
2300
2301#define CVT_OP_MMX2XMM(op)\
2302{\
2303 asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
2304 asm volatile("emms\n"); \
2305 printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
2306 #op,\
2307 a.q[0],\
2308 r.q[1], r.q[0]);\
2309}
2310
2311#define CVT_OP_REG2XMM(op)\
2312{\
2313 asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
2314 printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
2315 #op,\
2316 a.l[0],\
2317 r.q[1], r.q[0]);\
2318}
2319
2320#define CVT_OP_XMM2REG(op)\
2321{\
2322 asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
2323 printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2324 #op,\
2325 a.q[1], a.q[0],\
2326 r.l[0]);\
2327}
2328
2329struct fpxstate {
2330 uint16_t fpuc;
2331 uint16_t fpus;
2332 uint16_t fptag;
2333 uint16_t fop;
2334 uint32_t fpuip;
2335 uint16_t cs_sel;
2336 uint16_t dummy0;
2337 uint32_t fpudp;
2338 uint16_t ds_sel;
2339 uint16_t dummy1;
2340 uint32_t mxcsr;
2341 uint32_t mxcsr_mask;
2342 uint8_t fpregs1[8 * 16];
2343 uint8_t xmm_regs[8 * 16];
2344 uint8_t dummy2[224];
2345};
2346
2347static struct fpxstate fpx_state __attribute__((aligned(16)));
2348static struct fpxstate fpx_state2 __attribute__((aligned(16)));
2349
2350void test_fxsave(void)
2351{
2352 struct fpxstate *fp = &fpx_state;
2353 struct fpxstate *fp2 = &fpx_state2;
2354 int i, nb_xmm;
2355 XMMReg a, b;
2356 a.q[0] = test_values[0][0];
2357 a.q[1] = test_values[0][1];
2358 b.q[0] = test_values[1][0];
2359 b.q[1] = test_values[1][1];
2360
2361 asm("movdqa %2, %%xmm0\n"
2362 "movdqa %3, %%xmm7\n"
2363#if defined(__x86_64__)
2364 "movdqa %2, %%xmm15\n"
2365#endif
2366 " fld1\n"
2367 " fldpi\n"
2368 " fldln2\n"
2369 " fxsave %0\n"
2370 " fxrstor %0\n"
2371 " fxsave %1\n"
2372 " fninit\n"
2373 : "=m" (*(uint32_t *)fp2), "=m" (*(uint32_t *)fp)
2374 : "m" (a), "m" (b));
2375 printf("fpuc=%04x\n", fp->fpuc);
2376 printf("fpus=%04x\n", fp->fpus);
2377 printf("fptag=%04x\n", fp->fptag);
2378 for(i = 0; i < 3; i++) {
2379 printf("ST%d: " FMT64X " %04x\n",
2380 i,
2381 *(uint64_t *)&fp->fpregs1[i * 16],
2382 *(uint16_t *)&fp->fpregs1[i * 16 + 8]);
2383 }
2384 printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
2385#if defined(__x86_64__)
2386 nb_xmm = 16;
2387#else
2388 nb_xmm = 8;
2389#endif
2390 for(i = 0; i < nb_xmm; i++) {
2391 printf("xmm%d: " FMT64X "" FMT64X "\n",
2392 i,
2393 *(uint64_t *)&fp->xmm_regs[i * 16],
2394 *(uint64_t *)&fp->xmm_regs[i * 16 + 8]);
2395 }
2396}
2397
2398void test_sse(void)
2399{
2400 XMMReg r, a, b;
2401 int i;
2402
2403 MMX_OP2(punpcklbw);
2404 MMX_OP2(punpcklwd);
2405 MMX_OP2(punpckldq);
2406 MMX_OP2(packsswb);
2407 MMX_OP2(pcmpgtb);
2408 MMX_OP2(pcmpgtw);
2409 MMX_OP2(pcmpgtd);
2410 MMX_OP2(packuswb);
2411 MMX_OP2(punpckhbw);
2412 MMX_OP2(punpckhwd);
2413 MMX_OP2(punpckhdq);
2414 MMX_OP2(packssdw);
2415 MMX_OP2(pcmpeqb);
2416 MMX_OP2(pcmpeqw);
2417 MMX_OP2(pcmpeqd);
2418
2419 MMX_OP2(paddq);
2420 MMX_OP2(pmullw);
2421 MMX_OP2(psubusb);
2422 MMX_OP2(psubusw);
2423 MMX_OP2(pminub);
2424 MMX_OP2(pand);
2425 MMX_OP2(paddusb);
2426 MMX_OP2(paddusw);
2427 MMX_OP2(pmaxub);
2428 MMX_OP2(pandn);
2429
2430 MMX_OP2(pmulhuw);
2431 MMX_OP2(pmulhw);
2432
2433 MMX_OP2(psubsb);
2434 MMX_OP2(psubsw);
2435 MMX_OP2(pminsw);
2436 MMX_OP2(por);
2437 MMX_OP2(paddsb);
2438 MMX_OP2(paddsw);
2439 MMX_OP2(pmaxsw);
2440 MMX_OP2(pxor);
2441 MMX_OP2(pmuludq);
2442 MMX_OP2(pmaddwd);
2443 MMX_OP2(psadbw);
2444 MMX_OP2(psubb);
2445 MMX_OP2(psubw);
2446 MMX_OP2(psubd);
2447 MMX_OP2(psubq);
2448 MMX_OP2(paddb);
2449 MMX_OP2(paddw);
2450 MMX_OP2(paddd);
2451
2452 MMX_OP2(pavgb);
2453 MMX_OP2(pavgw);
2454
2455 asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
2456 printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
2457
2458 asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
2459 printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
2460
2461 a.q[0] = test_values[0][0];
2462 a.q[1] = test_values[0][1];
2463 asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2464 printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2465
2466 asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2467 printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2468
2469 asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2470 printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2471
2472 asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2473 printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2474
2475 {
2476 r.q[0] = -1;
2477 r.q[1] = -1;
2478
2479 a.q[0] = test_values[0][0];
2480 a.q[1] = test_values[0][1];
2481 b.q[0] = test_values[1][0];
2482 b.q[1] = test_values[1][1];
2483 asm volatile("maskmovq %1, %0" :
2484 : "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
2485 : "memory");
2486 printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n",
2487 "maskmov",
2488 r.q[0],
2489 a.q[0],
2490 b.q[0]);
2491 asm volatile("maskmovdqu %1, %0" :
2492 : "x" (a.dq), "x" (b.dq), "D" (&r)
2493 : "memory");
2494 printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n",
2495 "maskmov",
2496 r.q[1], r.q[0],
2497 a.q[1], a.q[0],
2498 b.q[1], b.q[0]);
2499 }
2500
2501 asm volatile ("emms");
2502
2503 SSE_OP2(punpcklqdq);
2504 SSE_OP2(punpckhqdq);
2505 SSE_OP2(andps);
2506 SSE_OP2(andpd);
2507 SSE_OP2(andnps);
2508 SSE_OP2(andnpd);
2509 SSE_OP2(orps);
2510 SSE_OP2(orpd);
2511 SSE_OP2(xorps);
2512 SSE_OP2(xorpd);
2513
2514 SSE_OP2(unpcklps);
2515 SSE_OP2(unpcklpd);
2516 SSE_OP2(unpckhps);
2517 SSE_OP2(unpckhpd);
2518
2519 SHUF_OP(shufps, 0x78);
2520 SHUF_OP(shufpd, 0x02);
2521
2522 PSHUF_OP(pshufd, 0x78);
2523 PSHUF_OP(pshuflw, 0x78);
2524 PSHUF_OP(pshufhw, 0x78);
2525
2526 SHIFT_OP(psrlw, 7);
2527 SHIFT_OP(psrlw, 16);
2528 SHIFT_OP(psraw, 7);
2529 SHIFT_OP(psraw, 16);
2530 SHIFT_OP(psllw, 7);
2531 SHIFT_OP(psllw, 16);
2532
2533 SHIFT_OP(psrld, 7);
2534 SHIFT_OP(psrld, 32);
2535 SHIFT_OP(psrad, 7);
2536 SHIFT_OP(psrad, 32);
2537 SHIFT_OP(pslld, 7);
2538 SHIFT_OP(pslld, 32);
2539
2540 SHIFT_OP(psrlq, 7);
2541 SHIFT_OP(psrlq, 32);
2542 SHIFT_OP(psllq, 7);
2543 SHIFT_OP(psllq, 32);
2544
2545 SHIFT_IM(psrldq, 16);
2546 SHIFT_IM(psrldq, 7);
2547 SHIFT_IM(pslldq, 16);
2548 SHIFT_IM(pslldq, 7);
2549
2550 MOVMSK(movmskps);
2551 MOVMSK(movmskpd);
2552
2553 /* FPU specific ops */
2554
2555 {
2556 uint32_t mxcsr;
2557 asm volatile("stmxcsr %0" : "=m" (mxcsr));
2558 printf("mxcsr=%08x\n", mxcsr & 0x1f80);
2559 asm volatile("ldmxcsr %0" : : "m" (mxcsr));
2560 }
2561
2562 test_sse_comi(2, -1);
2563 test_sse_comi(2, 2);
2564 test_sse_comi(2, 3);
2565 test_sse_comi(2, q_nan.d);
2566 test_sse_comi(q_nan.d, -1);
2567
2568 for(i = 0; i < 2; i++) {
2569 a.s[0] = 2.7;
2570 a.s[1] = 3.4;
2571 a.s[2] = 4;
2572 a.s[3] = -6.3;
2573 b.s[0] = 45.7;
2574 b.s[1] = 353.4;
2575 b.s[2] = 4;
2576 b.s[3] = 56.3;
2577 if (i == 1) {
2578 a.s[0] = q_nan.d;
2579 b.s[3] = q_nan.d;
2580 }
2581
2582 SSE_OPS(add);
2583 SSE_OPS(mul);
2584 SSE_OPS(sub);
2585 SSE_OPS(min);
2586 SSE_OPS(div);
2587 SSE_OPS(max);
2588 SSE_OPS(sqrt);
2589 SSE_OPS(cmpeq);
2590 SSE_OPS(cmplt);
2591 SSE_OPS(cmple);
2592 SSE_OPS(cmpunord);
2593 SSE_OPS(cmpneq);
2594 SSE_OPS(cmpnlt);
2595 SSE_OPS(cmpnle);
2596 SSE_OPS(cmpord);
2597
2598
2599 a.d[0] = 2.7;
2600 a.d[1] = -3.4;
2601 b.d[0] = 45.7;
2602 b.d[1] = -53.4;
2603 if (i == 1) {
2604 a.d[0] = q_nan.d;
2605 b.d[1] = q_nan.d;
2606 }
2607 SSE_OPD(add);
2608 SSE_OPD(mul);
2609 SSE_OPD(sub);
2610 SSE_OPD(min);
2611 SSE_OPD(div);
2612 SSE_OPD(max);
2613 SSE_OPD(sqrt);
2614 SSE_OPD(cmpeq);
2615 SSE_OPD(cmplt);
2616 SSE_OPD(cmple);
2617 SSE_OPD(cmpunord);
2618 SSE_OPD(cmpneq);
2619 SSE_OPD(cmpnlt);
2620 SSE_OPD(cmpnle);
2621 SSE_OPD(cmpord);
2622 }
2623
2624 /* float to float/int */
2625 a.s[0] = 2.7;
2626 a.s[1] = 3.4;
2627 a.s[2] = 4;
2628 a.s[3] = -6.3;
2629 CVT_OP_XMM(cvtps2pd);
2630 CVT_OP_XMM(cvtss2sd);
2631 CVT_OP_XMM2MMX(cvtps2pi);
2632 CVT_OP_XMM2MMX(cvttps2pi);
2633 CVT_OP_XMM2REG(cvtss2si);
2634 CVT_OP_XMM2REG(cvttss2si);
2635 CVT_OP_XMM(cvtps2dq);
2636 CVT_OP_XMM(cvttps2dq);
2637
2638 a.d[0] = 2.6;
2639 a.d[1] = -3.4;
2640 CVT_OP_XMM(cvtpd2ps);
2641 CVT_OP_XMM(cvtsd2ss);
2642 CVT_OP_XMM2MMX(cvtpd2pi);
2643 CVT_OP_XMM2MMX(cvttpd2pi);
2644 CVT_OP_XMM2REG(cvtsd2si);
2645 CVT_OP_XMM2REG(cvttsd2si);
2646 CVT_OP_XMM(cvtpd2dq);
2647 CVT_OP_XMM(cvttpd2dq);
2648
2649 /* sse/mmx moves */
2650 CVT_OP_XMM2MMX(movdq2q);
2651 CVT_OP_MMX2XMM(movq2dq);
2652
2653 /* int to float */
2654 a.l[0] = -6;
2655 a.l[1] = 2;
2656 a.l[2] = 100;
2657 a.l[3] = -60000;
2658 CVT_OP_MMX2XMM(cvtpi2ps);
2659 CVT_OP_MMX2XMM(cvtpi2pd);
2660 CVT_OP_REG2XMM(cvtsi2ss);
2661 CVT_OP_REG2XMM(cvtsi2sd);
2662 CVT_OP_XMM(cvtdq2ps);
2663 CVT_OP_XMM(cvtdq2pd);
2664
2665 /* XXX: test PNI insns */
2666#if 0
2667 SSE_OP2(movshdup);
2668#endif
2669 asm volatile ("emms");
2670}
2671
2672#endif
2673
2674#define TEST_CONV_RAX(op)\
2675{\
2676 unsigned long a, r;\
2677 a = i2l(0x8234a6f8);\
2678 r = a;\
2679 asm volatile(#op : "=a" (r) : "0" (r));\
2680 printf("%-10s A=" FMTLX " R=" FMTLX "\n", #op, a, r);\
2681}
2682
2683#define TEST_CONV_RAX_RDX(op)\
2684{\
2685 unsigned long a, d, r, rh; \
2686 a = i2l(0x8234a6f8);\
2687 d = i2l(0x8345a1f2);\
2688 r = a;\
2689 rh = d;\
2690 asm volatile(#op : "=a" (r), "=d" (rh) : "0" (r), "1" (rh)); \
2691 printf("%-10s A=" FMTLX " R=" FMTLX ":" FMTLX "\n", #op, a, r, rh); \
2692}
2693
2694void test_conv(void)
2695{
2696 TEST_CONV_RAX(cbw);
2697 TEST_CONV_RAX(cwde);
2698#if defined(__x86_64__)
2699 TEST_CONV_RAX(cdqe);
2700#endif
2701
2702 TEST_CONV_RAX_RDX(cwd);
2703 TEST_CONV_RAX_RDX(cdq);
2704#if defined(__x86_64__)
2705 TEST_CONV_RAX_RDX(cqo);
2706#endif
2707
2708 {
2709 unsigned long a, r;
2710 a = i2l(0x12345678);
2711 asm volatile("bswapl %k0" : "=r" (r) : "0" (a));
2712 printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapl", a, r);
2713 }
2714#if defined(__x86_64__)
2715 {
2716 unsigned long a, r;
2717 a = i2l(0x12345678);
2718 asm volatile("bswapq %0" : "=r" (r) : "0" (a));
2719 printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapq", a, r);
2720 }
2721#endif
2722}
2723
2724extern void *__start_initcall;
2725extern void *__stop_initcall;
2726
2727
2728int main(int argc, char **argv)
2729{
2730 void **ptr;
2731 void (*func)(void);
2732
2733 ptr = &__start_initcall;
2734 while (ptr != &__stop_initcall) {
2735 func = *ptr++;
2736 func();
2737 }
2738 test_bsx();
2739 test_mul();
2740 test_jcc();
2741 test_loop();
2742 test_floats();
2743#if !defined(__x86_64__)
2744 test_bcd();
2745#endif
2746 test_xchg();
2747 test_string();
2748 test_misc();
2749 test_lea();
2750#ifdef TEST_SEGS
2751 test_segs();
2752 test_code16();
2753#endif
2754#ifdef TEST_VM86
2755 test_vm86();
2756#endif
2757#if !defined(__x86_64__)
2758 test_exceptions();
2759 test_self_modifying_code();
2760 test_single_step();
2761#endif
2762 test_enter();
2763 test_conv();
2764#ifdef TEST_SSE
2765 test_sse();
2766 test_fxsave();
2767#endif
2768 return 0;
2769}
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