test-i386.c@ 35487

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1	/*
2	* x86 CPU test
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*/
20
21	/*
22	* Oracle GPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Oracle elects to use only
24	* the General Public License version 2 (GPLv2) at this time for any software where
25	* a choice of GPL license versions is made available with the language indicating
26	* that GPLv2 or any later version may be used, or where a choice of which version
27	* of the GPL is applied is otherwise unspecified.
28	*/
29
30	#define _GNU_SOURCE
31	#include <stdlib.h>
32	#include <stdio.h>
33	#include <string.h>
34	#include <inttypes.h>
35	#include <math.h>
36	#include <signal.h>
37	#include <setjmp.h>
38	#include <errno.h>
39	#include <sys/ucontext.h>
40	#include <sys/mman.h>
41
42	#if !defined(__x86_64__)
43	#define TEST_VM86
44	#define TEST_SEGS
45	#endif
46	//#define LINUX_VM86_IOPL_FIX
47	//#define TEST_P4_FLAGS
48	#if defined(__x86_64__)
49	#define TEST_SSE
50	#define TEST_CMOV 1
51	#define TEST_FCOMI 1
52	#else
53	//#define TEST_SSE
54	#define TEST_CMOV 0
55	#define TEST_FCOMI 0
56	#endif
57
58	#if defined(__x86_64__)
59	#define FMT64X "%016lx"
60	#define FMTLX "%016lx"
61	#define X86_64_ONLY(x) x
62	#else
63	#define FMT64X "%016" PRIx64
64	#define FMTLX "%08lx"
65	#define X86_64_ONLY(x)
66	#endif
67
68	#ifdef TEST_VM86
69	#include <asm/vm86.h>
70	#endif
71
72	#define xglue(x, y) x ## y
73	#define glue(x, y) xglue(x, y)
74	#define stringify(s) tostring(s)
75	#define tostring(s) #s
76
77	#define CC_C 0x0001
78	#define CC_P 0x0004
79	#define CC_A 0x0010
80	#define CC_Z 0x0040
81	#define CC_S 0x0080
82	#define CC_O 0x0800
83
84	#define __init_call __attribute__ ((unused,__section__ ("initcall")))
85
86	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)
87
88	#if defined(__x86_64__)
89	static inline long i2l(long v)
90	{
91	return v \| ((v ^ 0xabcd) << 32);
92	}
93	#else
94	static inline long i2l(long v)
95	{
96	return v;
97	}
98	#endif
99
100	#define OP add
101	#include "test-i386.h"
102
103	#define OP sub
104	#include "test-i386.h"
105
106	#define OP xor
107	#include "test-i386.h"
108
109	#define OP and
110	#include "test-i386.h"
111
112	#define OP or
113	#include "test-i386.h"
114
115	#define OP cmp
116	#include "test-i386.h"
117
118	#define OP adc
119	#define OP_CC
120	#include "test-i386.h"
121
122	#define OP sbb
123	#define OP_CC
124	#include "test-i386.h"
125
126	#define OP inc
127	#define OP_CC
128	#define OP1
129	#include "test-i386.h"
130
131	#define OP dec
132	#define OP_CC
133	#define OP1
134	#include "test-i386.h"
135
136	#define OP neg
137	#define OP_CC
138	#define OP1
139	#include "test-i386.h"
140
141	#define OP not
142	#define OP_CC
143	#define OP1
144	#include "test-i386.h"
145
146	#undef CC_MASK
147	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O)
148
149	#define OP shl
150	#include "test-i386-shift.h"
151
152	#define OP shr
153	#include "test-i386-shift.h"
154
155	#define OP sar
156	#include "test-i386-shift.h"
157
158	#define OP rol
159	#include "test-i386-shift.h"
160
161	#define OP ror
162	#include "test-i386-shift.h"
163
164	#define OP rcr
165	#define OP_CC
166	#include "test-i386-shift.h"
167
168	#define OP rcl
169	#define OP_CC
170	#include "test-i386-shift.h"
171
172	#define OP shld
173	#define OP_SHIFTD
174	#define OP_NOBYTE
175	#include "test-i386-shift.h"
176
177	#define OP shrd
178	#define OP_SHIFTD
179	#define OP_NOBYTE
180	#include "test-i386-shift.h"
181
182	/* XXX: should be more precise ? */
183	#undef CC_MASK
184	#define CC_MASK (CC_C)
185
186	#define OP bt
187	#define OP_NOBYTE
188	#include "test-i386-shift.h"
189
190	#define OP bts
191	#define OP_NOBYTE
192	#include "test-i386-shift.h"
193
194	#define OP btr
195	#define OP_NOBYTE
196	#include "test-i386-shift.h"
197
198	#define OP btc
199	#define OP_NOBYTE
200	#include "test-i386-shift.h"
201
202	/* lea test (modrm support) */
203	#define TEST_LEAQ(STR)\
204	{\
205	asm("lea " STR ", %0"\
206	: "=r" (res)\
207	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
208	printf("lea %s = " FMTLX "\n", STR, res);\
209	}
210
211	#define TEST_LEA(STR)\
212	{\
213	asm("lea " STR ", %0"\
214	: "=r" (res)\
215	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
216	printf("lea %s = " FMTLX "\n", STR, res);\
217	}
218
219	#define TEST_LEA16(STR)\
220	{\
221	asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
222	: "=wq" (res)\
223	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
224	printf("lea %s = %08lx\n", STR, res);\
225	}
226
227
228	void test_lea(void)
229	{
230	long eax, ebx, ecx, edx, esi, edi, res;
231	eax = i2l(0x0001);
232	ebx = i2l(0x0002);
233	ecx = i2l(0x0004);
234	edx = i2l(0x0008);
235	esi = i2l(0x0010);
236	edi = i2l(0x0020);
237
238	TEST_LEA("0x4000");
239
240	TEST_LEA("(%%eax)");
241	TEST_LEA("(%%ebx)");
242	TEST_LEA("(%%ecx)");
243	TEST_LEA("(%%edx)");
244	TEST_LEA("(%%esi)");
245	TEST_LEA("(%%edi)");
246
247	TEST_LEA("0x40(%%eax)");
248	TEST_LEA("0x40(%%ebx)");
249	TEST_LEA("0x40(%%ecx)");
250	TEST_LEA("0x40(%%edx)");
251	TEST_LEA("0x40(%%esi)");
252	TEST_LEA("0x40(%%edi)");
253
254	TEST_LEA("0x4000(%%eax)");
255	TEST_LEA("0x4000(%%ebx)");
256	TEST_LEA("0x4000(%%ecx)");
257	TEST_LEA("0x4000(%%edx)");
258	TEST_LEA("0x4000(%%esi)");
259	TEST_LEA("0x4000(%%edi)");
260
261	TEST_LEA("(%%eax, %%ecx)");
262	TEST_LEA("(%%ebx, %%edx)");
263	TEST_LEA("(%%ecx, %%ecx)");
264	TEST_LEA("(%%edx, %%ecx)");
265	TEST_LEA("(%%esi, %%ecx)");
266	TEST_LEA("(%%edi, %%ecx)");
267
268	TEST_LEA("0x40(%%eax, %%ecx)");
269	TEST_LEA("0x4000(%%ebx, %%edx)");
270
271	TEST_LEA("(%%ecx, %%ecx, 2)");
272	TEST_LEA("(%%edx, %%ecx, 4)");
273	TEST_LEA("(%%esi, %%ecx, 8)");
274
275	TEST_LEA("(,%%eax, 2)");
276	TEST_LEA("(,%%ebx, 4)");
277	TEST_LEA("(,%%ecx, 8)");
278
279	TEST_LEA("0x40(,%%eax, 2)");
280	TEST_LEA("0x40(,%%ebx, 4)");
281	TEST_LEA("0x40(,%%ecx, 8)");
282
283
284	TEST_LEA("-10(%%ecx, %%ecx, 2)");
285	TEST_LEA("-10(%%edx, %%ecx, 4)");
286	TEST_LEA("-10(%%esi, %%ecx, 8)");
287
288	TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
289	TEST_LEA("0x4000(%%edx, %%ecx, 4)");
290	TEST_LEA("0x4000(%%esi, %%ecx, 8)");
291
292	#if defined(__x86_64__)
293	TEST_LEAQ("0x4000");
294	TEST_LEAQ("0x4000(%%rip)");
295
296	TEST_LEAQ("(%%rax)");
297	TEST_LEAQ("(%%rbx)");
298	TEST_LEAQ("(%%rcx)");
299	TEST_LEAQ("(%%rdx)");
300	TEST_LEAQ("(%%rsi)");
301	TEST_LEAQ("(%%rdi)");
302
303	TEST_LEAQ("0x40(%%rax)");
304	TEST_LEAQ("0x40(%%rbx)");
305	TEST_LEAQ("0x40(%%rcx)");
306	TEST_LEAQ("0x40(%%rdx)");
307	TEST_LEAQ("0x40(%%rsi)");
308	TEST_LEAQ("0x40(%%rdi)");
309
310	TEST_LEAQ("0x4000(%%rax)");
311	TEST_LEAQ("0x4000(%%rbx)");
312	TEST_LEAQ("0x4000(%%rcx)");
313	TEST_LEAQ("0x4000(%%rdx)");
314	TEST_LEAQ("0x4000(%%rsi)");
315	TEST_LEAQ("0x4000(%%rdi)");
316
317	TEST_LEAQ("(%%rax, %%rcx)");
318	TEST_LEAQ("(%%rbx, %%rdx)");
319	TEST_LEAQ("(%%rcx, %%rcx)");
320	TEST_LEAQ("(%%rdx, %%rcx)");
321	TEST_LEAQ("(%%rsi, %%rcx)");
322	TEST_LEAQ("(%%rdi, %%rcx)");
323
324	TEST_LEAQ("0x40(%%rax, %%rcx)");
325	TEST_LEAQ("0x4000(%%rbx, %%rdx)");
326
327	TEST_LEAQ("(%%rcx, %%rcx, 2)");
328	TEST_LEAQ("(%%rdx, %%rcx, 4)");
329	TEST_LEAQ("(%%rsi, %%rcx, 8)");
330
331	TEST_LEAQ("(,%%rax, 2)");
332	TEST_LEAQ("(,%%rbx, 4)");
333	TEST_LEAQ("(,%%rcx, 8)");
334
335	TEST_LEAQ("0x40(,%%rax, 2)");
336	TEST_LEAQ("0x40(,%%rbx, 4)");
337	TEST_LEAQ("0x40(,%%rcx, 8)");
338
339
340	TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
341	TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
342	TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
343
344	TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
345	TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
346	TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
347	#else
348	/* limited 16 bit addressing test */
349	TEST_LEA16("0x4000");
350	TEST_LEA16("(%%bx)");
351	TEST_LEA16("(%%si)");
352	TEST_LEA16("(%%di)");
353	TEST_LEA16("0x40(%%bx)");
354	TEST_LEA16("0x40(%%si)");
355	TEST_LEA16("0x40(%%di)");
356	TEST_LEA16("0x4000(%%bx)");
357	TEST_LEA16("0x4000(%%si)");
358	TEST_LEA16("(%%bx,%%si)");
359	TEST_LEA16("(%%bx,%%di)");
360	TEST_LEA16("0x40(%%bx,%%si)");
361	TEST_LEA16("0x40(%%bx,%%di)");
362	TEST_LEA16("0x4000(%%bx,%%si)");
363	TEST_LEA16("0x4000(%%bx,%%di)");
364	#endif
365	}
366
367	#define TEST_JCC(JCC, v1, v2)\
368	{\
369	int res;\
370	asm("movl $1, %0\n\t"\
371	"cmpl %2, %1\n\t"\
372	"j" JCC " 1f\n\t"\
373	"movl $0, %0\n\t"\
374	"1:\n\t"\
375	: "=r" (res)\
376	: "r" (v1), "r" (v2));\
377	printf("%-10s %d\n", "j" JCC, res);\
378	\
379	asm("movl $0, %0\n\t"\
380	"cmpl %2, %1\n\t"\
381	"set" JCC " %b0\n\t"\
382	: "=r" (res)\
383	: "r" (v1), "r" (v2));\
384	printf("%-10s %d\n", "set" JCC, res);\
385	if (TEST_CMOV) {\
386	long val = i2l(1);\
387	long res = i2l(0x12345678);\
388	X86_64_ONLY(\
389	asm("cmpl %2, %1\n\t"\
390	"cmov" JCC "q %3, %0\n\t"\
391	: "=r" (res)\
392	: "r" (v1), "r" (v2), "m" (val), "0" (res));\
393	printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
394	asm("cmpl %2, %1\n\t"\
395	"cmov" JCC "l %k3, %k0\n\t"\
396	: "=r" (res)\
397	: "r" (v1), "r" (v2), "m" (val), "0" (res));\
398	printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
399	asm("cmpl %2, %1\n\t"\
400	"cmov" JCC "w %w3, %w0\n\t"\
401	: "=r" (res)\
402	: "r" (v1), "r" (v2), "r" (1), "0" (res));\
403	printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
404	} \
405	}
406
407	/* various jump tests */
408	void test_jcc(void)
409	{
410	TEST_JCC("ne", 1, 1);
411	TEST_JCC("ne", 1, 0);
412
413	TEST_JCC("e", 1, 1);
414	TEST_JCC("e", 1, 0);
415
416	TEST_JCC("l", 1, 1);
417	TEST_JCC("l", 1, 0);
418	TEST_JCC("l", 1, -1);
419
420	TEST_JCC("le", 1, 1);
421	TEST_JCC("le", 1, 0);
422	TEST_JCC("le", 1, -1);
423
424	TEST_JCC("ge", 1, 1);
425	TEST_JCC("ge", 1, 0);
426	TEST_JCC("ge", -1, 1);
427
428	TEST_JCC("g", 1, 1);
429	TEST_JCC("g", 1, 0);
430	TEST_JCC("g", 1, -1);
431
432	TEST_JCC("b", 1, 1);
433	TEST_JCC("b", 1, 0);
434	TEST_JCC("b", 1, -1);
435
436	TEST_JCC("be", 1, 1);
437	TEST_JCC("be", 1, 0);
438	TEST_JCC("be", 1, -1);
439
440	TEST_JCC("ae", 1, 1);
441	TEST_JCC("ae", 1, 0);
442	TEST_JCC("ae", 1, -1);
443
444	TEST_JCC("a", 1, 1);
445	TEST_JCC("a", 1, 0);
446	TEST_JCC("a", 1, -1);
447
448
449	TEST_JCC("p", 1, 1);
450	TEST_JCC("p", 1, 0);
451
452	TEST_JCC("np", 1, 1);
453	TEST_JCC("np", 1, 0);
454
455	TEST_JCC("o", 0x7fffffff, 0);
456	TEST_JCC("o", 0x7fffffff, -1);
457
458	TEST_JCC("no", 0x7fffffff, 0);
459	TEST_JCC("no", 0x7fffffff, -1);
460
461	TEST_JCC("s", 0, 1);
462	TEST_JCC("s", 0, -1);
463	TEST_JCC("s", 0, 0);
464
465	TEST_JCC("ns", 0, 1);
466	TEST_JCC("ns", 0, -1);
467	TEST_JCC("ns", 0, 0);
468	}
469
470	#undef CC_MASK
471	#ifdef TEST_P4_FLAGS
472	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)
473	#else
474	#define CC_MASK (CC_O \| CC_C)
475	#endif
476
477	#define OP mul
478	#include "test-i386-muldiv.h"
479
480	#define OP imul
481	#include "test-i386-muldiv.h"
482
483	void test_imulw2(long op0, long op1)
484	{
485	long res, s1, s0, flags;
486	s0 = op0;
487	s1 = op1;
488	res = s0;
489	flags = 0;
490	asm volatile ("push %4\n\t"
491	"popf\n\t"
492	"imulw %w2, %w0\n\t"
493	"pushf\n\t"
494	"pop %1\n\t"
495	: "=q" (res), "=g" (flags)
496	: "q" (s1), "0" (res), "1" (flags));
497	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
498	"imulw", s0, s1, res, flags & CC_MASK);
499	}
500
501	void test_imull2(long op0, long op1)
502	{
503	long res, s1, s0, flags;
504	s0 = op0;
505	s1 = op1;
506	res = s0;
507	flags = 0;
508	asm volatile ("push %4\n\t"
509	"popf\n\t"
510	"imull %k2, %k0\n\t"
511	"pushf\n\t"
512	"pop %1\n\t"
513	: "=q" (res), "=g" (flags)
514	: "q" (s1), "0" (res), "1" (flags));
515	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
516	"imull", s0, s1, res, flags & CC_MASK);
517	}
518
519	#if defined(__x86_64__)
520	void test_imulq2(long op0, long op1)
521	{
522	long res, s1, s0, flags;
523	s0 = op0;
524	s1 = op1;
525	res = s0;
526	flags = 0;
527	asm volatile ("push %4\n\t"
528	"popf\n\t"
529	"imulq %2, %0\n\t"
530	"pushf\n\t"
531	"pop %1\n\t"
532	: "=q" (res), "=g" (flags)
533	: "q" (s1), "0" (res), "1" (flags));
534	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
535	"imulq", s0, s1, res, flags & CC_MASK);
536	}
537	#endif
538
539	#define TEST_IMUL_IM(size, rsize, op0, op1)\
540	{\
541	long res, flags, s1;\
542	flags = 0;\
543	res = 0;\
544	s1 = op1;\
545	asm volatile ("push %3\n\t"\
546	"popf\n\t"\
547	"imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
548	"pushf\n\t"\
549	"pop %1\n\t"\
550	: "=r" (res), "=g" (flags)\
551	: "r" (s1), "1" (flags), "0" (res));\
552	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
553	"imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
554	}
555
556
557	#undef CC_MASK
558	#define CC_MASK (0)
559
560	#define OP div
561	#include "test-i386-muldiv.h"
562
563	#define OP idiv
564	#include "test-i386-muldiv.h"
565
566	void test_mul(void)
567	{
568	test_imulb(0x1234561d, 4);
569	test_imulb(3, -4);
570	test_imulb(0x80, 0x80);
571	test_imulb(0x10, 0x10);
572
573	test_imulw(0, 0x1234001d, 45);
574	test_imulw(0, 23, -45);
575	test_imulw(0, 0x8000, 0x8000);
576	test_imulw(0, 0x100, 0x100);
577
578	test_imull(0, 0x1234001d, 45);
579	test_imull(0, 23, -45);
580	test_imull(0, 0x80000000, 0x80000000);
581	test_imull(0, 0x10000, 0x10000);
582
583	test_mulb(0x1234561d, 4);
584	test_mulb(3, -4);
585	test_mulb(0x80, 0x80);
586	test_mulb(0x10, 0x10);
587
588	test_mulw(0, 0x1234001d, 45);
589	test_mulw(0, 23, -45);
590	test_mulw(0, 0x8000, 0x8000);
591	test_mulw(0, 0x100, 0x100);
592
593	test_mull(0, 0x1234001d, 45);
594	test_mull(0, 23, -45);
595	test_mull(0, 0x80000000, 0x80000000);
596	test_mull(0, 0x10000, 0x10000);
597
598	test_imulw2(0x1234001d, 45);
599	test_imulw2(23, -45);
600	test_imulw2(0x8000, 0x8000);
601	test_imulw2(0x100, 0x100);
602
603	test_imull2(0x1234001d, 45);
604	test_imull2(23, -45);
605	test_imull2(0x80000000, 0x80000000);
606	test_imull2(0x10000, 0x10000);
607
608	TEST_IMUL_IM("w", "w", 45, 0x1234);
609	TEST_IMUL_IM("w", "w", -45, 23);
610	TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
611	TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
612
613	TEST_IMUL_IM("l", "k", 45, 0x1234);
614	TEST_IMUL_IM("l", "k", -45, 23);
615	TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
616	TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
617
618	test_idivb(0x12341678, 0x127e);
619	test_idivb(0x43210123, -5);
620	test_idivb(0x12340004, -1);
621
622	test_idivw(0, 0x12345678, 12347);
623	test_idivw(0, -23223, -45);
624	test_idivw(0, 0x12348000, -1);
625	test_idivw(0x12343, 0x12345678, 0x81238567);
626
627	test_idivl(0, 0x12345678, 12347);
628	test_idivl(0, -233223, -45);
629	test_idivl(0, 0x80000000, -1);
630	test_idivl(0x12343, 0x12345678, 0x81234567);
631
632	test_divb(0x12341678, 0x127e);
633	test_divb(0x43210123, -5);
634	test_divb(0x12340004, -1);
635
636	test_divw(0, 0x12345678, 12347);
637	test_divw(0, -23223, -45);
638	test_divw(0, 0x12348000, -1);
639	test_divw(0x12343, 0x12345678, 0x81238567);
640
641	test_divl(0, 0x12345678, 12347);
642	test_divl(0, -233223, -45);
643	test_divl(0, 0x80000000, -1);
644	test_divl(0x12343, 0x12345678, 0x81234567);
645
646	#if defined(__x86_64__)
647	test_imulq(0, 0x1234001d1234001d, 45);
648	test_imulq(0, 23, -45);
649	test_imulq(0, 0x8000000000000000, 0x8000000000000000);
650	test_imulq(0, 0x100000000, 0x100000000);
651
652	test_mulq(0, 0x1234001d1234001d, 45);
653	test_mulq(0, 23, -45);
654	test_mulq(0, 0x8000000000000000, 0x8000000000000000);
655	test_mulq(0, 0x100000000, 0x100000000);
656
657	test_imulq2(0x1234001d1234001d, 45);
658	test_imulq2(23, -45);
659	test_imulq2(0x8000000000000000, 0x8000000000000000);
660	test_imulq2(0x100000000, 0x100000000);
661
662	TEST_IMUL_IM("q", "", 45, 0x12341234);
663	TEST_IMUL_IM("q", "", -45, 23);
664	TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
665	TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
666
667	test_idivq(0, 0x12345678abcdef, 12347);
668	test_idivq(0, -233223, -45);
669	test_idivq(0, 0x8000000000000000, -1);
670	test_idivq(0x12343, 0x12345678, 0x81234567);
671
672	test_divq(0, 0x12345678abcdef, 12347);
673	test_divq(0, -233223, -45);
674	test_divq(0, 0x8000000000000000, -1);
675	test_divq(0x12343, 0x12345678, 0x81234567);
676	#endif
677	}
678
679	#define TEST_BSX(op, size, op0)\
680	{\
681	long res, val, resz;\
682	val = op0;\
683	asm("xor %1, %1\n"\
684	"mov $0x12345678, %0\n"\
685	#op " %" size "2, %" size "0 ; setz %b1" \
686	: "=r" (res), "=q" (resz)\
687	: "g" (val));\
688	printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
689	}
690
691	void test_bsx(void)
692	{
693	TEST_BSX(bsrw, "w", 0);
694	TEST_BSX(bsrw, "w", 0x12340128);
695	TEST_BSX(bsfw, "w", 0);
696	TEST_BSX(bsfw, "w", 0x12340128);
697	TEST_BSX(bsrl, "k", 0);
698	TEST_BSX(bsrl, "k", 0x00340128);
699	TEST_BSX(bsfl, "k", 0);
700	TEST_BSX(bsfl, "k", 0x00340128);
701	#if defined(__x86_64__)
702	TEST_BSX(bsrq, "", 0);
703	TEST_BSX(bsrq, "", 0x003401281234);
704	TEST_BSX(bsfq, "", 0);
705	TEST_BSX(bsfq, "", 0x003401281234);
706	#endif
707	}
708
709	/**********************************************/
710
711	union float64u {
712	double d;
713	uint64_t l;
714	};
715
716	union float64u q_nan = { .l = 0xFFF8000000000000 };
717	union float64u s_nan = { .l = 0xFFF0000000000000 };
718
719	void test_fops(double a, double b)
720	{
721	printf("a=%f b=%f a+b=%f\n", a, b, a + b);
722	printf("a=%f b=%f a-b=%f\n", a, b, a - b);
723	printf("a=%f b=%f ab=%f\n", a, b, a b);
724	printf("a=%f b=%f a/b=%f\n", a, b, a / b);
725	printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
726	printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
727	printf("a=%f sin(a)=%f\n", a, sin(a));
728	printf("a=%f cos(a)=%f\n", a, cos(a));
729	printf("a=%f tan(a)=%f\n", a, tan(a));
730	printf("a=%f log(a)=%f\n", a, log(a));
731	printf("a=%f exp(a)=%f\n", a, exp(a));
732	printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
733	/* just to test some op combining */
734	printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
735	printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
736	printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
737
738	}
739
740	void fpu_clear_exceptions(void)
741	{
742	struct __attribute__((packed)) {
743	uint16_t fpuc;
744	uint16_t dummy1;
745	uint16_t fpus;
746	uint16_t dummy2;
747	uint16_t fptag;
748	uint16_t dummy3;
749	uint32_t ignored[4];
750	long double fpregs[8];
751	} float_env32;
752
753	asm volatile ("fnstenv %0\n" : : "m" (float_env32));
754	float_env32.fpus &= ~0x7f;
755	asm volatile ("fldenv %0\n" : : "m" (float_env32));
756	}
757
758	/* XXX: display exception bits when supported */
759	#define FPUS_EMASK 0x0000
760	//#define FPUS_EMASK 0x007f
761
762	void test_fcmp(double a, double b)
763	{
764	long eflags, fpus;
765
766	fpu_clear_exceptions();
767	asm("fcom %2\n"
768	"fstsw %%ax\n"
769	: "=a" (fpus)
770	: "t" (a), "u" (b));
771	printf("fcom(%f %f)=%04lx \n",
772	a, b, fpus & (0x4500 \| FPUS_EMASK));
773	fpu_clear_exceptions();
774	asm("fucom %2\n"
775	"fstsw %%ax\n"
776	: "=a" (fpus)
777	: "t" (a), "u" (b));
778	printf("fucom(%f %f)=%04lx\n",
779	a, b, fpus & (0x4500 \| FPUS_EMASK));
780	if (TEST_FCOMI) {
781	/* test f(u)comi instruction */
782	fpu_clear_exceptions();
783	asm("fcomi %3, %2\n"
784	"fstsw %%ax\n"
785	"pushf\n"
786	"pop %0\n"
787	: "=r" (eflags), "=a" (fpus)
788	: "t" (a), "u" (b));
789	printf("fcomi(%f %f)=%04lx %02lx\n",
790	a, b, fpus & FPUS_EMASK, eflags & (CC_Z \| CC_P \| CC_C));
791	fpu_clear_exceptions();
792	asm("fucomi %3, %2\n"
793	"fstsw %%ax\n"
794	"pushf\n"
795	"pop %0\n"
796	: "=r" (eflags), "=a" (fpus)
797	: "t" (a), "u" (b));
798	printf("fucomi(%f %f)=%04lx %02lx\n",
799	a, b, fpus & FPUS_EMASK, eflags & (CC_Z \| CC_P \| CC_C));
800	}
801	fpu_clear_exceptions();
802	asm volatile("fxam\n"
803	"fstsw %%ax\n"
804	: "=a" (fpus)
805	: "t" (a));
806	printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
807	fpu_clear_exceptions();
808	}
809
810	void test_fcvt(double a)
811	{
812	float fa;
813	long double la;
814	int16_t fpuc;
815	int i;
816	int64_t lla;
817	int ia;
818	int16_t wa;
819	double ra;
820
821	fa = a;
822	la = a;
823	printf("(float)%f = %f\n", a, fa);
824	printf("(long double)%f = %Lf\n", a, la);
825	printf("a=" FMT64X "\n", (uint64_t )&a);
826	printf("la=" FMT64X " %04x\n", (uint64_t )&la,
827	(unsigned short )((char *)(&la) + 8));
828
829	/* test all roundings */
830	asm volatile ("fstcw %0" : "=m" (fpuc));
831	for(i=0;i<4;i++) {
832	asm volatile ("fldcw %0" : : "m" ((fpuc & ~0x0c00) \| (i << 10)));
833	asm volatile ("fist %0" : "=m" (wa) : "t" (a));
834	asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
835	asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
836	asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
837	asm volatile ("fldcw %0" : : "m" (fpuc));
838	printf("(short)a = %d\n", wa);
839	printf("(int)a = %d\n", ia);
840	printf("(int64_t)a = " FMT64X "\n", lla);
841	printf("rint(a) = %f\n", ra);
842	}
843	}
844
845	#define TEST(N) \
846	asm("fld" #N : "=t" (a)); \
847	printf("fld" #N "= %f\n", a);
848
849	void test_fconst(void)
850	{
851	double a;
852	TEST(1);
853	TEST(l2t);
854	TEST(l2e);
855	TEST(pi);
856	TEST(lg2);
857	TEST(ln2);
858	TEST(z);
859	}
860
861	void test_fbcd(double a)
862	{
863	unsigned short bcd[5];
864	double b;
865
866	asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
867	asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
868	printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
869	a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
870	}
871
872	#define TEST_ENV(env, save, restore)\
873	{\
874	memset((env), 0xaa, sizeof(*(env)));\
875	for(i=0;i<5;i++)\
876	asm volatile ("fldl %0" : : "m" (dtab[i]));\
877	asm volatile (save " %0\n" : : "m" (*(env)));\
878	asm volatile (restore " %0\n": : "m" (*(env)));\
879	for(i=0;i<5;i++)\
880	asm volatile ("fstpl %0" : "=m" (rtab[i]));\
881	for(i=0;i<5;i++)\
882	printf("res[%d]=%f\n", i, rtab[i]);\
883	printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
884	(env)->fpuc,\
885	(env)->fpus & 0xff00,\
886	(env)->fptag);\
887	}
888
889	void test_fenv(void)
890	{
891	struct __attribute__((packed)) {
892	uint16_t fpuc;
893	uint16_t dummy1;
894	uint16_t fpus;
895	uint16_t dummy2;
896	uint16_t fptag;
897	uint16_t dummy3;
898	uint32_t ignored[4];
899	long double fpregs[8];
900	} float_env32;
901	struct __attribute__((packed)) {
902	uint16_t fpuc;
903	uint16_t fpus;
904	uint16_t fptag;
905	uint16_t ignored[4];
906	long double fpregs[8];
907	} float_env16;
908	double dtab[8];
909	double rtab[8];
910	int i;
911
912	for(i=0;i<8;i++)
913	dtab[i] = i + 1;
914
915	TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
916	TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
917	TEST_ENV(&float_env32, "fnstenv", "fldenv");
918	TEST_ENV(&float_env32, "fnsave", "frstor");
919
920	/* test for ffree */
921	for(i=0;i<5;i++)
922	asm volatile ("fldl %0" : : "m" (dtab[i]));
923	asm volatile("ffree %st(2)");
924	asm volatile ("fnstenv %0\n" : : "m" (float_env32));
925	asm volatile ("fninit");
926	printf("fptag=%04x\n", float_env32.fptag);
927	}
928
929
930	#define TEST_FCMOV(a, b, eflags, CC)\
931	{\
932	double res;\
933	asm("push %3\n"\
934	"popf\n"\
935	"fcmov" CC " %2, %0\n"\
936	: "=t" (res)\
937	: "0" (a), "u" (b), "g" (eflags));\
938	printf("fcmov%s eflags=0x%04lx-> %f\n", \
939	CC, (long)eflags, res);\
940	}
941
942	void test_fcmov(void)
943	{
944	double a, b;
945	long eflags, i;
946
947	a = 1.0;
948	b = 2.0;
949	for(i = 0; i < 4; i++) {
950	eflags = 0;
951	if (i & 1)
952	eflags \|= CC_C;
953	if (i & 2)
954	eflags \|= CC_Z;
955	TEST_FCMOV(a, b, eflags, "b");
956	TEST_FCMOV(a, b, eflags, "e");
957	TEST_FCMOV(a, b, eflags, "be");
958	TEST_FCMOV(a, b, eflags, "nb");
959	TEST_FCMOV(a, b, eflags, "ne");
960	TEST_FCMOV(a, b, eflags, "nbe");
961	}
962	TEST_FCMOV(a, b, 0, "u");
963	TEST_FCMOV(a, b, CC_P, "u");
964	TEST_FCMOV(a, b, 0, "nu");
965	TEST_FCMOV(a, b, CC_P, "nu");
966	}
967
968	void test_floats(void)
969	{
970	test_fops(2, 3);
971	test_fops(1.4, -5);
972	test_fcmp(2, -1);
973	test_fcmp(2, 2);
974	test_fcmp(2, 3);
975	test_fcmp(2, q_nan.d);
976	test_fcmp(q_nan.d, -1);
977	test_fcmp(-1.0/0.0, -1);
978	test_fcmp(1.0/0.0, -1);
979	test_fcvt(0.5);
980	test_fcvt(-0.5);
981	test_fcvt(1.0/7.0);
982	test_fcvt(-1.0/9.0);
983	test_fcvt(32768);
984	test_fcvt(-1e20);
985	test_fcvt(-1.0/0.0);
986	test_fcvt(1.0/0.0);
987	test_fcvt(q_nan.d);
988	test_fconst();
989	test_fbcd(1234567890123456);
990	test_fbcd(-123451234567890);
991	test_fenv();
992	if (TEST_CMOV) {
993	test_fcmov();
994	}
995	}
996
997	/**********************************************/
998	#if !defined(__x86_64__)
999
1000	#define TEST_BCD(op, op0, cc_in, cc_mask)\
1001	{\
1002	int res, flags;\
1003	res = op0;\
1004	flags = cc_in;\
1005	asm ("push %3\n\t"\
1006	"popf\n\t"\
1007	#op "\n\t"\
1008	"pushf\n\t"\
1009	"pop %1\n\t"\
1010	: "=a" (res), "=g" (flags)\
1011	: "0" (res), "1" (flags));\
1012	printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",\
1013	#op, op0, res, cc_in, flags & cc_mask);\
1014	}
1015
1016	void test_bcd(void)
1017	{
1018	TEST_BCD(daa, 0x12340503, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1019	TEST_BCD(daa, 0x12340506, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1020	TEST_BCD(daa, 0x12340507, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1021	TEST_BCD(daa, 0x12340559, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1022	TEST_BCD(daa, 0x12340560, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1023	TEST_BCD(daa, 0x1234059f, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1024	TEST_BCD(daa, 0x123405a0, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1025	TEST_BCD(daa, 0x12340503, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1026	TEST_BCD(daa, 0x12340506, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1027	TEST_BCD(daa, 0x12340503, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1028	TEST_BCD(daa, 0x12340506, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1029	TEST_BCD(daa, 0x12340503, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1030	TEST_BCD(daa, 0x12340506, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1031
1032	TEST_BCD(das, 0x12340503, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1033	TEST_BCD(das, 0x12340506, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1034	TEST_BCD(das, 0x12340507, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1035	TEST_BCD(das, 0x12340559, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1036	TEST_BCD(das, 0x12340560, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1037	TEST_BCD(das, 0x1234059f, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1038	TEST_BCD(das, 0x123405a0, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1039	TEST_BCD(das, 0x12340503, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1040	TEST_BCD(das, 0x12340506, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1041	TEST_BCD(das, 0x12340503, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1042	TEST_BCD(das, 0x12340506, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1043	TEST_BCD(das, 0x12340503, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1044	TEST_BCD(das, 0x12340506, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1045
1046	TEST_BCD(aaa, 0x12340205, CC_A, (CC_C \| CC_A));
1047	TEST_BCD(aaa, 0x12340306, CC_A, (CC_C \| CC_A));
1048	TEST_BCD(aaa, 0x1234040a, CC_A, (CC_C \| CC_A));
1049	TEST_BCD(aaa, 0x123405fa, CC_A, (CC_C \| CC_A));
1050	TEST_BCD(aaa, 0x12340205, 0, (CC_C \| CC_A));
1051	TEST_BCD(aaa, 0x12340306, 0, (CC_C \| CC_A));
1052	TEST_BCD(aaa, 0x1234040a, 0, (CC_C \| CC_A));
1053	TEST_BCD(aaa, 0x123405fa, 0, (CC_C \| CC_A));
1054
1055	TEST_BCD(aas, 0x12340205, CC_A, (CC_C \| CC_A));
1056	TEST_BCD(aas, 0x12340306, CC_A, (CC_C \| CC_A));
1057	TEST_BCD(aas, 0x1234040a, CC_A, (CC_C \| CC_A));
1058	TEST_BCD(aas, 0x123405fa, CC_A, (CC_C \| CC_A));
1059	TEST_BCD(aas, 0x12340205, 0, (CC_C \| CC_A));
1060	TEST_BCD(aas, 0x12340306, 0, (CC_C \| CC_A));
1061	TEST_BCD(aas, 0x1234040a, 0, (CC_C \| CC_A));
1062	TEST_BCD(aas, 0x123405fa, 0, (CC_C \| CC_A));
1063
1064	TEST_BCD(aam, 0x12340547, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));
1065	TEST_BCD(aad, 0x12340407, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));
1066	}
1067	#endif
1068
1069	#define TEST_XCHG(op, size, opconst)\
1070	{\
1071	long op0, op1;\
1072	op0 = i2l(0x12345678);\
1073	op1 = i2l(0xfbca7654);\
1074	asm(#op " %" size "0, %" size "1" \
1075	: "=q" (op0), opconst (op1) \
1076	: "0" (op0), "1" (op1));\
1077	printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
1078	#op, op0, op1);\
1079	}
1080
1081	#define TEST_CMPXCHG(op, size, opconst, eax)\
1082	{\
1083	long op0, op1, op2;\
1084	op0 = i2l(0x12345678);\
1085	op1 = i2l(0xfbca7654);\
1086	op2 = i2l(eax);\
1087	asm(#op " %" size "0, %" size "1" \
1088	: "=q" (op0), opconst (op1) \
1089	: "0" (op0), "1" (op1), "a" (op2));\
1090	printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
1091	#op, op2, op0, op1);\
1092	}
1093
1094	void test_xchg(void)
1095	{
1096	#if defined(__x86_64__)
1097	TEST_XCHG(xchgq, "", "=q");
1098	#endif
1099	TEST_XCHG(xchgl, "k", "=q");
1100	TEST_XCHG(xchgw, "w", "=q");
1101	TEST_XCHG(xchgb, "b", "=q");
1102
1103	#if defined(__x86_64__)
1104	TEST_XCHG(xchgq, "", "=m");
1105	#endif
1106	TEST_XCHG(xchgl, "k", "=m");
1107	TEST_XCHG(xchgw, "w", "=m");
1108	TEST_XCHG(xchgb, "b", "=m");
1109
1110	#if defined(__x86_64__)
1111	TEST_XCHG(xaddq, "", "=q");
1112	#endif
1113	TEST_XCHG(xaddl, "k", "=q");
1114	TEST_XCHG(xaddw, "w", "=q");
1115	TEST_XCHG(xaddb, "b", "=q");
1116
1117	{
1118	int res;
1119	res = 0x12345678;
1120	asm("xaddl %1, %0" : "=r" (res) : "0" (res));
1121	printf("xaddl same res=%08x\n", res);
1122	}
1123
1124	#if defined(__x86_64__)
1125	TEST_XCHG(xaddq, "", "=m");
1126	#endif
1127	TEST_XCHG(xaddl, "k", "=m");
1128	TEST_XCHG(xaddw, "w", "=m");
1129	TEST_XCHG(xaddb, "b", "=m");
1130
1131	#if defined(__x86_64__)
1132	TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfbca7654);
1133	#endif
1134	TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfbca7654);
1135	TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfbca7654);
1136	TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfbca7654);
1137
1138	#if defined(__x86_64__)
1139	TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfffefdfc);
1140	#endif
1141	TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfffefdfc);
1142	TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfffefdfc);
1143	TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfffefdfc);
1144
1145	#if defined(__x86_64__)
1146	TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfbca7654);
1147	#endif
1148	TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfbca7654);
1149	TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfbca7654);
1150	TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfbca7654);
1151
1152	#if defined(__x86_64__)
1153	TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfffefdfc);
1154	#endif
1155	TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfffefdfc);
1156	TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfffefdfc);
1157	TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfffefdfc);
1158
1159	{
1160	uint64_t op0, op1, op2;
1161	long i, eflags;
1162
1163	for(i = 0; i < 2; i++) {
1164	op0 = 0x123456789abcd;
1165	if (i == 0)
1166	op1 = 0xfbca765423456;
1167	else
1168	op1 = op0;
1169	op2 = 0x6532432432434;
1170	asm("cmpxchg8b %1\n"
1171	"pushf\n"
1172	"pop %2\n"
1173	: "=A" (op0), "=m" (op1), "=g" (eflags)
1174	: "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
1175	printf("cmpxchg8b: op0=" FMT64X " op1=" FMT64X " CC=%02lx\n",
1176	op0, op1, eflags & CC_Z);
1177	}
1178	}
1179	}
1180
1181	#ifdef TEST_SEGS
1182	/**********************************************/
1183	/* segmentation tests */
1184
1185	#include <asm/ldt.h>
1186	#include <linux/unistd.h>
1187	#include <linux/version.h>
1188
1189	_syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount)
1190
1191	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
1192	#define modify_ldt_ldt_s user_desc
1193	#endif
1194
1195	#define MK_SEL(n) (((n) << 3) \| 7)
1196
1197	uint8_t seg_data1[4096];
1198	uint8_t seg_data2[4096];
1199
1200	#define TEST_LR(op, size, seg, mask)\
1201	{\
1202	int res, res2;\
1203	res = 0x12345678;\
1204	asm (op " %" size "2, %" size "0\n" \
1205	"movl $0, %1\n"\
1206	"jnz 1f\n"\
1207	"movl $1, %1\n"\
1208	"1:\n"\
1209	: "=r" (res), "=r" (res2) : "m" (seg), "0" (res));\
1210	printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
1211	}
1212
1213	/* NOTE: we use Linux modify_ldt syscall */
1214	void test_segs(void)
1215	{
1216	struct modify_ldt_ldt_s ldt;
1217	long long ldt_table[3];
1218	int res, res2;
1219	char tmp;
1220	struct {
1221	uint32_t offset;
1222	uint16_t seg;
1223	} __attribute__((packed)) segoff;
1224
1225	ldt.entry_number = 1;
1226	ldt.base_addr = (unsigned long)&seg_data1;
1227	ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1228	ldt.seg_32bit = 1;
1229	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1230	ldt.read_exec_only = 0;
1231	ldt.limit_in_pages = 1;
1232	ldt.seg_not_present = 0;
1233	ldt.useable = 1;
1234	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1235
1236	ldt.entry_number = 2;
1237	ldt.base_addr = (unsigned long)&seg_data2;
1238	ldt.limit = (sizeof(seg_data2) + 0xfff) >> 12;
1239	ldt.seg_32bit = 1;
1240	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1241	ldt.read_exec_only = 0;
1242	ldt.limit_in_pages = 1;
1243	ldt.seg_not_present = 0;
1244	ldt.useable = 1;
1245	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1246
1247	modify_ldt(0, &ldt_table, sizeof(ldt_table)); /* read ldt entries */
1248	#if 0
1249	{
1250	int i;
1251	for(i=0;i<3;i++)
1252	printf("%d: %016Lx\n", i, ldt_table[i]);
1253	}
1254	#endif
1255	/* do some tests with fs or gs */
1256	asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1257
1258	seg_data1[1] = 0xaa;
1259	seg_data2[1] = 0x55;
1260
1261	asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
1262	printf("FS[1] = %02x\n", res);
1263
1264	asm volatile ("pushl %%gs\n"
1265	"movl %1, %%gs\n"
1266	"gs movzbl 0x1, %0\n"
1267	"popl %%gs\n"
1268	: "=r" (res)
1269	: "r" (MK_SEL(2)));
1270	printf("GS[1] = %02x\n", res);
1271
1272	/* tests with ds/ss (implicit segment case) */
1273	tmp = 0xa5;
1274	asm volatile ("pushl %%ebp\n\t"
1275	"pushl %%ds\n\t"
1276	"movl %2, %%ds\n\t"
1277	"movl %3, %%ebp\n\t"
1278	"movzbl 0x1, %0\n\t"
1279	"movzbl (%%ebp), %1\n\t"
1280	"popl %%ds\n\t"
1281	"popl %%ebp\n\t"
1282	: "=r" (res), "=r" (res2)
1283	: "r" (MK_SEL(1)), "r" (&tmp));
1284	printf("DS[1] = %02x\n", res);
1285	printf("SS[tmp] = %02x\n", res2);
1286
1287	segoff.seg = MK_SEL(2);
1288	segoff.offset = 0xabcdef12;
1289	asm volatile("lfs %2, %0\n\t"
1290	"movl %%fs, %1\n\t"
1291	: "=r" (res), "=g" (res2)
1292	: "m" (segoff));
1293	printf("FS:reg = %04x:%08x\n", res2, res);
1294
1295	TEST_LR("larw", "w", MK_SEL(2), 0x0100);
1296	TEST_LR("larl", "", MK_SEL(2), 0x0100);
1297	TEST_LR("lslw", "w", MK_SEL(2), 0);
1298	TEST_LR("lsll", "", MK_SEL(2), 0);
1299
1300	TEST_LR("larw", "w", 0xfff8, 0);
1301	TEST_LR("larl", "", 0xfff8, 0);
1302	TEST_LR("lslw", "w", 0xfff8, 0);
1303	TEST_LR("lsll", "", 0xfff8, 0);
1304	}
1305
1306	/* 16 bit code test */
1307	extern char code16_start, code16_end;
1308	extern char code16_func1;
1309	extern char code16_func2;
1310	extern char code16_func3;
1311
1312	void test_code16(void)
1313	{
1314	struct modify_ldt_ldt_s ldt;
1315	int res, res2;
1316
1317	/* build a code segment */
1318	ldt.entry_number = 1;
1319	ldt.base_addr = (unsigned long)&code16_start;
1320	ldt.limit = &code16_end - &code16_start;
1321	ldt.seg_32bit = 0;
1322	ldt.contents = MODIFY_LDT_CONTENTS_CODE;
1323	ldt.read_exec_only = 0;
1324	ldt.limit_in_pages = 0;
1325	ldt.seg_not_present = 0;
1326	ldt.useable = 1;
1327	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1328
1329	/* call the first function */
1330	asm volatile ("lcall %1, %2"
1331	: "=a" (res)
1332	: "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc");
1333	printf("func1() = 0x%08x\n", res);
1334	asm volatile ("lcall %2, %3"
1335	: "=a" (res), "=c" (res2)
1336	: "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc");
1337	printf("func2() = 0x%08x spdec=%d\n", res, res2);
1338	asm volatile ("lcall %1, %2"
1339	: "=a" (res)
1340	: "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc");
1341	printf("func3() = 0x%08x\n", res);
1342	}
1343	#endif
1344
1345	#if defined(__x86_64__)
1346	asm(".globl func_lret\n"
1347	"func_lret:\n"
1348	"movl $0x87654641, %eax\n"
1349	"lretq\n");
1350	#else
1351	asm(".globl func_lret\n"
1352	"func_lret:\n"
1353	"movl $0x87654321, %eax\n"
1354	"lret\n"
1355
1356	".globl func_iret\n"
1357	"func_iret:\n"
1358	"movl $0xabcd4321, %eax\n"
1359	"iret\n");
1360	#endif
1361
1362	extern char func_lret;
1363	extern char func_iret;
1364
1365	void test_misc(void)
1366	{
1367	char table[256];
1368	long res, i;
1369
1370	for(i=0;i<256;i++) table[i] = 256 - i;
1371	res = 0x12345678;
1372	asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
1373	printf("xlat: EAX=" FMTLX "\n", res);
1374
1375	#if defined(__x86_64__)
1376	{
1377	static struct __attribute__((packed)) {
1378	uint32_t offset;
1379	uint16_t seg;
1380	} desc;
1381	long cs_sel;
1382
1383	asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
1384
1385	asm volatile ("push %1\n"
1386	"call func_lret\n"
1387	: "=a" (res)
1388	: "r" (cs_sel) : "memory", "cc");
1389	printf("func_lret=" FMTLX "\n", res);
1390
1391	/* NOTE: we assume that &func_lret < 4GB */
1392	desc.offset = (long)&func_lret;
1393	desc.seg = cs_sel;
1394
1395	asm volatile ("xor %%rax, %%rax\n"
1396	"rex64 lcall %1\n"
1397	: "=a" (res)
1398	: "m" (desc)
1399	: "memory", "cc");
1400	printf("func_lret2=" FMTLX "\n", res);
1401
1402	asm volatile ("push %2\n"
1403	"mov $ 1f, %%rax\n"
1404	"push %%rax\n"
1405	"ljmp %1\n"
1406	"1:\n"
1407	: "=a" (res)
1408	: "m" (desc), "b" (cs_sel)
1409	: "memory", "cc");
1410	printf("func_lret3=" FMTLX "\n", res);
1411	}
1412	#else
1413	asm volatile ("push %%cs ; call %1"
1414	: "=a" (res)
1415	: "m" (func_lret): "memory", "cc");
1416	printf("func_lret=" FMTLX "\n", res);
1417
1418	asm volatile ("pushf ; push %%cs ; call %1"
1419	: "=a" (res)
1420	: "m" (func_iret): "memory", "cc");
1421	printf("func_iret=" FMTLX "\n", res);
1422	#endif
1423
1424	#if defined(__x86_64__)
1425	/* specific popl test */
1426	asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
1427	: "=g" (res));
1428	printf("popl esp=" FMTLX "\n", res);
1429	#else
1430	/* specific popl test */
1431	asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
1432	: "=g" (res));
1433	printf("popl esp=" FMTLX "\n", res);
1434
1435	/* specific popw test */
1436	asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
1437	: "=g" (res));
1438	printf("popw esp=" FMTLX "\n", res);
1439	#endif
1440	}
1441
1442	uint8_t str_buffer[4096];
1443
1444	#define TEST_STRING1(OP, size, DF, REP)\
1445	{\
1446	long esi, edi, eax, ecx, eflags;\
1447	\
1448	esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
1449	edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
1450	eax = i2l(0x12345678);\
1451	ecx = 17;\
1452	\
1453	asm volatile ("push $0\n\t"\
1454	"popf\n\t"\
1455	DF "\n\t"\
1456	REP #OP size "\n\t"\
1457	"cld\n\t"\
1458	"pushf\n\t"\
1459	"pop %4\n\t"\
1460	: "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
1461	: "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
1462	printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
1463	REP #OP size, esi, edi, eax, ecx,\
1464	(int)(eflags & (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)));\
1465	}
1466
1467	#define TEST_STRING(OP, REP)\
1468	TEST_STRING1(OP, "b", "", REP);\
1469	TEST_STRING1(OP, "w", "", REP);\
1470	TEST_STRING1(OP, "l", "", REP);\
1471	X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
1472	TEST_STRING1(OP, "b", "std", REP);\
1473	TEST_STRING1(OP, "w", "std", REP);\
1474	TEST_STRING1(OP, "l", "std", REP);\
1475	X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
1476
1477	void test_string(void)
1478	{
1479	int i;
1480	for(i = 0;i < sizeof(str_buffer); i++)
1481	str_buffer[i] = i + 0x56;
1482	TEST_STRING(stos, "");
1483	TEST_STRING(stos, "rep ");
1484	TEST_STRING(lods, ""); /* to verify stos */
1485	TEST_STRING(lods, "rep ");
1486	TEST_STRING(movs, "");
1487	TEST_STRING(movs, "rep ");
1488	TEST_STRING(lods, ""); /* to verify stos */
1489
1490	/* XXX: better tests */
1491	TEST_STRING(scas, "");
1492	TEST_STRING(scas, "repz ");
1493	TEST_STRING(scas, "repnz ");
1494	TEST_STRING(cmps, "");
1495	TEST_STRING(cmps, "repz ");
1496	TEST_STRING(cmps, "repnz ");
1497	}
1498
1499	#ifdef TEST_VM86
1500	/* VM86 test */
1501
1502	static inline void set_bit(uint8_t *a, unsigned int bit)
1503	{
1504	a[bit / 8] \|= (1 << (bit % 8));
1505	}
1506
1507	static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
1508	{
1509	return (uint8_t *)((seg << 4) + (reg & 0xffff));
1510	}
1511
1512	static inline void pushw(struct vm86_regs *r, int val)
1513	{
1514	r->esp = (r->esp & ~0xffff) \| ((r->esp - 2) & 0xffff);
1515	(uint16_t )seg_to_linear(r->ss, r->esp) = val;
1516	}
1517
1518	#undef __syscall_return
1519	#define __syscall_return(type, res) \
1520	do { \
1521	return (type) (res); \
1522	} while (0)
1523
1524	_syscall2(int, vm86, int, func, struct vm86plus_struct *, v86)
1525
1526	extern char vm86_code_start;
1527	extern char vm86_code_end;
1528
1529	#define VM86_CODE_CS 0x100
1530	#define VM86_CODE_IP 0x100
1531
1532	void test_vm86(void)
1533	{
1534	struct vm86plus_struct ctx;
1535	struct vm86_regs *r;
1536	uint8_t *vm86_mem;
1537	int seg, ret;
1538
1539	vm86_mem = mmap((void *)0x00000000, 0x110000,
1540	PROT_WRITE \| PROT_READ \| PROT_EXEC,
1541	MAP_FIXED \| MAP_ANON \| MAP_PRIVATE, -1, 0);
1542	if (vm86_mem == MAP_FAILED) {
1543	printf("ERROR: could not map vm86 memory");
1544	return;
1545	}
1546	memset(&ctx, 0, sizeof(ctx));
1547
1548	/* init basic registers */
1549	r = &ctx.regs;
1550	r->eip = VM86_CODE_IP;
1551	r->esp = 0xfffe;
1552	seg = VM86_CODE_CS;
1553	r->cs = seg;
1554	r->ss = seg;
1555	r->ds = seg;
1556	r->es = seg;
1557	r->fs = seg;
1558	r->gs = seg;
1559	r->eflags = VIF_MASK;
1560
1561	/* move code to proper address. We use the same layout as a .com
1562	dos program. */
1563	memcpy(vm86_mem + (VM86_CODE_CS << 4) + VM86_CODE_IP,
1564	&vm86_code_start, &vm86_code_end - &vm86_code_start);
1565
1566	/* mark int 0x21 as being emulated */
1567	set_bit((uint8_t *)&ctx.int_revectored, 0x21);
1568
1569	for(;;) {
1570	ret = vm86(VM86_ENTER, &ctx);
1571	switch(VM86_TYPE(ret)) {
1572	case VM86_INTx:
1573	{
1574	int int_num, ah, v;
1575
1576	int_num = VM86_ARG(ret);
1577	if (int_num != 0x21)
1578	goto unknown_int;
1579	ah = (r->eax >> 8) & 0xff;
1580	switch(ah) {
1581	case 0x00: /* exit */
1582	goto the_end;
1583	case 0x02: /* write char */
1584	{
1585	uint8_t c = r->edx;
1586	putchar(c);
1587	}
1588	break;
1589	case 0x09: /* write string */
1590	{
1591	uint8_t c, *ptr;
1592	ptr = seg_to_linear(r->ds, r->edx);
1593	for(;;) {
1594	c = *ptr++;
1595	if (c == '$')
1596	break;
1597	putchar(c);
1598	}
1599	r->eax = (r->eax & ~0xff) \| '$';
1600	}
1601	break;
1602	case 0xff: /* extension: write eflags number in edx */
1603	v = (int)r->edx;
1604	#ifndef LINUX_VM86_IOPL_FIX
1605	v &= ~0x3000;
1606	#endif
1607	printf("%08x\n", v);
1608	break;
1609	default:
1610	unknown_int:
1611	printf("unsupported int 0x%02x\n", int_num);
1612	goto the_end;
1613	}
1614	}
1615	break;
1616	case VM86_SIGNAL:
1617	/* a signal came, we just ignore that */
1618	break;
1619	case VM86_STI:
1620	break;
1621	default:
1622	printf("ERROR: unhandled vm86 return code (0x%x)\n", ret);
1623	goto the_end;
1624	}
1625	}
1626	the_end:
1627	printf("VM86 end\n");
1628	munmap(vm86_mem, 0x110000);
1629	}
1630	#endif
1631
1632	/* exception tests */
1633	#if defined(__i386__) && !defined(REG_EAX)
1634	#define REG_EAX EAX
1635	#define REG_EBX EBX
1636	#define REG_ECX ECX
1637	#define REG_EDX EDX
1638	#define REG_ESI ESI
1639	#define REG_EDI EDI
1640	#define REG_EBP EBP
1641	#define REG_ESP ESP
1642	#define REG_EIP EIP
1643	#define REG_EFL EFL
1644	#define REG_TRAPNO TRAPNO
1645	#define REG_ERR ERR
1646	#endif
1647
1648	#if defined(__x86_64__)
1649	#define REG_EIP REG_RIP
1650	#endif
1651
1652	jmp_buf jmp_env;
1653	int v1;
1654	int tab[2];
1655
1656	void sig_handler(int sig, siginfo_t info, void puc)
1657	{
1658	struct ucontext *uc = puc;
1659
1660	printf("si_signo=%d si_errno=%d si_code=%d",
1661	info->si_signo, info->si_errno, info->si_code);
1662	printf(" si_addr=0x%08lx",
1663	(unsigned long)info->si_addr);
1664	printf("\n");
1665
1666	printf("trapno=" FMTLX " err=" FMTLX,
1667	(long)uc->uc_mcontext.gregs[REG_TRAPNO],
1668	(long)uc->uc_mcontext.gregs[REG_ERR]);
1669	printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
1670	printf("\n");
1671	longjmp(jmp_env, 1);
1672	}
1673
1674	void test_exceptions(void)
1675	{
1676	struct sigaction act;
1677	volatile int val;
1678
1679	act.sa_sigaction = sig_handler;
1680	sigemptyset(&act.sa_mask);
1681	act.sa_flags = SA_SIGINFO \| SA_NODEFER;
1682	sigaction(SIGFPE, &act, NULL);
1683	sigaction(SIGILL, &act, NULL);
1684	sigaction(SIGSEGV, &act, NULL);
1685	sigaction(SIGBUS, &act, NULL);
1686	sigaction(SIGTRAP, &act, NULL);
1687
1688	/* test division by zero reporting */
1689	printf("DIVZ exception:\n");
1690	if (setjmp(jmp_env) == 0) {
1691	/* now divide by zero */
1692	v1 = 0;
1693	v1 = 2 / v1;
1694	}
1695
1696	#if !defined(__x86_64__)
1697	printf("BOUND exception:\n");
1698	if (setjmp(jmp_env) == 0) {
1699	/* bound exception */
1700	tab[0] = 1;
1701	tab[1] = 10;
1702	asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
1703	}
1704	#endif
1705
1706	#ifdef TEST_SEGS
1707	printf("segment exceptions:\n");
1708	if (setjmp(jmp_env) == 0) {
1709	/* load an invalid segment */
1710	asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) \| 1));
1711	}
1712	if (setjmp(jmp_env) == 0) {
1713	/* null data segment is valid */
1714	asm volatile ("movl %0, %%fs" : : "r" (3));
1715	/* null stack segment */
1716	asm volatile ("movl %0, %%ss" : : "r" (3));
1717	}
1718
1719	{
1720	struct modify_ldt_ldt_s ldt;
1721	ldt.entry_number = 1;
1722	ldt.base_addr = (unsigned long)&seg_data1;
1723	ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1724	ldt.seg_32bit = 1;
1725	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1726	ldt.read_exec_only = 0;
1727	ldt.limit_in_pages = 1;
1728	ldt.seg_not_present = 1;
1729	ldt.useable = 1;
1730	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1731
1732	if (setjmp(jmp_env) == 0) {
1733	/* segment not present */
1734	asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1735	}
1736	}
1737	#endif
1738
1739	/* test SEGV reporting */
1740	printf("PF exception:\n");
1741	if (setjmp(jmp_env) == 0) {
1742	val = 1;
1743	/* we add a nop to test a weird PC retrieval case */
1744	asm volatile ("nop");
1745	/* now store in an invalid address */
1746	(char )0x1234 = 1;
1747	}
1748
1749	/* test SEGV reporting */
1750	printf("PF exception:\n");
1751	if (setjmp(jmp_env) == 0) {
1752	val = 1;
1753	/* read from an invalid address */
1754	v1 = (char )0x1234;
1755	}
1756
1757	/* test illegal instruction reporting */
1758	printf("UD2 exception:\n");
1759	if (setjmp(jmp_env) == 0) {
1760	/* now execute an invalid instruction */
1761	asm volatile("ud2");
1762	}
1763	printf("lock nop exception:\n");
1764	if (setjmp(jmp_env) == 0) {
1765	/* now execute an invalid instruction */
1766	asm volatile("lock nop");
1767	}
1768
1769	printf("INT exception:\n");
1770	if (setjmp(jmp_env) == 0) {
1771	asm volatile ("int $0xfd");
1772	}
1773	if (setjmp(jmp_env) == 0) {
1774	asm volatile ("int $0x01");
1775	}
1776	if (setjmp(jmp_env) == 0) {
1777	asm volatile (".byte 0xcd, 0x03");
1778	}
1779	if (setjmp(jmp_env) == 0) {
1780	asm volatile ("int $0x04");
1781	}
1782	if (setjmp(jmp_env) == 0) {
1783	asm volatile ("int $0x05");
1784	}
1785
1786	printf("INT3 exception:\n");
1787	if (setjmp(jmp_env) == 0) {
1788	asm volatile ("int3");
1789	}
1790
1791	printf("CLI exception:\n");
1792	if (setjmp(jmp_env) == 0) {
1793	asm volatile ("cli");
1794	}
1795
1796	printf("STI exception:\n");
1797	if (setjmp(jmp_env) == 0) {
1798	asm volatile ("cli");
1799	}
1800
1801	#if !defined(__x86_64__)
1802	printf("INTO exception:\n");
1803	if (setjmp(jmp_env) == 0) {
1804	/* overflow exception */
1805	asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
1806	}
1807	#endif
1808
1809	printf("OUTB exception:\n");
1810	if (setjmp(jmp_env) == 0) {
1811	asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
1812	}
1813
1814	printf("INB exception:\n");
1815	if (setjmp(jmp_env) == 0) {
1816	asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
1817	}
1818
1819	printf("REP OUTSB exception:\n");
1820	if (setjmp(jmp_env) == 0) {
1821	asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
1822	}
1823
1824	printf("REP INSB exception:\n");
1825	if (setjmp(jmp_env) == 0) {
1826	asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
1827	}
1828
1829	printf("HLT exception:\n");
1830	if (setjmp(jmp_env) == 0) {
1831	asm volatile ("hlt");
1832	}
1833
1834	printf("single step exception:\n");
1835	val = 0;
1836	if (setjmp(jmp_env) == 0) {
1837	asm volatile ("pushf\n"
1838	"orl $0x00100, (%%esp)\n"
1839	"popf\n"
1840	"movl $0xabcd, %0\n"
1841	"movl $0x0, %0\n" : "=m" (val) : : "cc", "memory");
1842	}
1843	printf("val=0x%x\n", val);
1844	}
1845
1846	#if !defined(__x86_64__)
1847	/* specific precise single step test */
1848	void sig_trap_handler(int sig, siginfo_t info, void puc)
1849	{
1850	struct ucontext *uc = puc;
1851	printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
1852	}
1853
1854	const uint8_t sstep_buf1[4] = { 1, 2, 3, 4};
1855	uint8_t sstep_buf2[4];
1856
1857	void test_single_step(void)
1858	{
1859	struct sigaction act;
1860	volatile int val;
1861	int i;
1862
1863	val = 0;
1864	act.sa_sigaction = sig_trap_handler;
1865	sigemptyset(&act.sa_mask);
1866	act.sa_flags = SA_SIGINFO;
1867	sigaction(SIGTRAP, &act, NULL);
1868	asm volatile ("pushf\n"
1869	"orl $0x00100, (%%esp)\n"
1870	"popf\n"
1871	"movl $0xabcd, %0\n"
1872
1873	/* jmp test */
1874	"movl $3, %%ecx\n"
1875	"1:\n"
1876	"addl $1, %0\n"
1877	"decl %%ecx\n"
1878	"jnz 1b\n"
1879
1880	/* movsb: the single step should stop at each movsb iteration */
1881	"movl $sstep_buf1, %%esi\n"
1882	"movl $sstep_buf2, %%edi\n"
1883	"movl $0, %%ecx\n"
1884	"rep movsb\n"
1885	"movl $3, %%ecx\n"
1886	"rep movsb\n"
1887	"movl $1, %%ecx\n"
1888	"rep movsb\n"
1889
1890	/* cmpsb: the single step should stop at each cmpsb iteration */
1891	"movl $sstep_buf1, %%esi\n"
1892	"movl $sstep_buf2, %%edi\n"
1893	"movl $0, %%ecx\n"
1894	"rep cmpsb\n"
1895	"movl $4, %%ecx\n"
1896	"rep cmpsb\n"
1897
1898	/* getpid() syscall: single step should skip one
1899	instruction */
1900	"movl $20, %%eax\n"
1901	"int $0x80\n"
1902	"movl $0, %%eax\n"
1903
1904	/* when modifying SS, trace is not done on the next
1905	instruction */
1906	"movl %%ss, %%ecx\n"
1907	"movl %%ecx, %%ss\n"
1908	"addl $1, %0\n"
1909	"movl $1, %%eax\n"
1910	"movl %%ecx, %%ss\n"
1911	"jmp 1f\n"
1912	"addl $1, %0\n"
1913	"1:\n"
1914	"movl $1, %%eax\n"
1915	"pushl %%ecx\n"
1916	"popl %%ss\n"
1917	"addl $1, %0\n"
1918	"movl $1, %%eax\n"
1919
1920	"pushf\n"
1921	"andl $~0x00100, (%%esp)\n"
1922	"popf\n"
1923	: "=m" (val)
1924	:
1925	: "cc", "memory", "eax", "ecx", "esi", "edi");
1926	printf("val=%d\n", val);
1927	for(i = 0; i < 4; i++)
1928	printf("sstep_buf2[%d] = %d\n", i, sstep_buf2[i]);
1929	}
1930
1931	/* self modifying code test */
1932	uint8_t code[] = {
1933	0xb8, 0x1, 0x00, 0x00, 0x00, /* movl $1, %eax */
1934	0xc3, /* ret */
1935	};
1936
1937	asm("smc_code2:\n"
1938	"movl 4(%esp), %eax\n"
1939	"movl %eax, smc_patch_addr2 + 1\n"
1940	"nop\n"
1941	"nop\n"
1942	"nop\n"
1943	"nop\n"
1944	"nop\n"
1945	"nop\n"
1946	"nop\n"
1947	"nop\n"
1948	"smc_patch_addr2:\n"
1949	"movl $1, %eax\n"
1950	"ret\n");
1951
1952	typedef int FuncType(void);
1953	extern int smc_code2(int);
1954	void test_self_modifying_code(void)
1955	{
1956	int i;
1957
1958	printf("self modifying code:\n");
1959	printf("func1 = 0x%x\n", ((FuncType *)code)());
1960	for(i = 2; i <= 4; i++) {
1961	code[1] = i;
1962	printf("func%d = 0x%x\n", i, ((FuncType *)code)());
1963	}
1964
1965	/* more difficult test : the modified code is just after the
1966	modifying instruction. It is forbidden in Intel specs, but it
1967	is used by old DOS programs */
1968	for(i = 2; i <= 4; i++) {
1969	printf("smc_code2(%d) = %d\n", i, smc_code2(i));
1970	}
1971	}
1972	#endif
1973
1974	long enter_stack[4096];
1975
1976	#if defined(__x86_64__)
1977	#define RSP "%%rsp"
1978	#define RBP "%%rbp"
1979	#else
1980	#define RSP "%%esp"
1981	#define RBP "%%ebp"
1982	#endif
1983
1984	#define TEST_ENTER(size, stack_type, level)\
1985	{\
1986	long esp_save, esp_val, ebp_val, ebp_save, i;\
1987	stack_type ptr, stack_end, *stack_ptr;\
1988	memset(enter_stack, 0, sizeof(enter_stack));\
1989	stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
1990	ebp_val = (long)stack_ptr;\
1991	for(i=1;i<=32;i++)\
1992	*--stack_ptr = i;\
1993	esp_val = (long)stack_ptr;\
1994	asm("mov " RSP ", %[esp_save]\n"\
1995	"mov " RBP ", %[ebp_save]\n"\
1996	"mov %[esp_val], " RSP "\n"\
1997	"mov %[ebp_val], " RBP "\n"\
1998	"enter" size " $8, $" #level "\n"\
1999	"mov " RSP ", %[esp_val]\n"\
2000	"mov " RBP ", %[ebp_val]\n"\
2001	"mov %[esp_save], " RSP "\n"\
2002	"mov %[ebp_save], " RBP "\n"\
2003	: [esp_save] "=r" (esp_save),\
2004	[ebp_save] "=r" (ebp_save),\
2005	[esp_val] "=r" (esp_val),\
2006	[ebp_val] "=r" (ebp_val)\
2007	: "[esp_val]" (esp_val),\
2008	"[ebp_val]" (ebp_val));\
2009	printf("level=%d:\n", level);\
2010	printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
2011	printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
2012	for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
2013	printf(FMTLX "\n", (long)ptr[0]);\
2014	}
2015
2016	static void test_enter(void)
2017	{
2018	#if defined(__x86_64__)
2019	TEST_ENTER("q", uint64_t, 0);
2020	TEST_ENTER("q", uint64_t, 1);
2021	TEST_ENTER("q", uint64_t, 2);
2022	TEST_ENTER("q", uint64_t, 31);
2023	#else
2024	TEST_ENTER("l", uint32_t, 0);
2025	TEST_ENTER("l", uint32_t, 1);
2026	TEST_ENTER("l", uint32_t, 2);
2027	TEST_ENTER("l", uint32_t, 31);
2028	#endif
2029
2030	TEST_ENTER("w", uint16_t, 0);
2031	TEST_ENTER("w", uint16_t, 1);
2032	TEST_ENTER("w", uint16_t, 2);
2033	TEST_ENTER("w", uint16_t, 31);
2034	}
2035
2036	#ifdef TEST_SSE
2037
2038	typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
2039	typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
2040
2041	typedef union {
2042	double d[2];
2043	float s[4];
2044	uint32_t l[4];
2045	uint64_t q[2];
2046	__m128 dq;
2047	} XMMReg;
2048
2049	static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
2050	{ 0x456723c698694873, 0xdc515cff944a58ec },
2051	{ 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
2052	{ 0x007c62c2085427f8, 0x231be9e8cde7438d },
2053	{ 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
2054	};
2055
2056	#define SSE_OP(op)\
2057	{\
2058	asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2059	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2060	#op,\
2061	a.q[1], a.q[0],\
2062	b.q[1], b.q[0],\
2063	r.q[1], r.q[0]);\
2064	}
2065
2066	#define SSE_OP2(op)\
2067	{\
2068	int i;\
2069	for(i=0;i<2;i++) {\
2070	a.q[0] = test_values[2*i][0];\
2071	a.q[1] = test_values[2*i][1];\
2072	b.q[0] = test_values[2*i+1][0];\
2073	b.q[1] = test_values[2*i+1][1];\
2074	SSE_OP(op);\
2075	}\
2076	}
2077
2078	#define MMX_OP2(op)\
2079	{\
2080	int i;\
2081	for(i=0;i<2;i++) {\
2082	a.q[0] = test_values[2*i][0];\
2083	b.q[0] = test_values[2*i+1][0];\
2084	asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
2085	printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
2086	#op,\
2087	a.q[0],\
2088	b.q[0],\
2089	r.q[0]);\
2090	}\
2091	SSE_OP2(op);\
2092	}
2093
2094	#define SHUF_OP(op, ib)\
2095	{\
2096	a.q[0] = test_values[0][0];\
2097	a.q[1] = test_values[0][1];\
2098	b.q[0] = test_values[1][0];\
2099	b.q[1] = test_values[1][1];\
2100	asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2101	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2102	#op,\
2103	a.q[1], a.q[0],\
2104	b.q[1], b.q[0],\
2105	ib,\
2106	r.q[1], r.q[0]);\
2107	}
2108
2109	#define PSHUF_OP(op, ib)\
2110	{\
2111	int i;\
2112	for(i=0;i<2;i++) {\
2113	a.q[0] = test_values[2*i][0];\
2114	a.q[1] = test_values[2*i][1];\
2115	asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2116	printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2117	#op,\
2118	a.q[1], a.q[0],\
2119	ib,\
2120	r.q[1], r.q[0]);\
2121	}\
2122	}
2123
2124	#define SHIFT_IM(op, ib)\
2125	{\
2126	int i;\
2127	for(i=0;i<2;i++) {\
2128	a.q[0] = test_values[2*i][0];\
2129	a.q[1] = test_values[2*i][1];\
2130	asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
2131	printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2132	#op,\
2133	a.q[1], a.q[0],\
2134	ib,\
2135	r.q[1], r.q[0]);\
2136	}\
2137	}
2138
2139	#define SHIFT_OP(op, ib)\
2140	{\
2141	int i;\
2142	SHIFT_IM(op, ib);\
2143	for(i=0;i<2;i++) {\
2144	a.q[0] = test_values[2*i][0];\
2145	a.q[1] = test_values[2*i][1];\
2146	b.q[0] = ib;\
2147	b.q[1] = 0;\
2148	asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2149	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2150	#op,\
2151	a.q[1], a.q[0],\
2152	b.q[1], b.q[0],\
2153	r.q[1], r.q[0]);\
2154	}\
2155	}
2156
2157	#define MOVMSK(op)\
2158	{\
2159	int i, reg;\
2160	for(i=0;i<2;i++) {\
2161	a.q[0] = test_values[2*i][0];\
2162	a.q[1] = test_values[2*i][1];\
2163	asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
2164	printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2165	#op,\
2166	a.q[1], a.q[0],\
2167	reg);\
2168	}\
2169	}
2170
2171	#define SSE_OPS(a) \
2172	SSE_OP(a ## ps);\
2173	SSE_OP(a ## ss);
2174
2175	#define SSE_OPD(a) \
2176	SSE_OP(a ## pd);\
2177	SSE_OP(a ## sd);
2178
2179	#define SSE_COMI(op, field)\
2180	{\
2181	unsigned int eflags;\
2182	XMMReg a, b;\
2183	a.field[0] = a1;\
2184	b.field[0] = b1;\
2185	asm volatile (#op " %2, %1\n"\
2186	"pushf\n"\
2187	"pop %0\n"\
2188	: "=m" (eflags)\
2189	: "x" (a.dq), "x" (b.dq));\
2190	printf("%-9s: a=%f b=%f cc=%04x\n",\
2191	#op, a1, b1,\
2192	eflags & (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));\
2193	}
2194
2195	void test_sse_comi(double a1, double b1)
2196	{
2197	SSE_COMI(ucomiss, s);
2198	SSE_COMI(ucomisd, d);
2199	SSE_COMI(comiss, s);
2200	SSE_COMI(comisd, d);
2201	}
2202
2203	#define CVT_OP_XMM(op)\
2204	{\
2205	asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2206	printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2207	#op,\
2208	a.q[1], a.q[0],\
2209	r.q[1], r.q[0]);\
2210	}
2211
2212	/* Force %xmm0 usage to avoid the case where both register index are 0
2213	to test instruction decoding more extensively */
2214	#define CVT_OP_XMM2MMX(op)\
2215	{\
2216	asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
2217	: "%xmm0");\
2218	printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
2219	#op,\
2220	a.q[1], a.q[0],\
2221	r.q[0]);\
2222	}
2223
2224	#define CVT_OP_MMX2XMM(op)\
2225	{\
2226	asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
2227	printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
2228	#op,\
2229	a.q[0],\
2230	r.q[1], r.q[0]);\
2231	}
2232
2233	#define CVT_OP_REG2XMM(op)\
2234	{\
2235	asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
2236	printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
2237	#op,\
2238	a.l[0],\
2239	r.q[1], r.q[0]);\
2240	}
2241
2242	#define CVT_OP_XMM2REG(op)\
2243	{\
2244	asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
2245	printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2246	#op,\
2247	a.q[1], a.q[0],\
2248	r.l[0]);\
2249	}
2250
2251	struct fpxstate {
2252	uint16_t fpuc;
2253	uint16_t fpus;
2254	uint16_t fptag;
2255	uint16_t fop;
2256	uint32_t fpuip;
2257	uint16_t cs_sel;
2258	uint16_t dummy0;
2259	uint32_t fpudp;
2260	uint16_t ds_sel;
2261	uint16_t dummy1;
2262	uint32_t mxcsr;
2263	uint32_t mxcsr_mask;
2264	uint8_t fpregs1[8 * 16];
2265	uint8_t xmm_regs[8 * 16];
2266	uint8_t dummy2[224];
2267	};
2268
2269	static struct fpxstate fpx_state __attribute__((aligned(16)));
2270	static struct fpxstate fpx_state2 __attribute__((aligned(16)));
2271
2272	void test_fxsave(void)
2273	{
2274	struct fpxstate *fp = &fpx_state;
2275	struct fpxstate *fp2 = &fpx_state2;
2276	int i, nb_xmm;
2277	XMMReg a, b;
2278	a.q[0] = test_values[0][0];
2279	a.q[1] = test_values[0][1];
2280	b.q[0] = test_values[1][0];
2281	b.q[1] = test_values[1][1];
2282
2283	asm("movdqa %2, %%xmm0\n"
2284	"movdqa %3, %%xmm7\n"
2285	#if defined(__x86_64__)
2286	"movdqa %2, %%xmm15\n"
2287	#endif
2288	" fld1\n"
2289	" fldpi\n"
2290	" fldln2\n"
2291	" fxsave %0\n"
2292	" fxrstor %0\n"
2293	" fxsave %1\n"
2294	" fninit\n"
2295	: "=m" ((uint32_t )fp2), "=m" ((uint32_t )fp)
2296	: "m" (a), "m" (b));
2297	printf("fpuc=%04x\n", fp->fpuc);
2298	printf("fpus=%04x\n", fp->fpus);
2299	printf("fptag=%04x\n", fp->fptag);
2300	for(i = 0; i < 3; i++) {
2301	printf("ST%d: " FMT64X " %04x\n",
2302	i,
2303	(uint64_t )&fp->fpregs1[i * 16],
2304	(uint16_t )&fp->fpregs1[i * 16 + 8]);
2305	}
2306	printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
2307	#if defined(__x86_64__)
2308	nb_xmm = 16;
2309	#else
2310	nb_xmm = 8;
2311	#endif
2312	for(i = 0; i < nb_xmm; i++) {
2313	printf("xmm%d: " FMT64X "" FMT64X "\n",
2314	i,
2315	(uint64_t )&fp->xmm_regs[i * 16],
2316	(uint64_t )&fp->xmm_regs[i * 16 + 8]);
2317	}
2318	}
2319
2320	void test_sse(void)
2321	{
2322	XMMReg r, a, b;
2323	int i;
2324
2325	MMX_OP2(punpcklbw);
2326	MMX_OP2(punpcklwd);
2327	MMX_OP2(punpckldq);
2328	MMX_OP2(packsswb);
2329	MMX_OP2(pcmpgtb);
2330	MMX_OP2(pcmpgtw);
2331	MMX_OP2(pcmpgtd);
2332	MMX_OP2(packuswb);
2333	MMX_OP2(punpckhbw);
2334	MMX_OP2(punpckhwd);
2335	MMX_OP2(punpckhdq);
2336	MMX_OP2(packssdw);
2337	MMX_OP2(pcmpeqb);
2338	MMX_OP2(pcmpeqw);
2339	MMX_OP2(pcmpeqd);
2340
2341	MMX_OP2(paddq);
2342	MMX_OP2(pmullw);
2343	MMX_OP2(psubusb);
2344	MMX_OP2(psubusw);
2345	MMX_OP2(pminub);
2346	MMX_OP2(pand);
2347	MMX_OP2(paddusb);
2348	MMX_OP2(paddusw);
2349	MMX_OP2(pmaxub);
2350	MMX_OP2(pandn);
2351
2352	MMX_OP2(pmulhuw);
2353	MMX_OP2(pmulhw);
2354
2355	MMX_OP2(psubsb);
2356	MMX_OP2(psubsw);
2357	MMX_OP2(pminsw);
2358	MMX_OP2(por);
2359	MMX_OP2(paddsb);
2360	MMX_OP2(paddsw);
2361	MMX_OP2(pmaxsw);
2362	MMX_OP2(pxor);
2363	MMX_OP2(pmuludq);
2364	MMX_OP2(pmaddwd);
2365	MMX_OP2(psadbw);
2366	MMX_OP2(psubb);
2367	MMX_OP2(psubw);
2368	MMX_OP2(psubd);
2369	MMX_OP2(psubq);
2370	MMX_OP2(paddb);
2371	MMX_OP2(paddw);
2372	MMX_OP2(paddd);
2373
2374	MMX_OP2(pavgb);
2375	MMX_OP2(pavgw);
2376
2377	asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
2378	printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
2379
2380	asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
2381	printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
2382
2383	a.q[0] = test_values[0][0];
2384	a.q[1] = test_values[0][1];
2385	asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2386	printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2387
2388	asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2389	printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2390
2391	asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2392	printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2393
2394	asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2395	printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2396
2397	{
2398	r.q[0] = -1;
2399	r.q[1] = -1;
2400
2401	a.q[0] = test_values[0][0];
2402	a.q[1] = test_values[0][1];
2403	b.q[0] = test_values[1][0];
2404	b.q[1] = test_values[1][1];
2405	asm volatile("maskmovq %1, %0" :
2406	: "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
2407	: "memory");
2408	printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n",
2409	"maskmov",
2410	r.q[0],
2411	a.q[0],
2412	b.q[0]);
2413	asm volatile("maskmovdqu %1, %0" :
2414	: "x" (a.dq), "x" (b.dq), "D" (&r)
2415	: "memory");
2416	printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n",
2417	"maskmov",
2418	r.q[1], r.q[0],
2419	a.q[1], a.q[0],
2420	b.q[1], b.q[0]);
2421	}
2422
2423	asm volatile ("emms");
2424
2425	SSE_OP2(punpcklqdq);
2426	SSE_OP2(punpckhqdq);
2427	SSE_OP2(andps);
2428	SSE_OP2(andpd);
2429	SSE_OP2(andnps);
2430	SSE_OP2(andnpd);
2431	SSE_OP2(orps);
2432	SSE_OP2(orpd);
2433	SSE_OP2(xorps);
2434	SSE_OP2(xorpd);
2435
2436	SSE_OP2(unpcklps);
2437	SSE_OP2(unpcklpd);
2438	SSE_OP2(unpckhps);
2439	SSE_OP2(unpckhpd);
2440
2441	SHUF_OP(shufps, 0x78);
2442	SHUF_OP(shufpd, 0x02);
2443
2444	PSHUF_OP(pshufd, 0x78);
2445	PSHUF_OP(pshuflw, 0x78);
2446	PSHUF_OP(pshufhw, 0x78);
2447
2448	SHIFT_OP(psrlw, 7);
2449	SHIFT_OP(psrlw, 16);
2450	SHIFT_OP(psraw, 7);
2451	SHIFT_OP(psraw, 16);
2452	SHIFT_OP(psllw, 7);
2453	SHIFT_OP(psllw, 16);
2454
2455	SHIFT_OP(psrld, 7);
2456	SHIFT_OP(psrld, 32);
2457	SHIFT_OP(psrad, 7);
2458	SHIFT_OP(psrad, 32);
2459	SHIFT_OP(pslld, 7);
2460	SHIFT_OP(pslld, 32);
2461
2462	SHIFT_OP(psrlq, 7);
2463	SHIFT_OP(psrlq, 32);
2464	SHIFT_OP(psllq, 7);
2465	SHIFT_OP(psllq, 32);
2466
2467	SHIFT_IM(psrldq, 16);
2468	SHIFT_IM(psrldq, 7);
2469	SHIFT_IM(pslldq, 16);
2470	SHIFT_IM(pslldq, 7);
2471
2472	MOVMSK(movmskps);
2473	MOVMSK(movmskpd);
2474
2475	/* FPU specific ops */
2476
2477	{
2478	uint32_t mxcsr;
2479	asm volatile("stmxcsr %0" : "=m" (mxcsr));
2480	printf("mxcsr=%08x\n", mxcsr & 0x1f80);
2481	asm volatile("ldmxcsr %0" : : "m" (mxcsr));
2482	}
2483
2484	test_sse_comi(2, -1);
2485	test_sse_comi(2, 2);
2486	test_sse_comi(2, 3);
2487	test_sse_comi(2, q_nan.d);
2488	test_sse_comi(q_nan.d, -1);
2489
2490	for(i = 0; i < 2; i++) {
2491	a.s[0] = 2.7;
2492	a.s[1] = 3.4;
2493	a.s[2] = 4;
2494	a.s[3] = -6.3;
2495	b.s[0] = 45.7;
2496	b.s[1] = 353.4;
2497	b.s[2] = 4;
2498	b.s[3] = 56.3;
2499	if (i == 1) {
2500	a.s[0] = q_nan.d;
2501	b.s[3] = q_nan.d;
2502	}
2503
2504	SSE_OPS(add);
2505	SSE_OPS(mul);
2506	SSE_OPS(sub);
2507	SSE_OPS(min);
2508	SSE_OPS(div);
2509	SSE_OPS(max);
2510	SSE_OPS(sqrt);
2511	SSE_OPS(cmpeq);
2512	SSE_OPS(cmplt);
2513	SSE_OPS(cmple);
2514	SSE_OPS(cmpunord);
2515	SSE_OPS(cmpneq);
2516	SSE_OPS(cmpnlt);
2517	SSE_OPS(cmpnle);
2518	SSE_OPS(cmpord);
2519
2520
2521	a.d[0] = 2.7;
2522	a.d[1] = -3.4;
2523	b.d[0] = 45.7;
2524	b.d[1] = -53.4;
2525	if (i == 1) {
2526	a.d[0] = q_nan.d;
2527	b.d[1] = q_nan.d;
2528	}
2529	SSE_OPD(add);
2530	SSE_OPD(mul);
2531	SSE_OPD(sub);
2532	SSE_OPD(min);
2533	SSE_OPD(div);
2534	SSE_OPD(max);
2535	SSE_OPD(sqrt);
2536	SSE_OPD(cmpeq);
2537	SSE_OPD(cmplt);
2538	SSE_OPD(cmple);
2539	SSE_OPD(cmpunord);
2540	SSE_OPD(cmpneq);
2541	SSE_OPD(cmpnlt);
2542	SSE_OPD(cmpnle);
2543	SSE_OPD(cmpord);
2544	}
2545
2546	/* float to float/int */
2547	a.s[0] = 2.7;
2548	a.s[1] = 3.4;
2549	a.s[2] = 4;
2550	a.s[3] = -6.3;
2551	CVT_OP_XMM(cvtps2pd);
2552	CVT_OP_XMM(cvtss2sd);
2553	CVT_OP_XMM2MMX(cvtps2pi);
2554	CVT_OP_XMM2MMX(cvttps2pi);
2555	CVT_OP_XMM2REG(cvtss2si);
2556	CVT_OP_XMM2REG(cvttss2si);
2557	CVT_OP_XMM(cvtps2dq);
2558	CVT_OP_XMM(cvttps2dq);
2559
2560	a.d[0] = 2.6;
2561	a.d[1] = -3.4;
2562	CVT_OP_XMM(cvtpd2ps);
2563	CVT_OP_XMM(cvtsd2ss);
2564	CVT_OP_XMM2MMX(cvtpd2pi);
2565	CVT_OP_XMM2MMX(cvttpd2pi);
2566	CVT_OP_XMM2REG(cvtsd2si);
2567	CVT_OP_XMM2REG(cvttsd2si);
2568	CVT_OP_XMM(cvtpd2dq);
2569	CVT_OP_XMM(cvttpd2dq);
2570
2571	/* sse/mmx moves */
2572	CVT_OP_XMM2MMX(movdq2q);
2573	CVT_OP_MMX2XMM(movq2dq);
2574
2575	/* int to float */
2576	a.l[0] = -6;
2577	a.l[1] = 2;
2578	a.l[2] = 100;
2579	a.l[3] = -60000;
2580	CVT_OP_MMX2XMM(cvtpi2ps);
2581	CVT_OP_MMX2XMM(cvtpi2pd);
2582	CVT_OP_REG2XMM(cvtsi2ss);
2583	CVT_OP_REG2XMM(cvtsi2sd);
2584	CVT_OP_XMM(cvtdq2ps);
2585	CVT_OP_XMM(cvtdq2pd);
2586
2587	/* XXX: test PNI insns */
2588	#if 0
2589	SSE_OP2(movshdup);
2590	#endif
2591	asm volatile ("emms");
2592	}
2593
2594	#endif
2595
2596	extern void *__start_initcall;
2597	extern void *__stop_initcall;
2598
2599
2600	int main(int argc, char **argv)
2601	{
2602	void **ptr;
2603	void (*func)(void);
2604
2605	ptr = &__start_initcall;
2606	while (ptr != &__stop_initcall) {
2607	func = *ptr++;
2608	func();
2609	}
2610	test_bsx();
2611	test_mul();
2612	test_jcc();
2613	test_floats();
2614	#if !defined(__x86_64__)
2615	test_bcd();
2616	#endif
2617	test_xchg();
2618	test_string();
2619	test_misc();
2620	test_lea();
2621	#ifdef TEST_SEGS
2622	test_segs();
2623	test_code16();
2624	#endif
2625	#ifdef TEST_VM86
2626	test_vm86();
2627	#endif
2628	test_exceptions();
2629	#if !defined(__x86_64__)
2630	test_self_modifying_code();
2631	test_single_step();
2632	#endif
2633	test_enter();
2634	#ifdef TEST_SSE
2635	test_sse();
2636	test_fxsave();
2637	#endif
2638	return 0;
2639	}

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source: vbox/trunk/src/recompiler/tests/test-i386.c@ 35487

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