| 1 | /*
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| 2 | * Tiny Code Generator for QEMU
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| 3 | *
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| 4 | * Copyright (c) 2008 Fabrice Bellard
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| 5 | *
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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| 7 | * of this software and associated documentation files (the "Software"), to deal
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| 8 | * in the Software without restriction, including without limitation the rights
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| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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| 10 | * copies of the Software, and to permit persons to whom the Software is
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| 11 | * furnished to do so, subject to the following conditions:
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| 12 | *
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| 13 | * The above copyright notice and this permission notice shall be included in
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| 14 | * all copies or substantial portions of the Software.
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| 15 | *
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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| 22 | * THE SOFTWARE.
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| 23 | */
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| 24 |
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| 25 | /*
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| 26 | * DEF(name, oargs, iargs, cargs, flags)
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| 27 | */
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| 28 |
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| 29 | /* predefined ops */
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| 30 | DEF(end, 0, 0, 0, 0) /* must be kept first */
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| 31 | DEF(nop, 0, 0, 0, 0)
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| 32 | DEF(nop1, 0, 0, 1, 0)
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| 33 | DEF(nop2, 0, 0, 2, 0)
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| 34 | DEF(nop3, 0, 0, 3, 0)
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| 35 | DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
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| 36 |
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| 37 | DEF(discard, 1, 0, 0, 0)
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| 38 |
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| 39 | DEF(set_label, 0, 0, 1, 0)
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| 40 | DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
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| 41 | DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 42 | DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 43 |
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| 44 | DEF(mov_i32, 1, 1, 0, 0)
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| 45 | DEF(movi_i32, 1, 0, 1, 0)
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| 46 | DEF(setcond_i32, 1, 2, 1, 0)
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| 47 | /* load/store */
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| 48 | DEF(ld8u_i32, 1, 1, 1, 0)
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| 49 | DEF(ld8s_i32, 1, 1, 1, 0)
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| 50 | DEF(ld16u_i32, 1, 1, 1, 0)
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| 51 | DEF(ld16s_i32, 1, 1, 1, 0)
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| 52 | DEF(ld_i32, 1, 1, 1, 0)
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| 53 | DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 54 | DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 55 | DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 56 | /* arith */
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| 57 | DEF(add_i32, 1, 2, 0, 0)
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| 58 | DEF(sub_i32, 1, 2, 0, 0)
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| 59 | DEF(mul_i32, 1, 2, 0, 0)
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| 60 | #ifdef TCG_TARGET_HAS_div_i32
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| 61 | DEF(div_i32, 1, 2, 0, 0)
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| 62 | DEF(divu_i32, 1, 2, 0, 0)
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| 63 | DEF(rem_i32, 1, 2, 0, 0)
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| 64 | DEF(remu_i32, 1, 2, 0, 0)
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| 65 | #endif
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| 66 | #ifdef TCG_TARGET_HAS_div2_i32
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| 67 | DEF(div2_i32, 2, 3, 0, 0)
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| 68 | DEF(divu2_i32, 2, 3, 0, 0)
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| 69 | #endif
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| 70 | DEF(and_i32, 1, 2, 0, 0)
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| 71 | DEF(or_i32, 1, 2, 0, 0)
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| 72 | DEF(xor_i32, 1, 2, 0, 0)
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| 73 | /* shifts/rotates */
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| 74 | DEF(shl_i32, 1, 2, 0, 0)
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| 75 | DEF(shr_i32, 1, 2, 0, 0)
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| 76 | DEF(sar_i32, 1, 2, 0, 0)
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| 77 | #ifdef TCG_TARGET_HAS_rot_i32
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| 78 | DEF(rotl_i32, 1, 2, 0, 0)
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| 79 | DEF(rotr_i32, 1, 2, 0, 0)
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| 80 | #endif
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| 81 |
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| 82 | DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 83 | #if TCG_TARGET_REG_BITS == 32
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| 84 | DEF(add2_i32, 2, 4, 0, 0)
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| 85 | DEF(sub2_i32, 2, 4, 0, 0)
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| 86 | DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 87 | DEF(mulu2_i32, 2, 2, 0, 0)
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| 88 | DEF(setcond2_i32, 1, 4, 1, 0)
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| 89 | #endif
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| 90 | #ifdef TCG_TARGET_HAS_ext8s_i32
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| 91 | DEF(ext8s_i32, 1, 1, 0, 0)
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| 92 | #endif
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| 93 | #ifdef TCG_TARGET_HAS_ext16s_i32
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| 94 | DEF(ext16s_i32, 1, 1, 0, 0)
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| 95 | #endif
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| 96 | #ifdef TCG_TARGET_HAS_ext8u_i32
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| 97 | DEF(ext8u_i32, 1, 1, 0, 0)
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| 98 | #endif
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| 99 | #ifdef TCG_TARGET_HAS_ext16u_i32
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| 100 | DEF(ext16u_i32, 1, 1, 0, 0)
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| 101 | #endif
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| 102 | #ifdef TCG_TARGET_HAS_bswap16_i32
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| 103 | DEF(bswap16_i32, 1, 1, 0, 0)
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| 104 | #endif
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| 105 | #ifdef TCG_TARGET_HAS_bswap32_i32
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| 106 | DEF(bswap32_i32, 1, 1, 0, 0)
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| 107 | #endif
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| 108 | #ifdef TCG_TARGET_HAS_not_i32
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| 109 | DEF(not_i32, 1, 1, 0, 0)
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| 110 | #endif
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| 111 | #ifdef TCG_TARGET_HAS_neg_i32
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| 112 | DEF(neg_i32, 1, 1, 0, 0)
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| 113 | #endif
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| 114 | #ifdef TCG_TARGET_HAS_andc_i32
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| 115 | DEF(andc_i32, 1, 2, 0, 0)
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| 116 | #endif
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| 117 | #ifdef TCG_TARGET_HAS_orc_i32
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| 118 | DEF(orc_i32, 1, 2, 0, 0)
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| 119 | #endif
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| 120 | #ifdef TCG_TARGET_HAS_eqv_i32
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| 121 | DEF(eqv_i32, 1, 2, 0, 0)
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| 122 | #endif
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| 123 | #ifdef TCG_TARGET_HAS_nand_i32
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| 124 | DEF(nand_i32, 1, 2, 0, 0)
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| 125 | #endif
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| 126 | #ifdef TCG_TARGET_HAS_nor_i32
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| 127 | DEF(nor_i32, 1, 2, 0, 0)
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| 128 | #endif
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| 129 |
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| 130 | #if TCG_TARGET_REG_BITS == 64
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| 131 | DEF(mov_i64, 1, 1, 0, 0)
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| 132 | DEF(movi_i64, 1, 0, 1, 0)
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| 133 | DEF(setcond_i64, 1, 2, 1, 0)
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| 134 | /* load/store */
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| 135 | DEF(ld8u_i64, 1, 1, 1, 0)
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| 136 | DEF(ld8s_i64, 1, 1, 1, 0)
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| 137 | DEF(ld16u_i64, 1, 1, 1, 0)
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| 138 | DEF(ld16s_i64, 1, 1, 1, 0)
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| 139 | DEF(ld32u_i64, 1, 1, 1, 0)
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| 140 | DEF(ld32s_i64, 1, 1, 1, 0)
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| 141 | DEF(ld_i64, 1, 1, 1, 0)
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| 142 | DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 143 | DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 144 | DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 145 | DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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| 146 | /* arith */
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| 147 | DEF(add_i64, 1, 2, 0, 0)
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| 148 | DEF(sub_i64, 1, 2, 0, 0)
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| 149 | DEF(mul_i64, 1, 2, 0, 0)
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| 150 | #ifdef TCG_TARGET_HAS_div_i64
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| 151 | DEF(div_i64, 1, 2, 0, 0)
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| 152 | DEF(divu_i64, 1, 2, 0, 0)
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| 153 | DEF(rem_i64, 1, 2, 0, 0)
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| 154 | DEF(remu_i64, 1, 2, 0, 0)
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| 155 | #endif
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| 156 | #ifdef TCG_TARGET_HAS_div2_i64
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| 157 | DEF(div2_i64, 2, 3, 0, 0)
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| 158 | DEF(divu2_i64, 2, 3, 0, 0)
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| 159 | #endif
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| 160 | DEF(and_i64, 1, 2, 0, 0)
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| 161 | DEF(or_i64, 1, 2, 0, 0)
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| 162 | DEF(xor_i64, 1, 2, 0, 0)
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| 163 | /* shifts/rotates */
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| 164 | DEF(shl_i64, 1, 2, 0, 0)
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| 165 | DEF(shr_i64, 1, 2, 0, 0)
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| 166 | DEF(sar_i64, 1, 2, 0, 0)
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| 167 | #ifdef TCG_TARGET_HAS_rot_i64
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| 168 | DEF(rotl_i64, 1, 2, 0, 0)
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| 169 | DEF(rotr_i64, 1, 2, 0, 0)
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| 170 | #endif
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| 171 |
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| 172 | DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 173 | #ifdef TCG_TARGET_HAS_ext8s_i64
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| 174 | DEF(ext8s_i64, 1, 1, 0, 0)
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| 175 | #endif
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| 176 | #ifdef TCG_TARGET_HAS_ext16s_i64
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| 177 | DEF(ext16s_i64, 1, 1, 0, 0)
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| 178 | #endif
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| 179 | #ifdef TCG_TARGET_HAS_ext32s_i64
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| 180 | DEF(ext32s_i64, 1, 1, 0, 0)
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| 181 | #endif
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| 182 | #ifdef TCG_TARGET_HAS_ext8u_i64
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| 183 | DEF(ext8u_i64, 1, 1, 0, 0)
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| 184 | #endif
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| 185 | #ifdef TCG_TARGET_HAS_ext16u_i64
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| 186 | DEF(ext16u_i64, 1, 1, 0, 0)
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| 187 | #endif
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| 188 | #ifdef TCG_TARGET_HAS_ext32u_i64
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| 189 | DEF(ext32u_i64, 1, 1, 0, 0)
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| 190 | #endif
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| 191 | #ifdef TCG_TARGET_HAS_bswap16_i64
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| 192 | DEF(bswap16_i64, 1, 1, 0, 0)
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| 193 | #endif
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| 194 | #ifdef TCG_TARGET_HAS_bswap32_i64
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| 195 | DEF(bswap32_i64, 1, 1, 0, 0)
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| 196 | #endif
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| 197 | #ifdef TCG_TARGET_HAS_bswap64_i64
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| 198 | DEF(bswap64_i64, 1, 1, 0, 0)
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| 199 | #endif
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| 200 | #ifdef TCG_TARGET_HAS_not_i64
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| 201 | DEF(not_i64, 1, 1, 0, 0)
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| 202 | #endif
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| 203 | #ifdef TCG_TARGET_HAS_neg_i64
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| 204 | DEF(neg_i64, 1, 1, 0, 0)
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| 205 | #endif
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| 206 | #ifdef TCG_TARGET_HAS_andc_i64
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| 207 | DEF(andc_i64, 1, 2, 0, 0)
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| 208 | #endif
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| 209 | #ifdef TCG_TARGET_HAS_orc_i64
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| 210 | DEF(orc_i64, 1, 2, 0, 0)
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| 211 | #endif
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| 212 | #ifdef TCG_TARGET_HAS_eqv_i64
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| 213 | DEF(eqv_i64, 1, 2, 0, 0)
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| 214 | #endif
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| 215 | #ifdef TCG_TARGET_HAS_nand_i64
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| 216 | DEF(nand_i64, 1, 2, 0, 0)
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| 217 | #endif
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| 218 | #ifdef TCG_TARGET_HAS_nor_i64
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| 219 | DEF(nor_i64, 1, 2, 0, 0)
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| 220 | #endif
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| 221 | #endif
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| 222 |
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| 223 | /* QEMU specific */
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| 224 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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| 225 | DEF(debug_insn_start, 0, 0, 2, 0)
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| 226 | #else
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| 227 | DEF(debug_insn_start, 0, 0, 1, 0)
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| 228 | #endif
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| 229 | DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 230 | DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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| 231 | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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| 232 | constants must be defined */
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| 233 | #if TCG_TARGET_REG_BITS == 32
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| 234 | #if TARGET_LONG_BITS == 32
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| 235 | DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 236 | #else
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| 237 | DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 238 | #endif
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| 239 | #if TARGET_LONG_BITS == 32
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| 240 | DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 241 | #else
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| 242 | DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 243 | #endif
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| 244 | #if TARGET_LONG_BITS == 32
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| 245 | DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 246 | #else
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| 247 | DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 248 | #endif
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| 249 | #if TARGET_LONG_BITS == 32
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| 250 | DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 251 | #else
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| 252 | DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 253 | #endif
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| 254 | #if TARGET_LONG_BITS == 32
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| 255 | DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 256 | #else
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| 257 | DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 258 | #endif
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| 259 | #if TARGET_LONG_BITS == 32
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| 260 | DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 261 | #else
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| 262 | DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 263 | #endif
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| 264 |
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| 265 | #if TARGET_LONG_BITS == 32
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| 266 | DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 267 | #else
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| 268 | DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 269 | #endif
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| 270 | #if TARGET_LONG_BITS == 32
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| 271 | DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 272 | #else
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| 273 | DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 274 | #endif
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| 275 | #if TARGET_LONG_BITS == 32
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| 276 | DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 277 | #else
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| 278 | DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 279 | #endif
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| 280 | #if TARGET_LONG_BITS == 32
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| 281 | DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 282 | #else
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| 283 | DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 284 | #endif
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| 285 |
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| 286 | #else /* TCG_TARGET_REG_BITS == 32 */
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| 287 |
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| 288 | DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 289 | DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 290 | DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 291 | DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 292 | DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 293 | DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 294 | DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 295 | DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 296 |
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| 297 | DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 298 | DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 299 | DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 300 | DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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| 301 |
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| 302 | #endif /* TCG_TARGET_REG_BITS != 32 */
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| 303 |
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| 304 | #undef DEF
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