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source: vbox/trunk/src/recompiler/target-i386/helper.c@ 509

Last change on this file since 509 was 1, checked in by vboxsync, 55 years ago

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1/*
2 * i386 helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "exec.h"
21#ifdef VBOX
22#include <VBox/err.h>
23#endif
24
25//#define DEBUG_PCALL
26
27#if 0
28#define raise_exception_err(a, b)\
29do {\
30 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
31 (raise_exception_err)(a, b);\
32} while (0)
33#endif
34
35const uint8_t parity_table[256] = {
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
44 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
45 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
46 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
58 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
59 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
60 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
61 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
62 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
65 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
66 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
68};
69
70/* modulo 17 table */
71const uint8_t rclw_table[32] = {
72 0, 1, 2, 3, 4, 5, 6, 7,
73 8, 9,10,11,12,13,14,15,
74 16, 0, 1, 2, 3, 4, 5, 6,
75 7, 8, 9,10,11,12,13,14,
76};
77
78/* modulo 9 table */
79const uint8_t rclb_table[32] = {
80 0, 1, 2, 3, 4, 5, 6, 7,
81 8, 0, 1, 2, 3, 4, 5, 6,
82 7, 8, 0, 1, 2, 3, 4, 5,
83 6, 7, 8, 0, 1, 2, 3, 4,
84};
85
86const CPU86_LDouble f15rk[7] =
87{
88 0.00000000000000000000L,
89 1.00000000000000000000L,
90 3.14159265358979323851L, /*pi*/
91 0.30102999566398119523L, /*lg2*/
92 0.69314718055994530943L, /*ln2*/
93 1.44269504088896340739L, /*l2e*/
94 3.32192809488736234781L, /*l2t*/
95};
96
97/* thread support */
98
99spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
100
101void cpu_lock(void)
102{
103 spin_lock(&global_cpu_lock);
104}
105
106void cpu_unlock(void)
107{
108 spin_unlock(&global_cpu_lock);
109}
110
111void cpu_loop_exit(void)
112{
113 /* NOTE: the register at this point must be saved by hand because
114 longjmp restore them */
115 regs_to_env();
116 longjmp(env->jmp_env, 1);
117}
118
119/* return non zero if error */
120static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
121 int selector)
122{
123 SegmentCache *dt;
124 int index;
125 target_ulong ptr;
126
127 if (selector & 0x4)
128 dt = &env->ldt;
129 else
130 dt = &env->gdt;
131 index = selector & ~7;
132 if ((index + 7) > dt->limit)
133 return -1;
134 ptr = dt->base + index;
135 *e1_ptr = ldl_kernel(ptr);
136 *e2_ptr = ldl_kernel(ptr + 4);
137 return 0;
138}
139
140static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
141{
142 unsigned int limit;
143 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
144 if (e2 & DESC_G_MASK)
145 limit = (limit << 12) | 0xfff;
146 return limit;
147}
148
149static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
150{
151 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
152}
153
154static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
155{
156 sc->base = get_seg_base(e1, e2);
157 sc->limit = get_seg_limit(e1, e2);
158 sc->flags = e2;
159}
160
161/* init the segment cache in vm86 mode. */
162static inline void load_seg_vm(int seg, int selector)
163{
164 selector &= 0xffff;
165 cpu_x86_load_seg_cache(env, seg, selector,
166 (selector << 4), 0xffff, 0);
167}
168
169static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
170 uint32_t *esp_ptr, int dpl)
171{
172 int type, index, shift;
173
174#if 0
175 {
176 int i;
177 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
178 for(i=0;i<env->tr.limit;i++) {
179 printf("%02x ", env->tr.base[i]);
180 if ((i & 7) == 7) printf("\n");
181 }
182 printf("\n");
183 }
184#endif
185
186 if (!(env->tr.flags & DESC_P_MASK))
187 cpu_abort(env, "invalid tss");
188 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
189 if ((type & 7) != 1)
190 cpu_abort(env, "invalid tss type %d", type);
191 shift = type >> 3;
192 index = (dpl * 4 + 2) << shift;
193 if (index + (4 << shift) - 1 > env->tr.limit)
194 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
195 if (shift == 0) {
196 *esp_ptr = lduw_kernel(env->tr.base + index);
197 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
198 } else {
199 *esp_ptr = ldl_kernel(env->tr.base + index);
200 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
201 }
202}
203
204/* XXX: merge with load_seg() */
205static void tss_load_seg(int seg_reg, int selector)
206{
207 uint32_t e1, e2;
208 int rpl, dpl, cpl;
209
210 if ((selector & 0xfffc) != 0) {
211 if (load_segment(&e1, &e2, selector) != 0)
212 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
213 if (!(e2 & DESC_S_MASK))
214 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
215 rpl = selector & 3;
216 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
217 cpl = env->hflags & HF_CPL_MASK;
218 if (seg_reg == R_CS) {
219 if (!(e2 & DESC_CS_MASK))
220 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
221 /* XXX: is it correct ? */
222 if (dpl != rpl)
223 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
224 if ((e2 & DESC_C_MASK) && dpl > rpl)
225 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
226
227 } else if (seg_reg == R_SS) {
228 /* SS must be writable data */
229 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
230 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231 if (dpl != cpl || dpl != rpl)
232 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
233 } else {
234 /* not readable code */
235 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
236 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
237 /* if data or non conforming code, checks the rights */
238 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
239 if (dpl < cpl || dpl < rpl)
240 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
241 }
242 }
243 if (!(e2 & DESC_P_MASK))
244 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
245 cpu_x86_load_seg_cache(env, seg_reg, selector,
246 get_seg_base(e1, e2),
247 get_seg_limit(e1, e2),
248 e2);
249 } else {
250 if (seg_reg == R_SS || seg_reg == R_CS)
251 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
252 }
253}
254
255#define SWITCH_TSS_JMP 0
256#define SWITCH_TSS_IRET 1
257#define SWITCH_TSS_CALL 2
258
259/* XXX: restore CPU state in registers (PowerPC case) */
260static void switch_tss(int tss_selector,
261 uint32_t e1, uint32_t e2, int source,
262 uint32_t next_eip)
263{
264 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
265 target_ulong tss_base;
266 uint32_t new_regs[8], new_segs[6];
267 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
268 uint32_t old_eflags, eflags_mask;
269 SegmentCache *dt;
270 int index;
271 target_ulong ptr;
272
273 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
274#ifdef DEBUG_PCALL
275 if (loglevel & CPU_LOG_PCALL)
276 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
277#endif
278
279#if defined(VBOX) && defined(DEBUG)
280 printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
281#endif
282
283 /* if task gate, we read the TSS segment and we load it */
284 if (type == 5) {
285 if (!(e2 & DESC_P_MASK))
286 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
287 tss_selector = e1 >> 16;
288 if (tss_selector & 4)
289 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
290 if (load_segment(&e1, &e2, tss_selector) != 0)
291 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
292 if (e2 & DESC_S_MASK)
293 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
294 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
295 if ((type & 7) != 1)
296 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
297 }
298
299 if (!(e2 & DESC_P_MASK))
300 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
301
302 if (type & 8)
303 tss_limit_max = 103;
304 else
305 tss_limit_max = 43;
306 tss_limit = get_seg_limit(e1, e2);
307 tss_base = get_seg_base(e1, e2);
308 if ((tss_selector & 4) != 0 ||
309 tss_limit < tss_limit_max)
310 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
311 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
312 if (old_type & 8)
313 old_tss_limit_max = 103;
314 else
315 old_tss_limit_max = 43;
316
317 /* read all the registers from the new TSS */
318 if (type & 8) {
319 /* 32 bit */
320 new_cr3 = ldl_kernel(tss_base + 0x1c);
321 new_eip = ldl_kernel(tss_base + 0x20);
322 new_eflags = ldl_kernel(tss_base + 0x24);
323 for(i = 0; i < 8; i++)
324 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
325 for(i = 0; i < 6; i++)
326 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
327 new_ldt = lduw_kernel(tss_base + 0x60);
328 new_trap = ldl_kernel(tss_base + 0x64);
329 } else {
330 /* 16 bit */
331 new_cr3 = 0;
332 new_eip = lduw_kernel(tss_base + 0x0e);
333 new_eflags = lduw_kernel(tss_base + 0x10);
334 for(i = 0; i < 8; i++)
335 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
336 for(i = 0; i < 4; i++)
337 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
338 new_ldt = lduw_kernel(tss_base + 0x2a);
339 new_segs[R_FS] = 0;
340 new_segs[R_GS] = 0;
341 new_trap = 0;
342 }
343
344 /* NOTE: we must avoid memory exceptions during the task switch,
345 so we make dummy accesses before */
346 /* XXX: it can still fail in some cases, so a bigger hack is
347 necessary to valid the TLB after having done the accesses */
348
349 v1 = ldub_kernel(env->tr.base);
350 v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
351 stb_kernel(env->tr.base, v1);
352 stb_kernel(env->tr.base + old_tss_limit_max, v2);
353
354 /* clear busy bit (it is restartable) */
355 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
356 target_ulong ptr;
357 uint32_t e2;
358 ptr = env->gdt.base + (env->tr.selector & ~7);
359 e2 = ldl_kernel(ptr + 4);
360 e2 &= ~DESC_TSS_BUSY_MASK;
361 stl_kernel(ptr + 4, e2);
362 }
363 old_eflags = compute_eflags();
364 if (source == SWITCH_TSS_IRET)
365 old_eflags &= ~NT_MASK;
366
367 /* save the current state in the old TSS */
368 if (type & 8) {
369 /* 32 bit */
370 stl_kernel(env->tr.base + 0x20, next_eip);
371 stl_kernel(env->tr.base + 0x24, old_eflags);
372 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
373 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
374 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
375 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
376 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
377 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
378 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
379 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
380 for(i = 0; i < 6; i++)
381 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
382
383#if defined(VBOX) && defined(DEBUG)
384 printf("TSS 32 bits switch\n");
385 printf("Saving CS=%08X\n", env->segs[R_CS].selector);
386#endif
387
388 } else {
389 /* 16 bit */
390 stw_kernel(env->tr.base + 0x0e, next_eip);
391 stw_kernel(env->tr.base + 0x10, old_eflags);
392 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
393 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
394 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
395 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
396 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
397 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
398 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
399 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
400 for(i = 0; i < 4; i++)
401 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
402 }
403
404 /* now if an exception occurs, it will occurs in the next task
405 context */
406
407 if (source == SWITCH_TSS_CALL) {
408 stw_kernel(tss_base, env->tr.selector);
409 new_eflags |= NT_MASK;
410 }
411
412 /* set busy bit */
413 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
414 target_ulong ptr;
415 uint32_t e2;
416 ptr = env->gdt.base + (tss_selector & ~7);
417 e2 = ldl_kernel(ptr + 4);
418 e2 |= DESC_TSS_BUSY_MASK;
419 stl_kernel(ptr + 4, e2);
420 }
421
422 /* set the new CPU state */
423 /* from this point, any exception which occurs can give problems */
424 env->cr[0] |= CR0_TS_MASK;
425 env->hflags |= HF_TS_MASK;
426 env->tr.selector = tss_selector;
427 env->tr.base = tss_base;
428 env->tr.limit = tss_limit;
429 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
430
431 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
432 cpu_x86_update_cr3(env, new_cr3);
433 }
434
435 /* load all registers without an exception, then reload them with
436 possible exception */
437 env->eip = new_eip;
438 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
439 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
440 if (!(type & 8))
441 eflags_mask &= 0xffff;
442 load_eflags(new_eflags, eflags_mask);
443 /* XXX: what to do in 16 bit case ? */
444 EAX = new_regs[0];
445 ECX = new_regs[1];
446 EDX = new_regs[2];
447 EBX = new_regs[3];
448 ESP = new_regs[4];
449 EBP = new_regs[5];
450 ESI = new_regs[6];
451 EDI = new_regs[7];
452 if (new_eflags & VM_MASK) {
453 for(i = 0; i < 6; i++)
454 load_seg_vm(i, new_segs[i]);
455 /* in vm86, CPL is always 3 */
456 cpu_x86_set_cpl(env, 3);
457 } else {
458 /* CPL is set the RPL of CS */
459 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
460 /* first just selectors as the rest may trigger exceptions */
461 for(i = 0; i < 6; i++)
462 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
463 }
464
465 env->ldt.selector = new_ldt & ~4;
466 env->ldt.base = 0;
467 env->ldt.limit = 0;
468 env->ldt.flags = 0;
469
470 /* load the LDT */
471 if (new_ldt & 4)
472 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
473
474 if ((new_ldt & 0xfffc) != 0) {
475 dt = &env->gdt;
476 index = new_ldt & ~7;
477 if ((index + 7) > dt->limit)
478 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
479 ptr = dt->base + index;
480 e1 = ldl_kernel(ptr);
481 e2 = ldl_kernel(ptr + 4);
482 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
483 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
484 if (!(e2 & DESC_P_MASK))
485 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486 load_seg_cache_raw_dt(&env->ldt, e1, e2);
487 }
488
489 /* load the segments */
490 if (!(new_eflags & VM_MASK)) {
491 tss_load_seg(R_CS, new_segs[R_CS]);
492 tss_load_seg(R_SS, new_segs[R_SS]);
493 tss_load_seg(R_ES, new_segs[R_ES]);
494 tss_load_seg(R_DS, new_segs[R_DS]);
495 tss_load_seg(R_FS, new_segs[R_FS]);
496 tss_load_seg(R_GS, new_segs[R_GS]);
497 }
498
499 /* check that EIP is in the CS segment limits */
500 if (new_eip > env->segs[R_CS].limit) {
501 /* XXX: different exception if CALL ? */
502 raise_exception_err(EXCP0D_GPF, 0);
503 }
504}
505
506/* check if Port I/O is allowed in TSS */
507static inline void check_io(int addr, int size)
508{
509 int io_offset, val, mask;
510
511 /* TSS must be a valid 32 bit one */
512 if (!(env->tr.flags & DESC_P_MASK) ||
513 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
514 env->tr.limit < 103)
515 goto fail;
516 io_offset = lduw_kernel(env->tr.base + 0x66);
517 io_offset += (addr >> 3);
518 /* Note: the check needs two bytes */
519 if ((io_offset + 1) > env->tr.limit)
520 goto fail;
521 val = lduw_kernel(env->tr.base + io_offset);
522 val >>= (addr & 7);
523 mask = (1 << size) - 1;
524 /* all bits must be zero to allow the I/O */
525 if ((val & mask) != 0) {
526 fail:
527 raise_exception_err(EXCP0D_GPF, 0);
528 }
529}
530
531void check_iob_T0(void)
532{
533 check_io(T0, 1);
534}
535
536void check_iow_T0(void)
537{
538 check_io(T0, 2);
539}
540
541void check_iol_T0(void)
542{
543 check_io(T0, 4);
544}
545
546void check_iob_DX(void)
547{
548 check_io(EDX & 0xffff, 1);
549}
550
551void check_iow_DX(void)
552{
553 check_io(EDX & 0xffff, 2);
554}
555
556void check_iol_DX(void)
557{
558 check_io(EDX & 0xffff, 4);
559}
560
561static inline unsigned int get_sp_mask(unsigned int e2)
562{
563 if (e2 & DESC_B_MASK)
564 return 0xffffffff;
565 else
566 return 0xffff;
567}
568
569/* XXX: add a is_user flag to have proper security support */
570#define PUSHW(ssp, sp, sp_mask, val)\
571{\
572 sp -= 2;\
573 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
574}
575
576#define PUSHL(ssp, sp, sp_mask, val)\
577{\
578 sp -= 4;\
579 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
580}
581
582#define POPW(ssp, sp, sp_mask, val)\
583{\
584 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
585 sp += 2;\
586}
587
588#define POPL(ssp, sp, sp_mask, val)\
589{\
590 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
591 sp += 4;\
592}
593
594/* protected mode interrupt */
595static void do_interrupt_protected(int intno, int is_int, int error_code,
596 unsigned int next_eip, int is_hw)
597{
598 SegmentCache *dt;
599 target_ulong ptr, ssp;
600 int type, dpl, selector, ss_dpl, cpl, sp_mask;
601 int has_error_code, new_stack, shift;
602 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
603 uint32_t old_eip;
604
605#ifdef VBOX
606 if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
607 cpu_loop_exit();
608#endif
609
610 has_error_code = 0;
611 if (!is_int && !is_hw) {
612 switch(intno) {
613 case 8:
614 case 10:
615 case 11:
616 case 12:
617 case 13:
618 case 14:
619 case 17:
620 has_error_code = 1;
621 break;
622 }
623 }
624 if (is_int)
625 old_eip = next_eip;
626 else
627 old_eip = env->eip;
628
629 dt = &env->idt;
630 if (intno * 8 + 7 > dt->limit)
631 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
632 ptr = dt->base + intno * 8;
633 e1 = ldl_kernel(ptr);
634 e2 = ldl_kernel(ptr + 4);
635 /* check gate type */
636 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
637 switch(type) {
638 case 5: /* task gate */
639 /* must do that check here to return the correct error code */
640 if (!(e2 & DESC_P_MASK))
641 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
642 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
643 if (has_error_code) {
644 int mask, type;
645 /* push the error code */
646 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
647 shift = type >> 3;
648 if (env->segs[R_SS].flags & DESC_B_MASK)
649 mask = 0xffffffff;
650 else
651 mask = 0xffff;
652 esp = (ESP - (2 << shift)) & mask;
653 ssp = env->segs[R_SS].base + esp;
654 if (shift)
655 stl_kernel(ssp, error_code);
656 else
657 stw_kernel(ssp, error_code);
658 ESP = (esp & mask) | (ESP & ~mask);
659 }
660 return;
661 case 6: /* 286 interrupt gate */
662 case 7: /* 286 trap gate */
663 case 14: /* 386 interrupt gate */
664 case 15: /* 386 trap gate */
665 break;
666 default:
667 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
668 break;
669 }
670 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
671 cpl = env->hflags & HF_CPL_MASK;
672 /* check privledge if software int */
673 if (is_int && dpl < cpl)
674 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
675 /* check valid bit */
676 if (!(e2 & DESC_P_MASK))
677 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
678 selector = e1 >> 16;
679 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
680 if ((selector & 0xfffc) == 0)
681 raise_exception_err(EXCP0D_GPF, 0);
682
683 if (load_segment(&e1, &e2, selector) != 0)
684 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
685 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
686 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
687 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
688 if (dpl > cpl)
689 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
690 if (!(e2 & DESC_P_MASK))
691 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
692 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
693 /* to inner priviledge */
694 get_ss_esp_from_tss(&ss, &esp, dpl);
695 if ((ss & 0xfffc) == 0)
696 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
697 if ((ss & 3) != dpl)
698 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
699 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
700 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
701 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
702 if (ss_dpl != dpl)
703 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
704 if (!(ss_e2 & DESC_S_MASK) ||
705 (ss_e2 & DESC_CS_MASK) ||
706 !(ss_e2 & DESC_W_MASK))
707 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
708 if (!(ss_e2 & DESC_P_MASK))
709 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
710 new_stack = 1;
711 sp_mask = get_sp_mask(ss_e2);
712 ssp = get_seg_base(ss_e1, ss_e2);
713#if defined(VBOX) && defined(DEBUG)
714 printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
715#endif
716 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
717 /* to same priviledge */
718 if (env->eflags & VM_MASK)
719 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
720 new_stack = 0;
721 sp_mask = get_sp_mask(env->segs[R_SS].flags);
722 ssp = env->segs[R_SS].base;
723 esp = ESP;
724 dpl = cpl;
725 } else {
726 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
727 new_stack = 0; /* avoid warning */
728 sp_mask = 0; /* avoid warning */
729 ssp = 0; /* avoid warning */
730 esp = 0; /* avoid warning */
731 }
732
733 shift = type >> 3;
734
735#if 0
736 /* XXX: check that enough room is available */
737 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
738 if (env->eflags & VM_MASK)
739 push_size += 8;
740 push_size <<= shift;
741#endif
742 if (shift == 1) {
743 if (new_stack) {
744 if (env->eflags & VM_MASK) {
745 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
746 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
747 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
748 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
749 }
750 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
751 PUSHL(ssp, esp, sp_mask, ESP);
752 }
753 PUSHL(ssp, esp, sp_mask, compute_eflags());
754 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
755 PUSHL(ssp, esp, sp_mask, old_eip);
756 if (has_error_code) {
757 PUSHL(ssp, esp, sp_mask, error_code);
758 }
759 } else {
760 if (new_stack) {
761 if (env->eflags & VM_MASK) {
762 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
763 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
764 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
765 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
766 }
767 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
768 PUSHW(ssp, esp, sp_mask, ESP);
769 }
770 PUSHW(ssp, esp, sp_mask, compute_eflags());
771 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
772 PUSHW(ssp, esp, sp_mask, old_eip);
773 if (has_error_code) {
774 PUSHW(ssp, esp, sp_mask, error_code);
775 }
776 }
777
778 if (new_stack) {
779 if (env->eflags & VM_MASK) {
780 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
781 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
782 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
783 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
784 }
785 ss = (ss & ~3) | dpl;
786 cpu_x86_load_seg_cache(env, R_SS, ss,
787 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
788 }
789 ESP = (ESP & ~sp_mask) | (esp & sp_mask);
790
791 selector = (selector & ~3) | dpl;
792 cpu_x86_load_seg_cache(env, R_CS, selector,
793 get_seg_base(e1, e2),
794 get_seg_limit(e1, e2),
795 e2);
796 cpu_x86_set_cpl(env, dpl);
797 env->eip = offset;
798
799 /* interrupt gate clear IF mask */
800 if ((type & 1) == 0) {
801 env->eflags &= ~IF_MASK;
802 }
803 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
804}
805
806#ifdef TARGET_X86_64
807
808#define PUSHQ(sp, val)\
809{\
810 sp -= 8;\
811 stq_kernel(sp, (val));\
812}
813
814#define POPQ(sp, val)\
815{\
816 val = ldq_kernel(sp);\
817 sp += 8;\
818}
819
820static inline target_ulong get_rsp_from_tss(int level)
821{
822 int index;
823
824#if 0
825 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
826 env->tr.base, env->tr.limit);
827#endif
828
829 if (!(env->tr.flags & DESC_P_MASK))
830 cpu_abort(env, "invalid tss");
831 index = 8 * level + 4;
832 if ((index + 7) > env->tr.limit)
833 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
834 return ldq_kernel(env->tr.base + index);
835}
836
837/* 64 bit interrupt */
838static void do_interrupt64(int intno, int is_int, int error_code,
839 target_ulong next_eip, int is_hw)
840{
841 SegmentCache *dt;
842 target_ulong ptr;
843 int type, dpl, selector, cpl, ist;
844 int has_error_code, new_stack;
845 uint32_t e1, e2, e3, ss;
846 target_ulong old_eip, esp, offset;
847
848 has_error_code = 0;
849 if (!is_int && !is_hw) {
850 switch(intno) {
851 case 8:
852 case 10:
853 case 11:
854 case 12:
855 case 13:
856 case 14:
857 case 17:
858 has_error_code = 1;
859 break;
860 }
861 }
862 if (is_int)
863 old_eip = next_eip;
864 else
865 old_eip = env->eip;
866
867 dt = &env->idt;
868 if (intno * 16 + 15 > dt->limit)
869 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
870 ptr = dt->base + intno * 16;
871 e1 = ldl_kernel(ptr);
872 e2 = ldl_kernel(ptr + 4);
873 e3 = ldl_kernel(ptr + 8);
874 /* check gate type */
875 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
876 switch(type) {
877 case 14: /* 386 interrupt gate */
878 case 15: /* 386 trap gate */
879 break;
880 default:
881 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
882 break;
883 }
884 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
885 cpl = env->hflags & HF_CPL_MASK;
886 /* check privledge if software int */
887 if (is_int && dpl < cpl)
888 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
889 /* check valid bit */
890 if (!(e2 & DESC_P_MASK))
891 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
892 selector = e1 >> 16;
893 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
894 ist = e2 & 7;
895 if ((selector & 0xfffc) == 0)
896 raise_exception_err(EXCP0D_GPF, 0);
897
898 if (load_segment(&e1, &e2, selector) != 0)
899 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
900 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
901 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
902 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
903 if (dpl > cpl)
904 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
905 if (!(e2 & DESC_P_MASK))
906 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
907 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
908 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
909 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
910 /* to inner priviledge */
911 if (ist != 0)
912 esp = get_rsp_from_tss(ist + 3);
913 else
914 esp = get_rsp_from_tss(dpl);
915 esp &= ~0xfLL; /* align stack */
916 ss = 0;
917 new_stack = 1;
918 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
919 /* to same priviledge */
920 if (env->eflags & VM_MASK)
921 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
922 new_stack = 0;
923 if (ist != 0)
924 esp = get_rsp_from_tss(ist + 3);
925 else
926 esp = ESP;
927 esp &= ~0xfLL; /* align stack */
928 dpl = cpl;
929 } else {
930 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
931 new_stack = 0; /* avoid warning */
932 esp = 0; /* avoid warning */
933 }
934
935 PUSHQ(esp, env->segs[R_SS].selector);
936 PUSHQ(esp, ESP);
937 PUSHQ(esp, compute_eflags());
938 PUSHQ(esp, env->segs[R_CS].selector);
939 PUSHQ(esp, old_eip);
940 if (has_error_code) {
941 PUSHQ(esp, error_code);
942 }
943
944 if (new_stack) {
945 ss = 0 | dpl;
946 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
947 }
948 ESP = esp;
949
950 selector = (selector & ~3) | dpl;
951 cpu_x86_load_seg_cache(env, R_CS, selector,
952 get_seg_base(e1, e2),
953 get_seg_limit(e1, e2),
954 e2);
955 cpu_x86_set_cpl(env, dpl);
956 env->eip = offset;
957
958 /* interrupt gate clear IF mask */
959 if ((type & 1) == 0) {
960 env->eflags &= ~IF_MASK;
961 }
962 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
963}
964#endif
965
966void helper_syscall(int next_eip_addend)
967{
968 int selector;
969
970 if (!(env->efer & MSR_EFER_SCE)) {
971 raise_exception_err(EXCP06_ILLOP, 0);
972 }
973 selector = (env->star >> 32) & 0xffff;
974#ifdef TARGET_X86_64
975 if (env->hflags & HF_LMA_MASK) {
976 int code64;
977
978 ECX = env->eip + next_eip_addend;
979 env->regs[11] = compute_eflags();
980
981 code64 = env->hflags & HF_CS64_MASK;
982
983 cpu_x86_set_cpl(env, 0);
984 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
985 0, 0xffffffff,
986 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
987 DESC_S_MASK |
988 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
989 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
990 0, 0xffffffff,
991 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
992 DESC_S_MASK |
993 DESC_W_MASK | DESC_A_MASK);
994 env->eflags &= ~env->fmask;
995 if (code64)
996 env->eip = env->lstar;
997 else
998 env->eip = env->cstar;
999 } else
1000#endif
1001 {
1002 ECX = (uint32_t)(env->eip + next_eip_addend);
1003
1004 cpu_x86_set_cpl(env, 0);
1005 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1006 0, 0xffffffff,
1007 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1008 DESC_S_MASK |
1009 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1010 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1011 0, 0xffffffff,
1012 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1013 DESC_S_MASK |
1014 DESC_W_MASK | DESC_A_MASK);
1015 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
1016 env->eip = (uint32_t)env->star;
1017 }
1018}
1019
1020void helper_sysret(int dflag)
1021{
1022 int cpl, selector;
1023
1024 if (!(env->efer & MSR_EFER_SCE)) {
1025 raise_exception_err(EXCP06_ILLOP, 0);
1026 }
1027 cpl = env->hflags & HF_CPL_MASK;
1028 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1029 raise_exception_err(EXCP0D_GPF, 0);
1030 }
1031 selector = (env->star >> 48) & 0xffff;
1032#ifdef TARGET_X86_64
1033 if (env->hflags & HF_LMA_MASK) {
1034 if (dflag == 2) {
1035 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1036 0, 0xffffffff,
1037 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1038 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1039 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1040 DESC_L_MASK);
1041 env->eip = ECX;
1042 } else {
1043 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1044 0, 0xffffffff,
1045 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1046 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1047 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1048 env->eip = (uint32_t)ECX;
1049 }
1050 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1051 0, 0xffffffff,
1052 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1053 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1054 DESC_W_MASK | DESC_A_MASK);
1055 load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1056 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
1057 cpu_x86_set_cpl(env, 3);
1058 } else
1059#endif
1060 {
1061 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1062 0, 0xffffffff,
1063 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1064 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1065 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1066 env->eip = (uint32_t)ECX;
1067 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1068 0, 0xffffffff,
1069 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1070 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1071 DESC_W_MASK | DESC_A_MASK);
1072 env->eflags |= IF_MASK;
1073 cpu_x86_set_cpl(env, 3);
1074 }
1075#ifdef USE_KQEMU
1076 if (kqemu_is_ok(env)) {
1077 if (env->hflags & HF_LMA_MASK)
1078 CC_OP = CC_OP_EFLAGS;
1079 env->exception_index = -1;
1080 cpu_loop_exit();
1081 }
1082#endif
1083}
1084
1085#ifdef VBOX
1086/**
1087 * Checks and processes external VMM events.
1088 * Called by op_check_external_event() when any of the flags is set and can be serviced.
1089 */
1090void helper_external_event(void)
1091{
1092 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1093 {
1094 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1095 cpu_interrupt(env, CPU_INTERRUPT_HARD);
1096 }
1097 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1098 {
1099 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1100 cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1101 }
1102 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1103 {
1104 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1105 remR3DmaRun(env);
1106 }
1107 if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1108 {
1109 ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1110 remR3TimersRun(env);
1111 }
1112}
1113#endif /* VBOX */
1114
1115/* real mode interrupt */
1116static void do_interrupt_real(int intno, int is_int, int error_code,
1117 unsigned int next_eip)
1118{
1119 SegmentCache *dt;
1120 target_ulong ptr, ssp;
1121 int selector;
1122 uint32_t offset, esp;
1123 uint32_t old_cs, old_eip;
1124
1125 /* real mode (simpler !) */
1126 dt = &env->idt;
1127 if (intno * 4 + 3 > dt->limit)
1128 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1129 ptr = dt->base + intno * 4;
1130 offset = lduw_kernel(ptr);
1131 selector = lduw_kernel(ptr + 2);
1132 esp = ESP;
1133 ssp = env->segs[R_SS].base;
1134 if (is_int)
1135 old_eip = next_eip;
1136 else
1137 old_eip = env->eip;
1138 old_cs = env->segs[R_CS].selector;
1139 /* XXX: use SS segment size ? */
1140 PUSHW(ssp, esp, 0xffff, compute_eflags());
1141 PUSHW(ssp, esp, 0xffff, old_cs);
1142 PUSHW(ssp, esp, 0xffff, old_eip);
1143
1144 /* update processor state */
1145 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1146 env->eip = offset;
1147 env->segs[R_CS].selector = selector;
1148 env->segs[R_CS].base = (selector << 4);
1149 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1150}
1151
1152/* fake user mode interrupt */
1153void do_interrupt_user(int intno, int is_int, int error_code,
1154 target_ulong next_eip)
1155{
1156 SegmentCache *dt;
1157 target_ulong ptr;
1158 int dpl, cpl;
1159 uint32_t e2;
1160
1161 dt = &env->idt;
1162 ptr = dt->base + (intno * 8);
1163 e2 = ldl_kernel(ptr + 4);
1164
1165 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1166 cpl = env->hflags & HF_CPL_MASK;
1167 /* check privledge if software int */
1168 if (is_int && dpl < cpl)
1169 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1170
1171 /* Since we emulate only user space, we cannot do more than
1172 exiting the emulation with the suitable exception and error
1173 code */
1174 if (is_int)
1175 EIP = next_eip;
1176}
1177
1178/*
1179 * Begin execution of an interruption. is_int is TRUE if coming from
1180 * the int instruction. next_eip is the EIP value AFTER the interrupt
1181 * instruction. It is only relevant if is_int is TRUE.
1182 */
1183void do_interrupt(int intno, int is_int, int error_code,
1184 target_ulong next_eip, int is_hw)
1185{
1186#ifdef DEBUG_PCALL
1187 if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) {
1188 if ((env->cr[0] & CR0_PE_MASK)) {
1189 static int count;
1190 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1191 count, intno, error_code, is_int,
1192 env->hflags & HF_CPL_MASK,
1193 env->segs[R_CS].selector, EIP,
1194 (int)env->segs[R_CS].base + EIP,
1195 env->segs[R_SS].selector, ESP);
1196 if (intno == 0x0e) {
1197 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1198 } else {
1199 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1200 }
1201 fprintf(logfile, "\n");
1202#if 0
1203 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1204 {
1205 int i;
1206 uint8_t *ptr;
1207 fprintf(logfile, " code=");
1208 ptr = env->segs[R_CS].base + env->eip;
1209 for(i = 0; i < 16; i++) {
1210 fprintf(logfile, " %02x", ldub(ptr + i));
1211 }
1212 fprintf(logfile, "\n");
1213 }
1214#endif
1215 count++;
1216 }
1217 }
1218#endif
1219 if (env->cr[0] & CR0_PE_MASK) {
1220#if TARGET_X86_64
1221 if (env->hflags & HF_LMA_MASK) {
1222 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1223 } else
1224#endif
1225 {
1226 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1227 }
1228 } else {
1229 do_interrupt_real(intno, is_int, error_code, next_eip);
1230 }
1231}
1232
1233/*
1234 * Signal an interruption. It is executed in the main CPU loop.
1235 * is_int is TRUE if coming from the int instruction. next_eip is the
1236 * EIP value AFTER the interrupt instruction. It is only relevant if
1237 * is_int is TRUE.
1238 */
1239void raise_interrupt(int intno, int is_int, int error_code,
1240 int next_eip_addend)
1241{
1242#if defined(VBOX) && defined(DEBUG) && !defined(DEBUG_dmik)
1243 Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend));
1244#endif
1245 env->exception_index = intno;
1246 env->error_code = error_code;
1247 env->exception_is_int = is_int;
1248 env->exception_next_eip = env->eip + next_eip_addend;
1249 cpu_loop_exit();
1250}
1251
1252/* same as raise_exception_err, but do not restore global registers */
1253static void raise_exception_err_norestore(int exception_index, int error_code)
1254{
1255 env->exception_index = exception_index;
1256 env->error_code = error_code;
1257 env->exception_is_int = 0;
1258 env->exception_next_eip = 0;
1259 longjmp(env->jmp_env, 1);
1260}
1261
1262/* shortcuts to generate exceptions */
1263
1264void (raise_exception_err)(int exception_index, int error_code)
1265{
1266 raise_interrupt(exception_index, 0, error_code, 0);
1267}
1268
1269void raise_exception(int exception_index)
1270{
1271 raise_interrupt(exception_index, 0, 0, 0);
1272}
1273
1274#ifdef BUGGY_GCC_DIV64
1275/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1276 call it from another function */
1277uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1278{
1279 *q_ptr = num / den;
1280 return num % den;
1281}
1282
1283int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1284{
1285 *q_ptr = num / den;
1286 return num % den;
1287}
1288#endif
1289
1290void helper_divl_EAX_T0(void)
1291{
1292 unsigned int den, r;
1293 uint64_t num, q;
1294
1295 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1296 den = T0;
1297 if (den == 0) {
1298 raise_exception(EXCP00_DIVZ);
1299 }
1300#ifdef BUGGY_GCC_DIV64
1301 r = div32(&q, num, den);
1302#else
1303 q = (num / den);
1304 r = (num % den);
1305#endif
1306 if (q > 0xffffffff)
1307 raise_exception(EXCP00_DIVZ);
1308 EAX = (uint32_t)q;
1309 EDX = (uint32_t)r;
1310}
1311
1312void helper_idivl_EAX_T0(void)
1313{
1314 int den, r;
1315 int64_t num, q;
1316
1317 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1318 den = T0;
1319 if (den == 0) {
1320 raise_exception(EXCP00_DIVZ);
1321 }
1322#ifdef BUGGY_GCC_DIV64
1323 r = idiv32(&q, num, den);
1324#else
1325 q = (num / den);
1326 r = (num % den);
1327#endif
1328 if (q != (int32_t)q)
1329 raise_exception(EXCP00_DIVZ);
1330 EAX = (uint32_t)q;
1331 EDX = (uint32_t)r;
1332}
1333
1334void helper_cmpxchg8b(void)
1335{
1336 uint64_t d;
1337 int eflags;
1338
1339 eflags = cc_table[CC_OP].compute_all();
1340 d = ldq(A0);
1341 if (d == (((uint64_t)EDX << 32) | EAX)) {
1342 stq(A0, ((uint64_t)ECX << 32) | EBX);
1343 eflags |= CC_Z;
1344 } else {
1345 EDX = d >> 32;
1346 EAX = d;
1347 eflags &= ~CC_Z;
1348 }
1349 CC_SRC = eflags;
1350}
1351
1352void helper_cpuid(void)
1353{
1354#ifndef VBOX
1355 switch((uint32_t)EAX) {
1356 case 0:
1357 EAX = 2; /* max EAX index supported */
1358 EBX = env->cpuid_vendor1;
1359 EDX = env->cpuid_vendor2;
1360 ECX = env->cpuid_vendor3;
1361 break;
1362 case 1:
1363 EAX = env->cpuid_version;
1364 EBX = 0;
1365 ECX = env->cpuid_ext_features;
1366 EDX = env->cpuid_features;
1367 break;
1368
1369 default:
1370 /* cache info: needed for Pentium Pro compatibility */
1371 EAX = 0x410601;
1372 EBX = 0;
1373 ECX = 0;
1374 EDX = 0;
1375 break;
1376
1377#ifdef TARGET_X86_64
1378 case 0x80000000:
1379 EAX = 0x80000008;
1380 EBX = env->cpuid_vendor1;
1381 EDX = env->cpuid_vendor2;
1382 ECX = env->cpuid_vendor3;
1383 break;
1384 case 0x80000001:
1385 EAX = env->cpuid_features;
1386 EBX = 0;
1387 ECX = 0;
1388 /* long mode + syscall/sysret features */
1389 EDX = (env->cpuid_features & 0x0183F3FF) | (1 << 29) | (1 << 11);
1390 break;
1391 case 0x80000008:
1392 /* virtual & phys address size in low 2 bytes. */
1393 EAX = 0x00003028;
1394 EBX = 0;
1395 ECX = 0;
1396 EDX = 0;
1397 break;
1398#endif
1399 }
1400#else /* VBOX */
1401 remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1402#endif /* VBOX */
1403}
1404
1405void helper_enter_level(int level, int data32)
1406{
1407 target_ulong ssp;
1408 uint32_t esp_mask, esp, ebp;
1409
1410 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1411 ssp = env->segs[R_SS].base;
1412 ebp = EBP;
1413 esp = ESP;
1414 if (data32) {
1415 /* 32 bit */
1416 esp -= 4;
1417 while (--level) {
1418 esp -= 4;
1419 ebp -= 4;
1420 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1421 }
1422 esp -= 4;
1423 stl(ssp + (esp & esp_mask), T1);
1424 } else {
1425 /* 16 bit */
1426 esp -= 2;
1427 while (--level) {
1428 esp -= 2;
1429 ebp -= 2;
1430 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1431 }
1432 esp -= 2;
1433 stw(ssp + (esp & esp_mask), T1);
1434 }
1435}
1436
1437#ifdef TARGET_X86_64
1438void helper_enter64_level(int level, int data64)
1439{
1440 target_ulong esp, ebp;
1441 ebp = EBP;
1442 esp = ESP;
1443
1444 if (data64) {
1445 /* 64 bit */
1446 esp -= 8;
1447 while (--level) {
1448 esp -= 8;
1449 ebp -= 8;
1450 stq(esp, ldq(ebp));
1451 }
1452 esp -= 8;
1453 stq(esp, T1);
1454 } else {
1455 /* 16 bit */
1456 esp -= 2;
1457 while (--level) {
1458 esp -= 2;
1459 ebp -= 2;
1460 stw(esp, lduw(ebp));
1461 }
1462 esp -= 2;
1463 stw(esp, T1);
1464 }
1465}
1466#endif
1467
1468void helper_lldt_T0(void)
1469{
1470 int selector;
1471 SegmentCache *dt;
1472 uint32_t e1, e2;
1473 int index, entry_limit;
1474 target_ulong ptr;
1475#ifdef VBOX
1476 Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1477 (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1478#endif
1479
1480 selector = T0 & 0xffff;
1481 if ((selector & 0xfffc) == 0) {
1482 /* XXX: NULL selector case: invalid LDT */
1483 env->ldt.base = 0;
1484 env->ldt.limit = 0;
1485 } else {
1486 if (selector & 0x4)
1487 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1488 dt = &env->gdt;
1489 index = selector & ~7;
1490#ifdef TARGET_X86_64
1491 if (env->hflags & HF_LMA_MASK)
1492 entry_limit = 15;
1493 else
1494#endif
1495 entry_limit = 7;
1496 if ((index + entry_limit) > dt->limit)
1497 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1498 ptr = dt->base + index;
1499 e1 = ldl_kernel(ptr);
1500 e2 = ldl_kernel(ptr + 4);
1501 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1502 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1503 if (!(e2 & DESC_P_MASK))
1504 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1505#ifdef TARGET_X86_64
1506 if (env->hflags & HF_LMA_MASK) {
1507 uint32_t e3;
1508 e3 = ldl_kernel(ptr + 8);
1509 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1510 env->ldt.base |= (target_ulong)e3 << 32;
1511 } else
1512#endif
1513 {
1514 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1515 }
1516 }
1517 env->ldt.selector = selector;
1518#ifdef VBOX
1519 Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
1520 (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
1521#endif
1522}
1523
1524void helper_ltr_T0(void)
1525{
1526 int selector;
1527 SegmentCache *dt;
1528 uint32_t e1, e2;
1529 int index, type, entry_limit;
1530 target_ulong ptr;
1531#ifdef VBOX
1532 Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
1533 (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
1534 env->tr.flags, (RTSEL)(T0 & 0xffff)));
1535#endif
1536
1537 selector = T0 & 0xffff;
1538 if ((selector & 0xfffc) == 0) {
1539 /* NULL selector case: invalid TR */
1540 env->tr.base = 0;
1541 env->tr.limit = 0;
1542 env->tr.flags = 0;
1543 } else {
1544 if (selector & 0x4)
1545 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1546 dt = &env->gdt;
1547 index = selector & ~7;
1548#ifdef TARGET_X86_64
1549 if (env->hflags & HF_LMA_MASK)
1550 entry_limit = 15;
1551 else
1552#endif
1553 entry_limit = 7;
1554 if ((index + entry_limit) > dt->limit)
1555 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1556 ptr = dt->base + index;
1557 e1 = ldl_kernel(ptr);
1558 e2 = ldl_kernel(ptr + 4);
1559 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1560 if ((e2 & DESC_S_MASK) ||
1561 (type != 1 && type != 9))
1562 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1563 if (!(e2 & DESC_P_MASK))
1564 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1565#ifdef TARGET_X86_64
1566 if (env->hflags & HF_LMA_MASK) {
1567 uint32_t e3;
1568 e3 = ldl_kernel(ptr + 8);
1569 load_seg_cache_raw_dt(&env->tr, e1, e2);
1570 env->tr.base |= (target_ulong)e3 << 32;
1571 } else
1572#endif
1573 {
1574 load_seg_cache_raw_dt(&env->tr, e1, e2);
1575 }
1576 e2 |= DESC_TSS_BUSY_MASK;
1577 stl_kernel(ptr + 4, e2);
1578 }
1579 env->tr.selector = selector;
1580#ifdef VBOX
1581 Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
1582 (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
1583 env->tr.flags, (RTSEL)(T0 & 0xffff)));
1584#endif
1585}
1586
1587/* only works if protected mode and not VM86. seg_reg must be != R_CS */
1588void load_seg(int seg_reg, int selector)
1589{
1590 uint32_t e1, e2;
1591 int cpl, dpl, rpl;
1592 SegmentCache *dt;
1593 int index;
1594 target_ulong ptr;
1595
1596 selector &= 0xffff;
1597 cpl = env->hflags & HF_CPL_MASK;
1598 if ((selector & 0xfffc) == 0) {
1599 /* null selector case */
1600 if (seg_reg == R_SS
1601#ifdef TARGET_X86_64
1602 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1603#endif
1604 )
1605 raise_exception_err(EXCP0D_GPF, 0);
1606 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1607 } else {
1608
1609 if (selector & 0x4)
1610 dt = &env->ldt;
1611 else
1612 dt = &env->gdt;
1613 index = selector & ~7;
1614 if ((index + 7) > dt->limit)
1615 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1616 ptr = dt->base + index;
1617 e1 = ldl_kernel(ptr);
1618 e2 = ldl_kernel(ptr + 4);
1619
1620 if (!(e2 & DESC_S_MASK))
1621 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1622 rpl = selector & 3;
1623 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1624 if (seg_reg == R_SS) {
1625 /* must be writable segment */
1626 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
1627 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1628 if (rpl != cpl || dpl != cpl)
1629 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1630 } else {
1631 /* must be readable segment */
1632 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
1633 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1634
1635 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1636 /* if not conforming code, test rights */
1637 if (dpl < cpl || dpl < rpl)
1638 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1639 }
1640 }
1641
1642 if (!(e2 & DESC_P_MASK)) {
1643 if (seg_reg == R_SS)
1644 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1645 else
1646 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1647 }
1648
1649 /* set the access bit if not already set */
1650 if (!(e2 & DESC_A_MASK)) {
1651 e2 |= DESC_A_MASK;
1652 stl_kernel(ptr + 4, e2);
1653 }
1654
1655 cpu_x86_load_seg_cache(env, seg_reg, selector,
1656 get_seg_base(e1, e2),
1657 get_seg_limit(e1, e2),
1658 e2);
1659#if 0
1660 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1661 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1662#endif
1663 }
1664}
1665
1666/* protected mode jump */
1667void helper_ljmp_protected_T0_T1(int next_eip_addend)
1668{
1669 int new_cs, gate_cs, type;
1670 uint32_t e1, e2, cpl, dpl, rpl, limit;
1671 target_ulong new_eip, next_eip;
1672
1673 new_cs = T0;
1674 new_eip = T1;
1675 if ((new_cs & 0xfffc) == 0)
1676 raise_exception_err(EXCP0D_GPF, 0);
1677 if (load_segment(&e1, &e2, new_cs) != 0)
1678 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1679 cpl = env->hflags & HF_CPL_MASK;
1680 if (e2 & DESC_S_MASK) {
1681 if (!(e2 & DESC_CS_MASK))
1682 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1683 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1684 if (e2 & DESC_C_MASK) {
1685 /* conforming code segment */
1686 if (dpl > cpl)
1687 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1688 } else {
1689 /* non conforming code segment */
1690 rpl = new_cs & 3;
1691 if (rpl > cpl)
1692 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1693 if (dpl != cpl)
1694 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1695 }
1696 if (!(e2 & DESC_P_MASK))
1697 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1698 limit = get_seg_limit(e1, e2);
1699 if (new_eip > limit &&
1700 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
1701 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1702 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1703 get_seg_base(e1, e2), limit, e2);
1704 EIP = new_eip;
1705 } else {
1706 /* jump to call or task gate */
1707 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1708 rpl = new_cs & 3;
1709 cpl = env->hflags & HF_CPL_MASK;
1710 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1711 switch(type) {
1712 case 1: /* 286 TSS */
1713 case 9: /* 386 TSS */
1714 case 5: /* task gate */
1715 if (dpl < cpl || dpl < rpl)
1716 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1717 next_eip = env->eip + next_eip_addend;
1718 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1719 CC_OP = CC_OP_EFLAGS;
1720 break;
1721 case 4: /* 286 call gate */
1722 case 12: /* 386 call gate */
1723 if ((dpl < cpl) || (dpl < rpl))
1724 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1725 if (!(e2 & DESC_P_MASK))
1726 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1727 gate_cs = e1 >> 16;
1728 new_eip = (e1 & 0xffff);
1729 if (type == 12)
1730 new_eip |= (e2 & 0xffff0000);
1731 if (load_segment(&e1, &e2, gate_cs) != 0)
1732 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1733 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1734 /* must be code segment */
1735 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1736 (DESC_S_MASK | DESC_CS_MASK)))
1737 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1738 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1739 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
1740 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1741 if (!(e2 & DESC_P_MASK))
1742 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1743 limit = get_seg_limit(e1, e2);
1744 if (new_eip > limit)
1745 raise_exception_err(EXCP0D_GPF, 0);
1746 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1747 get_seg_base(e1, e2), limit, e2);
1748 EIP = new_eip;
1749 break;
1750 default:
1751 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1752 break;
1753 }
1754 }
1755}
1756
1757/* real mode call */
1758void helper_lcall_real_T0_T1(int shift, int next_eip)
1759{
1760 int new_cs, new_eip;
1761 uint32_t esp, esp_mask;
1762 target_ulong ssp;
1763
1764 new_cs = T0;
1765 new_eip = T1;
1766 esp = ESP;
1767 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1768 ssp = env->segs[R_SS].base;
1769 if (shift) {
1770 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1771 PUSHL(ssp, esp, esp_mask, next_eip);
1772 } else {
1773 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1774 PUSHW(ssp, esp, esp_mask, next_eip);
1775 }
1776
1777 ESP = (ESP & ~esp_mask) | (esp & esp_mask);
1778 env->eip = new_eip;
1779 env->segs[R_CS].selector = new_cs;
1780 env->segs[R_CS].base = (new_cs << 4);
1781}
1782
1783/* protected mode call */
1784void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
1785{
1786 int new_cs, new_stack, i;
1787 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1788 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
1789 uint32_t val, limit, old_sp_mask;
1790 target_ulong ssp, old_ssp, next_eip, new_eip;
1791
1792 new_cs = T0;
1793 new_eip = T1;
1794 next_eip = env->eip + next_eip_addend;
1795#ifdef DEBUG_PCALL
1796 if (loglevel & CPU_LOG_PCALL) {
1797 fprintf(logfile, "lcall %04x:%08x s=%d\n",
1798 new_cs, (uint32_t)new_eip, shift);
1799 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1800 }
1801#endif
1802 if ((new_cs & 0xfffc) == 0)
1803 raise_exception_err(EXCP0D_GPF, 0);
1804 if (load_segment(&e1, &e2, new_cs) != 0)
1805 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1806 cpl = env->hflags & HF_CPL_MASK;
1807#ifdef DEBUG_PCALL
1808 if (loglevel & CPU_LOG_PCALL) {
1809 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
1810 }
1811#endif
1812 if (e2 & DESC_S_MASK) {
1813 if (!(e2 & DESC_CS_MASK))
1814 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1815 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1816 if (e2 & DESC_C_MASK) {
1817 /* conforming code segment */
1818 if (dpl > cpl)
1819 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1820 } else {
1821 /* non conforming code segment */
1822 rpl = new_cs & 3;
1823 if (rpl > cpl)
1824 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1825 if (dpl != cpl)
1826 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1827 }
1828 if (!(e2 & DESC_P_MASK))
1829 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1830
1831#ifdef TARGET_X86_64
1832 /* XXX: check 16/32 bit cases in long mode */
1833 if (shift == 2) {
1834 target_ulong rsp;
1835 /* 64 bit case */
1836 rsp = ESP;
1837 PUSHQ(rsp, env->segs[R_CS].selector);
1838 PUSHQ(rsp, next_eip);
1839 /* from this point, not restartable */
1840 ESP = rsp;
1841 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1842 get_seg_base(e1, e2),
1843 get_seg_limit(e1, e2), e2);
1844 EIP = new_eip;
1845 } else
1846#endif
1847 {
1848 sp = ESP;
1849 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1850 ssp = env->segs[R_SS].base;
1851 if (shift) {
1852 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1853 PUSHL(ssp, sp, sp_mask, next_eip);
1854 } else {
1855 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1856 PUSHW(ssp, sp, sp_mask, next_eip);
1857 }
1858
1859 limit = get_seg_limit(e1, e2);
1860 if (new_eip > limit)
1861 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1862 /* from this point, not restartable */
1863 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1864 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1865 get_seg_base(e1, e2), limit, e2);
1866 EIP = new_eip;
1867 }
1868 } else {
1869 /* check gate type */
1870 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1871 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1872 rpl = new_cs & 3;
1873 switch(type) {
1874 case 1: /* available 286 TSS */
1875 case 9: /* available 386 TSS */
1876 case 5: /* task gate */
1877 if (dpl < cpl || dpl < rpl)
1878 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1879 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1880 CC_OP = CC_OP_EFLAGS;
1881 return;
1882 case 4: /* 286 call gate */
1883 case 12: /* 386 call gate */
1884 break;
1885 default:
1886 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1887 break;
1888 }
1889 shift = type >> 3;
1890
1891 if (dpl < cpl || dpl < rpl)
1892 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1893 /* check valid bit */
1894 if (!(e2 & DESC_P_MASK))
1895 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1896 selector = e1 >> 16;
1897 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1898 param_count = e2 & 0x1f;
1899 if ((selector & 0xfffc) == 0)
1900 raise_exception_err(EXCP0D_GPF, 0);
1901
1902 if (load_segment(&e1, &e2, selector) != 0)
1903 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1904 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
1905 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1906 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1907 if (dpl > cpl)
1908 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1909 if (!(e2 & DESC_P_MASK))
1910 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1911
1912 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1913 /* to inner priviledge */
1914 get_ss_esp_from_tss(&ss, &sp, dpl);
1915#ifdef DEBUG_PCALL
1916 if (loglevel & CPU_LOG_PCALL)
1917 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
1918 ss, sp, param_count, ESP);
1919#endif
1920 if ((ss & 0xfffc) == 0)
1921 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1922 if ((ss & 3) != dpl)
1923 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1924 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
1925 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1926 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1927 if (ss_dpl != dpl)
1928 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1929 if (!(ss_e2 & DESC_S_MASK) ||
1930 (ss_e2 & DESC_CS_MASK) ||
1931 !(ss_e2 & DESC_W_MASK))
1932 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1933 if (!(ss_e2 & DESC_P_MASK))
1934 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1935
1936 // push_size = ((param_count * 2) + 8) << shift;
1937
1938 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1939 old_ssp = env->segs[R_SS].base;
1940
1941 sp_mask = get_sp_mask(ss_e2);
1942 ssp = get_seg_base(ss_e1, ss_e2);
1943 if (shift) {
1944 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1945 PUSHL(ssp, sp, sp_mask, ESP);
1946 for(i = param_count - 1; i >= 0; i--) {
1947 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
1948 PUSHL(ssp, sp, sp_mask, val);
1949 }
1950 } else {
1951 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1952 PUSHW(ssp, sp, sp_mask, ESP);
1953 for(i = param_count - 1; i >= 0; i--) {
1954 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
1955 PUSHW(ssp, sp, sp_mask, val);
1956 }
1957 }
1958 new_stack = 1;
1959 } else {
1960 /* to same priviledge */
1961 sp = ESP;
1962 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1963 ssp = env->segs[R_SS].base;
1964 // push_size = (4 << shift);
1965 new_stack = 0;
1966 }
1967
1968 if (shift) {
1969 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1970 PUSHL(ssp, sp, sp_mask, next_eip);
1971 } else {
1972 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1973 PUSHW(ssp, sp, sp_mask, next_eip);
1974 }
1975
1976 /* from this point, not restartable */
1977
1978 if (new_stack) {
1979 ss = (ss & ~3) | dpl;
1980 cpu_x86_load_seg_cache(env, R_SS, ss,
1981 ssp,
1982 get_seg_limit(ss_e1, ss_e2),
1983 ss_e2);
1984 }
1985
1986 selector = (selector & ~3) | dpl;
1987 cpu_x86_load_seg_cache(env, R_CS, selector,
1988 get_seg_base(e1, e2),
1989 get_seg_limit(e1, e2),
1990 e2);
1991 cpu_x86_set_cpl(env, dpl);
1992 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1993 EIP = offset;
1994 }
1995#ifdef USE_KQEMU
1996 if (kqemu_is_ok(env)) {
1997 env->exception_index = -1;
1998 cpu_loop_exit();
1999 }
2000#endif
2001}
2002
2003/* real and vm86 mode iret */
2004void helper_iret_real(int shift)
2005{
2006 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2007 target_ulong ssp;
2008 int eflags_mask;
2009
2010#ifdef VBOX
2011 remR3TrapClear(env->pVM);
2012#endif
2013
2014 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2015 sp = ESP;
2016 ssp = env->segs[R_SS].base;
2017 if (shift == 1) {
2018 /* 32 bits */
2019 POPL(ssp, sp, sp_mask, new_eip);
2020 POPL(ssp, sp, sp_mask, new_cs);
2021 new_cs &= 0xffff;
2022 POPL(ssp, sp, sp_mask, new_eflags);
2023 } else {
2024 /* 16 bits */
2025 POPW(ssp, sp, sp_mask, new_eip);
2026 POPW(ssp, sp, sp_mask, new_cs);
2027 POPW(ssp, sp, sp_mask, new_eflags);
2028 }
2029 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2030 load_seg_vm(R_CS, new_cs);
2031 env->eip = new_eip;
2032 if (env->eflags & VM_MASK)
2033 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
2034 else
2035 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
2036 if (shift == 0)
2037 eflags_mask &= 0xffff;
2038 load_eflags(new_eflags, eflags_mask);
2039}
2040
2041static inline void validate_seg(int seg_reg, int cpl)
2042{
2043 int dpl;
2044 uint32_t e2;
2045
2046 e2 = env->segs[seg_reg].flags;
2047 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2048 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2049 /* data or non conforming code segment */
2050 if (dpl < cpl) {
2051 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2052 }
2053 }
2054}
2055
2056/* protected mode iret */
2057static inline void helper_ret_protected(int shift, int is_iret, int addend)
2058{
2059 uint32_t new_cs, new_eflags, new_ss;
2060 uint32_t new_es, new_ds, new_fs, new_gs;
2061 uint32_t e1, e2, ss_e1, ss_e2;
2062 int cpl, dpl, rpl, eflags_mask, iopl;
2063 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2064
2065#ifdef TARGET_X86_64
2066 if (shift == 2)
2067 sp_mask = -1;
2068 else
2069#endif
2070 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2071 sp = ESP;
2072 ssp = env->segs[R_SS].base;
2073 new_eflags = 0; /* avoid warning */
2074#ifdef TARGET_X86_64
2075 if (shift == 2) {
2076 POPQ(sp, new_eip);
2077 POPQ(sp, new_cs);
2078 new_cs &= 0xffff;
2079 if (is_iret) {
2080 POPQ(sp, new_eflags);
2081 }
2082 } else
2083#endif
2084 if (shift == 1) {
2085 /* 32 bits */
2086 POPL(ssp, sp, sp_mask, new_eip);
2087 POPL(ssp, sp, sp_mask, new_cs);
2088 new_cs &= 0xffff;
2089 if (is_iret) {
2090 POPL(ssp, sp, sp_mask, new_eflags);
2091#if defined(VBOX) && defined(DEBUG)
2092 printf("iret: new CS %04X\n", new_cs);
2093 printf("iret: new EIP %08X\n", new_eip);
2094 printf("iret: new EFLAGS %08X\n", new_eflags);
2095 printf("iret: EAX=%08x\n", EAX);
2096#endif
2097
2098 if (new_eflags & VM_MASK)
2099 goto return_to_vm86;
2100 }
2101#ifdef VBOX
2102 if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
2103 {
2104#ifdef DEBUG
2105 printf("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc);
2106#endif
2107 new_cs = new_cs & 0xfffc;
2108 }
2109#endif
2110 } else {
2111 /* 16 bits */
2112 POPW(ssp, sp, sp_mask, new_eip);
2113 POPW(ssp, sp, sp_mask, new_cs);
2114 if (is_iret)
2115 POPW(ssp, sp, sp_mask, new_eflags);
2116 }
2117#ifdef DEBUG_PCALL
2118 if (loglevel & CPU_LOG_PCALL) {
2119 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2120 new_cs, new_eip, shift, addend);
2121 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2122 }
2123#endif
2124 if ((new_cs & 0xfffc) == 0)
2125 {
2126#if defined(VBOX) && defined(DEBUG)
2127 printf("new_cs & 0xfffc) == 0\n");
2128#endif
2129 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2130 }
2131 if (load_segment(&e1, &e2, new_cs) != 0)
2132 {
2133#if defined(VBOX) && defined(DEBUG)
2134 printf("load_segment failed\n");
2135#endif
2136 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2137 }
2138 if (!(e2 & DESC_S_MASK) ||
2139 !(e2 & DESC_CS_MASK))
2140 {
2141#if defined(VBOX) && defined(DEBUG)
2142 printf("e2 mask %08x\n", e2);
2143#endif
2144 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2145 }
2146 cpl = env->hflags & HF_CPL_MASK;
2147 rpl = new_cs & 3;
2148 if (rpl < cpl)
2149 {
2150#if defined(VBOX) && defined(DEBUG)
2151 printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2152#endif
2153 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2154 }
2155 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2156 if (e2 & DESC_C_MASK) {
2157 if (dpl > rpl)
2158 {
2159#if defined(VBOX) && defined(DEBUG)
2160 printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2161#endif
2162 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2163 }
2164 } else {
2165 if (dpl != rpl)
2166 {
2167#if defined(VBOX) && defined(DEBUG)
2168 printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2169#endif
2170 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2171 }
2172 }
2173 if (!(e2 & DESC_P_MASK))
2174 {
2175#if defined(VBOX) && defined(DEBUG)
2176 printf("DESC_P_MASK e2=%08x\n", e2);
2177#endif
2178 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2179 }
2180 sp += addend;
2181 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2182 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2183 /* return to same priledge level */
2184 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2185 get_seg_base(e1, e2),
2186 get_seg_limit(e1, e2),
2187 e2);
2188 } else {
2189 /* return to different priviledge level */
2190#ifdef TARGET_X86_64
2191 if (shift == 2) {
2192 POPQ(sp, new_esp);
2193 POPQ(sp, new_ss);
2194 new_ss &= 0xffff;
2195 } else
2196#endif
2197 if (shift == 1) {
2198 /* 32 bits */
2199 POPL(ssp, sp, sp_mask, new_esp);
2200 POPL(ssp, sp, sp_mask, new_ss);
2201 new_ss &= 0xffff;
2202 } else {
2203 /* 16 bits */
2204 POPW(ssp, sp, sp_mask, new_esp);
2205 POPW(ssp, sp, sp_mask, new_ss);
2206 }
2207#ifdef DEBUG_PCALL
2208 if (loglevel & CPU_LOG_PCALL) {
2209 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2210 new_ss, new_esp);
2211 }
2212#endif
2213 if ((new_ss & 0xfffc) == 0) {
2214#ifdef TARGET_X86_64
2215 /* NULL ss is allowed in long mode if cpl != 3*/
2216 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2217 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2218 0, 0xffffffff,
2219 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2220 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2221 DESC_W_MASK | DESC_A_MASK);
2222 } else
2223#endif
2224 {
2225 raise_exception_err(EXCP0D_GPF, 0);
2226 }
2227 } else {
2228 if ((new_ss & 3) != rpl)
2229 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2230 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2231 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2232 if (!(ss_e2 & DESC_S_MASK) ||
2233 (ss_e2 & DESC_CS_MASK) ||
2234 !(ss_e2 & DESC_W_MASK))
2235 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2236 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2237 if (dpl != rpl)
2238 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2239 if (!(ss_e2 & DESC_P_MASK))
2240 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2241 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2242 get_seg_base(ss_e1, ss_e2),
2243 get_seg_limit(ss_e1, ss_e2),
2244 ss_e2);
2245 }
2246
2247 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2248 get_seg_base(e1, e2),
2249 get_seg_limit(e1, e2),
2250 e2);
2251 cpu_x86_set_cpl(env, rpl);
2252 sp = new_esp;
2253#ifdef TARGET_X86_64
2254 if (env->hflags & HF_CS64_MASK)
2255 sp_mask = -1;
2256 else
2257#endif
2258 sp_mask = get_sp_mask(ss_e2);
2259
2260 /* validate data segments */
2261 validate_seg(R_ES, rpl);
2262 validate_seg(R_DS, rpl);
2263 validate_seg(R_FS, rpl);
2264 validate_seg(R_GS, rpl);
2265
2266 sp += addend;
2267 }
2268 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2269 env->eip = new_eip;
2270 if (is_iret) {
2271 /* NOTE: 'cpl' is the _old_ CPL */
2272 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2273 if (cpl == 0)
2274 eflags_mask |= IOPL_MASK;
2275 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2276 if (cpl <= iopl)
2277 eflags_mask |= IF_MASK;
2278 if (shift == 0)
2279 eflags_mask &= 0xffff;
2280 load_eflags(new_eflags, eflags_mask);
2281 }
2282 return;
2283
2284 return_to_vm86:
2285
2286#if 0 // defined(VBOX) && defined(DEBUG)
2287 printf("V86: new CS %04X\n", new_cs);
2288 printf("V86: Descriptor %08X:%08X\n", e2, e1);
2289 printf("V86: new EIP %08X\n", new_eip);
2290 printf("V86: new EFLAGS %08X\n", new_eflags);
2291#endif
2292
2293 POPL(ssp, sp, sp_mask, new_esp);
2294 POPL(ssp, sp, sp_mask, new_ss);
2295 POPL(ssp, sp, sp_mask, new_es);
2296 POPL(ssp, sp, sp_mask, new_ds);
2297 POPL(ssp, sp, sp_mask, new_fs);
2298 POPL(ssp, sp, sp_mask, new_gs);
2299
2300 /* modify processor state */
2301 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
2302 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
2303 load_seg_vm(R_CS, new_cs & 0xffff);
2304 cpu_x86_set_cpl(env, 3);
2305 load_seg_vm(R_SS, new_ss & 0xffff);
2306 load_seg_vm(R_ES, new_es & 0xffff);
2307 load_seg_vm(R_DS, new_ds & 0xffff);
2308 load_seg_vm(R_FS, new_fs & 0xffff);
2309 load_seg_vm(R_GS, new_gs & 0xffff);
2310
2311 env->eip = new_eip & 0xffff;
2312 ESP = new_esp;
2313}
2314
2315void helper_iret_protected(int shift, int next_eip)
2316{
2317 int tss_selector, type;
2318 uint32_t e1, e2;
2319
2320#ifdef VBOX
2321 remR3TrapClear(env->pVM);
2322#endif
2323
2324 /* specific case for TSS */
2325 if (env->eflags & NT_MASK) {
2326#ifdef TARGET_X86_64
2327 if (env->hflags & HF_LMA_MASK)
2328 raise_exception_err(EXCP0D_GPF, 0);
2329#endif
2330 tss_selector = lduw_kernel(env->tr.base + 0);
2331 if (tss_selector & 4)
2332 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2333 if (load_segment(&e1, &e2, tss_selector) != 0)
2334 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2335 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2336 /* NOTE: we check both segment and busy TSS */
2337 if (type != 3)
2338 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2339 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2340 } else {
2341 helper_ret_protected(shift, 1, 0);
2342 }
2343}
2344
2345void helper_lret_protected(int shift, int addend)
2346{
2347 helper_ret_protected(shift, 0, addend);
2348}
2349
2350void helper_sysenter(void)
2351{
2352 if (env->sysenter_cs == 0) {
2353 raise_exception_err(EXCP0D_GPF, 0);
2354 }
2355 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2356 cpu_x86_set_cpl(env, 0);
2357 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2358 0, 0xffffffff,
2359 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2360 DESC_S_MASK |
2361 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2362 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2363 0, 0xffffffff,
2364 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2365 DESC_S_MASK |
2366 DESC_W_MASK | DESC_A_MASK);
2367 ESP = env->sysenter_esp;
2368 EIP = env->sysenter_eip;
2369}
2370
2371void helper_sysexit(void)
2372{
2373 int cpl;
2374
2375 cpl = env->hflags & HF_CPL_MASK;
2376 if (env->sysenter_cs == 0 || cpl != 0) {
2377 raise_exception_err(EXCP0D_GPF, 0);
2378 }
2379 cpu_x86_set_cpl(env, 3);
2380 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
2381 0, 0xffffffff,
2382 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2383 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2384 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2385 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
2386 0, 0xffffffff,
2387 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2388 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2389 DESC_W_MASK | DESC_A_MASK);
2390 ESP = ECX;
2391 EIP = EDX;
2392}
2393
2394void helper_movl_crN_T0(int reg)
2395{
2396#if !defined(CONFIG_USER_ONLY)
2397 switch(reg) {
2398 case 0:
2399 cpu_x86_update_cr0(env, T0);
2400 break;
2401 case 3:
2402 cpu_x86_update_cr3(env, T0);
2403 break;
2404 case 4:
2405 cpu_x86_update_cr4(env, T0);
2406 break;
2407 case 8:
2408 cpu_set_apic_tpr(env, T0);
2409 break;
2410 default:
2411 env->cr[reg] = T0;
2412 break;
2413 }
2414#endif
2415}
2416
2417/* XXX: do more */
2418void helper_movl_drN_T0(int reg)
2419{
2420 env->dr[reg] = T0;
2421}
2422
2423void helper_invlpg(unsigned int addr)
2424{
2425 cpu_x86_flush_tlb(env, addr);
2426}
2427
2428void helper_rdtsc(void)
2429{
2430 uint64_t val;
2431
2432 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2433 raise_exception(EXCP0D_GPF);
2434 }
2435 val = cpu_get_tsc(env);
2436 EAX = (uint32_t)(val);
2437 EDX = (uint32_t)(val >> 32);
2438}
2439
2440#if defined(CONFIG_USER_ONLY)
2441void helper_wrmsr(void)
2442{
2443}
2444
2445void helper_rdmsr(void)
2446{
2447}
2448#else
2449void helper_wrmsr(void)
2450{
2451 uint64_t val;
2452
2453 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2454
2455 switch((uint32_t)ECX) {
2456 case MSR_IA32_SYSENTER_CS:
2457 env->sysenter_cs = val & 0xffff;
2458 break;
2459 case MSR_IA32_SYSENTER_ESP:
2460 env->sysenter_esp = val;
2461 break;
2462 case MSR_IA32_SYSENTER_EIP:
2463 env->sysenter_eip = val;
2464 break;
2465 case MSR_IA32_APICBASE:
2466 cpu_set_apic_base(env, val);
2467 break;
2468#ifdef TARGET_X86_64
2469 case MSR_EFER:
2470#define MSR_EFER_UPDATE_MASK (MSR_EFER_SCE | MSR_EFER_LME | \
2471 MSR_EFER_NXE | MSR_EFER_FFXSR)
2472 env->efer = (env->efer & ~MSR_EFER_UPDATE_MASK) |
2473 (val & MSR_EFER_UPDATE_MASK);
2474 break;
2475 case MSR_STAR:
2476 env->star = val;
2477 break;
2478 case MSR_LSTAR:
2479 env->lstar = val;
2480 break;
2481 case MSR_CSTAR:
2482 env->cstar = val;
2483 break;
2484 case MSR_FMASK:
2485 env->fmask = val;
2486 break;
2487 case MSR_FSBASE:
2488 env->segs[R_FS].base = val;
2489 break;
2490 case MSR_GSBASE:
2491 env->segs[R_GS].base = val;
2492 break;
2493 case MSR_KERNELGSBASE:
2494 env->kernelgsbase = val;
2495 break;
2496#endif
2497 default:
2498 /* XXX: exception ? */
2499 break;
2500 }
2501}
2502
2503void helper_rdmsr(void)
2504{
2505 uint64_t val;
2506 switch((uint32_t)ECX) {
2507 case MSR_IA32_SYSENTER_CS:
2508 val = env->sysenter_cs;
2509 break;
2510 case MSR_IA32_SYSENTER_ESP:
2511 val = env->sysenter_esp;
2512 break;
2513 case MSR_IA32_SYSENTER_EIP:
2514 val = env->sysenter_eip;
2515 break;
2516 case MSR_IA32_APICBASE:
2517 val = cpu_get_apic_base(env);
2518 break;
2519#ifdef TARGET_X86_64
2520 case MSR_EFER:
2521 val = env->efer;
2522 break;
2523 case MSR_STAR:
2524 val = env->star;
2525 break;
2526 case MSR_LSTAR:
2527 val = env->lstar;
2528 break;
2529 case MSR_CSTAR:
2530 val = env->cstar;
2531 break;
2532 case MSR_FMASK:
2533 val = env->fmask;
2534 break;
2535 case MSR_FSBASE:
2536 val = env->segs[R_FS].base;
2537 break;
2538 case MSR_GSBASE:
2539 val = env->segs[R_GS].base;
2540 break;
2541 case MSR_KERNELGSBASE:
2542 val = env->kernelgsbase;
2543 break;
2544#endif
2545 default:
2546 /* XXX: exception ? */
2547 val = 0;
2548 break;
2549 }
2550 EAX = (uint32_t)(val);
2551 EDX = (uint32_t)(val >> 32);
2552}
2553#endif
2554
2555void helper_lsl(void)
2556{
2557 unsigned int selector, limit;
2558 uint32_t e1, e2, eflags;
2559 int rpl, dpl, cpl, type;
2560
2561 eflags = cc_table[CC_OP].compute_all();
2562 selector = T0 & 0xffff;
2563 if (load_segment(&e1, &e2, selector) != 0)
2564 goto fail;
2565 rpl = selector & 3;
2566 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2567 cpl = env->hflags & HF_CPL_MASK;
2568 if (e2 & DESC_S_MASK) {
2569 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2570 /* conforming */
2571 } else {
2572 if (dpl < cpl || dpl < rpl)
2573 goto fail;
2574 }
2575 } else {
2576 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2577 switch(type) {
2578 case 1:
2579 case 2:
2580 case 3:
2581 case 9:
2582 case 11:
2583 break;
2584 default:
2585 goto fail;
2586 }
2587 if (dpl < cpl || dpl < rpl) {
2588 fail:
2589 CC_SRC = eflags & ~CC_Z;
2590 return;
2591 }
2592 }
2593 limit = get_seg_limit(e1, e2);
2594 T1 = limit;
2595 CC_SRC = eflags | CC_Z;
2596}
2597
2598void helper_lar(void)
2599{
2600 unsigned int selector;
2601 uint32_t e1, e2, eflags;
2602 int rpl, dpl, cpl, type;
2603
2604 eflags = cc_table[CC_OP].compute_all();
2605 selector = T0 & 0xffff;
2606 if ((selector & 0xfffc) == 0)
2607 goto fail;
2608 if (load_segment(&e1, &e2, selector) != 0)
2609 goto fail;
2610 rpl = selector & 3;
2611 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2612 cpl = env->hflags & HF_CPL_MASK;
2613 if (e2 & DESC_S_MASK) {
2614 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2615 /* conforming */
2616 } else {
2617 if (dpl < cpl || dpl < rpl)
2618 goto fail;
2619 }
2620 } else {
2621 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2622 switch(type) {
2623 case 1:
2624 case 2:
2625 case 3:
2626 case 4:
2627 case 5:
2628 case 9:
2629 case 11:
2630 case 12:
2631 break;
2632 default:
2633 goto fail;
2634 }
2635 if (dpl < cpl || dpl < rpl) {
2636 fail:
2637 CC_SRC = eflags & ~CC_Z;
2638 return;
2639 }
2640 }
2641 T1 = e2 & 0x00f0ff00;
2642 CC_SRC = eflags | CC_Z;
2643}
2644
2645void helper_verr(void)
2646{
2647 unsigned int selector;
2648 uint32_t e1, e2, eflags;
2649 int rpl, dpl, cpl;
2650
2651 eflags = cc_table[CC_OP].compute_all();
2652 selector = T0 & 0xffff;
2653 if ((selector & 0xfffc) == 0)
2654 goto fail;
2655 if (load_segment(&e1, &e2, selector) != 0)
2656 goto fail;
2657 if (!(e2 & DESC_S_MASK))
2658 goto fail;
2659 rpl = selector & 3;
2660 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2661 cpl = env->hflags & HF_CPL_MASK;
2662 if (e2 & DESC_CS_MASK) {
2663 if (!(e2 & DESC_R_MASK))
2664 goto fail;
2665 if (!(e2 & DESC_C_MASK)) {
2666 if (dpl < cpl || dpl < rpl)
2667 goto fail;
2668 }
2669 } else {
2670 if (dpl < cpl || dpl < rpl) {
2671 fail:
2672 CC_SRC = eflags & ~CC_Z;
2673 return;
2674 }
2675 }
2676 CC_SRC = eflags | CC_Z;
2677}
2678
2679void helper_verw(void)
2680{
2681 unsigned int selector;
2682 uint32_t e1, e2, eflags;
2683 int rpl, dpl, cpl;
2684
2685 eflags = cc_table[CC_OP].compute_all();
2686 selector = T0 & 0xffff;
2687 if ((selector & 0xfffc) == 0)
2688 goto fail;
2689 if (load_segment(&e1, &e2, selector) != 0)
2690 goto fail;
2691 if (!(e2 & DESC_S_MASK))
2692 goto fail;
2693 rpl = selector & 3;
2694 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2695 cpl = env->hflags & HF_CPL_MASK;
2696 if (e2 & DESC_CS_MASK) {
2697 goto fail;
2698 } else {
2699 if (dpl < cpl || dpl < rpl)
2700 goto fail;
2701 if (!(e2 & DESC_W_MASK)) {
2702 fail:
2703 CC_SRC = eflags & ~CC_Z;
2704 return;
2705 }
2706 }
2707 CC_SRC = eflags | CC_Z;
2708}
2709
2710/* FPU helpers */
2711
2712void helper_fldt_ST0_A0(void)
2713{
2714 int new_fpstt;
2715 new_fpstt = (env->fpstt - 1) & 7;
2716 env->fpregs[new_fpstt].d = helper_fldt(A0);
2717 env->fpstt = new_fpstt;
2718 env->fptags[new_fpstt] = 0; /* validate stack entry */
2719}
2720
2721void helper_fstt_ST0_A0(void)
2722{
2723 helper_fstt(ST0, A0);
2724}
2725
2726void fpu_set_exception(int mask)
2727{
2728 env->fpus |= mask;
2729 if (env->fpus & (~env->fpuc & FPUC_EM))
2730 env->fpus |= FPUS_SE | FPUS_B;
2731}
2732
2733CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
2734{
2735 if (b == 0.0)
2736 fpu_set_exception(FPUS_ZE);
2737 return a / b;
2738}
2739
2740void fpu_raise_exception(void)
2741{
2742 if (env->cr[0] & CR0_NE_MASK) {
2743 raise_exception(EXCP10_COPR);
2744 }
2745#if !defined(CONFIG_USER_ONLY)
2746 else {
2747 cpu_set_ferr(env);
2748 }
2749#endif
2750}
2751
2752/* BCD ops */
2753
2754void helper_fbld_ST0_A0(void)
2755{
2756 CPU86_LDouble tmp;
2757 uint64_t val;
2758 unsigned int v;
2759 int i;
2760
2761 val = 0;
2762 for(i = 8; i >= 0; i--) {
2763 v = ldub(A0 + i);
2764 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
2765 }
2766 tmp = val;
2767 if (ldub(A0 + 9) & 0x80)
2768 tmp = -tmp;
2769 fpush();
2770 ST0 = tmp;
2771}
2772
2773void helper_fbst_ST0_A0(void)
2774{
2775 CPU86_LDouble tmp;
2776 int v;
2777 target_ulong mem_ref, mem_end;
2778 int64_t val;
2779
2780 tmp = rint(ST0);
2781 val = (int64_t)tmp;
2782 mem_ref = A0;
2783 mem_end = mem_ref + 9;
2784 if (val < 0) {
2785 stb(mem_end, 0x80);
2786 val = -val;
2787 } else {
2788 stb(mem_end, 0x00);
2789 }
2790 while (mem_ref < mem_end) {
2791 if (val == 0)
2792 break;
2793 v = val % 100;
2794 val = val / 100;
2795 v = ((v / 10) << 4) | (v % 10);
2796 stb(mem_ref++, v);
2797 }
2798 while (mem_ref < mem_end) {
2799 stb(mem_ref++, 0);
2800 }
2801}
2802
2803void helper_f2xm1(void)
2804{
2805 ST0 = pow(2.0,ST0) - 1.0;
2806}
2807
2808void helper_fyl2x(void)
2809{
2810 CPU86_LDouble fptemp;
2811
2812 fptemp = ST0;
2813 if (fptemp>0.0){
2814 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
2815 ST1 *= fptemp;
2816 fpop();
2817 } else {
2818 env->fpus &= (~0x4700);
2819 env->fpus |= 0x400;
2820 }
2821}
2822
2823void helper_fptan(void)
2824{
2825 CPU86_LDouble fptemp;
2826
2827 fptemp = ST0;
2828 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2829 env->fpus |= 0x400;
2830 } else {
2831 ST0 = tan(fptemp);
2832 fpush();
2833 ST0 = 1.0;
2834 env->fpus &= (~0x400); /* C2 <-- 0 */
2835 /* the above code is for |arg| < 2**52 only */
2836 }
2837}
2838
2839void helper_fpatan(void)
2840{
2841 CPU86_LDouble fptemp, fpsrcop;
2842
2843 fpsrcop = ST1;
2844 fptemp = ST0;
2845 ST1 = atan2(fpsrcop,fptemp);
2846 fpop();
2847}
2848
2849void helper_fxtract(void)
2850{
2851 CPU86_LDoubleU temp;
2852 unsigned int expdif;
2853
2854 temp.d = ST0;
2855 expdif = EXPD(temp) - EXPBIAS;
2856 /*DP exponent bias*/
2857 ST0 = expdif;
2858 fpush();
2859 BIASEXPONENT(temp);
2860 ST0 = temp.d;
2861}
2862
2863void helper_fprem1(void)
2864{
2865 CPU86_LDouble dblq, fpsrcop, fptemp;
2866 CPU86_LDoubleU fpsrcop1, fptemp1;
2867 int expdif;
2868 int q;
2869
2870 fpsrcop = ST0;
2871 fptemp = ST1;
2872 fpsrcop1.d = fpsrcop;
2873 fptemp1.d = fptemp;
2874 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2875 if (expdif < 53) {
2876 dblq = fpsrcop / fptemp;
2877 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2878 ST0 = fpsrcop - fptemp*dblq;
2879 q = (int)dblq; /* cutting off top bits is assumed here */
2880 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2881 /* (C0,C1,C3) <-- (q2,q1,q0) */
2882 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2883 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2884 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2885 } else {
2886 env->fpus |= 0x400; /* C2 <-- 1 */
2887 fptemp = pow(2.0, expdif-50);
2888 fpsrcop = (ST0 / ST1) / fptemp;
2889 /* fpsrcop = integer obtained by rounding to the nearest */
2890 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
2891 floor(fpsrcop): ceil(fpsrcop);
2892 ST0 -= (ST1 * fpsrcop * fptemp);
2893 }
2894}
2895
2896void helper_fprem(void)
2897{
2898 CPU86_LDouble dblq, fpsrcop, fptemp;
2899 CPU86_LDoubleU fpsrcop1, fptemp1;
2900 int expdif;
2901 int q;
2902
2903 fpsrcop = ST0;
2904 fptemp = ST1;
2905 fpsrcop1.d = fpsrcop;
2906 fptemp1.d = fptemp;
2907 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2908 if ( expdif < 53 ) {
2909 dblq = fpsrcop / fptemp;
2910 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2911 ST0 = fpsrcop - fptemp*dblq;
2912 q = (int)dblq; /* cutting off top bits is assumed here */
2913 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2914 /* (C0,C1,C3) <-- (q2,q1,q0) */
2915 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2916 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2917 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2918 } else {
2919 env->fpus |= 0x400; /* C2 <-- 1 */
2920 fptemp = pow(2.0, expdif-50);
2921 fpsrcop = (ST0 / ST1) / fptemp;
2922 /* fpsrcop = integer obtained by chopping */
2923 fpsrcop = (fpsrcop < 0.0)?
2924 -(floor(fabs(fpsrcop))): floor(fpsrcop);
2925 ST0 -= (ST1 * fpsrcop * fptemp);
2926 }
2927}
2928
2929void helper_fyl2xp1(void)
2930{
2931 CPU86_LDouble fptemp;
2932
2933 fptemp = ST0;
2934 if ((fptemp+1.0)>0.0) {
2935 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
2936 ST1 *= fptemp;
2937 fpop();
2938 } else {
2939 env->fpus &= (~0x4700);
2940 env->fpus |= 0x400;
2941 }
2942}
2943
2944void helper_fsqrt(void)
2945{
2946 CPU86_LDouble fptemp;
2947
2948 fptemp = ST0;
2949 if (fptemp<0.0) {
2950 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2951 env->fpus |= 0x400;
2952 }
2953 ST0 = sqrt(fptemp);
2954}
2955
2956void helper_fsincos(void)
2957{
2958 CPU86_LDouble fptemp;
2959
2960 fptemp = ST0;
2961 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2962 env->fpus |= 0x400;
2963 } else {
2964 ST0 = sin(fptemp);
2965 fpush();
2966 ST0 = cos(fptemp);
2967 env->fpus &= (~0x400); /* C2 <-- 0 */
2968 /* the above code is for |arg| < 2**63 only */
2969 }
2970}
2971
2972void helper_frndint(void)
2973{
2974 CPU86_LDouble a;
2975
2976 a = ST0;
2977#ifdef __arm__
2978 switch(env->fpuc & RC_MASK) {
2979 default:
2980 case RC_NEAR:
2981 asm("rndd %0, %1" : "=f" (a) : "f"(a));
2982 break;
2983 case RC_DOWN:
2984 asm("rnddm %0, %1" : "=f" (a) : "f"(a));
2985 break;
2986 case RC_UP:
2987 asm("rnddp %0, %1" : "=f" (a) : "f"(a));
2988 break;
2989 case RC_CHOP:
2990 asm("rnddz %0, %1" : "=f" (a) : "f"(a));
2991 break;
2992 }
2993#else
2994 a = rint(a);
2995#endif
2996 ST0 = a;
2997}
2998
2999void helper_fscale(void)
3000{
3001 CPU86_LDouble fpsrcop, fptemp;
3002
3003 fpsrcop = 2.0;
3004 fptemp = pow(fpsrcop,ST1);
3005 ST0 *= fptemp;
3006}
3007
3008void helper_fsin(void)
3009{
3010 CPU86_LDouble fptemp;
3011
3012 fptemp = ST0;
3013 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3014 env->fpus |= 0x400;
3015 } else {
3016 ST0 = sin(fptemp);
3017 env->fpus &= (~0x400); /* C2 <-- 0 */
3018 /* the above code is for |arg| < 2**53 only */
3019 }
3020}
3021
3022void helper_fcos(void)
3023{
3024 CPU86_LDouble fptemp;
3025
3026 fptemp = ST0;
3027 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3028 env->fpus |= 0x400;
3029 } else {
3030 ST0 = cos(fptemp);
3031 env->fpus &= (~0x400); /* C2 <-- 0 */
3032 /* the above code is for |arg5 < 2**63 only */
3033 }
3034}
3035
3036void helper_fxam_ST0(void)
3037{
3038 CPU86_LDoubleU temp;
3039 int expdif;
3040
3041 temp.d = ST0;
3042
3043 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3044 if (SIGND(temp))
3045 env->fpus |= 0x200; /* C1 <-- 1 */
3046
3047 /* XXX: test fptags too */
3048 expdif = EXPD(temp);
3049 if (expdif == MAXEXPD) {
3050#ifdef USE_X86LDOUBLE
3051 if (MANTD(temp) == 0x8000000000000000ULL)
3052#else
3053 if (MANTD(temp) == 0)
3054#endif
3055 env->fpus |= 0x500 /*Infinity*/;
3056 else
3057 env->fpus |= 0x100 /*NaN*/;
3058 } else if (expdif == 0) {
3059 if (MANTD(temp) == 0)
3060 env->fpus |= 0x4000 /*Zero*/;
3061 else
3062 env->fpus |= 0x4400 /*Denormal*/;
3063 } else {
3064 env->fpus |= 0x400;
3065 }
3066}
3067
3068void helper_fstenv(target_ulong ptr, int data32)
3069{
3070 int fpus, fptag, exp, i;
3071 uint64_t mant;
3072 CPU86_LDoubleU tmp;
3073
3074 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3075 fptag = 0;
3076 for (i=7; i>=0; i--) {
3077 fptag <<= 2;
3078 if (env->fptags[i]) {
3079 fptag |= 3;
3080 } else {
3081 tmp.d = env->fpregs[i].d;
3082 exp = EXPD(tmp);
3083 mant = MANTD(tmp);
3084 if (exp == 0 && mant == 0) {
3085 /* zero */
3086 fptag |= 1;
3087 } else if (exp == 0 || exp == MAXEXPD
3088#ifdef USE_X86LDOUBLE
3089 || (mant & (1LL << 63)) == 0
3090#endif
3091 ) {
3092 /* NaNs, infinity, denormal */
3093 fptag |= 2;
3094 }
3095 }
3096 }
3097 if (data32) {
3098 /* 32 bit */
3099 stl(ptr, env->fpuc);
3100 stl(ptr + 4, fpus);
3101 stl(ptr + 8, fptag);
3102 stl(ptr + 12, 0); /* fpip */
3103 stl(ptr + 16, 0); /* fpcs */
3104 stl(ptr + 20, 0); /* fpoo */
3105 stl(ptr + 24, 0); /* fpos */
3106 } else {
3107 /* 16 bit */
3108 stw(ptr, env->fpuc);
3109 stw(ptr + 2, fpus);
3110 stw(ptr + 4, fptag);
3111 stw(ptr + 6, 0);
3112 stw(ptr + 8, 0);
3113 stw(ptr + 10, 0);
3114 stw(ptr + 12, 0);
3115 }
3116}
3117
3118void helper_fldenv(target_ulong ptr, int data32)
3119{
3120 int i, fpus, fptag;
3121
3122 if (data32) {
3123 env->fpuc = lduw(ptr);
3124 fpus = lduw(ptr + 4);
3125 fptag = lduw(ptr + 8);
3126 }
3127 else {
3128 env->fpuc = lduw(ptr);
3129 fpus = lduw(ptr + 2);
3130 fptag = lduw(ptr + 4);
3131 }
3132 env->fpstt = (fpus >> 11) & 7;
3133 env->fpus = fpus & ~0x3800;
3134 for(i = 0;i < 8; i++) {
3135 env->fptags[i] = ((fptag & 3) == 3);
3136 fptag >>= 2;
3137 }
3138}
3139
3140void helper_fsave(target_ulong ptr, int data32)
3141{
3142 CPU86_LDouble tmp;
3143 int i;
3144
3145 helper_fstenv(ptr, data32);
3146
3147 ptr += (14 << data32);
3148 for(i = 0;i < 8; i++) {
3149 tmp = ST(i);
3150 helper_fstt(tmp, ptr);
3151 ptr += 10;
3152 }
3153
3154 /* fninit */
3155 env->fpus = 0;
3156 env->fpstt = 0;
3157 env->fpuc = 0x37f;
3158 env->fptags[0] = 1;
3159 env->fptags[1] = 1;
3160 env->fptags[2] = 1;
3161 env->fptags[3] = 1;
3162 env->fptags[4] = 1;
3163 env->fptags[5] = 1;
3164 env->fptags[6] = 1;
3165 env->fptags[7] = 1;
3166}
3167
3168void helper_frstor(target_ulong ptr, int data32)
3169{
3170 CPU86_LDouble tmp;
3171 int i;
3172
3173 helper_fldenv(ptr, data32);
3174 ptr += (14 << data32);
3175
3176 for(i = 0;i < 8; i++) {
3177 tmp = helper_fldt(ptr);
3178 ST(i) = tmp;
3179 ptr += 10;
3180 }
3181}
3182
3183void helper_fxsave(target_ulong ptr, int data64)
3184{
3185 int fpus, fptag, i, nb_xmm_regs;
3186 CPU86_LDouble tmp;
3187 target_ulong addr;
3188
3189 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3190 fptag = 0;
3191 for(i = 0; i < 8; i++) {
3192 fptag |= (env->fptags[i] << i);
3193 }
3194 stw(ptr, env->fpuc);
3195 stw(ptr + 2, fpus);
3196 stw(ptr + 4, fptag ^ 0xff);
3197
3198 addr = ptr + 0x20;
3199 for(i = 0;i < 8; i++) {
3200 tmp = ST(i);
3201 helper_fstt(tmp, addr);
3202 addr += 16;
3203 }
3204
3205 if (env->cr[4] & CR4_OSFXSR_MASK) {
3206 /* XXX: finish it */
3207 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3208 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3209 nb_xmm_regs = 8 << data64;
3210 addr = ptr + 0xa0;
3211 for(i = 0; i < nb_xmm_regs; i++) {
3212 stq(addr, env->xmm_regs[i].XMM_Q(0));
3213 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3214 addr += 16;
3215 }
3216 }
3217}
3218
3219void helper_fxrstor(target_ulong ptr, int data64)
3220{
3221 int i, fpus, fptag, nb_xmm_regs;
3222 CPU86_LDouble tmp;
3223 target_ulong addr;
3224
3225 env->fpuc = lduw(ptr);
3226 fpus = lduw(ptr + 2);
3227 fptag = lduw(ptr + 4);
3228 env->fpstt = (fpus >> 11) & 7;
3229 env->fpus = fpus & ~0x3800;
3230 fptag ^= 0xff;
3231 for(i = 0;i < 8; i++) {
3232 env->fptags[i] = ((fptag >> i) & 1);
3233 }
3234
3235 addr = ptr + 0x20;
3236 for(i = 0;i < 8; i++) {
3237 tmp = helper_fldt(addr);
3238 ST(i) = tmp;
3239 addr += 16;
3240 }
3241
3242 if (env->cr[4] & CR4_OSFXSR_MASK) {
3243 /* XXX: finish it, endianness */
3244 env->mxcsr = ldl(ptr + 0x18);
3245 //ldl(ptr + 0x1c);
3246 nb_xmm_regs = 8 << data64;
3247 addr = ptr + 0xa0;
3248 for(i = 0; i < nb_xmm_regs; i++) {
3249#if !defined(VBOX) || __GNUC__ < 4
3250 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3251 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3252#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3253# if 1
3254 env->xmm_regs[i].XMM_L(0) = ldl(addr);
3255 env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3256 env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3257 env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3258# else
3259 /* this works fine on Mac OS X, gcc 4.0.1 */
3260 uint64_t u64 = ldq(addr);
3261 env->xmm_regs[i].XMM_Q(0);
3262 u64 = ldq(addr + 4);
3263 env->xmm_regs[i].XMM_Q(1) = u64;
3264# endif
3265#endif
3266 addr += 16;
3267 }
3268 }
3269}
3270
3271#ifndef USE_X86LDOUBLE
3272
3273void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3274{
3275 CPU86_LDoubleU temp;
3276 int e;
3277
3278 temp.d = f;
3279 /* mantissa */
3280 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3281 /* exponent + sign */
3282 e = EXPD(temp) - EXPBIAS + 16383;
3283 e |= SIGND(temp) >> 16;
3284 *pexp = e;
3285}
3286
3287CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3288{
3289 CPU86_LDoubleU temp;
3290 int e;
3291 uint64_t ll;
3292
3293 /* XXX: handle overflow ? */
3294 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3295 e |= (upper >> 4) & 0x800; /* sign */
3296 ll = (mant >> 11) & ((1LL << 52) - 1);
3297#ifdef __arm__
3298 temp.l.upper = (e << 20) | (ll >> 32);
3299 temp.l.lower = ll;
3300#else
3301 temp.ll = ll | ((uint64_t)e << 52);
3302#endif
3303 return temp.d;
3304}
3305
3306#else
3307
3308void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3309{
3310 CPU86_LDoubleU temp;
3311
3312 temp.d = f;
3313 *pmant = temp.l.lower;
3314 *pexp = temp.l.upper;
3315}
3316
3317CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3318{
3319 CPU86_LDoubleU temp;
3320
3321 temp.l.upper = upper;
3322 temp.l.lower = mant;
3323 return temp.d;
3324}
3325#endif
3326
3327#ifdef TARGET_X86_64
3328
3329//#define DEBUG_MULDIV
3330
3331static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3332{
3333 *plow += a;
3334 /* carry test */
3335 if (*plow < a)
3336 (*phigh)++;
3337 *phigh += b;
3338}
3339
3340static void neg128(uint64_t *plow, uint64_t *phigh)
3341{
3342 *plow = ~ *plow;
3343 *phigh = ~ *phigh;
3344 add128(plow, phigh, 1, 0);
3345}
3346
3347static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3348{
3349 uint32_t a0, a1, b0, b1;
3350 uint64_t v;
3351
3352 a0 = a;
3353 a1 = a >> 32;
3354
3355 b0 = b;
3356 b1 = b >> 32;
3357
3358 v = (uint64_t)a0 * (uint64_t)b0;
3359 *plow = v;
3360 *phigh = 0;
3361
3362 v = (uint64_t)a0 * (uint64_t)b1;
3363 add128(plow, phigh, v << 32, v >> 32);
3364
3365 v = (uint64_t)a1 * (uint64_t)b0;
3366 add128(plow, phigh, v << 32, v >> 32);
3367
3368 v = (uint64_t)a1 * (uint64_t)b1;
3369 *phigh += v;
3370#ifdef DEBUG_MULDIV
3371 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
3372 a, b, *phigh, *plow);
3373#endif
3374}
3375
3376static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3377{
3378 int sa, sb;
3379 sa = (a < 0);
3380 if (sa)
3381 a = -a;
3382 sb = (b < 0);
3383 if (sb)
3384 b = -b;
3385 mul64(plow, phigh, a, b);
3386 if (sa ^ sb) {
3387 neg128(plow, phigh);
3388 }
3389}
3390
3391/* return TRUE if overflow */
3392static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3393{
3394 uint64_t q, r, a1, a0;
3395 int i, qb, ab;
3396
3397 a0 = *plow;
3398 a1 = *phigh;
3399 if (a1 == 0) {
3400 q = a0 / b;
3401 r = a0 % b;
3402 *plow = q;
3403 *phigh = r;
3404 } else {
3405 if (a1 >= b)
3406 return 1;
3407 /* XXX: use a better algorithm */
3408 for(i = 0; i < 64; i++) {
3409 ab = a1 >> 63;
3410 a1 = (a1 << 1) | (a0 >> 63);
3411 if (ab || a1 >= b) {
3412 a1 -= b;
3413 qb = 1;
3414 } else {
3415 qb = 0;
3416 }
3417 a0 = (a0 << 1) | qb;
3418 }
3419#if defined(DEBUG_MULDIV)
3420 printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n",
3421 *phigh, *plow, b, a0, a1);
3422#endif
3423 *plow = a0;
3424 *phigh = a1;
3425 }
3426 return 0;
3427}
3428
3429/* return TRUE if overflow */
3430static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
3431{
3432 int sa, sb;
3433 sa = ((int64_t)*phigh < 0);
3434 if (sa)
3435 neg128(plow, phigh);
3436 sb = (b < 0);
3437 if (sb)
3438 b = -b;
3439 if (div64(plow, phigh, b) != 0)
3440 return 1;
3441 if (sa ^ sb) {
3442 if (*plow > (1ULL << 63))
3443 return 1;
3444 *plow = - *plow;
3445 } else {
3446 if (*plow >= (1ULL << 63))
3447 return 1;
3448 }
3449 if (sa)
3450 *phigh = - *phigh;
3451 return 0;
3452}
3453
3454void helper_mulq_EAX_T0(void)
3455{
3456 uint64_t r0, r1;
3457
3458 mul64(&r0, &r1, EAX, T0);
3459 EAX = r0;
3460 EDX = r1;
3461 CC_DST = r0;
3462 CC_SRC = r1;
3463}
3464
3465void helper_imulq_EAX_T0(void)
3466{
3467 uint64_t r0, r1;
3468
3469 imul64(&r0, &r1, EAX, T0);
3470 EAX = r0;
3471 EDX = r1;
3472 CC_DST = r0;
3473 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3474}
3475
3476void helper_imulq_T0_T1(void)
3477{
3478 uint64_t r0, r1;
3479
3480 imul64(&r0, &r1, T0, T1);
3481 T0 = r0;
3482 CC_DST = r0;
3483 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3484}
3485
3486void helper_divq_EAX_T0(void)
3487{
3488 uint64_t r0, r1;
3489 if (T0 == 0) {
3490 raise_exception(EXCP00_DIVZ);
3491 }
3492 r0 = EAX;
3493 r1 = EDX;
3494 if (div64(&r0, &r1, T0))
3495 raise_exception(EXCP00_DIVZ);
3496 EAX = r0;
3497 EDX = r1;
3498}
3499
3500void helper_idivq_EAX_T0(void)
3501{
3502 uint64_t r0, r1;
3503 if (T0 == 0) {
3504 raise_exception(EXCP00_DIVZ);
3505 }
3506 r0 = EAX;
3507 r1 = EDX;
3508 if (idiv64(&r0, &r1, T0))
3509 raise_exception(EXCP00_DIVZ);
3510 EAX = r0;
3511 EDX = r1;
3512}
3513
3514#endif
3515
3516/* XXX: do it */
3517int fpu_isnan(double a)
3518{
3519 return 0;
3520}
3521
3522void helper_hlt(void)
3523{
3524 env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
3525 env->exception_index = EXCP_HLT;
3526 cpu_loop_exit();
3527}
3528
3529void helper_monitor(void)
3530{
3531 if (ECX != 0)
3532 raise_exception(EXCP0D_GPF);
3533 /* XXX: store address ? */
3534}
3535
3536void helper_mwait(void)
3537{
3538 if (ECX != 0)
3539 raise_exception(EXCP0D_GPF);
3540#ifdef VBOX
3541 helper_hlt();
3542#else
3543 /* XXX: not complete but not completely erroneous */
3544 if (env->cpu_index != 0 || env->next_cpu != NULL) {
3545 /* more than one CPU: do not sleep because another CPU may
3546 wake this one */
3547 } else {
3548 helper_hlt();
3549 }
3550#endif
3551}
3552
3553float approx_rsqrt(float a)
3554{
3555 return 1.0 / sqrt(a);
3556}
3557
3558float approx_rcp(float a)
3559{
3560 return 1.0 / a;
3561}
3562
3563/* XXX: find a better solution */
3564double helper_sqrt(double a)
3565{
3566 return sqrt(a);
3567}
3568
3569#if !defined(CONFIG_USER_ONLY)
3570
3571#define MMUSUFFIX _mmu
3572#define GETPC() (__builtin_return_address(0))
3573
3574#define SHIFT 0
3575#include "softmmu_template.h"
3576
3577#define SHIFT 1
3578#include "softmmu_template.h"
3579
3580#define SHIFT 2
3581#include "softmmu_template.h"
3582
3583#define SHIFT 3
3584#include "softmmu_template.h"
3585
3586#endif
3587
3588/* try to fill the TLB and return an exception if error. If retaddr is
3589 NULL, it means that the function was called in C code (i.e. not
3590 from generated code or from helper.c) */
3591/* XXX: fix it to restore all registers */
3592void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
3593{
3594 TranslationBlock *tb;
3595 int ret;
3596 unsigned long pc;
3597 CPUX86State *saved_env;
3598
3599 /* XXX: hack to restore env in all cases, even if not called from
3600 generated code */
3601 saved_env = env;
3602 env = cpu_single_env;
3603
3604 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
3605 if (ret) {
3606 if (retaddr) {
3607 /* now we have a real cpu fault */
3608 pc = (unsigned long)retaddr;
3609 tb = tb_find_pc(pc);
3610 if (tb) {
3611 /* the PC is inside the translated code. It means that we have
3612 a virtual CPU fault */
3613 cpu_restore_state(tb, env, pc, NULL);
3614 }
3615 }
3616 if (retaddr)
3617 raise_exception_err(EXCP0E_PAGE, env->error_code);
3618 else {
3619 raise_exception_err_norestore(EXCP0E_PAGE, env->error_code);
3620 }
3621 }
3622 env = saved_env;
3623}
3624
3625#if defined(VBOX)
3626
3627/**
3628 * Correctly computes the eflags.
3629 * @returns eflags.
3630 * @param env1 CPU environment.
3631 */
3632uint32_t raw_compute_eflags(CPUX86State *env1)
3633{
3634 CPUX86State *savedenv = env;
3635 env = env1;
3636 uint32_t efl = compute_eflags();
3637 env = savedenv;
3638 return efl;
3639}
3640
3641/**
3642 * Reads byte from virtual address in guest memory area.
3643 * XXX: is it working for any addresses? swapped out pages?
3644 * @returns readed data byte.
3645 * @param env1 CPU environment.
3646 * @param pvAddr GC Virtual address.
3647 */
3648uint8_t read_byte(CPUX86State *env1, target_ulong addr)
3649{
3650 CPUX86State *savedenv = env;
3651 env = env1;
3652 uint8_t u8 = ldub_kernel(addr);
3653 env = savedenv;
3654 return u8;
3655}
3656
3657/**
3658 * Reads byte from virtual address in guest memory area.
3659 * XXX: is it working for any addresses? swapped out pages?
3660 * @returns readed data byte.
3661 * @param env1 CPU environment.
3662 * @param pvAddr GC Virtual address.
3663 */
3664uint16_t read_word(CPUX86State *env1, target_ulong addr)
3665{
3666 CPUX86State *savedenv = env;
3667 env = env1;
3668 uint16_t u16 = lduw_kernel(addr);
3669 env = savedenv;
3670 return u16;
3671}
3672
3673/**
3674 * Reads byte from virtual address in guest memory area.
3675 * XXX: is it working for any addresses? swapped out pages?
3676 * @returns readed data byte.
3677 * @param env1 CPU environment.
3678 * @param pvAddr GC Virtual address.
3679 */
3680uint32_t read_dword(CPUX86State *env1, target_ulong addr)
3681{
3682 CPUX86State *savedenv = env;
3683 env = env1;
3684 uint32_t u32 = ldl_kernel(addr);
3685 env = savedenv;
3686 return u32;
3687}
3688
3689/**
3690 * Writes byte to virtual address in guest memory area.
3691 * XXX: is it working for any addresses? swapped out pages?
3692 * @returns readed data byte.
3693 * @param env1 CPU environment.
3694 * @param pvAddr GC Virtual address.
3695 * @param val byte value
3696 */
3697void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
3698{
3699 CPUX86State *savedenv = env;
3700 env = env1;
3701 stb(addr, val);
3702 env = savedenv;
3703}
3704
3705void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
3706{
3707 CPUX86State *savedenv = env;
3708 env = env1;
3709 stw(addr, val);
3710 env = savedenv;
3711}
3712
3713void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
3714{
3715 CPUX86State *savedenv = env;
3716 env = env1;
3717 stl(addr, val);
3718 env = savedenv;
3719}
3720
3721/**
3722 * Correctly loads selector into segment register with updating internal
3723 * qemu data/caches.
3724 * @param env1 CPU environment.
3725 * @param seg_reg Segment register.
3726 * @param selector Selector to load.
3727 */
3728void sync_seg(CPUX86State *env1, int seg_reg, int selector)
3729{
3730 CPUX86State *savedenv = env;
3731 env = env1;
3732#ifdef VBOX
3733 if (setjmp(env1->jmp_env) == 0)
3734 {
3735#endif
3736 if (seg_reg == R_CS)
3737 {
3738 uint32_t e1, e2;
3739 load_segment(&e1, &e2, selector);
3740 cpu_x86_load_seg_cache(env, R_CS, selector,
3741 get_seg_base(e1, e2),
3742 get_seg_limit(e1, e2),
3743 e2);
3744 }
3745 else
3746 load_seg(seg_reg, selector);
3747 env = savedenv;
3748
3749#ifdef VBOX
3750 /* Successful sync. */
3751 env1->segs[seg_reg].newselector = 0;
3752 }
3753 else
3754 {
3755 env = savedenv;
3756
3757 /* Postpone sync until the guest uses the selector. */
3758 env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
3759 env1->segs[seg_reg].newselector = selector;
3760#ifdef VBOX_STRICT
3761 printf("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector);
3762#endif
3763 }
3764#endif
3765
3766}
3767
3768
3769/**
3770 * Correctly loads a new ldtr selector.
3771 *
3772 * @param env1 CPU environment.
3773 * @param selector Selector to load.
3774 */
3775void sync_ldtr(CPUX86State *env1, int selector)
3776{
3777 CPUX86State *saved_env = env;
3778 target_ulong saved_T0 = T0;
3779#ifdef VBOX
3780 if (setjmp(env1->jmp_env) == 0)
3781 {
3782#endif
3783 env = env1;
3784 T0 = selector;
3785 helper_lldt_T0();
3786 T0 = saved_T0;
3787 env = saved_env;
3788#ifdef VBOX
3789 }
3790 else
3791 {
3792 T0 = saved_T0;
3793 env = saved_env;
3794#ifdef VBOX_STRICT
3795 cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
3796#endif
3797 }
3798#endif
3799}
3800
3801/**
3802 * Correctly loads a new tr selector.
3803 *
3804 * @param env1 CPU environment.
3805 * @param selector Selector to load.
3806 */
3807int sync_tr(CPUX86State *env1, int selector)
3808{
3809 /* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
3810 SegmentCache *dt;
3811 uint32_t e1, e2;
3812 int index, type, entry_limit;
3813 target_ulong ptr;
3814 CPUX86State *saved_env = env;
3815 env = env1;
3816
3817 selector &= 0xffff;
3818 if ((selector & 0xfffc) == 0) {
3819 /* NULL selector case: invalid TR */
3820 env->tr.base = 0;
3821 env->tr.limit = 0;
3822 env->tr.flags = 0;
3823 } else {
3824 if (selector & 0x4)
3825 goto l_failure;
3826 dt = &env->gdt;
3827 index = selector & ~7;
3828#ifdef TARGET_X86_64
3829 if (env->hflags & HF_LMA_MASK)
3830 entry_limit = 15;
3831 else
3832#endif
3833 entry_limit = 7;
3834 if ((index + entry_limit) > dt->limit)
3835 goto l_failure;
3836 ptr = dt->base + index;
3837 e1 = ldl_kernel(ptr);
3838 e2 = ldl_kernel(ptr + 4);
3839 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3840 if ((e2 & DESC_S_MASK) /*||
3841 (type != 1 && type != 9)*/)
3842 goto l_failure;
3843 if (!(e2 & DESC_P_MASK))
3844 goto l_failure;
3845#ifdef TARGET_X86_64
3846 if (env->hflags & HF_LMA_MASK) {
3847 uint32_t e3;
3848 e3 = ldl_kernel(ptr + 8);
3849 load_seg_cache_raw_dt(&env->tr, e1, e2);
3850 env->tr.base |= (target_ulong)e3 << 32;
3851 } else
3852#endif
3853 {
3854 load_seg_cache_raw_dt(&env->tr, e1, e2);
3855 }
3856 e2 |= DESC_TSS_BUSY_MASK;
3857 stl_kernel(ptr + 4, e2);
3858 }
3859 env->tr.selector = selector;
3860
3861 env = saved_env;
3862 return 0;
3863l_failure:
3864 AssertMsgFailed(("selector=%d\n", selector));
3865 return -1;
3866}
3867
3868int emulate_single_instr(CPUX86State *env1)
3869{
3870 TranslationBlock *current;
3871 TranslationBlock tb_temp;
3872 int csize;
3873 void (*gen_func)(void);
3874 uint8_t *pvCode;
3875 uint32_t old_eip;
3876
3877 /* ensures env is loaded in ebp! */
3878 CPUX86State *savedenv = env;
3879 env = env1;
3880
3881 RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
3882
3883 pvCode = env->pvCodeBuffer;
3884
3885 // Setup temporary translation block
3886 tb_temp.hash_next = 0;
3887 tb_temp.jmp_first = 0;
3888 tb_temp.jmp_next[0] = 0;
3889 tb_temp.jmp_next[1] = 0;
3890 tb_temp.page_addr[0] = 0;
3891 tb_temp.page_addr[1] = 0;
3892 tb_temp.page_next[0] = 0;
3893 tb_temp.page_next[1] = 0;
3894 tb_temp.hash_next = 0;
3895
3896 tb_temp.tb_next_offset[0] = 0xffff;
3897 tb_temp.tb_next_offset[1] = 0xffff;
3898
3899 tb_temp.cs_base = (unsigned long)env->segs[R_CS].base;
3900 tb_temp.pc = tb_temp.cs_base + env->eip;
3901 tb_temp.cflags = 0;
3902 tb_temp.flags = env->hflags;
3903 tb_temp.flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
3904 tb_temp.tc_ptr = pvCode;
3905
3906 current = env->current_tb;
3907 env->current_tb = NULL;
3908
3909 // Translate only one instruction
3910 ASMAtomicOrS32(&env->state, CPU_EMULATE_SINGLE_INSTR);
3911 if (cpu_gen_code(env, &tb_temp, env->cbCodeBuffer, &csize) < 0)
3912 {
3913 AssertFailed();
3914 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
3915 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
3916 env = savedenv;
3917 return -1;
3918 }
3919#ifdef DEBUG
3920 if(csize > env->cbCodeBuffer)
3921 {
3922 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
3923 AssertFailed();
3924 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
3925 env = savedenv;
3926 return -1;
3927 }
3928 if (tb_temp.tc_ptr != pvCode)
3929 {
3930 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
3931 AssertFailed();
3932 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
3933 env = savedenv;
3934 return -1;
3935 }
3936#endif
3937 ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
3938
3939 tb_link(&tb_temp);
3940
3941 old_eip = env->eip;
3942 // Execute it using emulation
3943 gen_func = (void *)tb_temp.tc_ptr;
3944 env->current_tb = &tb_temp;
3945
3946 // eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
3947 // perhaps not a very safe hack
3948 while(old_eip == env->eip)
3949 {
3950 gen_func();
3951 /*
3952 * Exit once we detect an external interrupt and interrupts are enabled
3953 */
3954 if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT|CPU_INTERRUPT_EXTERNAL_TIMER)) ||
3955 ( (env->eflags & IF_MASK) &&
3956 !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
3957 (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
3958 {
3959 break;
3960 }
3961 }
3962 env->current_tb = current;
3963
3964 RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
3965
3966 if (env->hflags & HF_INHIBIT_IRQ_MASK)
3967 {
3968 Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK)\n"));
3969 env->hflags &= ~HF_INHIBIT_IRQ_MASK;
3970 emulate_single_instr(env);
3971 }
3972
3973 env = savedenv;
3974 return 0;
3975}
3976
3977int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr,
3978 uint32_t *esp_ptr, int dpl)
3979{
3980 int type, index, shift;
3981
3982 CPUX86State *savedenv = env;
3983 env = env1;
3984
3985 if (!(env->tr.flags & DESC_P_MASK))
3986 cpu_abort(env, "invalid tss");
3987 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
3988 if ((type & 7) != 1)
3989 cpu_abort(env, "invalid tss type %d", type);
3990 shift = type >> 3;
3991 index = (dpl * 4 + 2) << shift;
3992 if (index + (4 << shift) - 1 > env->tr.limit)
3993 {
3994 env = savedenv;
3995 return 0;
3996 }
3997 //raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
3998
3999 if (shift == 0) {
4000 *esp_ptr = lduw_kernel(env->tr.base + index);
4001 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
4002 } else {
4003 *esp_ptr = ldl_kernel(env->tr.base + index);
4004 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
4005 }
4006
4007 env = savedenv;
4008 return 1;
4009}
4010
4011//*****************************************************************************
4012// Needs to be at the bottom of the file (overriding macros)
4013
4014static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4015{
4016 return *(CPU86_LDouble *)ptr;
4017}
4018
4019static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4020{
4021 *(CPU86_LDouble *)ptr = f;
4022}
4023
4024#undef stw
4025#undef stl
4026#undef stq
4027#define stw(a,b) *(uint16_t *)(a) = (uint16_t)(b)
4028#define stl(a,b) *(uint32_t *)(a) = (uint32_t)(b)
4029#define stq(a,b) *(uint64_t *)(a) = (uint64_t)(b)
4030#define data64 0
4031
4032//*****************************************************************************
4033void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr)
4034{
4035 int fpus, fptag, i, nb_xmm_regs;
4036 CPU86_LDouble tmp;
4037 uint8_t *addr;
4038
4039 if (env->cpuid_features & CPUID_FXSR)
4040 {
4041 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
4042 fptag = 0;
4043 for(i = 0; i < 8; i++) {
4044 fptag |= (env->fptags[i] << i);
4045 }
4046 stw(ptr, env->fpuc);
4047 stw(ptr + 2, fpus);
4048 stw(ptr + 4, fptag ^ 0xff);
4049
4050 addr = ptr + 0x20;
4051 for(i = 0;i < 8; i++) {
4052 tmp = ST(i);
4053 helper_fstt_raw(tmp, addr);
4054 addr += 16;
4055 }
4056
4057 if (env->cr[4] & CR4_OSFXSR_MASK) {
4058 /* XXX: finish it */
4059 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4060 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4061 nb_xmm_regs = 8 << data64;
4062 addr = ptr + 0xa0;
4063 for(i = 0; i < nb_xmm_regs; i++) {
4064#if __GNUC__ < 4
4065 stq(addr, env->xmm_regs[i].XMM_Q(0));
4066 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4067#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4068 stl(addr, env->xmm_regs[i].XMM_L(0));
4069 stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4070 stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4071 stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4072#endif
4073 addr += 16;
4074 }
4075 }
4076 }
4077 else
4078 {
4079 PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4080 int fptag;
4081
4082 fp->FCW = env->fpuc;
4083 fp->FSW = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
4084 fptag = 0;
4085 for (i=7; i>=0; i--) {
4086 fptag <<= 2;
4087 if (env->fptags[i]) {
4088 fptag |= 3;
4089 } else {
4090 /* the FPU automatically computes it */
4091 }
4092 }
4093 fp->FTW = fptag;
4094
4095 for(i = 0;i < 8; i++) {
4096 tmp = ST(i);
4097 helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4098 }
4099 }
4100}
4101
4102//*****************************************************************************
4103#undef lduw
4104#undef ldl
4105#undef ldq
4106#define lduw(a) *(uint16_t *)(a)
4107#define ldl(a) *(uint32_t *)(a)
4108#define ldq(a) *(uint64_t *)(a)
4109//*****************************************************************************
4110void save_raw_fp_state(CPUX86State *env, uint8_t *ptr)
4111{
4112 int i, fpus, fptag, nb_xmm_regs;
4113 CPU86_LDouble tmp;
4114 uint8_t *addr;
4115
4116 if (env->cpuid_features & CPUID_FXSR)
4117 {
4118 env->fpuc = lduw(ptr);
4119 fpus = lduw(ptr + 2);
4120 fptag = lduw(ptr + 4);
4121 env->fpstt = (fpus >> 11) & 7;
4122 env->fpus = fpus & ~0x3800;
4123 fptag ^= 0xff;
4124 for(i = 0;i < 8; i++) {
4125 env->fptags[i] = ((fptag >> i) & 1);
4126 }
4127
4128 addr = ptr + 0x20;
4129 for(i = 0;i < 8; i++) {
4130 tmp = helper_fldt_raw(addr);
4131 ST(i) = tmp;
4132 addr += 16;
4133 }
4134
4135 if (env->cr[4] & CR4_OSFXSR_MASK) {
4136 /* XXX: finish it, endianness */
4137 env->mxcsr = ldl(ptr + 0x18);
4138 //ldl(ptr + 0x1c);
4139 nb_xmm_regs = 8 << data64;
4140 addr = ptr + 0xa0;
4141 for(i = 0; i < nb_xmm_regs; i++) {
4142 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4143 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4144 addr += 16;
4145 }
4146 }
4147 }
4148 else
4149 {
4150 PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4151 int fptag, j;
4152
4153 env->fpuc = fp->FCW;
4154 env->fpstt = (fp->FSW >> 11) & 7;
4155 env->fpus = fp->FSW & ~0x3800;
4156 fptag = fp->FTW;
4157 for(i = 0;i < 8; i++) {
4158 env->fptags[i] = ((fptag & 3) == 3);
4159 fptag >>= 2;
4160 }
4161 j = env->fpstt;
4162 for(i = 0;i < 8; i++) {
4163 tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4164 ST(i) = tmp;
4165 }
4166 }
4167}
4168//*****************************************************************************
4169//*****************************************************************************
4170
4171#endif
4172
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