VirtualBox

source: vbox/trunk/src/recompiler/target-i386/cpu.h@ 47678

Last change on this file since 47678 was 47678, checked in by vboxsync, 11 years ago

recompiler: Clear the unusable bit when the present bit is set.

  • Property svn:eol-style set to native
File size: 34.8 KB
Line 
1/*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
22 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
23 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
24 * a choice of LGPL license versions is made available with the language indicating
25 * that LGPLv2 or any later version may be used, or where a choice of which version
26 * of the LGPL is applied is otherwise unspecified.
27 */
28
29#ifndef CPU_I386_H
30#define CPU_I386_H
31
32#include "config.h"
33
34#ifdef TARGET_X86_64
35#define TARGET_LONG_BITS 64
36#else
37#define TARGET_LONG_BITS 32
38#endif
39
40/* target supports implicit self modifying code */
41#define TARGET_HAS_SMC
42/* support for self modifying code even if the modified instruction is
43 close to the modifying instruction */
44#define TARGET_HAS_PRECISE_SMC
45
46#define TARGET_HAS_ICE 1
47
48#ifdef TARGET_X86_64
49#define ELF_MACHINE EM_X86_64
50#else
51#define ELF_MACHINE EM_386
52#endif
53
54#define CPUState struct CPUX86State
55
56#include "cpu-defs.h"
57
58#include "softfloat.h"
59
60#ifdef VBOX
61# include <iprt/critsect.h>
62# include <iprt/thread.h>
63# include <iprt/assert.h>
64# include <iprt/asm.h>
65# include <VBox/vmm/vmm.h>
66# include <VBox/vmm/stam.h>
67# include <VBox/vmm/cpumctx.h>
68#endif /* VBOX */
69
70#define R_EAX 0
71#define R_ECX 1
72#define R_EDX 2
73#define R_EBX 3
74#define R_ESP 4
75#define R_EBP 5
76#define R_ESI 6
77#define R_EDI 7
78
79#define R_AL 0
80#define R_CL 1
81#define R_DL 2
82#define R_BL 3
83#define R_AH 4
84#define R_CH 5
85#define R_DH 6
86#define R_BH 7
87
88#define R_ES 0
89#define R_CS 1
90#define R_SS 2
91#define R_DS 3
92#define R_FS 4
93#define R_GS 5
94
95/* segment descriptor fields */
96#define DESC_G_MASK (1 << 23)
97#define DESC_B_SHIFT 22
98#define DESC_B_MASK (1 << DESC_B_SHIFT)
99#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
100#define DESC_L_MASK (1 << DESC_L_SHIFT)
101#define DESC_AVL_MASK (1 << 20)
102#define DESC_P_MASK (1 << 15)
103#define DESC_DPL_SHIFT 13
104#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
105#define DESC_S_MASK (1 << 12)
106#define DESC_TYPE_SHIFT 8
107#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
108#define DESC_A_MASK (1 << 8)
109
110#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
111#define DESC_C_MASK (1 << 10) /* code: conforming */
112#define DESC_R_MASK (1 << 9) /* code: readable */
113
114#define DESC_E_MASK (1 << 10) /* data: expansion direction */
115#define DESC_W_MASK (1 << 9) /* data: writable */
116
117#define DESC_TSS_BUSY_MASK (1 << 9)
118#ifdef VBOX
119# define DESC_INTEL_UNUSABLE RT_BIT_32(16+8) /**< Internal VT-x bit for NULL sectors. */
120#endif
121
122/* eflags masks */
123#define CC_C 0x0001
124#define CC_P 0x0004
125#define CC_A 0x0010
126#define CC_Z 0x0040
127#define CC_S 0x0080
128#define CC_O 0x0800
129
130#define TF_SHIFT 8
131#define IOPL_SHIFT 12
132#define VM_SHIFT 17
133
134#define TF_MASK 0x00000100
135#define IF_MASK 0x00000200
136#define DF_MASK 0x00000400
137#define IOPL_MASK 0x00003000
138#define NT_MASK 0x00004000
139#define RF_MASK 0x00010000
140#define VM_MASK 0x00020000
141#define AC_MASK 0x00040000
142#define VIF_MASK 0x00080000
143#define VIP_MASK 0x00100000
144#define ID_MASK 0x00200000
145
146/* hidden flags - used internally by qemu to represent additional cpu
147 states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
148 redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
149 position to ease oring with eflags. */
150/* current cpl */
151#define HF_CPL_SHIFT 0
152/* true if soft mmu is being used */
153#define HF_SOFTMMU_SHIFT 2
154/* true if hardware interrupts must be disabled for next instruction */
155#define HF_INHIBIT_IRQ_SHIFT 3
156/* 16 or 32 segments */
157#define HF_CS32_SHIFT 4
158#define HF_SS32_SHIFT 5
159/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
160#define HF_ADDSEG_SHIFT 6
161/* copy of CR0.PE (protected mode) */
162#define HF_PE_SHIFT 7
163#define HF_TF_SHIFT 8 /* must be same as eflags */
164#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
165#define HF_EM_SHIFT 10
166#define HF_TS_SHIFT 11
167#define HF_IOPL_SHIFT 12 /* must be same as eflags */
168#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
169#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
170#define HF_RF_SHIFT 16 /* must be same as eflags */
171#define HF_VM_SHIFT 17 /* must be same as eflags */
172#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
173#define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
174#define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
175#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
176
177#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
178#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
179#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
180#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
181#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
182#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
183#define HF_PE_MASK (1 << HF_PE_SHIFT)
184#define HF_TF_MASK (1 << HF_TF_SHIFT)
185#define HF_MP_MASK (1 << HF_MP_SHIFT)
186#define HF_EM_MASK (1 << HF_EM_SHIFT)
187#define HF_TS_MASK (1 << HF_TS_SHIFT)
188#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
189#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
190#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
191#define HF_RF_MASK (1 << HF_RF_SHIFT)
192#define HF_VM_MASK (1 << HF_VM_SHIFT)
193#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
194#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
195#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
196#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
197
198/* hflags2 */
199
200#define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
201#define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
202#define HF2_NMI_SHIFT 2 /* CPU serving NMI */
203#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
204
205#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
206#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
207#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
208#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
209
210#define CR0_PE_SHIFT 0
211#define CR0_MP_SHIFT 1
212
213#define CR0_PE_MASK (1 << 0)
214#define CR0_MP_MASK (1 << 1)
215#define CR0_EM_MASK (1 << 2)
216#define CR0_TS_MASK (1 << 3)
217#define CR0_ET_MASK (1 << 4)
218#define CR0_NE_MASK (1 << 5)
219#define CR0_WP_MASK (1 << 16)
220#define CR0_AM_MASK (1 << 18)
221#define CR0_PG_MASK (1 << 31)
222
223#define CR4_VME_MASK (1 << 0)
224#define CR4_PVI_MASK (1 << 1)
225#define CR4_TSD_MASK (1 << 2)
226#define CR4_DE_MASK (1 << 3)
227#define CR4_PSE_MASK (1 << 4)
228#define CR4_PAE_MASK (1 << 5)
229#define CR4_MCE_MASK (1 << 6)
230#define CR4_PGE_MASK (1 << 7)
231#define CR4_PCE_MASK (1 << 8)
232#define CR4_OSFXSR_SHIFT 9
233#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
234#define CR4_OSXMMEXCPT_MASK (1 << 10)
235
236#define DR6_BD (1 << 13)
237#define DR6_BS (1 << 14)
238#define DR6_BT (1 << 15)
239#define DR6_FIXED_1 0xffff0ff0
240
241#define DR7_GD (1 << 13)
242#define DR7_TYPE_SHIFT 16
243#define DR7_LEN_SHIFT 18
244#define DR7_FIXED_1 0x00000400
245
246#define PG_PRESENT_BIT 0
247#define PG_RW_BIT 1
248#define PG_USER_BIT 2
249#define PG_PWT_BIT 3
250#define PG_PCD_BIT 4
251#define PG_ACCESSED_BIT 5
252#define PG_DIRTY_BIT 6
253#define PG_PSE_BIT 7
254#define PG_GLOBAL_BIT 8
255#define PG_NX_BIT 63
256
257#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
258#define PG_RW_MASK (1 << PG_RW_BIT)
259#define PG_USER_MASK (1 << PG_USER_BIT)
260#define PG_PWT_MASK (1 << PG_PWT_BIT)
261#define PG_PCD_MASK (1 << PG_PCD_BIT)
262#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
263#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
264#define PG_PSE_MASK (1 << PG_PSE_BIT)
265#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
266#define PG_NX_MASK (1LL << PG_NX_BIT)
267
268#define PG_ERROR_W_BIT 1
269
270#define PG_ERROR_P_MASK 0x01
271#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
272#define PG_ERROR_U_MASK 0x04
273#define PG_ERROR_RSVD_MASK 0x08
274#define PG_ERROR_I_D_MASK 0x10
275
276#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
277
278#define MCE_CAP_DEF MCG_CTL_P
279#define MCE_BANKS_DEF 10
280
281#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
282
283#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
284#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
285#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
286
287#define MSR_IA32_TSC 0x10
288#define MSR_IA32_APICBASE 0x1b
289#define MSR_IA32_APICBASE_BSP (1<<8)
290#define MSR_IA32_APICBASE_ENABLE (1<<11)
291#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
292
293#define MSR_MTRRcap 0xfe
294#define MSR_MTRRcap_VCNT 8
295#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
296#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
297
298#define MSR_IA32_SYSENTER_CS 0x174
299#define MSR_IA32_SYSENTER_ESP 0x175
300#define MSR_IA32_SYSENTER_EIP 0x176
301
302#define MSR_MCG_CAP 0x179
303#define MSR_MCG_STATUS 0x17a
304#define MSR_MCG_CTL 0x17b
305
306#define MSR_IA32_PERF_STATUS 0x198
307
308#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
309#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
310
311#define MSR_MTRRfix64K_00000 0x250
312#define MSR_MTRRfix16K_80000 0x258
313#define MSR_MTRRfix16K_A0000 0x259
314#define MSR_MTRRfix4K_C0000 0x268
315#define MSR_MTRRfix4K_C8000 0x269
316#define MSR_MTRRfix4K_D0000 0x26a
317#define MSR_MTRRfix4K_D8000 0x26b
318#define MSR_MTRRfix4K_E0000 0x26c
319#define MSR_MTRRfix4K_E8000 0x26d
320#define MSR_MTRRfix4K_F0000 0x26e
321#define MSR_MTRRfix4K_F8000 0x26f
322
323#define MSR_PAT 0x277
324
325#define MSR_MTRRdefType 0x2ff
326
327#define MSR_MC0_CTL 0x400
328#define MSR_MC0_STATUS 0x401
329#define MSR_MC0_ADDR 0x402
330#define MSR_MC0_MISC 0x403
331
332#define MSR_EFER 0xc0000080
333
334#define MSR_EFER_SCE (1 << 0)
335#define MSR_EFER_LME (1 << 8)
336#define MSR_EFER_LMA (1 << 10)
337#define MSR_EFER_NXE (1 << 11)
338#define MSR_EFER_SVME (1 << 12)
339#define MSR_EFER_FFXSR (1 << 14)
340
341#ifdef VBOX
342# define MSR_APIC_RANGE_START 0x800
343# define MSR_APIC_RANGE_END 0x900
344#endif
345
346#define MSR_STAR 0xc0000081
347#define MSR_LSTAR 0xc0000082
348#define MSR_CSTAR 0xc0000083
349#define MSR_FMASK 0xc0000084
350#define MSR_FSBASE 0xc0000100
351#define MSR_GSBASE 0xc0000101
352#define MSR_KERNELGSBASE 0xc0000102
353#define MSR_TSC_AUX 0xc0000103
354
355#define MSR_VM_HSAVE_PA 0xc0010117
356
357/* cpuid_features bits */
358#define CPUID_FP87 (1 << 0)
359#define CPUID_VME (1 << 1)
360#define CPUID_DE (1 << 2)
361#define CPUID_PSE (1 << 3)
362#define CPUID_TSC (1 << 4)
363#define CPUID_MSR (1 << 5)
364#define CPUID_PAE (1 << 6)
365#define CPUID_MCE (1 << 7)
366#define CPUID_CX8 (1 << 8)
367#define CPUID_APIC (1 << 9)
368#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
369#define CPUID_MTRR (1 << 12)
370#define CPUID_PGE (1 << 13)
371#define CPUID_MCA (1 << 14)
372#define CPUID_CMOV (1 << 15)
373#define CPUID_PAT (1 << 16)
374#define CPUID_PSE36 (1 << 17)
375#define CPUID_PN (1 << 18)
376#define CPUID_CLFLUSH (1 << 19)
377#define CPUID_DTS (1 << 21)
378#define CPUID_ACPI (1 << 22)
379#define CPUID_MMX (1 << 23)
380#define CPUID_FXSR (1 << 24)
381#define CPUID_SSE (1 << 25)
382#define CPUID_SSE2 (1 << 26)
383#define CPUID_SS (1 << 27)
384#define CPUID_HT (1 << 28)
385#define CPUID_TM (1 << 29)
386#define CPUID_IA64 (1 << 30)
387#define CPUID_PBE (1 << 31)
388
389#define CPUID_EXT_SSE3 (1 << 0)
390#define CPUID_EXT_DTES64 (1 << 2)
391#define CPUID_EXT_MONITOR (1 << 3)
392#define CPUID_EXT_DSCPL (1 << 4)
393#define CPUID_EXT_VMX (1 << 5)
394#define CPUID_EXT_SMX (1 << 6)
395#define CPUID_EXT_EST (1 << 7)
396#define CPUID_EXT_TM2 (1 << 8)
397#define CPUID_EXT_SSSE3 (1 << 9)
398#define CPUID_EXT_CID (1 << 10)
399#define CPUID_EXT_CX16 (1 << 13)
400#define CPUID_EXT_XTPR (1 << 14)
401#define CPUID_EXT_PDCM (1 << 15)
402#define CPUID_EXT_DCA (1 << 18)
403#define CPUID_EXT_SSE41 (1 << 19)
404#define CPUID_EXT_SSE42 (1 << 20)
405#define CPUID_EXT_X2APIC (1 << 21)
406#define CPUID_EXT_MOVBE (1 << 22)
407#define CPUID_EXT_POPCNT (1 << 23)
408#define CPUID_EXT_XSAVE (1 << 26)
409#define CPUID_EXT_OSXSAVE (1 << 27)
410#define CPUID_EXT_HYPERVISOR (1 << 31)
411
412#define CPUID_EXT2_SYSCALL (1 << 11)
413#define CPUID_EXT2_MP (1 << 19)
414#define CPUID_EXT2_NX (1 << 20)
415#define CPUID_EXT2_MMXEXT (1 << 22)
416#define CPUID_EXT2_FFXSR (1 << 25)
417#define CPUID_EXT2_PDPE1GB (1 << 26)
418#define CPUID_EXT2_RDTSCP (1 << 27)
419#define CPUID_EXT2_LM (1 << 29)
420#define CPUID_EXT2_3DNOWEXT (1 << 30)
421#define CPUID_EXT2_3DNOW (1 << 31)
422
423#define CPUID_EXT3_LAHF_LM (1 << 0)
424#define CPUID_EXT3_CMP_LEG (1 << 1)
425#define CPUID_EXT3_SVM (1 << 2)
426#define CPUID_EXT3_EXTAPIC (1 << 3)
427#define CPUID_EXT3_CR8LEG (1 << 4)
428#define CPUID_EXT3_ABM (1 << 5)
429#define CPUID_EXT3_SSE4A (1 << 6)
430#define CPUID_EXT3_MISALIGNSSE (1 << 7)
431#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
432#define CPUID_EXT3_OSVW (1 << 9)
433#define CPUID_EXT3_IBS (1 << 10)
434#define CPUID_EXT3_SKINIT (1 << 12)
435
436#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
437#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
438#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
439
440#define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
441#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
442#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
443
444#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
445#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
446
447#define EXCP00_DIVZ 0
448#define EXCP01_DB 1
449#define EXCP02_NMI 2
450#define EXCP03_INT3 3
451#define EXCP04_INTO 4
452#define EXCP05_BOUND 5
453#define EXCP06_ILLOP 6
454#define EXCP07_PREX 7
455#define EXCP08_DBLE 8
456#define EXCP09_XERR 9
457#define EXCP0A_TSS 10
458#define EXCP0B_NOSEG 11
459#define EXCP0C_STACK 12
460#define EXCP0D_GPF 13
461#define EXCP0E_PAGE 14
462#define EXCP10_COPR 16
463#define EXCP11_ALGN 17
464#define EXCP12_MCHK 18
465
466#define EXCP_SYSCALL 0x100 /* only happens in user only emulation
467 for syscall instruction */
468
469enum {
470 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
471 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
472
473 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
474 CC_OP_MULW,
475 CC_OP_MULL,
476 CC_OP_MULQ,
477
478 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
479 CC_OP_ADDW,
480 CC_OP_ADDL,
481 CC_OP_ADDQ,
482
483 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
484 CC_OP_ADCW,
485 CC_OP_ADCL,
486 CC_OP_ADCQ,
487
488 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
489 CC_OP_SUBW,
490 CC_OP_SUBL,
491 CC_OP_SUBQ,
492
493 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
494 CC_OP_SBBW,
495 CC_OP_SBBL,
496 CC_OP_SBBQ,
497
498 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
499 CC_OP_LOGICW,
500 CC_OP_LOGICL,
501 CC_OP_LOGICQ,
502
503 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
504 CC_OP_INCW,
505 CC_OP_INCL,
506 CC_OP_INCQ,
507
508 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
509 CC_OP_DECW,
510 CC_OP_DECL,
511 CC_OP_DECQ,
512
513 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
514 CC_OP_SHLW,
515 CC_OP_SHLL,
516 CC_OP_SHLQ,
517
518 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
519 CC_OP_SARW,
520 CC_OP_SARL,
521 CC_OP_SARQ,
522
523 CC_OP_NB,
524};
525
526#ifdef FLOATX80
527#define USE_X86LDOUBLE
528#endif
529
530#ifdef USE_X86LDOUBLE
531typedef floatx80 CPU86_LDouble;
532#else
533typedef float64 CPU86_LDouble;
534#endif
535
536typedef struct SegmentCache {
537 uint32_t selector;
538#ifdef VBOX
539 /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
540 uint16_t newselector;
541 uint16_t fVBoxFlags;
542#endif
543 target_ulong base;
544 uint32_t limit;
545 uint32_t flags;
546} SegmentCache;
547
548typedef union {
549 uint8_t _b[16];
550 uint16_t _w[8];
551 uint32_t _l[4];
552 uint64_t _q[2];
553 float32 _s[4];
554 float64 _d[2];
555} XMMReg;
556
557typedef union {
558 uint8_t _b[8];
559 uint16_t _w[4];
560 uint32_t _l[2];
561 float32 _s[2];
562 uint64_t q;
563} MMXReg;
564
565#ifdef HOST_WORDS_BIGENDIAN
566#define XMM_B(n) _b[15 - (n)]
567#define XMM_W(n) _w[7 - (n)]
568#define XMM_L(n) _l[3 - (n)]
569#define XMM_S(n) _s[3 - (n)]
570#define XMM_Q(n) _q[1 - (n)]
571#define XMM_D(n) _d[1 - (n)]
572
573#define MMX_B(n) _b[7 - (n)]
574#define MMX_W(n) _w[3 - (n)]
575#define MMX_L(n) _l[1 - (n)]
576#define MMX_S(n) _s[1 - (n)]
577#else
578#define XMM_B(n) _b[n]
579#define XMM_W(n) _w[n]
580#define XMM_L(n) _l[n]
581#define XMM_S(n) _s[n]
582#define XMM_Q(n) _q[n]
583#define XMM_D(n) _d[n]
584
585#define MMX_B(n) _b[n]
586#define MMX_W(n) _w[n]
587#define MMX_L(n) _l[n]
588#define MMX_S(n) _s[n]
589#endif
590#define MMX_Q(n) q
591
592typedef union {
593#ifdef USE_X86LDOUBLE
594 CPU86_LDouble d __attribute__((aligned(16)));
595#else
596 CPU86_LDouble d;
597#endif
598 MMXReg mmx;
599} FPReg;
600
601typedef struct {
602 uint64_t base;
603 uint64_t mask;
604} MTRRVar;
605
606#define CPU_NB_REGS64 16
607#define CPU_NB_REGS32 8
608
609#ifdef TARGET_X86_64
610#define CPU_NB_REGS CPU_NB_REGS64
611#else
612#define CPU_NB_REGS CPU_NB_REGS32
613#endif
614
615#define NB_MMU_MODES 2
616
617typedef struct CPUX86State {
618 /* standard registers */
619 target_ulong regs[CPU_NB_REGS];
620 target_ulong eip;
621 target_ulong eflags; /* eflags register. During CPU emulation, CC
622 flags and DF are set to zero because they are
623 stored elsewhere */
624
625 /* emulator internal eflags handling */
626 target_ulong cc_src;
627 target_ulong cc_dst;
628 uint32_t cc_op;
629 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
630 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
631 are known at translation time. */
632 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
633
634 /* segments */
635 SegmentCache segs[6]; /* selector values */
636 SegmentCache ldt;
637 SegmentCache tr;
638 SegmentCache gdt; /* only base and limit are used */
639 SegmentCache idt; /* only base and limit are used */
640
641 target_ulong cr[5]; /* NOTE: cr1 is unused */
642 int32_t a20_mask;
643
644 /* FPU state */
645 unsigned int fpstt; /* top of stack index */
646 uint16_t fpus;
647 uint16_t fpuc;
648 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
649 FPReg fpregs[8];
650
651 /* emulator internal variables */
652 float_status fp_status;
653#ifdef VBOX
654 uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
655#endif
656 CPU86_LDouble ft0;
657#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
658 uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
659#endif
660
661 float_status mmx_status; /* for 3DNow! float ops */
662 float_status sse_status;
663 uint32_t mxcsr;
664 XMMReg xmm_regs[CPU_NB_REGS];
665 XMMReg xmm_t0;
666 MMXReg mmx_t0;
667 target_ulong cc_tmp; /* temporary for rcr/rcl */
668
669 /* sysenter registers */
670 uint32_t sysenter_cs;
671#ifdef VBOX
672 uint32_t alignment0;
673#endif
674 target_ulong sysenter_esp;
675 target_ulong sysenter_eip;
676 uint64_t efer;
677 uint64_t star;
678
679 uint64_t vm_hsave;
680 uint64_t vm_vmcb;
681 uint64_t tsc_offset;
682 uint64_t intercept;
683 uint16_t intercept_cr_read;
684 uint16_t intercept_cr_write;
685 uint16_t intercept_dr_read;
686 uint16_t intercept_dr_write;
687 uint32_t intercept_exceptions;
688 uint8_t v_tpr;
689
690#ifdef TARGET_X86_64
691 target_ulong lstar;
692 target_ulong cstar;
693 target_ulong fmask;
694 target_ulong kernelgsbase;
695#endif
696 uint64_t system_time_msr;
697 uint64_t wall_clock_msr;
698
699 uint64_t tsc;
700
701 uint64_t pat;
702
703 /* exception/interrupt handling */
704 int error_code;
705 int exception_is_int;
706 target_ulong exception_next_eip;
707 target_ulong dr[8]; /* debug registers */
708 union {
709 CPUBreakpoint *cpu_breakpoint[4];
710 CPUWatchpoint *cpu_watchpoint[4];
711 }; /* break/watchpoints for dr[0..3] */
712 uint32_t smbase;
713 int old_exception; /* exception in flight */
714
715 CPU_COMMON
716
717#ifdef VBOX
718 /** cpu state flags. (see defines below) */
719 uint32_t state;
720 /** The VM handle. */
721 PVM pVM;
722 /** The VMCPU handle. */
723 PVMCPU pVCpu;
724 /** code buffer for instruction emulation */
725 void *pvCodeBuffer;
726 /** code buffer size */
727 uint32_t cbCodeBuffer;
728#endif /* VBOX */
729
730 /* processor features (e.g. for CPUID insn) */
731#ifndef VBOX /* remR3CpuId deals with these */
732 uint32_t cpuid_level;
733 uint32_t cpuid_vendor1;
734 uint32_t cpuid_vendor2;
735 uint32_t cpuid_vendor3;
736 uint32_t cpuid_version;
737#endif /* !VBOX */
738 uint32_t cpuid_features;
739 uint32_t cpuid_ext_features;
740#ifndef VBOX
741 uint32_t cpuid_xlevel;
742 uint32_t cpuid_model[12];
743#endif /* !VBOX */
744 uint32_t cpuid_ext2_features;
745 uint32_t cpuid_ext3_features;
746 uint32_t cpuid_apic_id;
747#ifndef VBOX
748 int cpuid_vendor_override;
749
750 /* MTRRs */
751 uint64_t mtrr_fixed[11];
752 uint64_t mtrr_deftype;
753 MTRRVar mtrr_var[8];
754
755 /* For KVM */
756 uint32_t mp_state;
757 int32_t exception_injected;
758 int32_t interrupt_injected;
759 uint8_t soft_interrupt;
760 uint8_t nmi_injected;
761 uint8_t nmi_pending;
762 uint8_t has_error_code;
763 uint32_t sipi_vector;
764
765 uint32_t cpuid_kvm_features;
766
767 /* in order to simplify APIC support, we leave this pointer to the
768 user */
769 struct DeviceState *apic_state;
770
771 uint64 mcg_cap;
772 uint64 mcg_status;
773 uint64 mcg_ctl;
774 uint64 mce_banks[MCE_BANKS_DEF*4];
775
776 uint64_t tsc_aux;
777
778 /* vmstate */
779 uint16_t fpus_vmstate;
780 uint16_t fptag_vmstate;
781 uint16_t fpregs_format_vmstate;
782
783 uint64_t xstate_bv;
784 XMMReg ymmh_regs[CPU_NB_REGS];
785
786 uint64_t xcr0;
787#else /* VBOX */
788
789 /** Alignment padding. */
790# if HC_ARCH_BITS == 64 \
791 || ( HC_ARCH_BITS == 32 \
792 && !defined(RT_OS_WINDOWS) \
793 && ( (!defined(VBOX_ENABLE_VBOXREM64) && !defined(RT_OS_SOLARIS) && !defined(RT_OS_FREEBSD)) \
794 || (defined(VBOX_ENABLE_VBOXREM64) && (defined(RT_OS_SOLARIS) || defined(RT_OS_FREEBSD))) ) )
795 uint32_t alignment2[1];
796# endif
797
798 /** Profiling tb_flush. */
799 STAMPROFILE StatTbFlush;
800
801 /** Addends for HVA -> GPA translations. */
802 target_phys_addr_t phys_addends[NB_MMU_MODES][CPU_TLB_SIZE];
803#endif /* VBOX */
804} CPUX86State;
805
806#ifdef VBOX
807
808/* Version 1.6 structure; just for loading the old saved state */
809typedef struct SegmentCache_Ver16 {
810 uint32_t selector;
811 uint32_t base;
812 uint32_t limit;
813 uint32_t flags;
814 /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
815 uint32_t newselector;
816} SegmentCache_Ver16;
817
818# define CPU_NB_REGS_VER16 8
819
820/* Version 1.6 structure; just for loading the old saved state */
821typedef struct CPUX86State_Ver16 {
822# if TARGET_LONG_BITS > HOST_LONG_BITS
823 /* temporaries if we cannot store them in host registers */
824 uint32_t t0, t1, t2;
825# endif
826
827 /* standard registers */
828 uint32_t regs[CPU_NB_REGS_VER16];
829 uint32_t eip;
830 uint32_t eflags; /* eflags register. During CPU emulation, CC
831 flags and DF are set to zero because they are
832 stored elsewhere */
833
834 /* emulator internal eflags handling */
835 uint32_t cc_src;
836 uint32_t cc_dst;
837 uint32_t cc_op;
838 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
839 uint32_t hflags; /* hidden flags, see HF_xxx constants */
840
841 /* segments */
842 SegmentCache_Ver16 segs[6]; /* selector values */
843 SegmentCache_Ver16 ldt;
844 SegmentCache_Ver16 tr;
845 SegmentCache_Ver16 gdt; /* only base and limit are used */
846 SegmentCache_Ver16 idt; /* only base and limit are used */
847
848 uint32_t cr[5]; /* NOTE: cr1 is unused */
849 uint32_t a20_mask;
850
851 /* FPU state */
852 unsigned int fpstt; /* top of stack index */
853 unsigned int fpus;
854 unsigned int fpuc;
855 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
856 union {
857# ifdef USE_X86LDOUBLE
858 CPU86_LDouble d __attribute__((aligned(16)));
859# else
860 CPU86_LDouble d;
861# endif
862 MMXReg mmx;
863 } fpregs[8];
864
865 /* emulator internal variables */
866 float_status fp_status;
867# ifdef VBOX
868 uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
869# endif
870 CPU86_LDouble ft0;
871# if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
872 uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
873# endif
874 union {
875 float f;
876 double d;
877 int i32;
878 int64_t i64;
879 } fp_convert;
880
881 float_status sse_status;
882 uint32_t mxcsr;
883 XMMReg xmm_regs[CPU_NB_REGS_VER16];
884 XMMReg xmm_t0;
885 MMXReg mmx_t0;
886
887 /* sysenter registers */
888 uint32_t sysenter_cs;
889 uint32_t sysenter_esp;
890 uint32_t sysenter_eip;
891# ifdef VBOX
892 uint32_t alignment0;
893# endif
894 uint64_t efer;
895 uint64_t star;
896
897 uint64_t pat;
898
899 /* temporary data for USE_CODE_COPY mode */
900# ifdef USE_CODE_COPY
901 uint32_t tmp0;
902 uint32_t saved_esp;
903 int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
904# endif
905
906 /* exception/interrupt handling */
907 jmp_buf jmp_env;
908} CPUX86State_Ver16;
909
910/** CPUX86State state flags
911 * @{ */
912# define CPU_RAW_RING0 0x0002 /* Set after first time RawR0 is executed, never cleared. */
913# define CPU_EMULATE_SINGLE_INSTR 0x0040 /* Execute a single instruction in emulation mode */
914# define CPU_EMULATE_SINGLE_STEP 0x0080 /* go into single step mode */
915# define CPU_RAW_HM 0x0100 /* Set after first time HWACC is executed, never cleared. */
916/** @} */
917#endif /* !VBOX */
918
919#ifdef VBOX
920CPUX86State *cpu_x86_init(CPUX86State *env, const char *cpu_model);
921#else /* !VBOX */
922CPUX86State *cpu_x86_init(const char *cpu_model);
923#endif /* !VBOX */
924int cpu_x86_exec(CPUX86State *s);
925void cpu_x86_close(CPUX86State *s);
926void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
927 const char *optarg);
928void x86_cpudef_setup(void);
929
930int cpu_get_pic_interrupt(CPUX86State *s);
931/* MSDOS compatibility mode FPU exception support */
932void cpu_set_ferr(CPUX86State *s);
933
934/* this function must always be used to load data in the segment
935 cache: it synchronizes the hflags with the segment cache values */
936static inline void cpu_x86_load_seg_cache(CPUX86State *env,
937 int seg_reg, unsigned int selector,
938 target_ulong base,
939 unsigned int limit,
940 unsigned int flags)
941{
942 SegmentCache *sc;
943 unsigned int new_hflags;
944
945 sc = &env->segs[seg_reg];
946 sc->selector = selector;
947 sc->base = base;
948 sc->limit = limit;
949#ifndef VBOX
950 sc->flags = flags;
951#else
952 if (flags & DESC_P_MASK)
953 {
954 flags |= DESC_A_MASK; /* Make sure the A bit is set to avoid trouble. */
955 flags &= ~DESC_INTEL_UNUSABLE;
956 }
957 else if (selector < 4U)
958 flags |= DESC_INTEL_UNUSABLE;
959 else
960 flags &= ~DESC_INTEL_UNUSABLE;
961 sc->flags = flags;
962 sc->newselector = 0;
963 sc->fVBoxFlags = CPUMSELREG_FLAGS_VALID;
964#endif
965
966 /* update the hidden flags */
967 {
968 if (seg_reg == R_CS) {
969#ifdef TARGET_X86_64
970 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
971 /* long mode */
972 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
973 env->hflags &= ~(HF_ADDSEG_MASK);
974 } else
975#endif
976 {
977 /* legacy / compatibility case */
978 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
979 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
980 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
981 new_hflags;
982 }
983 }
984 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
985 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
986 if (env->hflags & HF_CS64_MASK) {
987 /* zero base assumed for DS, ES and SS in long mode */
988 } else if (!(env->cr[0] & CR0_PE_MASK) ||
989 (env->eflags & VM_MASK) ||
990 !(env->hflags & HF_CS32_MASK)) {
991 /* XXX: try to avoid this test. The problem comes from the
992 fact that is real mode or vm86 mode we only modify the
993 'base' and 'selector' fields of the segment cache to go
994 faster. A solution may be to force addseg to one in
995 translate-i386.c. */
996 new_hflags |= HF_ADDSEG_MASK;
997 } else {
998 new_hflags |= ((env->segs[R_DS].base |
999 env->segs[R_ES].base |
1000 env->segs[R_SS].base) != 0) <<
1001 HF_ADDSEG_SHIFT;
1002 }
1003 env->hflags = (env->hflags &
1004 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1005 }
1006}
1007
1008static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
1009 int sipi_vector)
1010{
1011 env->eip = 0;
1012 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1013 sipi_vector << 12,
1014 env->segs[R_CS].limit,
1015 env->segs[R_CS].flags);
1016 env->halted = 0;
1017}
1018
1019int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1020 target_ulong *base, unsigned int *limit,
1021 unsigned int *flags);
1022
1023/* wrapper, just in case memory mappings must be changed */
1024static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
1025{
1026#if HF_CPL_MASK == 3
1027 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
1028#else
1029#error HF_CPL_MASK is hardcoded
1030#endif
1031}
1032
1033/* op_helper.c */
1034/* used for debug or cpu save/restore */
1035void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
1036CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
1037
1038/* cpu-exec.c */
1039/* the following helpers are only usable in user mode simulation as
1040 they can trigger unexpected exceptions */
1041void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1042void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1043void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1044
1045/* you can call this signal handler from your SIGBUS and SIGSEGV
1046 signal handlers to inform the virtual CPU of exceptions. non zero
1047 is returned if the signal was handled by the virtual CPU. */
1048int cpu_x86_signal_handler(int host_signum, void *pinfo,
1049 void *puc);
1050
1051/* cpuid.c */
1052void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1053 uint32_t *eax, uint32_t *ebx,
1054 uint32_t *ecx, uint32_t *edx);
1055int cpu_x86_register (CPUX86State *env, const char *cpu_model);
1056void cpu_clear_apic_feature(CPUX86State *env);
1057
1058/* helper.c */
1059int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
1060 int is_write, int mmu_idx, int is_softmmu);
1061#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
1062void cpu_x86_set_a20(CPUX86State *env, int a20_state);
1063
1064static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
1065{
1066 return (dr7 >> (index * 2)) & 3;
1067}
1068
1069static inline int hw_breakpoint_type(unsigned long dr7, int index)
1070{
1071 return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
1072}
1073
1074static inline int hw_breakpoint_len(unsigned long dr7, int index)
1075{
1076 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
1077 return (len == 2) ? 8 : len + 1;
1078}
1079
1080void hw_breakpoint_insert(CPUX86State *env, int index);
1081void hw_breakpoint_remove(CPUX86State *env, int index);
1082int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
1083
1084/* will be suppressed */
1085void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1086void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1087void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1088
1089/* hw/pc.c */
1090void cpu_smm_update(CPUX86State *env);
1091uint64_t cpu_get_tsc(CPUX86State *env);
1092
1093/* used to debug */
1094#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
1095#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
1096
1097#ifdef VBOX
1098int cpu_rdmsr(CPUX86State *env, uint32_t idMsr, uint64_t *puValue);
1099int cpu_wrmsr(CPUX86State *env, uint32_t idMsr, uint64_t uValue);
1100void cpu_trap_raw(CPUX86State *env1);
1101
1102/* in helper.c */
1103uint8_t read_byte(CPUX86State *env1, target_ulong addr);
1104uint16_t read_word(CPUX86State *env1, target_ulong addr);
1105void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val);
1106uint32_t read_dword(CPUX86State *env1, target_ulong addr);
1107void write_word(CPUX86State *env1, target_ulong addr, uint16_t val);
1108void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val);
1109/* in helper.c */
1110int emulate_single_instr(CPUX86State *env1);
1111int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl);
1112
1113void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr);
1114void save_raw_fp_state(CPUX86State *env, uint8_t *ptr);
1115#endif /* VBOX */
1116
1117#define TARGET_PAGE_BITS 12
1118
1119#ifdef TARGET_X86_64
1120#define TARGET_PHYS_ADDR_SPACE_BITS 52
1121/* ??? This is really 48 bits, sign-extended, but the only thing
1122 accessible to userland with bit 48 set is the VSYSCALL, and that
1123 is handled via other mechanisms. */
1124#define TARGET_VIRT_ADDR_SPACE_BITS 47
1125#else
1126#define TARGET_PHYS_ADDR_SPACE_BITS 36
1127#define TARGET_VIRT_ADDR_SPACE_BITS 32
1128#endif
1129
1130#define cpu_init cpu_x86_init
1131#define cpu_exec cpu_x86_exec
1132#define cpu_gen_code cpu_x86_gen_code
1133#define cpu_signal_handler cpu_x86_signal_handler
1134#define cpu_list_id x86_cpu_list
1135#define cpudef_setup x86_cpudef_setup
1136
1137#define CPU_SAVE_VERSION 12
1138
1139/* MMU modes definitions */
1140#define MMU_MODE0_SUFFIX _kernel
1141#define MMU_MODE1_SUFFIX _user
1142#define MMU_USER_IDX 1
1143static inline int cpu_mmu_index (CPUState *env)
1144{
1145 return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
1146}
1147
1148/* translate.c */
1149void optimize_flags_init(void);
1150
1151typedef struct CCTable {
1152 int (*compute_all)(void); /* return all the flags */
1153 int (*compute_c)(void); /* return the C flag */
1154} CCTable;
1155
1156#if defined(CONFIG_USER_ONLY)
1157static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
1158{
1159 if (newsp)
1160 env->regs[R_ESP] = newsp;
1161 env->regs[R_EAX] = 0;
1162}
1163#endif
1164
1165#include "cpu-all.h"
1166#include "svm.h"
1167
1168#ifndef VBOX
1169#if !defined(CONFIG_USER_ONLY)
1170#include "hw/apic.h"
1171#endif
1172#else /* VBOX */
1173extern void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
1174extern uint8_t cpu_get_apic_tpr(CPUX86State *env);
1175extern uint64_t cpu_get_apic_base(CPUX86State *env);
1176#endif /* VBOX */
1177
1178static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1179 target_ulong *cs_base, int *flags)
1180{
1181 *cs_base = env->segs[R_CS].base;
1182 *pc = *cs_base + env->eip;
1183 *flags = env->hflags |
1184 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
1185}
1186
1187#ifndef VBOX
1188void apic_init_reset(CPUState *env);
1189void apic_sipi(CPUState *env);
1190void do_cpu_init(CPUState *env);
1191void do_cpu_sipi(CPUState *env);
1192#endif /* !VBOX */
1193#endif /* CPU_I386_H */
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