| 1 | /*
|
|---|
| 2 | * i386 virtual CPU header
|
|---|
| 3 | *
|
|---|
| 4 | * Copyright (c) 2003 Fabrice Bellard
|
|---|
| 5 | *
|
|---|
| 6 | * This library is free software; you can redistribute it and/or
|
|---|
| 7 | * modify it under the terms of the GNU Lesser General Public
|
|---|
| 8 | * License as published by the Free Software Foundation; either
|
|---|
| 9 | * version 2 of the License, or (at your option) any later version.
|
|---|
| 10 | *
|
|---|
| 11 | * This library is distributed in the hope that it will be useful,
|
|---|
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|---|
| 14 | * Lesser General Public License for more details.
|
|---|
| 15 | *
|
|---|
| 16 | * You should have received a copy of the GNU Lesser General Public
|
|---|
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|---|
| 18 | */
|
|---|
| 19 |
|
|---|
| 20 | /*
|
|---|
| 21 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
|
|---|
| 22 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
|
|---|
| 23 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
|
|---|
| 24 | * a choice of LGPL license versions is made available with the language indicating
|
|---|
| 25 | * that LGPLv2 or any later version may be used, or where a choice of which version
|
|---|
| 26 | * of the LGPL is applied is otherwise unspecified.
|
|---|
| 27 | */
|
|---|
| 28 |
|
|---|
| 29 | #ifndef CPU_I386_H
|
|---|
| 30 | #define CPU_I386_H
|
|---|
| 31 |
|
|---|
| 32 | #include "config.h"
|
|---|
| 33 |
|
|---|
| 34 | #ifdef TARGET_X86_64
|
|---|
| 35 | #define TARGET_LONG_BITS 64
|
|---|
| 36 | #else
|
|---|
| 37 | #define TARGET_LONG_BITS 32
|
|---|
| 38 | #endif
|
|---|
| 39 |
|
|---|
| 40 | /* target supports implicit self modifying code */
|
|---|
| 41 | #define TARGET_HAS_SMC
|
|---|
| 42 | /* support for self modifying code even if the modified instruction is
|
|---|
| 43 | close to the modifying instruction */
|
|---|
| 44 | #define TARGET_HAS_PRECISE_SMC
|
|---|
| 45 |
|
|---|
| 46 | #define TARGET_HAS_ICE 1
|
|---|
| 47 |
|
|---|
| 48 | #ifdef TARGET_X86_64
|
|---|
| 49 | #define ELF_MACHINE EM_X86_64
|
|---|
| 50 | #else
|
|---|
| 51 | #define ELF_MACHINE EM_386
|
|---|
| 52 | #endif
|
|---|
| 53 |
|
|---|
| 54 | #define CPUState struct CPUX86State
|
|---|
| 55 |
|
|---|
| 56 | #include "cpu-defs.h"
|
|---|
| 57 |
|
|---|
| 58 | #include "softfloat.h"
|
|---|
| 59 |
|
|---|
| 60 | #ifdef VBOX
|
|---|
| 61 | # include <iprt/critsect.h>
|
|---|
| 62 | # include <iprt/thread.h>
|
|---|
| 63 | # include <iprt/assert.h>
|
|---|
| 64 | # include <iprt/asm.h>
|
|---|
| 65 | # include <VBox/vmm/vmm.h>
|
|---|
| 66 | # include <VBox/vmm/stam.h>
|
|---|
| 67 | # include <VBox/vmm/cpumctx.h>
|
|---|
| 68 | #endif /* VBOX */
|
|---|
| 69 |
|
|---|
| 70 | #define R_EAX 0
|
|---|
| 71 | #define R_ECX 1
|
|---|
| 72 | #define R_EDX 2
|
|---|
| 73 | #define R_EBX 3
|
|---|
| 74 | #define R_ESP 4
|
|---|
| 75 | #define R_EBP 5
|
|---|
| 76 | #define R_ESI 6
|
|---|
| 77 | #define R_EDI 7
|
|---|
| 78 |
|
|---|
| 79 | #define R_AL 0
|
|---|
| 80 | #define R_CL 1
|
|---|
| 81 | #define R_DL 2
|
|---|
| 82 | #define R_BL 3
|
|---|
| 83 | #define R_AH 4
|
|---|
| 84 | #define R_CH 5
|
|---|
| 85 | #define R_DH 6
|
|---|
| 86 | #define R_BH 7
|
|---|
| 87 |
|
|---|
| 88 | #define R_ES 0
|
|---|
| 89 | #define R_CS 1
|
|---|
| 90 | #define R_SS 2
|
|---|
| 91 | #define R_DS 3
|
|---|
| 92 | #define R_FS 4
|
|---|
| 93 | #define R_GS 5
|
|---|
| 94 |
|
|---|
| 95 | /* segment descriptor fields */
|
|---|
| 96 | #define DESC_G_MASK (1 << 23)
|
|---|
| 97 | #define DESC_B_SHIFT 22
|
|---|
| 98 | #define DESC_B_MASK (1 << DESC_B_SHIFT)
|
|---|
| 99 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
|
|---|
| 100 | #define DESC_L_MASK (1 << DESC_L_SHIFT)
|
|---|
| 101 | #define DESC_AVL_MASK (1 << 20)
|
|---|
| 102 | #define DESC_P_MASK (1 << 15)
|
|---|
| 103 | #define DESC_DPL_SHIFT 13
|
|---|
| 104 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
|
|---|
| 105 | #define DESC_S_MASK (1 << 12)
|
|---|
| 106 | #define DESC_TYPE_SHIFT 8
|
|---|
| 107 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
|
|---|
| 108 | #define DESC_A_MASK (1 << 8)
|
|---|
| 109 |
|
|---|
| 110 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
|
|---|
| 111 | #define DESC_C_MASK (1 << 10) /* code: conforming */
|
|---|
| 112 | #define DESC_R_MASK (1 << 9) /* code: readable */
|
|---|
| 113 |
|
|---|
| 114 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */
|
|---|
| 115 | #define DESC_W_MASK (1 << 9) /* data: writable */
|
|---|
| 116 |
|
|---|
| 117 | #define DESC_TSS_BUSY_MASK (1 << 9)
|
|---|
| 118 |
|
|---|
| 119 | /* eflags masks */
|
|---|
| 120 | #define CC_C 0x0001
|
|---|
| 121 | #define CC_P 0x0004
|
|---|
| 122 | #define CC_A 0x0010
|
|---|
| 123 | #define CC_Z 0x0040
|
|---|
| 124 | #define CC_S 0x0080
|
|---|
| 125 | #define CC_O 0x0800
|
|---|
| 126 |
|
|---|
| 127 | #define TF_SHIFT 8
|
|---|
| 128 | #define IOPL_SHIFT 12
|
|---|
| 129 | #define VM_SHIFT 17
|
|---|
| 130 |
|
|---|
| 131 | #define TF_MASK 0x00000100
|
|---|
| 132 | #define IF_MASK 0x00000200
|
|---|
| 133 | #define DF_MASK 0x00000400
|
|---|
| 134 | #define IOPL_MASK 0x00003000
|
|---|
| 135 | #define NT_MASK 0x00004000
|
|---|
| 136 | #define RF_MASK 0x00010000
|
|---|
| 137 | #define VM_MASK 0x00020000
|
|---|
| 138 | #define AC_MASK 0x00040000
|
|---|
| 139 | #define VIF_MASK 0x00080000
|
|---|
| 140 | #define VIP_MASK 0x00100000
|
|---|
| 141 | #define ID_MASK 0x00200000
|
|---|
| 142 |
|
|---|
| 143 | /* hidden flags - used internally by qemu to represent additional cpu
|
|---|
| 144 | states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
|
|---|
| 145 | redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
|
|---|
| 146 | position to ease oring with eflags. */
|
|---|
| 147 | /* current cpl */
|
|---|
| 148 | #define HF_CPL_SHIFT 0
|
|---|
| 149 | /* true if soft mmu is being used */
|
|---|
| 150 | #define HF_SOFTMMU_SHIFT 2
|
|---|
| 151 | /* true if hardware interrupts must be disabled for next instruction */
|
|---|
| 152 | #define HF_INHIBIT_IRQ_SHIFT 3
|
|---|
| 153 | /* 16 or 32 segments */
|
|---|
| 154 | #define HF_CS32_SHIFT 4
|
|---|
| 155 | #define HF_SS32_SHIFT 5
|
|---|
| 156 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
|
|---|
| 157 | #define HF_ADDSEG_SHIFT 6
|
|---|
| 158 | /* copy of CR0.PE (protected mode) */
|
|---|
| 159 | #define HF_PE_SHIFT 7
|
|---|
| 160 | #define HF_TF_SHIFT 8 /* must be same as eflags */
|
|---|
| 161 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
|
|---|
| 162 | #define HF_EM_SHIFT 10
|
|---|
| 163 | #define HF_TS_SHIFT 11
|
|---|
| 164 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */
|
|---|
| 165 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
|
|---|
| 166 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
|
|---|
| 167 | #define HF_RF_SHIFT 16 /* must be same as eflags */
|
|---|
| 168 | #define HF_VM_SHIFT 17 /* must be same as eflags */
|
|---|
| 169 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
|
|---|
| 170 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
|
|---|
| 171 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
|
|---|
| 172 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
|
|---|
| 173 |
|
|---|
| 174 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
|
|---|
| 175 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
|
|---|
| 176 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
|
|---|
| 177 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
|
|---|
| 178 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
|
|---|
| 179 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
|
|---|
| 180 | #define HF_PE_MASK (1 << HF_PE_SHIFT)
|
|---|
| 181 | #define HF_TF_MASK (1 << HF_TF_SHIFT)
|
|---|
| 182 | #define HF_MP_MASK (1 << HF_MP_SHIFT)
|
|---|
| 183 | #define HF_EM_MASK (1 << HF_EM_SHIFT)
|
|---|
| 184 | #define HF_TS_MASK (1 << HF_TS_SHIFT)
|
|---|
| 185 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
|
|---|
| 186 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
|
|---|
| 187 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
|
|---|
| 188 | #define HF_RF_MASK (1 << HF_RF_SHIFT)
|
|---|
| 189 | #define HF_VM_MASK (1 << HF_VM_SHIFT)
|
|---|
| 190 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
|
|---|
| 191 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
|
|---|
| 192 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
|
|---|
| 193 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
|
|---|
| 194 |
|
|---|
| 195 | /* hflags2 */
|
|---|
| 196 |
|
|---|
| 197 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
|
|---|
| 198 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
|
|---|
| 199 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
|
|---|
| 200 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
|
|---|
| 201 |
|
|---|
| 202 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
|
|---|
| 203 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
|
|---|
| 204 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
|
|---|
| 205 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
|
|---|
| 206 |
|
|---|
| 207 | #define CR0_PE_SHIFT 0
|
|---|
| 208 | #define CR0_MP_SHIFT 1
|
|---|
| 209 |
|
|---|
| 210 | #define CR0_PE_MASK (1 << 0)
|
|---|
| 211 | #define CR0_MP_MASK (1 << 1)
|
|---|
| 212 | #define CR0_EM_MASK (1 << 2)
|
|---|
| 213 | #define CR0_TS_MASK (1 << 3)
|
|---|
| 214 | #define CR0_ET_MASK (1 << 4)
|
|---|
| 215 | #define CR0_NE_MASK (1 << 5)
|
|---|
| 216 | #define CR0_WP_MASK (1 << 16)
|
|---|
| 217 | #define CR0_AM_MASK (1 << 18)
|
|---|
| 218 | #define CR0_PG_MASK (1 << 31)
|
|---|
| 219 |
|
|---|
| 220 | #define CR4_VME_MASK (1 << 0)
|
|---|
| 221 | #define CR4_PVI_MASK (1 << 1)
|
|---|
| 222 | #define CR4_TSD_MASK (1 << 2)
|
|---|
| 223 | #define CR4_DE_MASK (1 << 3)
|
|---|
| 224 | #define CR4_PSE_MASK (1 << 4)
|
|---|
| 225 | #define CR4_PAE_MASK (1 << 5)
|
|---|
| 226 | #define CR4_MCE_MASK (1 << 6)
|
|---|
| 227 | #define CR4_PGE_MASK (1 << 7)
|
|---|
| 228 | #define CR4_PCE_MASK (1 << 8)
|
|---|
| 229 | #define CR4_OSFXSR_SHIFT 9
|
|---|
| 230 | #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
|
|---|
| 231 | #define CR4_OSXMMEXCPT_MASK (1 << 10)
|
|---|
| 232 |
|
|---|
| 233 | #define DR6_BD (1 << 13)
|
|---|
| 234 | #define DR6_BS (1 << 14)
|
|---|
| 235 | #define DR6_BT (1 << 15)
|
|---|
| 236 | #define DR6_FIXED_1 0xffff0ff0
|
|---|
| 237 |
|
|---|
| 238 | #define DR7_GD (1 << 13)
|
|---|
| 239 | #define DR7_TYPE_SHIFT 16
|
|---|
| 240 | #define DR7_LEN_SHIFT 18
|
|---|
| 241 | #define DR7_FIXED_1 0x00000400
|
|---|
| 242 |
|
|---|
| 243 | #define PG_PRESENT_BIT 0
|
|---|
| 244 | #define PG_RW_BIT 1
|
|---|
| 245 | #define PG_USER_BIT 2
|
|---|
| 246 | #define PG_PWT_BIT 3
|
|---|
| 247 | #define PG_PCD_BIT 4
|
|---|
| 248 | #define PG_ACCESSED_BIT 5
|
|---|
| 249 | #define PG_DIRTY_BIT 6
|
|---|
| 250 | #define PG_PSE_BIT 7
|
|---|
| 251 | #define PG_GLOBAL_BIT 8
|
|---|
| 252 | #define PG_NX_BIT 63
|
|---|
| 253 |
|
|---|
| 254 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
|
|---|
| 255 | #define PG_RW_MASK (1 << PG_RW_BIT)
|
|---|
| 256 | #define PG_USER_MASK (1 << PG_USER_BIT)
|
|---|
| 257 | #define PG_PWT_MASK (1 << PG_PWT_BIT)
|
|---|
| 258 | #define PG_PCD_MASK (1 << PG_PCD_BIT)
|
|---|
| 259 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
|
|---|
| 260 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
|
|---|
| 261 | #define PG_PSE_MASK (1 << PG_PSE_BIT)
|
|---|
| 262 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
|
|---|
| 263 | #define PG_NX_MASK (1LL << PG_NX_BIT)
|
|---|
| 264 |
|
|---|
| 265 | #define PG_ERROR_W_BIT 1
|
|---|
| 266 |
|
|---|
| 267 | #define PG_ERROR_P_MASK 0x01
|
|---|
| 268 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
|
|---|
| 269 | #define PG_ERROR_U_MASK 0x04
|
|---|
| 270 | #define PG_ERROR_RSVD_MASK 0x08
|
|---|
| 271 | #define PG_ERROR_I_D_MASK 0x10
|
|---|
| 272 |
|
|---|
| 273 | #define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
|
|---|
| 274 |
|
|---|
| 275 | #define MCE_CAP_DEF MCG_CTL_P
|
|---|
| 276 | #define MCE_BANKS_DEF 10
|
|---|
| 277 |
|
|---|
| 278 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
|
|---|
| 279 |
|
|---|
| 280 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
|
|---|
| 281 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
|
|---|
| 282 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
|
|---|
| 283 |
|
|---|
| 284 | #define MSR_IA32_TSC 0x10
|
|---|
| 285 | #define MSR_IA32_APICBASE 0x1b
|
|---|
| 286 | #define MSR_IA32_APICBASE_BSP (1<<8)
|
|---|
| 287 | #define MSR_IA32_APICBASE_ENABLE (1<<11)
|
|---|
| 288 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
|
|---|
| 289 |
|
|---|
| 290 | #define MSR_MTRRcap 0xfe
|
|---|
| 291 | #define MSR_MTRRcap_VCNT 8
|
|---|
| 292 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
|
|---|
| 293 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
|
|---|
| 294 |
|
|---|
| 295 | #define MSR_IA32_SYSENTER_CS 0x174
|
|---|
| 296 | #define MSR_IA32_SYSENTER_ESP 0x175
|
|---|
| 297 | #define MSR_IA32_SYSENTER_EIP 0x176
|
|---|
| 298 |
|
|---|
| 299 | #define MSR_MCG_CAP 0x179
|
|---|
| 300 | #define MSR_MCG_STATUS 0x17a
|
|---|
| 301 | #define MSR_MCG_CTL 0x17b
|
|---|
| 302 |
|
|---|
| 303 | #define MSR_IA32_PERF_STATUS 0x198
|
|---|
| 304 |
|
|---|
| 305 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
|
|---|
| 306 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
|
|---|
| 307 |
|
|---|
| 308 | #define MSR_MTRRfix64K_00000 0x250
|
|---|
| 309 | #define MSR_MTRRfix16K_80000 0x258
|
|---|
| 310 | #define MSR_MTRRfix16K_A0000 0x259
|
|---|
| 311 | #define MSR_MTRRfix4K_C0000 0x268
|
|---|
| 312 | #define MSR_MTRRfix4K_C8000 0x269
|
|---|
| 313 | #define MSR_MTRRfix4K_D0000 0x26a
|
|---|
| 314 | #define MSR_MTRRfix4K_D8000 0x26b
|
|---|
| 315 | #define MSR_MTRRfix4K_E0000 0x26c
|
|---|
| 316 | #define MSR_MTRRfix4K_E8000 0x26d
|
|---|
| 317 | #define MSR_MTRRfix4K_F0000 0x26e
|
|---|
| 318 | #define MSR_MTRRfix4K_F8000 0x26f
|
|---|
| 319 |
|
|---|
| 320 | #define MSR_PAT 0x277
|
|---|
| 321 |
|
|---|
| 322 | #define MSR_MTRRdefType 0x2ff
|
|---|
| 323 |
|
|---|
| 324 | #define MSR_MC0_CTL 0x400
|
|---|
| 325 | #define MSR_MC0_STATUS 0x401
|
|---|
| 326 | #define MSR_MC0_ADDR 0x402
|
|---|
| 327 | #define MSR_MC0_MISC 0x403
|
|---|
| 328 |
|
|---|
| 329 | #define MSR_EFER 0xc0000080
|
|---|
| 330 |
|
|---|
| 331 | #define MSR_EFER_SCE (1 << 0)
|
|---|
| 332 | #define MSR_EFER_LME (1 << 8)
|
|---|
| 333 | #define MSR_EFER_LMA (1 << 10)
|
|---|
| 334 | #define MSR_EFER_NXE (1 << 11)
|
|---|
| 335 | #define MSR_EFER_SVME (1 << 12)
|
|---|
| 336 | #define MSR_EFER_FFXSR (1 << 14)
|
|---|
| 337 |
|
|---|
| 338 | #ifdef VBOX
|
|---|
| 339 | # define MSR_APIC_RANGE_START 0x800
|
|---|
| 340 | # define MSR_APIC_RANGE_END 0x900
|
|---|
| 341 | #endif
|
|---|
| 342 |
|
|---|
| 343 | #define MSR_STAR 0xc0000081
|
|---|
| 344 | #define MSR_LSTAR 0xc0000082
|
|---|
| 345 | #define MSR_CSTAR 0xc0000083
|
|---|
| 346 | #define MSR_FMASK 0xc0000084
|
|---|
| 347 | #define MSR_FSBASE 0xc0000100
|
|---|
| 348 | #define MSR_GSBASE 0xc0000101
|
|---|
| 349 | #define MSR_KERNELGSBASE 0xc0000102
|
|---|
| 350 | #define MSR_TSC_AUX 0xc0000103
|
|---|
| 351 |
|
|---|
| 352 | #define MSR_VM_HSAVE_PA 0xc0010117
|
|---|
| 353 |
|
|---|
| 354 | /* cpuid_features bits */
|
|---|
| 355 | #define CPUID_FP87 (1 << 0)
|
|---|
| 356 | #define CPUID_VME (1 << 1)
|
|---|
| 357 | #define CPUID_DE (1 << 2)
|
|---|
| 358 | #define CPUID_PSE (1 << 3)
|
|---|
| 359 | #define CPUID_TSC (1 << 4)
|
|---|
| 360 | #define CPUID_MSR (1 << 5)
|
|---|
| 361 | #define CPUID_PAE (1 << 6)
|
|---|
| 362 | #define CPUID_MCE (1 << 7)
|
|---|
| 363 | #define CPUID_CX8 (1 << 8)
|
|---|
| 364 | #define CPUID_APIC (1 << 9)
|
|---|
| 365 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
|
|---|
| 366 | #define CPUID_MTRR (1 << 12)
|
|---|
| 367 | #define CPUID_PGE (1 << 13)
|
|---|
| 368 | #define CPUID_MCA (1 << 14)
|
|---|
| 369 | #define CPUID_CMOV (1 << 15)
|
|---|
| 370 | #define CPUID_PAT (1 << 16)
|
|---|
| 371 | #define CPUID_PSE36 (1 << 17)
|
|---|
| 372 | #define CPUID_PN (1 << 18)
|
|---|
| 373 | #define CPUID_CLFLUSH (1 << 19)
|
|---|
| 374 | #define CPUID_DTS (1 << 21)
|
|---|
| 375 | #define CPUID_ACPI (1 << 22)
|
|---|
| 376 | #define CPUID_MMX (1 << 23)
|
|---|
| 377 | #define CPUID_FXSR (1 << 24)
|
|---|
| 378 | #define CPUID_SSE (1 << 25)
|
|---|
| 379 | #define CPUID_SSE2 (1 << 26)
|
|---|
| 380 | #define CPUID_SS (1 << 27)
|
|---|
| 381 | #define CPUID_HT (1 << 28)
|
|---|
| 382 | #define CPUID_TM (1 << 29)
|
|---|
| 383 | #define CPUID_IA64 (1 << 30)
|
|---|
| 384 | #define CPUID_PBE (1 << 31)
|
|---|
| 385 |
|
|---|
| 386 | #define CPUID_EXT_SSE3 (1 << 0)
|
|---|
| 387 | #define CPUID_EXT_DTES64 (1 << 2)
|
|---|
| 388 | #define CPUID_EXT_MONITOR (1 << 3)
|
|---|
| 389 | #define CPUID_EXT_DSCPL (1 << 4)
|
|---|
| 390 | #define CPUID_EXT_VMX (1 << 5)
|
|---|
| 391 | #define CPUID_EXT_SMX (1 << 6)
|
|---|
| 392 | #define CPUID_EXT_EST (1 << 7)
|
|---|
| 393 | #define CPUID_EXT_TM2 (1 << 8)
|
|---|
| 394 | #define CPUID_EXT_SSSE3 (1 << 9)
|
|---|
| 395 | #define CPUID_EXT_CID (1 << 10)
|
|---|
| 396 | #define CPUID_EXT_CX16 (1 << 13)
|
|---|
| 397 | #define CPUID_EXT_XTPR (1 << 14)
|
|---|
| 398 | #define CPUID_EXT_PDCM (1 << 15)
|
|---|
| 399 | #define CPUID_EXT_DCA (1 << 18)
|
|---|
| 400 | #define CPUID_EXT_SSE41 (1 << 19)
|
|---|
| 401 | #define CPUID_EXT_SSE42 (1 << 20)
|
|---|
| 402 | #define CPUID_EXT_X2APIC (1 << 21)
|
|---|
| 403 | #define CPUID_EXT_MOVBE (1 << 22)
|
|---|
| 404 | #define CPUID_EXT_POPCNT (1 << 23)
|
|---|
| 405 | #define CPUID_EXT_XSAVE (1 << 26)
|
|---|
| 406 | #define CPUID_EXT_OSXSAVE (1 << 27)
|
|---|
| 407 | #define CPUID_EXT_HYPERVISOR (1 << 31)
|
|---|
| 408 |
|
|---|
| 409 | #define CPUID_EXT2_SYSCALL (1 << 11)
|
|---|
| 410 | #define CPUID_EXT2_MP (1 << 19)
|
|---|
| 411 | #define CPUID_EXT2_NX (1 << 20)
|
|---|
| 412 | #define CPUID_EXT2_MMXEXT (1 << 22)
|
|---|
| 413 | #define CPUID_EXT2_FFXSR (1 << 25)
|
|---|
| 414 | #define CPUID_EXT2_PDPE1GB (1 << 26)
|
|---|
| 415 | #define CPUID_EXT2_RDTSCP (1 << 27)
|
|---|
| 416 | #define CPUID_EXT2_LM (1 << 29)
|
|---|
| 417 | #define CPUID_EXT2_3DNOWEXT (1 << 30)
|
|---|
| 418 | #define CPUID_EXT2_3DNOW (1 << 31)
|
|---|
| 419 |
|
|---|
| 420 | #define CPUID_EXT3_LAHF_LM (1 << 0)
|
|---|
| 421 | #define CPUID_EXT3_CMP_LEG (1 << 1)
|
|---|
| 422 | #define CPUID_EXT3_SVM (1 << 2)
|
|---|
| 423 | #define CPUID_EXT3_EXTAPIC (1 << 3)
|
|---|
| 424 | #define CPUID_EXT3_CR8LEG (1 << 4)
|
|---|
| 425 | #define CPUID_EXT3_ABM (1 << 5)
|
|---|
| 426 | #define CPUID_EXT3_SSE4A (1 << 6)
|
|---|
| 427 | #define CPUID_EXT3_MISALIGNSSE (1 << 7)
|
|---|
| 428 | #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
|
|---|
| 429 | #define CPUID_EXT3_OSVW (1 << 9)
|
|---|
| 430 | #define CPUID_EXT3_IBS (1 << 10)
|
|---|
| 431 | #define CPUID_EXT3_SKINIT (1 << 12)
|
|---|
| 432 |
|
|---|
| 433 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
|
|---|
| 434 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
|
|---|
| 435 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
|
|---|
| 436 |
|
|---|
| 437 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
|
|---|
| 438 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
|
|---|
| 439 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
|
|---|
| 440 |
|
|---|
| 441 | #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
|
|---|
| 442 | #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
|
|---|
| 443 |
|
|---|
| 444 | #define EXCP00_DIVZ 0
|
|---|
| 445 | #define EXCP01_DB 1
|
|---|
| 446 | #define EXCP02_NMI 2
|
|---|
| 447 | #define EXCP03_INT3 3
|
|---|
| 448 | #define EXCP04_INTO 4
|
|---|
| 449 | #define EXCP05_BOUND 5
|
|---|
| 450 | #define EXCP06_ILLOP 6
|
|---|
| 451 | #define EXCP07_PREX 7
|
|---|
| 452 | #define EXCP08_DBLE 8
|
|---|
| 453 | #define EXCP09_XERR 9
|
|---|
| 454 | #define EXCP0A_TSS 10
|
|---|
| 455 | #define EXCP0B_NOSEG 11
|
|---|
| 456 | #define EXCP0C_STACK 12
|
|---|
| 457 | #define EXCP0D_GPF 13
|
|---|
| 458 | #define EXCP0E_PAGE 14
|
|---|
| 459 | #define EXCP10_COPR 16
|
|---|
| 460 | #define EXCP11_ALGN 17
|
|---|
| 461 | #define EXCP12_MCHK 18
|
|---|
| 462 |
|
|---|
| 463 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
|
|---|
| 464 | for syscall instruction */
|
|---|
| 465 |
|
|---|
| 466 | enum {
|
|---|
| 467 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
|
|---|
| 468 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
|
|---|
| 469 |
|
|---|
| 470 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
|
|---|
| 471 | CC_OP_MULW,
|
|---|
| 472 | CC_OP_MULL,
|
|---|
| 473 | CC_OP_MULQ,
|
|---|
| 474 |
|
|---|
| 475 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|---|
| 476 | CC_OP_ADDW,
|
|---|
| 477 | CC_OP_ADDL,
|
|---|
| 478 | CC_OP_ADDQ,
|
|---|
| 479 |
|
|---|
| 480 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|---|
| 481 | CC_OP_ADCW,
|
|---|
| 482 | CC_OP_ADCL,
|
|---|
| 483 | CC_OP_ADCQ,
|
|---|
| 484 |
|
|---|
| 485 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|---|
| 486 | CC_OP_SUBW,
|
|---|
| 487 | CC_OP_SUBL,
|
|---|
| 488 | CC_OP_SUBQ,
|
|---|
| 489 |
|
|---|
| 490 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|---|
| 491 | CC_OP_SBBW,
|
|---|
| 492 | CC_OP_SBBL,
|
|---|
| 493 | CC_OP_SBBQ,
|
|---|
| 494 |
|
|---|
| 495 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
|
|---|
| 496 | CC_OP_LOGICW,
|
|---|
| 497 | CC_OP_LOGICL,
|
|---|
| 498 | CC_OP_LOGICQ,
|
|---|
| 499 |
|
|---|
| 500 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
|---|
| 501 | CC_OP_INCW,
|
|---|
| 502 | CC_OP_INCL,
|
|---|
| 503 | CC_OP_INCQ,
|
|---|
| 504 |
|
|---|
| 505 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
|---|
| 506 | CC_OP_DECW,
|
|---|
| 507 | CC_OP_DECL,
|
|---|
| 508 | CC_OP_DECQ,
|
|---|
| 509 |
|
|---|
| 510 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
|
|---|
| 511 | CC_OP_SHLW,
|
|---|
| 512 | CC_OP_SHLL,
|
|---|
| 513 | CC_OP_SHLQ,
|
|---|
| 514 |
|
|---|
| 515 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
|
|---|
| 516 | CC_OP_SARW,
|
|---|
| 517 | CC_OP_SARL,
|
|---|
| 518 | CC_OP_SARQ,
|
|---|
| 519 |
|
|---|
| 520 | CC_OP_NB,
|
|---|
| 521 | };
|
|---|
| 522 |
|
|---|
| 523 | #ifdef FLOATX80
|
|---|
| 524 | #define USE_X86LDOUBLE
|
|---|
| 525 | #endif
|
|---|
| 526 |
|
|---|
| 527 | #ifdef USE_X86LDOUBLE
|
|---|
| 528 | typedef floatx80 CPU86_LDouble;
|
|---|
| 529 | #else
|
|---|
| 530 | typedef float64 CPU86_LDouble;
|
|---|
| 531 | #endif
|
|---|
| 532 |
|
|---|
| 533 | typedef struct SegmentCache {
|
|---|
| 534 | uint32_t selector;
|
|---|
| 535 | #ifdef VBOX
|
|---|
| 536 | /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
|
|---|
| 537 | uint16_t newselector;
|
|---|
| 538 | uint16_t fVBoxFlags;
|
|---|
| 539 | #endif
|
|---|
| 540 | target_ulong base;
|
|---|
| 541 | uint32_t limit;
|
|---|
| 542 | uint32_t flags;
|
|---|
| 543 | } SegmentCache;
|
|---|
| 544 |
|
|---|
| 545 | typedef union {
|
|---|
| 546 | uint8_t _b[16];
|
|---|
| 547 | uint16_t _w[8];
|
|---|
| 548 | uint32_t _l[4];
|
|---|
| 549 | uint64_t _q[2];
|
|---|
| 550 | float32 _s[4];
|
|---|
| 551 | float64 _d[2];
|
|---|
| 552 | } XMMReg;
|
|---|
| 553 |
|
|---|
| 554 | typedef union {
|
|---|
| 555 | uint8_t _b[8];
|
|---|
| 556 | uint16_t _w[4];
|
|---|
| 557 | uint32_t _l[2];
|
|---|
| 558 | float32 _s[2];
|
|---|
| 559 | uint64_t q;
|
|---|
| 560 | } MMXReg;
|
|---|
| 561 |
|
|---|
| 562 | #ifdef HOST_WORDS_BIGENDIAN
|
|---|
| 563 | #define XMM_B(n) _b[15 - (n)]
|
|---|
| 564 | #define XMM_W(n) _w[7 - (n)]
|
|---|
| 565 | #define XMM_L(n) _l[3 - (n)]
|
|---|
| 566 | #define XMM_S(n) _s[3 - (n)]
|
|---|
| 567 | #define XMM_Q(n) _q[1 - (n)]
|
|---|
| 568 | #define XMM_D(n) _d[1 - (n)]
|
|---|
| 569 |
|
|---|
| 570 | #define MMX_B(n) _b[7 - (n)]
|
|---|
| 571 | #define MMX_W(n) _w[3 - (n)]
|
|---|
| 572 | #define MMX_L(n) _l[1 - (n)]
|
|---|
| 573 | #define MMX_S(n) _s[1 - (n)]
|
|---|
| 574 | #else
|
|---|
| 575 | #define XMM_B(n) _b[n]
|
|---|
| 576 | #define XMM_W(n) _w[n]
|
|---|
| 577 | #define XMM_L(n) _l[n]
|
|---|
| 578 | #define XMM_S(n) _s[n]
|
|---|
| 579 | #define XMM_Q(n) _q[n]
|
|---|
| 580 | #define XMM_D(n) _d[n]
|
|---|
| 581 |
|
|---|
| 582 | #define MMX_B(n) _b[n]
|
|---|
| 583 | #define MMX_W(n) _w[n]
|
|---|
| 584 | #define MMX_L(n) _l[n]
|
|---|
| 585 | #define MMX_S(n) _s[n]
|
|---|
| 586 | #endif
|
|---|
| 587 | #define MMX_Q(n) q
|
|---|
| 588 |
|
|---|
| 589 | typedef union {
|
|---|
| 590 | #ifdef USE_X86LDOUBLE
|
|---|
| 591 | CPU86_LDouble d __attribute__((aligned(16)));
|
|---|
| 592 | #else
|
|---|
| 593 | CPU86_LDouble d;
|
|---|
| 594 | #endif
|
|---|
| 595 | MMXReg mmx;
|
|---|
| 596 | } FPReg;
|
|---|
| 597 |
|
|---|
| 598 | typedef struct {
|
|---|
| 599 | uint64_t base;
|
|---|
| 600 | uint64_t mask;
|
|---|
| 601 | } MTRRVar;
|
|---|
| 602 |
|
|---|
| 603 | #define CPU_NB_REGS64 16
|
|---|
| 604 | #define CPU_NB_REGS32 8
|
|---|
| 605 |
|
|---|
| 606 | #ifdef TARGET_X86_64
|
|---|
| 607 | #define CPU_NB_REGS CPU_NB_REGS64
|
|---|
| 608 | #else
|
|---|
| 609 | #define CPU_NB_REGS CPU_NB_REGS32
|
|---|
| 610 | #endif
|
|---|
| 611 |
|
|---|
| 612 | #define NB_MMU_MODES 2
|
|---|
| 613 |
|
|---|
| 614 | typedef struct CPUX86State {
|
|---|
| 615 | /* standard registers */
|
|---|
| 616 | target_ulong regs[CPU_NB_REGS];
|
|---|
| 617 | target_ulong eip;
|
|---|
| 618 | target_ulong eflags; /* eflags register. During CPU emulation, CC
|
|---|
| 619 | flags and DF are set to zero because they are
|
|---|
| 620 | stored elsewhere */
|
|---|
| 621 |
|
|---|
| 622 | /* emulator internal eflags handling */
|
|---|
| 623 | target_ulong cc_src;
|
|---|
| 624 | target_ulong cc_dst;
|
|---|
| 625 | uint32_t cc_op;
|
|---|
| 626 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
|---|
| 627 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
|
|---|
| 628 | are known at translation time. */
|
|---|
| 629 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
|
|---|
| 630 |
|
|---|
| 631 | /* segments */
|
|---|
| 632 | SegmentCache segs[6]; /* selector values */
|
|---|
| 633 | SegmentCache ldt;
|
|---|
| 634 | SegmentCache tr;
|
|---|
| 635 | SegmentCache gdt; /* only base and limit are used */
|
|---|
| 636 | SegmentCache idt; /* only base and limit are used */
|
|---|
| 637 |
|
|---|
| 638 | target_ulong cr[5]; /* NOTE: cr1 is unused */
|
|---|
| 639 | int32_t a20_mask;
|
|---|
| 640 |
|
|---|
| 641 | /* FPU state */
|
|---|
| 642 | unsigned int fpstt; /* top of stack index */
|
|---|
| 643 | uint16_t fpus;
|
|---|
| 644 | uint16_t fpuc;
|
|---|
| 645 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */
|
|---|
| 646 | FPReg fpregs[8];
|
|---|
| 647 |
|
|---|
| 648 | /* emulator internal variables */
|
|---|
| 649 | float_status fp_status;
|
|---|
| 650 | #ifdef VBOX
|
|---|
| 651 | uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
|
|---|
| 652 | #endif
|
|---|
| 653 | CPU86_LDouble ft0;
|
|---|
| 654 | #if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
|
|---|
| 655 | uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
|
|---|
| 656 | #endif
|
|---|
| 657 |
|
|---|
| 658 | float_status mmx_status; /* for 3DNow! float ops */
|
|---|
| 659 | float_status sse_status;
|
|---|
| 660 | uint32_t mxcsr;
|
|---|
| 661 | XMMReg xmm_regs[CPU_NB_REGS];
|
|---|
| 662 | XMMReg xmm_t0;
|
|---|
| 663 | MMXReg mmx_t0;
|
|---|
| 664 | target_ulong cc_tmp; /* temporary for rcr/rcl */
|
|---|
| 665 |
|
|---|
| 666 | /* sysenter registers */
|
|---|
| 667 | uint32_t sysenter_cs;
|
|---|
| 668 | #ifdef VBOX
|
|---|
| 669 | uint32_t alignment0;
|
|---|
| 670 | #endif
|
|---|
| 671 | target_ulong sysenter_esp;
|
|---|
| 672 | target_ulong sysenter_eip;
|
|---|
| 673 | uint64_t efer;
|
|---|
| 674 | uint64_t star;
|
|---|
| 675 |
|
|---|
| 676 | uint64_t vm_hsave;
|
|---|
| 677 | uint64_t vm_vmcb;
|
|---|
| 678 | uint64_t tsc_offset;
|
|---|
| 679 | uint64_t intercept;
|
|---|
| 680 | uint16_t intercept_cr_read;
|
|---|
| 681 | uint16_t intercept_cr_write;
|
|---|
| 682 | uint16_t intercept_dr_read;
|
|---|
| 683 | uint16_t intercept_dr_write;
|
|---|
| 684 | uint32_t intercept_exceptions;
|
|---|
| 685 | uint8_t v_tpr;
|
|---|
| 686 |
|
|---|
| 687 | #ifdef TARGET_X86_64
|
|---|
| 688 | target_ulong lstar;
|
|---|
| 689 | target_ulong cstar;
|
|---|
| 690 | target_ulong fmask;
|
|---|
| 691 | target_ulong kernelgsbase;
|
|---|
| 692 | #endif
|
|---|
| 693 | uint64_t system_time_msr;
|
|---|
| 694 | uint64_t wall_clock_msr;
|
|---|
| 695 |
|
|---|
| 696 | uint64_t tsc;
|
|---|
| 697 |
|
|---|
| 698 | uint64_t pat;
|
|---|
| 699 |
|
|---|
| 700 | /* exception/interrupt handling */
|
|---|
| 701 | int error_code;
|
|---|
| 702 | int exception_is_int;
|
|---|
| 703 | target_ulong exception_next_eip;
|
|---|
| 704 | target_ulong dr[8]; /* debug registers */
|
|---|
| 705 | union {
|
|---|
| 706 | CPUBreakpoint *cpu_breakpoint[4];
|
|---|
| 707 | CPUWatchpoint *cpu_watchpoint[4];
|
|---|
| 708 | }; /* break/watchpoints for dr[0..3] */
|
|---|
| 709 | uint32_t smbase;
|
|---|
| 710 | int old_exception; /* exception in flight */
|
|---|
| 711 |
|
|---|
| 712 | CPU_COMMON
|
|---|
| 713 |
|
|---|
| 714 | #ifdef VBOX
|
|---|
| 715 | /** cpu state flags. (see defines below) */
|
|---|
| 716 | uint32_t state;
|
|---|
| 717 | /** The VM handle. */
|
|---|
| 718 | PVM pVM;
|
|---|
| 719 | /** The VMCPU handle. */
|
|---|
| 720 | PVMCPU pVCpu;
|
|---|
| 721 | /** code buffer for instruction emulation */
|
|---|
| 722 | void *pvCodeBuffer;
|
|---|
| 723 | /** code buffer size */
|
|---|
| 724 | uint32_t cbCodeBuffer;
|
|---|
| 725 | #endif /* VBOX */
|
|---|
| 726 |
|
|---|
| 727 | /* processor features (e.g. for CPUID insn) */
|
|---|
| 728 | #ifndef VBOX /* remR3CpuId deals with these */
|
|---|
| 729 | uint32_t cpuid_level;
|
|---|
| 730 | uint32_t cpuid_vendor1;
|
|---|
| 731 | uint32_t cpuid_vendor2;
|
|---|
| 732 | uint32_t cpuid_vendor3;
|
|---|
| 733 | uint32_t cpuid_version;
|
|---|
| 734 | #endif /* !VBOX */
|
|---|
| 735 | uint32_t cpuid_features;
|
|---|
| 736 | uint32_t cpuid_ext_features;
|
|---|
| 737 | #ifndef VBOX
|
|---|
| 738 | uint32_t cpuid_xlevel;
|
|---|
| 739 | uint32_t cpuid_model[12];
|
|---|
| 740 | #endif /* !VBOX */
|
|---|
| 741 | uint32_t cpuid_ext2_features;
|
|---|
| 742 | uint32_t cpuid_ext3_features;
|
|---|
| 743 | uint32_t cpuid_apic_id;
|
|---|
| 744 | #ifndef VBOX
|
|---|
| 745 | int cpuid_vendor_override;
|
|---|
| 746 |
|
|---|
| 747 | /* MTRRs */
|
|---|
| 748 | uint64_t mtrr_fixed[11];
|
|---|
| 749 | uint64_t mtrr_deftype;
|
|---|
| 750 | MTRRVar mtrr_var[8];
|
|---|
| 751 |
|
|---|
| 752 | /* For KVM */
|
|---|
| 753 | uint32_t mp_state;
|
|---|
| 754 | int32_t exception_injected;
|
|---|
| 755 | int32_t interrupt_injected;
|
|---|
| 756 | uint8_t soft_interrupt;
|
|---|
| 757 | uint8_t nmi_injected;
|
|---|
| 758 | uint8_t nmi_pending;
|
|---|
| 759 | uint8_t has_error_code;
|
|---|
| 760 | uint32_t sipi_vector;
|
|---|
| 761 |
|
|---|
| 762 | uint32_t cpuid_kvm_features;
|
|---|
| 763 |
|
|---|
| 764 | /* in order to simplify APIC support, we leave this pointer to the
|
|---|
| 765 | user */
|
|---|
| 766 | struct DeviceState *apic_state;
|
|---|
| 767 |
|
|---|
| 768 | uint64 mcg_cap;
|
|---|
| 769 | uint64 mcg_status;
|
|---|
| 770 | uint64 mcg_ctl;
|
|---|
| 771 | uint64 mce_banks[MCE_BANKS_DEF*4];
|
|---|
| 772 |
|
|---|
| 773 | uint64_t tsc_aux;
|
|---|
| 774 |
|
|---|
| 775 | /* vmstate */
|
|---|
| 776 | uint16_t fpus_vmstate;
|
|---|
| 777 | uint16_t fptag_vmstate;
|
|---|
| 778 | uint16_t fpregs_format_vmstate;
|
|---|
| 779 |
|
|---|
| 780 | uint64_t xstate_bv;
|
|---|
| 781 | XMMReg ymmh_regs[CPU_NB_REGS];
|
|---|
| 782 |
|
|---|
| 783 | uint64_t xcr0;
|
|---|
| 784 | #else /* VBOX */
|
|---|
| 785 |
|
|---|
| 786 | /** Alignment padding. */
|
|---|
| 787 | # if HC_ARCH_BITS == 64 \
|
|---|
| 788 | || ( HC_ARCH_BITS == 32 \
|
|---|
| 789 | && !defined(RT_OS_WINDOWS) \
|
|---|
| 790 | && ( (!defined(VBOX_ENABLE_VBOXREM64) && !defined(RT_OS_SOLARIS) && !defined(RT_OS_FREEBSD)) \
|
|---|
| 791 | || (defined(VBOX_ENABLE_VBOXREM64) && (defined(RT_OS_SOLARIS) || defined(RT_OS_FREEBSD))) ) )
|
|---|
| 792 | uint32_t alignment2[1];
|
|---|
| 793 | # endif
|
|---|
| 794 |
|
|---|
| 795 | /** Profiling tb_flush. */
|
|---|
| 796 | STAMPROFILE StatTbFlush;
|
|---|
| 797 |
|
|---|
| 798 | /** Addends for HVA -> GPA translations. */
|
|---|
| 799 | target_phys_addr_t phys_addends[NB_MMU_MODES][CPU_TLB_SIZE];
|
|---|
| 800 | #endif /* VBOX */
|
|---|
| 801 | } CPUX86State;
|
|---|
| 802 |
|
|---|
| 803 | #ifdef VBOX
|
|---|
| 804 |
|
|---|
| 805 | /* Version 1.6 structure; just for loading the old saved state */
|
|---|
| 806 | typedef struct SegmentCache_Ver16 {
|
|---|
| 807 | uint32_t selector;
|
|---|
| 808 | uint32_t base;
|
|---|
| 809 | uint32_t limit;
|
|---|
| 810 | uint32_t flags;
|
|---|
| 811 | /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
|
|---|
| 812 | uint32_t newselector;
|
|---|
| 813 | } SegmentCache_Ver16;
|
|---|
| 814 |
|
|---|
| 815 | # define CPU_NB_REGS_VER16 8
|
|---|
| 816 |
|
|---|
| 817 | /* Version 1.6 structure; just for loading the old saved state */
|
|---|
| 818 | typedef struct CPUX86State_Ver16 {
|
|---|
| 819 | # if TARGET_LONG_BITS > HOST_LONG_BITS
|
|---|
| 820 | /* temporaries if we cannot store them in host registers */
|
|---|
| 821 | uint32_t t0, t1, t2;
|
|---|
| 822 | # endif
|
|---|
| 823 |
|
|---|
| 824 | /* standard registers */
|
|---|
| 825 | uint32_t regs[CPU_NB_REGS_VER16];
|
|---|
| 826 | uint32_t eip;
|
|---|
| 827 | uint32_t eflags; /* eflags register. During CPU emulation, CC
|
|---|
| 828 | flags and DF are set to zero because they are
|
|---|
| 829 | stored elsewhere */
|
|---|
| 830 |
|
|---|
| 831 | /* emulator internal eflags handling */
|
|---|
| 832 | uint32_t cc_src;
|
|---|
| 833 | uint32_t cc_dst;
|
|---|
| 834 | uint32_t cc_op;
|
|---|
| 835 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
|---|
| 836 | uint32_t hflags; /* hidden flags, see HF_xxx constants */
|
|---|
| 837 |
|
|---|
| 838 | /* segments */
|
|---|
| 839 | SegmentCache_Ver16 segs[6]; /* selector values */
|
|---|
| 840 | SegmentCache_Ver16 ldt;
|
|---|
| 841 | SegmentCache_Ver16 tr;
|
|---|
| 842 | SegmentCache_Ver16 gdt; /* only base and limit are used */
|
|---|
| 843 | SegmentCache_Ver16 idt; /* only base and limit are used */
|
|---|
| 844 |
|
|---|
| 845 | uint32_t cr[5]; /* NOTE: cr1 is unused */
|
|---|
| 846 | uint32_t a20_mask;
|
|---|
| 847 |
|
|---|
| 848 | /* FPU state */
|
|---|
| 849 | unsigned int fpstt; /* top of stack index */
|
|---|
| 850 | unsigned int fpus;
|
|---|
| 851 | unsigned int fpuc;
|
|---|
| 852 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */
|
|---|
| 853 | union {
|
|---|
| 854 | # ifdef USE_X86LDOUBLE
|
|---|
| 855 | CPU86_LDouble d __attribute__((aligned(16)));
|
|---|
| 856 | # else
|
|---|
| 857 | CPU86_LDouble d;
|
|---|
| 858 | # endif
|
|---|
| 859 | MMXReg mmx;
|
|---|
| 860 | } fpregs[8];
|
|---|
| 861 |
|
|---|
| 862 | /* emulator internal variables */
|
|---|
| 863 | float_status fp_status;
|
|---|
| 864 | # ifdef VBOX
|
|---|
| 865 | uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
|
|---|
| 866 | # endif
|
|---|
| 867 | CPU86_LDouble ft0;
|
|---|
| 868 | # if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
|
|---|
| 869 | uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
|
|---|
| 870 | # endif
|
|---|
| 871 | union {
|
|---|
| 872 | float f;
|
|---|
| 873 | double d;
|
|---|
| 874 | int i32;
|
|---|
| 875 | int64_t i64;
|
|---|
| 876 | } fp_convert;
|
|---|
| 877 |
|
|---|
| 878 | float_status sse_status;
|
|---|
| 879 | uint32_t mxcsr;
|
|---|
| 880 | XMMReg xmm_regs[CPU_NB_REGS_VER16];
|
|---|
| 881 | XMMReg xmm_t0;
|
|---|
| 882 | MMXReg mmx_t0;
|
|---|
| 883 |
|
|---|
| 884 | /* sysenter registers */
|
|---|
| 885 | uint32_t sysenter_cs;
|
|---|
| 886 | uint32_t sysenter_esp;
|
|---|
| 887 | uint32_t sysenter_eip;
|
|---|
| 888 | # ifdef VBOX
|
|---|
| 889 | uint32_t alignment0;
|
|---|
| 890 | # endif
|
|---|
| 891 | uint64_t efer;
|
|---|
| 892 | uint64_t star;
|
|---|
| 893 |
|
|---|
| 894 | uint64_t pat;
|
|---|
| 895 |
|
|---|
| 896 | /* temporary data for USE_CODE_COPY mode */
|
|---|
| 897 | # ifdef USE_CODE_COPY
|
|---|
| 898 | uint32_t tmp0;
|
|---|
| 899 | uint32_t saved_esp;
|
|---|
| 900 | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
|
|---|
| 901 | # endif
|
|---|
| 902 |
|
|---|
| 903 | /* exception/interrupt handling */
|
|---|
| 904 | jmp_buf jmp_env;
|
|---|
| 905 | } CPUX86State_Ver16;
|
|---|
| 906 |
|
|---|
| 907 | /** CPUX86State state flags
|
|---|
| 908 | * @{ */
|
|---|
| 909 | # define CPU_RAW_RING0 0x0002 /* Set after first time RawR0 is executed, never cleared. */
|
|---|
| 910 | # define CPU_EMULATE_SINGLE_INSTR 0x0040 /* Execute a single instruction in emulation mode */
|
|---|
| 911 | # define CPU_EMULATE_SINGLE_STEP 0x0080 /* go into single step mode */
|
|---|
| 912 | # define CPU_RAW_HWACC 0x0100 /* Set after first time HWACC is executed, never cleared. */
|
|---|
| 913 | /** @} */
|
|---|
| 914 | #endif /* !VBOX */
|
|---|
| 915 |
|
|---|
| 916 | #ifdef VBOX
|
|---|
| 917 | CPUX86State *cpu_x86_init(CPUX86State *env, const char *cpu_model);
|
|---|
| 918 | #else /* !VBOX */
|
|---|
| 919 | CPUX86State *cpu_x86_init(const char *cpu_model);
|
|---|
| 920 | #endif /* !VBOX */
|
|---|
| 921 | int cpu_x86_exec(CPUX86State *s);
|
|---|
| 922 | void cpu_x86_close(CPUX86State *s);
|
|---|
| 923 | void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
|
|---|
| 924 | const char *optarg);
|
|---|
| 925 | void x86_cpudef_setup(void);
|
|---|
| 926 |
|
|---|
| 927 | int cpu_get_pic_interrupt(CPUX86State *s);
|
|---|
| 928 | /* MSDOS compatibility mode FPU exception support */
|
|---|
| 929 | void cpu_set_ferr(CPUX86State *s);
|
|---|
| 930 |
|
|---|
| 931 | /* this function must always be used to load data in the segment
|
|---|
| 932 | cache: it synchronizes the hflags with the segment cache values */
|
|---|
| 933 | static inline void cpu_x86_load_seg_cache(CPUX86State *env,
|
|---|
| 934 | int seg_reg, unsigned int selector,
|
|---|
| 935 | target_ulong base,
|
|---|
| 936 | unsigned int limit,
|
|---|
| 937 | unsigned int flags)
|
|---|
| 938 | {
|
|---|
| 939 | SegmentCache *sc;
|
|---|
| 940 | unsigned int new_hflags;
|
|---|
| 941 |
|
|---|
| 942 | sc = &env->segs[seg_reg];
|
|---|
| 943 | sc->selector = selector;
|
|---|
| 944 | sc->base = base;
|
|---|
| 945 | sc->limit = limit;
|
|---|
| 946 | #ifndef VBOX
|
|---|
| 947 | sc->flags = flags;
|
|---|
| 948 | #else
|
|---|
| 949 | if (flags & DESC_P_MASK)
|
|---|
| 950 | flags |= DESC_A_MASK; /* Make sure the A bit is set to avoid trouble. */
|
|---|
| 951 | sc->flags = flags;
|
|---|
| 952 | sc->newselector = 0;
|
|---|
| 953 | sc->fVBoxFlags = CPUMSELREG_FLAGS_VALID;
|
|---|
| 954 | #endif
|
|---|
| 955 |
|
|---|
| 956 | /* update the hidden flags */
|
|---|
| 957 | {
|
|---|
| 958 | if (seg_reg == R_CS) {
|
|---|
| 959 | #ifdef TARGET_X86_64
|
|---|
| 960 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
|
|---|
| 961 | /* long mode */
|
|---|
| 962 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
|
|---|
| 963 | env->hflags &= ~(HF_ADDSEG_MASK);
|
|---|
| 964 | } else
|
|---|
| 965 | #endif
|
|---|
| 966 | {
|
|---|
| 967 | /* legacy / compatibility case */
|
|---|
| 968 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
|
|---|
| 969 | >> (DESC_B_SHIFT - HF_CS32_SHIFT);
|
|---|
| 970 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
|
|---|
| 971 | new_hflags;
|
|---|
| 972 | }
|
|---|
| 973 | }
|
|---|
| 974 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
|
|---|
| 975 | >> (DESC_B_SHIFT - HF_SS32_SHIFT);
|
|---|
| 976 | if (env->hflags & HF_CS64_MASK) {
|
|---|
| 977 | /* zero base assumed for DS, ES and SS in long mode */
|
|---|
| 978 | } else if (!(env->cr[0] & CR0_PE_MASK) ||
|
|---|
| 979 | (env->eflags & VM_MASK) ||
|
|---|
| 980 | !(env->hflags & HF_CS32_MASK)) {
|
|---|
| 981 | /* XXX: try to avoid this test. The problem comes from the
|
|---|
| 982 | fact that is real mode or vm86 mode we only modify the
|
|---|
| 983 | 'base' and 'selector' fields of the segment cache to go
|
|---|
| 984 | faster. A solution may be to force addseg to one in
|
|---|
| 985 | translate-i386.c. */
|
|---|
| 986 | new_hflags |= HF_ADDSEG_MASK;
|
|---|
| 987 | } else {
|
|---|
| 988 | new_hflags |= ((env->segs[R_DS].base |
|
|---|
| 989 | env->segs[R_ES].base |
|
|---|
| 990 | env->segs[R_SS].base) != 0) <<
|
|---|
| 991 | HF_ADDSEG_SHIFT;
|
|---|
| 992 | }
|
|---|
| 993 | env->hflags = (env->hflags &
|
|---|
| 994 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
|
|---|
| 995 | }
|
|---|
| 996 | }
|
|---|
| 997 |
|
|---|
| 998 | static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
|
|---|
| 999 | int sipi_vector)
|
|---|
| 1000 | {
|
|---|
| 1001 | env->eip = 0;
|
|---|
| 1002 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
|
|---|
| 1003 | sipi_vector << 12,
|
|---|
| 1004 | env->segs[R_CS].limit,
|
|---|
| 1005 | env->segs[R_CS].flags);
|
|---|
| 1006 | env->halted = 0;
|
|---|
| 1007 | }
|
|---|
| 1008 |
|
|---|
| 1009 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
|
|---|
| 1010 | target_ulong *base, unsigned int *limit,
|
|---|
| 1011 | unsigned int *flags);
|
|---|
| 1012 |
|
|---|
| 1013 | /* wrapper, just in case memory mappings must be changed */
|
|---|
| 1014 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
|
|---|
| 1015 | {
|
|---|
| 1016 | #if HF_CPL_MASK == 3
|
|---|
| 1017 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
|
|---|
| 1018 | #else
|
|---|
| 1019 | #error HF_CPL_MASK is hardcoded
|
|---|
| 1020 | #endif
|
|---|
| 1021 | }
|
|---|
| 1022 |
|
|---|
| 1023 | /* op_helper.c */
|
|---|
| 1024 | /* used for debug or cpu save/restore */
|
|---|
| 1025 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
|
|---|
| 1026 | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
|
|---|
| 1027 |
|
|---|
| 1028 | /* cpu-exec.c */
|
|---|
| 1029 | /* the following helpers are only usable in user mode simulation as
|
|---|
| 1030 | they can trigger unexpected exceptions */
|
|---|
| 1031 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
|
|---|
| 1032 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
|
|---|
| 1033 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
|
|---|
| 1034 |
|
|---|
| 1035 | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
|---|
| 1036 | signal handlers to inform the virtual CPU of exceptions. non zero
|
|---|
| 1037 | is returned if the signal was handled by the virtual CPU. */
|
|---|
| 1038 | int cpu_x86_signal_handler(int host_signum, void *pinfo,
|
|---|
| 1039 | void *puc);
|
|---|
| 1040 |
|
|---|
| 1041 | /* cpuid.c */
|
|---|
| 1042 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
|---|
| 1043 | uint32_t *eax, uint32_t *ebx,
|
|---|
| 1044 | uint32_t *ecx, uint32_t *edx);
|
|---|
| 1045 | int cpu_x86_register (CPUX86State *env, const char *cpu_model);
|
|---|
| 1046 | void cpu_clear_apic_feature(CPUX86State *env);
|
|---|
| 1047 |
|
|---|
| 1048 | /* helper.c */
|
|---|
| 1049 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
|---|
| 1050 | int is_write, int mmu_idx, int is_softmmu);
|
|---|
| 1051 | #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
|
|---|
| 1052 | void cpu_x86_set_a20(CPUX86State *env, int a20_state);
|
|---|
| 1053 |
|
|---|
| 1054 | static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
|
|---|
| 1055 | {
|
|---|
| 1056 | return (dr7 >> (index * 2)) & 3;
|
|---|
| 1057 | }
|
|---|
| 1058 |
|
|---|
| 1059 | static inline int hw_breakpoint_type(unsigned long dr7, int index)
|
|---|
| 1060 | {
|
|---|
| 1061 | return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
|
|---|
| 1062 | }
|
|---|
| 1063 |
|
|---|
| 1064 | static inline int hw_breakpoint_len(unsigned long dr7, int index)
|
|---|
| 1065 | {
|
|---|
| 1066 | int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
|
|---|
| 1067 | return (len == 2) ? 8 : len + 1;
|
|---|
| 1068 | }
|
|---|
| 1069 |
|
|---|
| 1070 | void hw_breakpoint_insert(CPUX86State *env, int index);
|
|---|
| 1071 | void hw_breakpoint_remove(CPUX86State *env, int index);
|
|---|
| 1072 | int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
|
|---|
| 1073 |
|
|---|
| 1074 | /* will be suppressed */
|
|---|
| 1075 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
|
|---|
| 1076 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
|
|---|
| 1077 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
|
|---|
| 1078 |
|
|---|
| 1079 | /* hw/pc.c */
|
|---|
| 1080 | void cpu_smm_update(CPUX86State *env);
|
|---|
| 1081 | uint64_t cpu_get_tsc(CPUX86State *env);
|
|---|
| 1082 |
|
|---|
| 1083 | /* used to debug */
|
|---|
| 1084 | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
|
|---|
| 1085 | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
|
|---|
| 1086 |
|
|---|
| 1087 | #ifdef VBOX
|
|---|
| 1088 | int cpu_rdmsr(CPUX86State *env, uint32_t idMsr, uint64_t *puValue);
|
|---|
| 1089 | int cpu_wrmsr(CPUX86State *env, uint32_t idMsr, uint64_t uValue);
|
|---|
| 1090 | void cpu_trap_raw(CPUX86State *env1);
|
|---|
| 1091 |
|
|---|
| 1092 | /* in helper.c */
|
|---|
| 1093 | uint8_t read_byte(CPUX86State *env1, target_ulong addr);
|
|---|
| 1094 | uint16_t read_word(CPUX86State *env1, target_ulong addr);
|
|---|
| 1095 | void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val);
|
|---|
| 1096 | uint32_t read_dword(CPUX86State *env1, target_ulong addr);
|
|---|
| 1097 | void write_word(CPUX86State *env1, target_ulong addr, uint16_t val);
|
|---|
| 1098 | void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val);
|
|---|
| 1099 | /* in helper.c */
|
|---|
| 1100 | int emulate_single_instr(CPUX86State *env1);
|
|---|
| 1101 | int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl);
|
|---|
| 1102 |
|
|---|
| 1103 | void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr);
|
|---|
| 1104 | void save_raw_fp_state(CPUX86State *env, uint8_t *ptr);
|
|---|
| 1105 | #endif /* VBOX */
|
|---|
| 1106 |
|
|---|
| 1107 | #define TARGET_PAGE_BITS 12
|
|---|
| 1108 |
|
|---|
| 1109 | #ifdef TARGET_X86_64
|
|---|
| 1110 | #define TARGET_PHYS_ADDR_SPACE_BITS 52
|
|---|
| 1111 | /* ??? This is really 48 bits, sign-extended, but the only thing
|
|---|
| 1112 | accessible to userland with bit 48 set is the VSYSCALL, and that
|
|---|
| 1113 | is handled via other mechanisms. */
|
|---|
| 1114 | #define TARGET_VIRT_ADDR_SPACE_BITS 47
|
|---|
| 1115 | #else
|
|---|
| 1116 | #define TARGET_PHYS_ADDR_SPACE_BITS 36
|
|---|
| 1117 | #define TARGET_VIRT_ADDR_SPACE_BITS 32
|
|---|
| 1118 | #endif
|
|---|
| 1119 |
|
|---|
| 1120 | #define cpu_init cpu_x86_init
|
|---|
| 1121 | #define cpu_exec cpu_x86_exec
|
|---|
| 1122 | #define cpu_gen_code cpu_x86_gen_code
|
|---|
| 1123 | #define cpu_signal_handler cpu_x86_signal_handler
|
|---|
| 1124 | #define cpu_list_id x86_cpu_list
|
|---|
| 1125 | #define cpudef_setup x86_cpudef_setup
|
|---|
| 1126 |
|
|---|
| 1127 | #define CPU_SAVE_VERSION 12
|
|---|
| 1128 |
|
|---|
| 1129 | /* MMU modes definitions */
|
|---|
| 1130 | #define MMU_MODE0_SUFFIX _kernel
|
|---|
| 1131 | #define MMU_MODE1_SUFFIX _user
|
|---|
| 1132 | #define MMU_USER_IDX 1
|
|---|
| 1133 | static inline int cpu_mmu_index (CPUState *env)
|
|---|
| 1134 | {
|
|---|
| 1135 | return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
|
|---|
| 1136 | }
|
|---|
| 1137 |
|
|---|
| 1138 | /* translate.c */
|
|---|
| 1139 | void optimize_flags_init(void);
|
|---|
| 1140 |
|
|---|
| 1141 | typedef struct CCTable {
|
|---|
| 1142 | int (*compute_all)(void); /* return all the flags */
|
|---|
| 1143 | int (*compute_c)(void); /* return the C flag */
|
|---|
| 1144 | } CCTable;
|
|---|
| 1145 |
|
|---|
| 1146 | #if defined(CONFIG_USER_ONLY)
|
|---|
| 1147 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
|
|---|
| 1148 | {
|
|---|
| 1149 | if (newsp)
|
|---|
| 1150 | env->regs[R_ESP] = newsp;
|
|---|
| 1151 | env->regs[R_EAX] = 0;
|
|---|
| 1152 | }
|
|---|
| 1153 | #endif
|
|---|
| 1154 |
|
|---|
| 1155 | #include "cpu-all.h"
|
|---|
| 1156 | #include "svm.h"
|
|---|
| 1157 |
|
|---|
| 1158 | #ifndef VBOX
|
|---|
| 1159 | #if !defined(CONFIG_USER_ONLY)
|
|---|
| 1160 | #include "hw/apic.h"
|
|---|
| 1161 | #endif
|
|---|
| 1162 | #else /* VBOX */
|
|---|
| 1163 | extern void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
|
|---|
| 1164 | extern uint8_t cpu_get_apic_tpr(CPUX86State *env);
|
|---|
| 1165 | extern uint64_t cpu_get_apic_base(CPUX86State *env);
|
|---|
| 1166 | #endif /* VBOX */
|
|---|
| 1167 |
|
|---|
| 1168 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
|
|---|
| 1169 | target_ulong *cs_base, int *flags)
|
|---|
| 1170 | {
|
|---|
| 1171 | *cs_base = env->segs[R_CS].base;
|
|---|
| 1172 | *pc = *cs_base + env->eip;
|
|---|
| 1173 | *flags = env->hflags |
|
|---|
| 1174 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
|
|---|
| 1175 | }
|
|---|
| 1176 |
|
|---|
| 1177 | #ifndef VBOX
|
|---|
| 1178 | void apic_init_reset(CPUState *env);
|
|---|
| 1179 | void apic_sipi(CPUState *env);
|
|---|
| 1180 | void do_cpu_init(CPUState *env);
|
|---|
| 1181 | void do_cpu_sipi(CPUState *env);
|
|---|
| 1182 | #endif /* !VBOX */
|
|---|
| 1183 | #endif /* CPU_I386_H */
|
|---|
