| 1 | /*
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| 2 | * Software MMU support
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| 3 | *
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| 4 | * Copyright (c) 2003 Fabrice Bellard
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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| 18 | */
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| 19 |
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| 20 | /*
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| 21 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 22 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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| 23 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 24 | * a choice of LGPL license versions is made available with the language indicating
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| 25 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 26 | * of the LGPL is applied is otherwise unspecified.
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| 27 | */
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| 28 | #include "qemu-timer.h"
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| 29 |
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| 30 | #define DATA_SIZE (1 << SHIFT)
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| 31 |
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| 32 | #if DATA_SIZE == 8
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| 33 | #define SUFFIX q
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| 34 | #define USUFFIX q
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| 35 | #define DATA_TYPE uint64_t
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| 36 | #ifdef VBOX
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| 37 | # define DATA_TYPE_PROMOTED uint64_t
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| 38 | #endif
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| 39 | #elif DATA_SIZE == 4
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| 40 | #define SUFFIX l
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| 41 | #define USUFFIX l
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| 42 | #define DATA_TYPE uint32_t
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| 43 | #ifdef VBOX
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| 44 | # define DATA_TYPE_PROMOTED RTCCUINTREG
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| 45 | #endif
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| 46 | #elif DATA_SIZE == 2
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| 47 | #define SUFFIX w
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| 48 | #define USUFFIX uw
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| 49 | #define DATA_TYPE uint16_t
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| 50 | #ifdef VBOX
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| 51 | # define DATA_TYPE_PROMOTED RTCCUINTREG
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| 52 | #endif
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| 53 | #elif DATA_SIZE == 1
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| 54 | #define SUFFIX b
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| 55 | #define USUFFIX ub
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| 56 | #define DATA_TYPE uint8_t
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| 57 | #ifdef VBOX
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| 58 | # define DATA_TYPE_PROMOTED RTCCUINTREG
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| 59 | #endif
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| 60 | #else
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| 61 | #error unsupported data size
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| 62 | #endif
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| 63 |
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| 64 | #ifdef SOFTMMU_CODE_ACCESS
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| 65 | #define READ_ACCESS_TYPE 2
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| 66 | #define ADDR_READ addr_code
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| 67 | #else
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| 68 | #define READ_ACCESS_TYPE 0
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| 69 | #define ADDR_READ addr_read
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| 70 | #endif
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| 71 |
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| 72 | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 73 | int mmu_idx,
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| 74 | void *retaddr);
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| 75 | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
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| 76 | target_ulong addr,
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| 77 | void *retaddr)
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| 78 | {
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| 79 | DATA_TYPE res;
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| 80 | int index;
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| 81 | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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| 82 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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| 83 | env->mem_io_pc = (unsigned long)retaddr;
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| 84 | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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| 85 | && !can_do_io(env)) {
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| 86 | cpu_io_recompile(env, retaddr);
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| 87 | }
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| 88 |
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| 89 | env->mem_io_vaddr = addr;
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| 90 | #if SHIFT <= 2
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| 91 | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
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| 92 | #else
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| 93 | #ifdef TARGET_WORDS_BIGENDIAN
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| 94 | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
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| 95 | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
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| 96 | #else
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| 97 | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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| 98 | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
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| 99 | #endif
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| 100 | #endif /* SHIFT > 2 */
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| 101 | return res;
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| 102 | }
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| 103 |
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| 104 | /* handle all cases except unaligned access which span two pages */
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| 105 | #ifndef VBOX
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| 106 | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 107 | int mmu_idx)
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| 108 | #else
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| 109 | /* Load helpers invoked from generated code, and TCG makes an assumption
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| 110 | that valid value takes the whole register, why gcc after 4.3 may
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| 111 | use only lower part of register for smaller types. So force promotion. */
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| 112 | DATA_TYPE_PROMOTED REGPARM
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| 113 | glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 114 | int mmu_idx)
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| 115 | #endif
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| 116 | {
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| 117 | DATA_TYPE res;
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| 118 | int index;
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| 119 | target_ulong tlb_addr;
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| 120 | target_phys_addr_t ioaddr;
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| 121 | unsigned long addend;
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| 122 | void *retaddr;
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| 123 |
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| 124 | /* test if there is match for unaligned or IO access */
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| 125 | /* XXX: could done more in memory macro in a non portable way */
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| 126 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 127 | redo:
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| 128 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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| 129 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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| 130 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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| 131 | /* IO access */
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| 132 | if ((addr & (DATA_SIZE - 1)) != 0)
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| 133 | goto do_unaligned_access;
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| 134 | retaddr = GETPC();
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| 135 | ioaddr = env->iotlb[mmu_idx][index];
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| 136 | res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
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| 137 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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| 138 | /* slow unaligned access (it spans two pages or IO) */
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| 139 | do_unaligned_access:
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| 140 | retaddr = GETPC();
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| 141 | #ifdef ALIGNED_ONLY
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| 142 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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| 143 | #endif
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| 144 | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
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| 145 | mmu_idx, retaddr);
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| 146 | } else {
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| 147 | /* unaligned/aligned access in the same page */
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| 148 | #ifdef ALIGNED_ONLY
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| 149 | if ((addr & (DATA_SIZE - 1)) != 0) {
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| 150 | retaddr = GETPC();
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| 151 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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| 152 | }
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| 153 | #endif
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| 154 | addend = env->tlb_table[mmu_idx][index].addend;
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| 155 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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| 156 | }
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| 157 | } else {
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| 158 | /* the page is not in the TLB : fill it */
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| 159 | retaddr = GETPC();
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| 160 | #ifdef ALIGNED_ONLY
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| 161 | if ((addr & (DATA_SIZE - 1)) != 0)
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| 162 | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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| 163 | #endif
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| 164 | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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| 165 | goto redo;
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| 166 | }
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| 167 | return res;
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| 168 | }
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| 169 |
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| 170 | /* handle all unaligned cases */
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| 171 | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 172 | int mmu_idx,
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| 173 | void *retaddr)
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| 174 | {
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| 175 | DATA_TYPE res, res1, res2;
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| 176 | int index, shift;
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| 177 | target_phys_addr_t ioaddr;
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| 178 | unsigned long addend;
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| 179 | target_ulong tlb_addr, addr1, addr2;
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| 180 |
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| 181 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 182 | redo:
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| 183 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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| 184 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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| 185 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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| 186 | /* IO access */
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| 187 | if ((addr & (DATA_SIZE - 1)) != 0)
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| 188 | goto do_unaligned_access;
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| 189 | ioaddr = env->iotlb[mmu_idx][index];
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| 190 | res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
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| 191 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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| 192 | do_unaligned_access:
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| 193 | /* slow unaligned access (it spans two pages) */
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| 194 | addr1 = addr & ~(DATA_SIZE - 1);
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| 195 | addr2 = addr1 + DATA_SIZE;
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| 196 | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
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| 197 | mmu_idx, retaddr);
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| 198 | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
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| 199 | mmu_idx, retaddr);
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| 200 | shift = (addr & (DATA_SIZE - 1)) * 8;
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| 201 | #ifdef TARGET_WORDS_BIGENDIAN
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| 202 | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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| 203 | #else
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| 204 | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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| 205 | #endif
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| 206 | res = (DATA_TYPE)res;
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| 207 | } else {
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| 208 | /* unaligned/aligned access in the same page */
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| 209 | addend = env->tlb_table[mmu_idx][index].addend;
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| 210 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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| 211 | }
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| 212 | } else {
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| 213 | /* the page is not in the TLB : fill it */
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| 214 | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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| 215 | goto redo;
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| 216 | }
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| 217 | return res;
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| 218 | }
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| 219 |
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| 220 | #ifndef SOFTMMU_CODE_ACCESS
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| 221 |
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| 222 | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 223 | DATA_TYPE val,
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| 224 | int mmu_idx,
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| 225 | void *retaddr);
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| 226 |
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| 227 | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
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| 228 | DATA_TYPE val,
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| 229 | target_ulong addr,
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| 230 | void *retaddr)
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| 231 | {
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| 232 | int index;
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| 233 | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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| 234 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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| 235 | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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| 236 | && !can_do_io(env)) {
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| 237 | cpu_io_recompile(env, retaddr);
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| 238 | }
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| 239 |
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| 240 | env->mem_io_vaddr = addr;
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| 241 | env->mem_io_pc = (unsigned long)retaddr;
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| 242 | #if SHIFT <= 2
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| 243 | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
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| 244 | #else
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| 245 | #ifdef TARGET_WORDS_BIGENDIAN
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| 246 | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
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| 247 | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
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| 248 | #else
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| 249 | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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| 250 | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
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| 251 | #endif
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| 252 | #endif /* SHIFT > 2 */
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| 253 | }
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| 254 |
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| 255 | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 256 | DATA_TYPE val,
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| 257 | int mmu_idx)
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| 258 | {
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| 259 | target_phys_addr_t ioaddr;
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| 260 | unsigned long addend;
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| 261 | target_ulong tlb_addr;
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| 262 | void *retaddr;
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| 263 | int index;
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| 264 |
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| 265 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 266 | redo:
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| 267 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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| 268 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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| 269 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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| 270 | /* IO access */
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| 271 | if ((addr & (DATA_SIZE - 1)) != 0)
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| 272 | goto do_unaligned_access;
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| 273 | retaddr = GETPC();
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| 274 | ioaddr = env->iotlb[mmu_idx][index];
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| 275 | glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
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| 276 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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| 277 | do_unaligned_access:
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| 278 | retaddr = GETPC();
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| 279 | #ifdef ALIGNED_ONLY
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| 280 | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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| 281 | #endif
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| 282 | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
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| 283 | mmu_idx, retaddr);
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| 284 | } else {
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| 285 | /* aligned/unaligned access in the same page */
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| 286 | #ifdef ALIGNED_ONLY
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| 287 | if ((addr & (DATA_SIZE - 1)) != 0) {
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| 288 | retaddr = GETPC();
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| 289 | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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| 290 | }
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| 291 | #endif
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| 292 | addend = env->tlb_table[mmu_idx][index].addend;
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| 293 | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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| 294 | }
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| 295 | } else {
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| 296 | /* the page is not in the TLB : fill it */
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| 297 | retaddr = GETPC();
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| 298 | #ifdef ALIGNED_ONLY
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| 299 | if ((addr & (DATA_SIZE - 1)) != 0)
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| 300 | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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| 301 | #endif
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| 302 | tlb_fill(addr, 1, mmu_idx, retaddr);
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| 303 | goto redo;
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| 304 | }
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| 305 | }
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| 306 |
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| 307 | /* handles all unaligned cases */
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| 308 | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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| 309 | DATA_TYPE val,
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| 310 | int mmu_idx,
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| 311 | void *retaddr)
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| 312 | {
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| 313 | target_phys_addr_t ioaddr;
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| 314 | unsigned long addend;
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| 315 | target_ulong tlb_addr;
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| 316 | int index, i;
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| 317 |
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| 318 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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| 319 | redo:
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| 320 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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| 321 | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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| 322 | if (tlb_addr & ~TARGET_PAGE_MASK) {
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| 323 | /* IO access */
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| 324 | if ((addr & (DATA_SIZE - 1)) != 0)
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| 325 | goto do_unaligned_access;
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| 326 | ioaddr = env->iotlb[mmu_idx][index];
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| 327 | glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
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| 328 | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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| 329 | do_unaligned_access:
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| 330 | /* XXX: not efficient, but simple */
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| 331 | /* Note: relies on the fact that tlb_fill() does not remove the
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| 332 | * previous page from the TLB cache. */
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| 333 | for(i = DATA_SIZE - 1; i >= 0; i--) {
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| 334 | #ifdef TARGET_WORDS_BIGENDIAN
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| 335 | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
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| 336 | mmu_idx, retaddr);
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| 337 | #else
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| 338 | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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| 339 | mmu_idx, retaddr);
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| 340 | #endif
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| 341 | }
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| 342 | } else {
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| 343 | /* aligned/unaligned access in the same page */
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| 344 | addend = env->tlb_table[mmu_idx][index].addend;
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| 345 | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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| 346 | }
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| 347 | } else {
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| 348 | /* the page is not in the TLB : fill it */
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| 349 | tlb_fill(addr, 1, mmu_idx, retaddr);
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| 350 | goto redo;
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| 351 | }
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| 352 | }
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| 353 |
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| 354 | #endif /* !defined(SOFTMMU_CODE_ACCESS) */
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| 355 |
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| 356 | #ifdef VBOX
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| 357 | # undef DATA_TYPE_PROMOTED
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| 358 | #endif
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| 359 | #undef READ_ACCESS_TYPE
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| 360 | #undef SHIFT
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| 361 | #undef DATA_TYPE
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| 362 | #undef SUFFIX
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| 363 | #undef USUFFIX
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| 364 | #undef DATA_SIZE
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| 365 | #undef ADDR_READ
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