1 | /*
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2 | * Software MMU support
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3 | *
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4 | * Copyright (c) 2003 Fabrice Bellard
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5 | *
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6 | * This library is free software; you can redistribute it and/or
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7 | * modify it under the terms of the GNU Lesser General Public
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8 | * License as published by the Free Software Foundation; either
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9 | * version 2 of the License, or (at your option) any later version.
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10 | *
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11 | * This library is distributed in the hope that it will be useful,
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | * Lesser General Public License for more details.
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15 | *
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16 | * You should have received a copy of the GNU Lesser General Public
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17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | */
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19 |
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20 | /*
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21 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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22 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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23 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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24 | * a choice of LGPL license versions is made available with the language indicating
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25 | * that LGPLv2 or any later version may be used, or where a choice of which version
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26 | * of the LGPL is applied is otherwise unspecified.
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27 | */
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28 |
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29 | #if DATA_SIZE == 8
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30 | #define SUFFIX q
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31 | #define USUFFIX q
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32 | #define DATA_TYPE uint64_t
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33 | #elif DATA_SIZE == 4
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34 | #define SUFFIX l
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35 | #define USUFFIX l
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36 | #define DATA_TYPE uint32_t
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37 | #elif DATA_SIZE == 2
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38 | #define SUFFIX w
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39 | #define USUFFIX uw
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40 | #define DATA_TYPE uint16_t
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41 | #define DATA_STYPE int16_t
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42 | #elif DATA_SIZE == 1
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43 | #define SUFFIX b
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44 | #define USUFFIX ub
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45 | #define DATA_TYPE uint8_t
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46 | #define DATA_STYPE int8_t
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47 | #else
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48 | #error unsupported data size
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49 | #endif
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50 |
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51 | #if ACCESS_TYPE < (NB_MMU_MODES)
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52 |
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53 | #define CPU_MMU_INDEX ACCESS_TYPE
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54 | #define MMUSUFFIX _mmu
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55 |
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56 | #elif ACCESS_TYPE == (NB_MMU_MODES)
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57 |
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58 | #define CPU_MMU_INDEX (cpu_mmu_index(env))
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59 | #define MMUSUFFIX _mmu
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60 |
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61 | #elif ACCESS_TYPE == (NB_MMU_MODES + 1)
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62 |
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63 | #define CPU_MMU_INDEX (cpu_mmu_index(env))
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64 | #define MMUSUFFIX _cmmu
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65 |
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66 | #else
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67 | #error invalid ACCESS_TYPE
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68 | #endif
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69 |
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70 | #if DATA_SIZE == 8
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71 | #define RES_TYPE uint64_t
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72 | #else
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73 | #define RES_TYPE uint32_t
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74 | #endif
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75 |
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76 | #if ACCESS_TYPE == (NB_MMU_MODES + 1)
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77 | #define ADDR_READ addr_code
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78 | #else
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79 | #define ADDR_READ addr_read
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80 | #endif
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81 |
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82 | /* generic load/store macros */
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83 |
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84 | static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
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85 | {
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86 | int page_index;
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87 | RES_TYPE res;
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88 | target_ulong addr;
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89 | uintptr_t physaddr;
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90 | int mmu_idx;
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91 |
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92 | addr = ptr;
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93 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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94 | mmu_idx = CPU_MMU_INDEX;
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95 | if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
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96 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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97 | res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
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98 | } else {
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99 | physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
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100 | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
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101 | }
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102 | return res;
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103 | }
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104 |
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105 | #if DATA_SIZE <= 2
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106 | static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
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107 | {
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108 | int res, page_index;
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109 | target_ulong addr;
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110 | uintptr_t physaddr;
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111 | int mmu_idx;
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112 |
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113 | addr = ptr;
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114 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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115 | mmu_idx = CPU_MMU_INDEX;
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116 | if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
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117 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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118 | res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
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119 | } else {
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120 | physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
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121 | res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
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122 | }
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123 | return res;
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124 | }
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125 | #endif
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126 |
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127 | #if ACCESS_TYPE != (NB_MMU_MODES + 1)
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128 |
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129 | /* generic store macro */
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130 |
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131 | static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
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132 | {
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133 | int page_index;
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134 | target_ulong addr;
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135 | uintptr_t physaddr;
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136 | int mmu_idx;
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137 |
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138 | addr = ptr;
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139 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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140 | mmu_idx = CPU_MMU_INDEX;
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141 | if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
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142 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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143 | glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
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144 | } else {
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145 | physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
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146 | glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
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147 | }
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148 | }
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149 |
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150 | #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
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151 |
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152 | #if ACCESS_TYPE != (NB_MMU_MODES + 1)
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153 |
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154 | #if DATA_SIZE == 8
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155 | static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
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156 | {
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157 | union {
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158 | float64 d;
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159 | uint64_t i;
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160 | } u;
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161 | u.i = glue(ldq, MEMSUFFIX)(ptr);
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162 | return u.d;
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163 | }
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164 |
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165 | static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
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166 | {
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167 | union {
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168 | float64 d;
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169 | uint64_t i;
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170 | } u;
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171 | u.d = v;
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172 | glue(stq, MEMSUFFIX)(ptr, u.i);
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173 | }
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174 | #endif /* DATA_SIZE == 8 */
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175 |
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176 | #if DATA_SIZE == 4
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177 | static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
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178 | {
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179 | union {
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180 | float32 f;
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181 | uint32_t i;
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182 | } u;
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183 | u.i = glue(ldl, MEMSUFFIX)(ptr);
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184 | return u.f;
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185 | }
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186 |
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187 | static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
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188 | {
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189 | union {
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190 | float32 f;
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191 | uint32_t i;
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192 | } u;
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193 | u.f = v;
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194 | glue(stl, MEMSUFFIX)(ptr, u.i);
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195 | }
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196 | #endif /* DATA_SIZE == 4 */
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197 |
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198 | #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
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199 |
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200 | #undef RES_TYPE
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201 | #undef DATA_TYPE
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202 | #undef DATA_STYPE
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203 | #undef SUFFIX
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204 | #undef USUFFIX
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205 | #undef DATA_SIZE
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206 | #undef CPU_MMU_INDEX
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207 | #undef MMUSUFFIX
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208 | #undef ADDR_READ
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