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source: vbox/trunk/src/recompiler/softmmu_header.h@ 1125

Last change on this file since 1125 was 1, checked in by vboxsync, 55 years ago

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1/*
2 * Software MMU support
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#if DATA_SIZE == 8
22#define SUFFIX q
23#define USUFFIX q
24#define DATA_TYPE uint64_t
25#elif DATA_SIZE == 4
26#define SUFFIX l
27#define USUFFIX l
28#define DATA_TYPE uint32_t
29#elif DATA_SIZE == 2
30#define SUFFIX w
31#define USUFFIX uw
32#define DATA_TYPE uint16_t
33#define DATA_STYPE int16_t
34#elif DATA_SIZE == 1
35#define SUFFIX b
36#define USUFFIX ub
37#define DATA_TYPE uint8_t
38#define DATA_STYPE int8_t
39#else
40#error unsupported data size
41#endif
42
43#if ACCESS_TYPE == 0
44
45#define CPU_MEM_INDEX 0
46#define MMUSUFFIX _mmu
47
48#elif ACCESS_TYPE == 1
49
50#define CPU_MEM_INDEX 1
51#define MMUSUFFIX _mmu
52
53#elif ACCESS_TYPE == 2
54
55#ifdef TARGET_I386
56#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
57#elif defined (TARGET_PPC)
58#define CPU_MEM_INDEX (msr_pr)
59#elif defined (TARGET_SPARC)
60#define CPU_MEM_INDEX ((env->psrs) == 0)
61#endif
62#define MMUSUFFIX _mmu
63
64#elif ACCESS_TYPE == 3
65
66#ifdef TARGET_I386
67#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
68#elif defined (TARGET_PPC)
69#define CPU_MEM_INDEX (msr_pr)
70#elif defined (TARGET_SPARC)
71#define CPU_MEM_INDEX ((env->psrs) == 0)
72#endif
73#define MMUSUFFIX _cmmu
74
75#else
76#error invalid ACCESS_TYPE
77#endif
78
79#if DATA_SIZE == 8
80#define RES_TYPE uint64_t
81#else
82#define RES_TYPE int
83#endif
84
85
86DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
87 int is_user);
88void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
89
90#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
91 (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
92
93static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
94{
95 int res;
96
97 asm volatile ("movl %1, %%edx\n"
98 "movl %1, %%eax\n"
99 "shrl %3, %%edx\n"
100 "andl %4, %%eax\n"
101 "andl %2, %%edx\n"
102 "leal %5(%%edx, %%ebp), %%edx\n"
103 "cmpl (%%edx), %%eax\n"
104 "movl %1, %%eax\n"
105 "je 1f\n"
106 "pushl %6\n"
107 "call %7\n"
108 "popl %%edx\n"
109 "movl %%eax, %0\n"
110 "jmp 2f\n"
111 "1:\n"
112 "addl 4(%%edx), %%eax\n"
113#if DATA_SIZE == 1
114 "movzbl (%%eax), %0\n"
115#elif DATA_SIZE == 2
116 "movzwl (%%eax), %0\n"
117#elif DATA_SIZE == 4
118 "movl (%%eax), %0\n"
119#else
120#error unsupported size
121#endif
122 "2:\n"
123 : "=r" (res)
124 : "r" (ptr),
125 "i" ((CPU_TLB_SIZE - 1) << 3),
126 "i" (TARGET_PAGE_BITS - 3),
127 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
128 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
129 "i" (CPU_MEM_INDEX),
130 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
131 : "%eax", "%ecx", "%edx", "memory", "cc");
132 return res;
133}
134
135#if DATA_SIZE <= 2
136static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
137{
138 int res;
139
140 asm volatile ("movl %1, %%edx\n"
141 "movl %1, %%eax\n"
142 "shrl %3, %%edx\n"
143 "andl %4, %%eax\n"
144 "andl %2, %%edx\n"
145 "leal %5(%%edx, %%ebp), %%edx\n"
146 "cmpl (%%edx), %%eax\n"
147 "movl %1, %%eax\n"
148 "je 1f\n"
149 "pushl %6\n"
150 "call %7\n"
151 "popl %%edx\n"
152#if DATA_SIZE == 1
153 "movsbl %%al, %0\n"
154#elif DATA_SIZE == 2
155 "movswl %%ax, %0\n"
156#else
157#error unsupported size
158#endif
159 "jmp 2f\n"
160 "1:\n"
161 "addl 4(%%edx), %%eax\n"
162#if DATA_SIZE == 1
163 "movsbl (%%eax), %0\n"
164#elif DATA_SIZE == 2
165 "movswl (%%eax), %0\n"
166#else
167#error unsupported size
168#endif
169 "2:\n"
170 : "=r" (res)
171 : "r" (ptr),
172 "i" ((CPU_TLB_SIZE - 1) << 3),
173 "i" (TARGET_PAGE_BITS - 3),
174 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
175 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
176 "i" (CPU_MEM_INDEX),
177 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
178 : "%eax", "%ecx", "%edx", "memory", "cc");
179 return res;
180}
181#endif
182
183#ifdef VBOX
184/* generic store macro */
185
186static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
187{
188 int index;
189 target_ulong addr;
190 unsigned long physaddr;
191 int is_user;
192
193 addr = ptr;
194 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
195 is_user = CPU_MEM_INDEX;
196 if (__builtin_expect(env->tlb_write[is_user][index].address !=
197 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
198 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
199 } else {
200 physaddr = addr + env->tlb_write[is_user][index].addend;
201 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
202 }
203}
204
205#else
206
207static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
208{
209 asm volatile ("movl %0, %%edx\n"
210 "movl %0, %%eax\n"
211 "shrl %3, %%edx\n"
212 "andl %4, %%eax\n"
213 "andl %2, %%edx\n"
214 "leal %5(%%edx, %%ebp), %%edx\n"
215 "cmpl (%%edx), %%eax\n"
216 "movl %0, %%eax\n"
217 "je 1f\n"
218#if DATA_SIZE == 1
219 "movzbl %b1, %%edx\n"
220#elif DATA_SIZE == 2
221 "movzwl %w1, %%edx\n"
222#elif DATA_SIZE == 4
223 "movl %1, %%edx\n"
224#else
225#error unsupported size
226#endif
227 "pushl %6\n"
228 "call %7\n"
229 "popl %%eax\n"
230 "jmp 2f\n"
231 "1:\n"
232 "addl 4(%%edx), %%eax\n"
233#if DATA_SIZE == 1
234 "movb %b1, (%%eax)\n"
235#elif DATA_SIZE == 2
236 "movw %w1, (%%eax)\n"
237#elif DATA_SIZE == 4
238 "movl %1, (%%eax)\n"
239#else
240#error unsupported size
241#endif
242 "2:\n"
243 :
244 : "r" (ptr),
245/* NOTE: 'q' would be needed as constraint, but we could not use it
246 with T1 ! */
247 "r" (v),
248 "i" ((CPU_TLB_SIZE - 1) << 3),
249 "i" (TARGET_PAGE_BITS - 3),
250 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
251 "m" (*(uint32_t *)offsetof(CPUState, tlb_write[CPU_MEM_INDEX][0].address)),
252 "i" (CPU_MEM_INDEX),
253 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
254 : "%eax", "%ecx", "%edx", "memory", "cc");
255}
256#endif /* VBOX */
257
258#else
259
260/* generic load/store macros */
261
262static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
263{
264 int index;
265 RES_TYPE res;
266 target_ulong addr;
267 unsigned long physaddr;
268 int is_user;
269
270 addr = ptr;
271 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
272 is_user = CPU_MEM_INDEX;
273 if (__builtin_expect(env->tlb_read[is_user][index].address !=
274 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
275 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
276 } else {
277 physaddr = addr + env->tlb_read[is_user][index].addend;
278 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
279 }
280 return res;
281}
282
283#if DATA_SIZE <= 2
284static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
285{
286 int res, index;
287 target_ulong addr;
288 unsigned long physaddr;
289 int is_user;
290
291 addr = ptr;
292 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
293 is_user = CPU_MEM_INDEX;
294 if (__builtin_expect(env->tlb_read[is_user][index].address !=
295 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
296 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
297 } else {
298 physaddr = addr + env->tlb_read[is_user][index].addend;
299 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
300 }
301 return res;
302}
303#endif
304
305/* generic store macro */
306
307static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
308{
309 int index;
310 target_ulong addr;
311 unsigned long physaddr;
312 int is_user;
313
314 addr = ptr;
315 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
316 is_user = CPU_MEM_INDEX;
317 if (__builtin_expect(env->tlb_write[is_user][index].address !=
318 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
319 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
320 } else {
321 physaddr = addr + env->tlb_write[is_user][index].addend;
322 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
323 }
324}
325
326#endif
327
328#if DATA_SIZE == 8
329static inline double glue(ldfq, MEMSUFFIX)(target_ulong ptr)
330{
331 union {
332 double d;
333 uint64_t i;
334 } u;
335 u.i = glue(ldq, MEMSUFFIX)(ptr);
336 return u.d;
337}
338
339static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, double v)
340{
341 union {
342 double d;
343 uint64_t i;
344 } u;
345 u.d = v;
346 glue(stq, MEMSUFFIX)(ptr, u.i);
347}
348#endif /* DATA_SIZE == 8 */
349
350#if DATA_SIZE == 4
351static inline float glue(ldfl, MEMSUFFIX)(target_ulong ptr)
352{
353 union {
354 float f;
355 uint32_t i;
356 } u;
357 u.i = glue(ldl, MEMSUFFIX)(ptr);
358 return u.f;
359}
360
361static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float v)
362{
363 union {
364 float f;
365 uint32_t i;
366 } u;
367 u.f = v;
368 glue(stl, MEMSUFFIX)(ptr, u.i);
369}
370#endif /* DATA_SIZE == 4 */
371
372#undef RES_TYPE
373#undef DATA_TYPE
374#undef DATA_STYPE
375#undef SUFFIX
376#undef USUFFIX
377#undef DATA_SIZE
378#undef CPU_MEM_INDEX
379#undef MMUSUFFIX
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