VirtualBox

source: vbox/trunk/src/recompiler/new/cpu-all.h@ 535

Last change on this file since 535 was 104, checked in by vboxsync, 18 years ago

phys_ram_size should be RTGCPHYS.

  • Property svn:eol-style set to native
File size: 29.2 KB
Line 
1/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_ALL_H
21#define CPU_ALL_H
22
23#ifdef VBOX
24# ifndef LOG_GROUP
25# include <VBox/log.h>
26# define LOG_GROUP LOG_GROUP_REM
27# endif
28#endif
29
30#if defined(__arm__) || defined(__sparc__)
31#define WORDS_ALIGNED
32#endif
33
34/* some important defines:
35 *
36 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
37 * memory accesses.
38 *
39 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
40 * otherwise little endian.
41 *
42 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
43 *
44 * TARGET_WORDS_BIGENDIAN : same for target cpu
45 */
46
47#include "bswap.h"
48
49#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
50#define BSWAP_NEEDED
51#endif
52
53#ifdef BSWAP_NEEDED
54
55static inline uint16_t tswap16(uint16_t s)
56{
57 return bswap16(s);
58}
59
60static inline uint32_t tswap32(uint32_t s)
61{
62 return bswap32(s);
63}
64
65static inline uint64_t tswap64(uint64_t s)
66{
67 return bswap64(s);
68}
69
70static inline void tswap16s(uint16_t *s)
71{
72 *s = bswap16(*s);
73}
74
75static inline void tswap32s(uint32_t *s)
76{
77 *s = bswap32(*s);
78}
79
80static inline void tswap64s(uint64_t *s)
81{
82 *s = bswap64(*s);
83}
84
85#else
86
87static inline uint16_t tswap16(uint16_t s)
88{
89 return s;
90}
91
92static inline uint32_t tswap32(uint32_t s)
93{
94 return s;
95}
96
97static inline uint64_t tswap64(uint64_t s)
98{
99 return s;
100}
101
102static inline void tswap16s(uint16_t *s)
103{
104}
105
106static inline void tswap32s(uint32_t *s)
107{
108}
109
110static inline void tswap64s(uint64_t *s)
111{
112}
113
114#endif
115
116#if TARGET_LONG_SIZE == 4
117#define tswapl(s) tswap32(s)
118#define tswapls(s) tswap32s((uint32_t *)(s))
119#define bswaptls(s) bswap32s(s)
120#else
121#define tswapl(s) tswap64(s)
122#define tswapls(s) tswap64s((uint64_t *)(s))
123#define bswaptls(s) bswap64s(s)
124#endif
125
126/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
127 endian ! */
128typedef union {
129 float64 d;
130#if defined(WORDS_BIGENDIAN) \
131 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
132 struct {
133 uint32_t upper;
134 uint32_t lower;
135 } l;
136#else
137 struct {
138 uint32_t lower;
139 uint32_t upper;
140 } l;
141#endif
142 uint64_t ll;
143} CPU_DoubleU;
144
145/* CPU memory access without any memory or io remapping */
146
147/*
148 * the generic syntax for the memory accesses is:
149 *
150 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
151 *
152 * store: st{type}{size}{endian}_{access_type}(ptr, val)
153 *
154 * type is:
155 * (empty): integer access
156 * f : float access
157 *
158 * sign is:
159 * (empty): for floats or 32 bit size
160 * u : unsigned
161 * s : signed
162 *
163 * size is:
164 * b: 8 bits
165 * w: 16 bits
166 * l: 32 bits
167 * q: 64 bits
168 *
169 * endian is:
170 * (empty): target cpu endianness or 8 bit access
171 * r : reversed target cpu endianness (not implemented yet)
172 * be : big endian (not implemented yet)
173 * le : little endian (not implemented yet)
174 *
175 * access_type is:
176 * raw : host memory access
177 * user : user mode access using soft MMU
178 * kernel : kernel mode access using soft MMU
179 */
180#ifdef VBOX
181
182#if !defined(REMR3PHYSREADWRITE_DEFINED)
183#define REMR3PHYSREADWRITE_DEFINED
184/* Header sharing between vbox & qemu is rather ugly. */
185void remR3PhysRead(uint8_t *pbSrcPhys, void *pvDst, unsigned cb);
186uint8_t remR3PhysReadU8(uint8_t *pbSrcPhys);
187int8_t remR3PhysReadS8(uint8_t *pbSrcPhys);
188uint16_t remR3PhysReadU16(uint8_t *pbSrcPhys);
189int16_t remR3PhysReadS16(uint8_t *pbSrcPhys);
190uint32_t remR3PhysReadU32(uint8_t *pbSrcPhys);
191int32_t remR3PhysReadS32(uint8_t *pbSrcPhys);
192uint64_t remR3PhysReadU64(uint8_t *pbSrcPhys);
193int64_t remR3PhysReadS64(uint8_t *pbSrcPhys);
194void remR3PhysWrite(uint8_t *pbDstPhys, const void *pvSrc, unsigned cb);
195void remR3PhysWriteU8(uint8_t *pbDstPhys, uint8_t val);
196void remR3PhysWriteU16(uint8_t *pbDstPhys, uint16_t val);
197void remR3PhysWriteU32(uint8_t *pbDstPhys, uint32_t val);
198void remR3PhysWriteU64(uint8_t *pbDstPhys, uint64_t val);
199#endif
200
201static inline int ldub_p(void *ptr)
202{
203 return remR3PhysReadU8(ptr);
204}
205
206static inline int ldsb_p(void *ptr)
207{
208 return remR3PhysReadS8(ptr);
209}
210
211static inline void stb_p(void *ptr, int v)
212{
213 remR3PhysWriteU8(ptr, v);
214}
215
216static inline int lduw_le_p(void *ptr)
217{
218 return remR3PhysReadU16(ptr);
219}
220
221static inline int ldsw_le_p(void *ptr)
222{
223 return remR3PhysReadS16(ptr);
224}
225
226static inline void stw_le_p(void *ptr, int v)
227{
228 remR3PhysWriteU16(ptr, v);
229}
230
231static inline int ldl_le_p(void *ptr)
232{
233 return remR3PhysReadU32(ptr);
234}
235
236static inline void stl_le_p(void *ptr, int v)
237{
238 remR3PhysWriteU32(ptr, v);
239}
240
241static inline void stq_le_p(void *ptr, uint64_t v)
242{
243 remR3PhysWriteU64(ptr, v);
244}
245
246static inline uint64_t ldq_le_p(void *ptr)
247{
248 return remR3PhysReadU64(ptr);
249}
250
251/* float access */
252
253static inline float32 ldfl_le_p(void *ptr)
254{
255 union {
256 float32 f;
257 uint32_t i;
258 } u;
259 u.i = ldl_le_p(ptr);
260 return u.f;
261}
262
263static inline void stfl_le_p(void *ptr, float32 v)
264{
265 union {
266 float32 f;
267 uint32_t i;
268 } u;
269 u.f = v;
270 stl_le_p(ptr, u.i);
271}
272
273static inline float64 ldfq_le_p(void *ptr)
274{
275 CPU_DoubleU u;
276 u.l.lower = ldl_le_p(ptr);
277 u.l.upper = ldl_le_p(ptr + 4);
278 return u.d;
279}
280
281static inline void stfq_le_p(void *ptr, float64 v)
282{
283 CPU_DoubleU u;
284 u.d = v;
285 stl_le_p(ptr, u.l.lower);
286 stl_le_p(ptr + 4, u.l.upper);
287}
288
289#else /* !VBOX */
290
291static inline int ldub_p(void *ptr)
292{
293 return *(uint8_t *)ptr;
294}
295
296static inline int ldsb_p(void *ptr)
297{
298 return *(int8_t *)ptr;
299}
300
301static inline void stb_p(void *ptr, int v)
302{
303 *(uint8_t *)ptr = v;
304}
305
306/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
307 kernel handles unaligned load/stores may give better results, but
308 it is a system wide setting : bad */
309#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
310
311/* conservative code for little endian unaligned accesses */
312static inline int lduw_le_p(void *ptr)
313{
314#ifdef __powerpc__
315 int val;
316 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
317 return val;
318#else
319 uint8_t *p = ptr;
320 return p[0] | (p[1] << 8);
321#endif
322}
323
324static inline int ldsw_le_p(void *ptr)
325{
326#ifdef __powerpc__
327 int val;
328 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
329 return (int16_t)val;
330#else
331 uint8_t *p = ptr;
332 return (int16_t)(p[0] | (p[1] << 8));
333#endif
334}
335
336static inline int ldl_le_p(void *ptr)
337{
338#ifdef __powerpc__
339 int val;
340 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
341 return val;
342#else
343 uint8_t *p = ptr;
344 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
345#endif
346}
347
348static inline uint64_t ldq_le_p(void *ptr)
349{
350 uint8_t *p = ptr;
351 uint32_t v1, v2;
352 v1 = ldl_le_p(p);
353 v2 = ldl_le_p(p + 4);
354 return v1 | ((uint64_t)v2 << 32);
355}
356
357static inline void stw_le_p(void *ptr, int v)
358{
359#ifdef __powerpc__
360 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
361#else
362 uint8_t *p = ptr;
363 p[0] = v;
364 p[1] = v >> 8;
365#endif
366}
367
368static inline void stl_le_p(void *ptr, int v)
369{
370#ifdef __powerpc__
371 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
372#else
373 uint8_t *p = ptr;
374 p[0] = v;
375 p[1] = v >> 8;
376 p[2] = v >> 16;
377 p[3] = v >> 24;
378#endif
379}
380
381static inline void stq_le_p(void *ptr, uint64_t v)
382{
383 uint8_t *p = ptr;
384 stl_le_p(p, (uint32_t)v);
385 stl_le_p(p + 4, v >> 32);
386}
387
388/* float access */
389
390static inline float32 ldfl_le_p(void *ptr)
391{
392 union {
393 float32 f;
394 uint32_t i;
395 } u;
396 u.i = ldl_le_p(ptr);
397 return u.f;
398}
399
400static inline void stfl_le_p(void *ptr, float32 v)
401{
402 union {
403 float32 f;
404 uint32_t i;
405 } u;
406 u.f = v;
407 stl_le_p(ptr, u.i);
408}
409
410static inline float64 ldfq_le_p(void *ptr)
411{
412 CPU_DoubleU u;
413 u.l.lower = ldl_le_p(ptr);
414 u.l.upper = ldl_le_p(ptr + 4);
415 return u.d;
416}
417
418static inline void stfq_le_p(void *ptr, float64 v)
419{
420 CPU_DoubleU u;
421 u.d = v;
422 stl_le_p(ptr, u.l.lower);
423 stl_le_p(ptr + 4, u.l.upper);
424}
425
426#else
427
428static inline int lduw_le_p(void *ptr)
429{
430 return *(uint16_t *)ptr;
431}
432
433static inline int ldsw_le_p(void *ptr)
434{
435 return *(int16_t *)ptr;
436}
437
438static inline int ldl_le_p(void *ptr)
439{
440 return *(uint32_t *)ptr;
441}
442
443static inline uint64_t ldq_le_p(void *ptr)
444{
445 return *(uint64_t *)ptr;
446}
447
448static inline void stw_le_p(void *ptr, int v)
449{
450 *(uint16_t *)ptr = v;
451}
452
453static inline void stl_le_p(void *ptr, int v)
454{
455 *(uint32_t *)ptr = v;
456}
457
458static inline void stq_le_p(void *ptr, uint64_t v)
459{
460 *(uint64_t *)ptr = v;
461}
462
463/* float access */
464
465static inline float32 ldfl_le_p(void *ptr)
466{
467 return *(float32 *)ptr;
468}
469
470static inline float64 ldfq_le_p(void *ptr)
471{
472 return *(float64 *)ptr;
473}
474
475static inline void stfl_le_p(void *ptr, float32 v)
476{
477 *(float32 *)ptr = v;
478}
479
480static inline void stfq_le_p(void *ptr, float64 v)
481{
482 *(float64 *)ptr = v;
483}
484#endif
485#endif /* !VBOX */
486
487#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
488
489static inline int lduw_be_p(void *ptr)
490{
491#if defined(__i386__)
492 int val;
493 asm volatile ("movzwl %1, %0\n"
494 "xchgb %b0, %h0\n"
495 : "=q" (val)
496 : "m" (*(uint16_t *)ptr));
497 return val;
498#else
499 uint8_t *b = (uint8_t *) ptr;
500 return ((b[0] << 8) | b[1]);
501#endif
502}
503
504static inline int ldsw_be_p(void *ptr)
505{
506#if defined(__i386__)
507 int val;
508 asm volatile ("movzwl %1, %0\n"
509 "xchgb %b0, %h0\n"
510 : "=q" (val)
511 : "m" (*(uint16_t *)ptr));
512 return (int16_t)val;
513#else
514 uint8_t *b = (uint8_t *) ptr;
515 return (int16_t)((b[0] << 8) | b[1]);
516#endif
517}
518
519static inline int ldl_be_p(void *ptr)
520{
521#if defined(__i386__) || defined(__x86_64__)
522 int val;
523 asm volatile ("movl %1, %0\n"
524 "bswap %0\n"
525 : "=r" (val)
526 : "m" (*(uint32_t *)ptr));
527 return val;
528#else
529 uint8_t *b = (uint8_t *) ptr;
530 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
531#endif
532}
533
534static inline uint64_t ldq_be_p(void *ptr)
535{
536 uint32_t a,b;
537 a = ldl_be_p(ptr);
538 b = ldl_be_p(ptr+4);
539 return (((uint64_t)a<<32)|b);
540}
541
542static inline void stw_be_p(void *ptr, int v)
543{
544#if defined(__i386__)
545 asm volatile ("xchgb %b0, %h0\n"
546 "movw %w0, %1\n"
547 : "=q" (v)
548 : "m" (*(uint16_t *)ptr), "0" (v));
549#else
550 uint8_t *d = (uint8_t *) ptr;
551 d[0] = v >> 8;
552 d[1] = v;
553#endif
554}
555
556static inline void stl_be_p(void *ptr, int v)
557{
558#if defined(__i386__) || defined(__x86_64__)
559 asm volatile ("bswap %0\n"
560 "movl %0, %1\n"
561 : "=r" (v)
562 : "m" (*(uint32_t *)ptr), "0" (v));
563#else
564 uint8_t *d = (uint8_t *) ptr;
565 d[0] = v >> 24;
566 d[1] = v >> 16;
567 d[2] = v >> 8;
568 d[3] = v;
569#endif
570}
571
572static inline void stq_be_p(void *ptr, uint64_t v)
573{
574 stl_be_p(ptr, v >> 32);
575 stl_be_p(ptr + 4, v);
576}
577
578/* float access */
579
580static inline float32 ldfl_be_p(void *ptr)
581{
582 union {
583 float32 f;
584 uint32_t i;
585 } u;
586 u.i = ldl_be_p(ptr);
587 return u.f;
588}
589
590static inline void stfl_be_p(void *ptr, float32 v)
591{
592 union {
593 float32 f;
594 uint32_t i;
595 } u;
596 u.f = v;
597 stl_be_p(ptr, u.i);
598}
599
600static inline float64 ldfq_be_p(void *ptr)
601{
602 CPU_DoubleU u;
603 u.l.upper = ldl_be_p(ptr);
604 u.l.lower = ldl_be_p(ptr + 4);
605 return u.d;
606}
607
608static inline void stfq_be_p(void *ptr, float64 v)
609{
610 CPU_DoubleU u;
611 u.d = v;
612 stl_be_p(ptr, u.l.upper);
613 stl_be_p(ptr + 4, u.l.lower);
614}
615
616#else
617
618static inline int lduw_be_p(void *ptr)
619{
620 return *(uint16_t *)ptr;
621}
622
623static inline int ldsw_be_p(void *ptr)
624{
625 return *(int16_t *)ptr;
626}
627
628static inline int ldl_be_p(void *ptr)
629{
630 return *(uint32_t *)ptr;
631}
632
633static inline uint64_t ldq_be_p(void *ptr)
634{
635 return *(uint64_t *)ptr;
636}
637
638static inline void stw_be_p(void *ptr, int v)
639{
640 *(uint16_t *)ptr = v;
641}
642
643static inline void stl_be_p(void *ptr, int v)
644{
645 *(uint32_t *)ptr = v;
646}
647
648static inline void stq_be_p(void *ptr, uint64_t v)
649{
650 *(uint64_t *)ptr = v;
651}
652
653/* float access */
654
655static inline float32 ldfl_be_p(void *ptr)
656{
657 return *(float32 *)ptr;
658}
659
660static inline float64 ldfq_be_p(void *ptr)
661{
662 return *(float64 *)ptr;
663}
664
665static inline void stfl_be_p(void *ptr, float32 v)
666{
667 *(float32 *)ptr = v;
668}
669
670static inline void stfq_be_p(void *ptr, float64 v)
671{
672 *(float64 *)ptr = v;
673}
674
675#endif
676
677/* target CPU memory access functions */
678#if defined(TARGET_WORDS_BIGENDIAN)
679#define lduw_p(p) lduw_be_p(p)
680#define ldsw_p(p) ldsw_be_p(p)
681#define ldl_p(p) ldl_be_p(p)
682#define ldq_p(p) ldq_be_p(p)
683#define ldfl_p(p) ldfl_be_p(p)
684#define ldfq_p(p) ldfq_be_p(p)
685#define stw_p(p, v) stw_be_p(p, v)
686#define stl_p(p, v) stl_be_p(p, v)
687#define stq_p(p, v) stq_be_p(p, v)
688#define stfl_p(p, v) stfl_be_p(p, v)
689#define stfq_p(p, v) stfq_be_p(p, v)
690#else
691#define lduw_p(p) lduw_le_p(p)
692#define ldsw_p(p) ldsw_le_p(p)
693#define ldl_p(p) ldl_le_p(p)
694#define ldq_p(p) ldq_le_p(p)
695#define ldfl_p(p) ldfl_le_p(p)
696#define ldfq_p(p) ldfq_le_p(p)
697#define stw_p(p, v) stw_le_p(p, v)
698#define stl_p(p, v) stl_le_p(p, v)
699#define stq_p(p, v) stq_le_p(p, v)
700#define stfl_p(p, v) stfl_le_p(p, v)
701#define stfq_p(p, v) stfq_le_p(p, v)
702#endif
703
704/* MMU memory access macros */
705
706#if defined(CONFIG_USER_ONLY)
707/* On some host systems the guest address space is reserved on the host.
708 * This allows the guest address space to be offset to a convenient location.
709 */
710//#define GUEST_BASE 0x20000000
711#define GUEST_BASE 0
712
713/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
714#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
715#define h2g(x) ((target_ulong)(x - GUEST_BASE))
716
717#define saddr(x) g2h(x)
718#define laddr(x) g2h(x)
719
720#else /* !CONFIG_USER_ONLY */
721/* NOTE: we use double casts if pointers and target_ulong have
722 different sizes */
723#define saddr(x) (uint8_t *)(long)(x)
724#define laddr(x) (uint8_t *)(long)(x)
725#endif
726
727#define ldub_raw(p) ldub_p(laddr((p)))
728#define ldsb_raw(p) ldsb_p(laddr((p)))
729#define lduw_raw(p) lduw_p(laddr((p)))
730#define ldsw_raw(p) ldsw_p(laddr((p)))
731#define ldl_raw(p) ldl_p(laddr((p)))
732#define ldq_raw(p) ldq_p(laddr((p)))
733#define ldfl_raw(p) ldfl_p(laddr((p)))
734#define ldfq_raw(p) ldfq_p(laddr((p)))
735#define stb_raw(p, v) stb_p(saddr((p)), v)
736#define stw_raw(p, v) stw_p(saddr((p)), v)
737#define stl_raw(p, v) stl_p(saddr((p)), v)
738#define stq_raw(p, v) stq_p(saddr((p)), v)
739#define stfl_raw(p, v) stfl_p(saddr((p)), v)
740#define stfq_raw(p, v) stfq_p(saddr((p)), v)
741
742
743#if defined(CONFIG_USER_ONLY)
744
745/* if user mode, no other memory access functions */
746#define ldub(p) ldub_raw(p)
747#define ldsb(p) ldsb_raw(p)
748#define lduw(p) lduw_raw(p)
749#define ldsw(p) ldsw_raw(p)
750#define ldl(p) ldl_raw(p)
751#define ldq(p) ldq_raw(p)
752#define ldfl(p) ldfl_raw(p)
753#define ldfq(p) ldfq_raw(p)
754#define stb(p, v) stb_raw(p, v)
755#define stw(p, v) stw_raw(p, v)
756#define stl(p, v) stl_raw(p, v)
757#define stq(p, v) stq_raw(p, v)
758#define stfl(p, v) stfl_raw(p, v)
759#define stfq(p, v) stfq_raw(p, v)
760
761#define ldub_code(p) ldub_raw(p)
762#define ldsb_code(p) ldsb_raw(p)
763#define lduw_code(p) lduw_raw(p)
764#define ldsw_code(p) ldsw_raw(p)
765#define ldl_code(p) ldl_raw(p)
766
767#define ldub_kernel(p) ldub_raw(p)
768#define ldsb_kernel(p) ldsb_raw(p)
769#define lduw_kernel(p) lduw_raw(p)
770#define ldsw_kernel(p) ldsw_raw(p)
771#define ldl_kernel(p) ldl_raw(p)
772#define ldfl_kernel(p) ldfl_raw(p)
773#define ldfq_kernel(p) ldfq_raw(p)
774#define stb_kernel(p, v) stb_raw(p, v)
775#define stw_kernel(p, v) stw_raw(p, v)
776#define stl_kernel(p, v) stl_raw(p, v)
777#define stq_kernel(p, v) stq_raw(p, v)
778#define stfl_kernel(p, v) stfl_raw(p, v)
779#define stfq_kernel(p, vt) stfq_raw(p, v)
780
781#endif /* defined(CONFIG_USER_ONLY) */
782
783/* page related stuff */
784
785#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
786#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
787#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
788
789/* ??? These should be the larger of unsigned long and target_ulong. */
790extern unsigned long qemu_real_host_page_size;
791extern unsigned long qemu_host_page_bits;
792extern unsigned long qemu_host_page_size;
793extern unsigned long qemu_host_page_mask;
794
795#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
796
797/* same as PROT_xxx */
798#define PAGE_READ 0x0001
799#define PAGE_WRITE 0x0002
800#define PAGE_EXEC 0x0004
801#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
802#define PAGE_VALID 0x0008
803/* original state of the write flag (used when tracking self-modifying
804 code */
805#define PAGE_WRITE_ORG 0x0010
806
807void page_dump(FILE *f);
808int page_get_flags(target_ulong address);
809void page_set_flags(target_ulong start, target_ulong end, int flags);
810void page_unprotect_range(target_ulong data, target_ulong data_size);
811
812#define SINGLE_CPU_DEFINES
813#ifdef SINGLE_CPU_DEFINES
814
815#if defined(TARGET_I386)
816
817#define CPUState CPUX86State
818#define cpu_init cpu_x86_init
819#define cpu_exec cpu_x86_exec
820#define cpu_gen_code cpu_x86_gen_code
821#define cpu_signal_handler cpu_x86_signal_handler
822
823#elif defined(TARGET_ARM)
824
825#define CPUState CPUARMState
826#define cpu_init cpu_arm_init
827#define cpu_exec cpu_arm_exec
828#define cpu_gen_code cpu_arm_gen_code
829#define cpu_signal_handler cpu_arm_signal_handler
830
831#elif defined(TARGET_SPARC)
832
833#define CPUState CPUSPARCState
834#define cpu_init cpu_sparc_init
835#define cpu_exec cpu_sparc_exec
836#define cpu_gen_code cpu_sparc_gen_code
837#define cpu_signal_handler cpu_sparc_signal_handler
838
839#elif defined(TARGET_PPC)
840
841#define CPUState CPUPPCState
842#define cpu_init cpu_ppc_init
843#define cpu_exec cpu_ppc_exec
844#define cpu_gen_code cpu_ppc_gen_code
845#define cpu_signal_handler cpu_ppc_signal_handler
846
847#elif defined(TARGET_M68K)
848#define CPUState CPUM68KState
849#define cpu_init cpu_m68k_init
850#define cpu_exec cpu_m68k_exec
851#define cpu_gen_code cpu_m68k_gen_code
852#define cpu_signal_handler cpu_m68k_signal_handler
853
854#elif defined(TARGET_MIPS)
855#define CPUState CPUMIPSState
856#define cpu_init cpu_mips_init
857#define cpu_exec cpu_mips_exec
858#define cpu_gen_code cpu_mips_gen_code
859#define cpu_signal_handler cpu_mips_signal_handler
860
861#elif defined(TARGET_SH4)
862#define CPUState CPUSH4State
863#define cpu_init cpu_sh4_init
864#define cpu_exec cpu_sh4_exec
865#define cpu_gen_code cpu_sh4_gen_code
866#define cpu_signal_handler cpu_sh4_signal_handler
867
868#else
869
870#error unsupported target CPU
871
872#endif
873
874#endif /* SINGLE_CPU_DEFINES */
875
876void cpu_dump_state(CPUState *env, FILE *f,
877 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
878 int flags);
879
880void cpu_abort(CPUState *env, const char *fmt, ...);
881extern CPUState *first_cpu;
882extern CPUState *cpu_single_env;
883extern int code_copy_enabled;
884
885#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
886#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
887#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
888#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
889#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
890#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
891#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
892
893#ifdef VBOX
894/** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
895#define CPU_INTERRUPT_SINGLE_INSTR 0x0200
896/** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
897#define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0400
898/** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
899#define CPU_INTERRUPT_RC 0x0800
900/** Exit current TB to process an external interrupt request (also in op.c!!) */
901#define CPU_INTERRUPT_EXTERNAL_EXIT 0x1000
902/** Exit current TB to process an external interrupt request (also in op.c!!) */
903#define CPU_INTERRUPT_EXTERNAL_HARD 0x2000
904/** Exit current TB to process an external interrupt request (also in op.c!!) */
905#define CPU_INTERRUPT_EXTERNAL_TIMER 0x4000
906/** Exit current TB to process an external interrupt request (also in op.c!!) */
907#define CPU_INTERRUPT_EXTERNAL_DMA 0x8000
908#endif /* VBOX */
909void cpu_interrupt(CPUState *s, int mask);
910void cpu_reset_interrupt(CPUState *env, int mask);
911
912int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
913int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
914void cpu_single_step(CPUState *env, int enabled);
915void cpu_reset(CPUState *s);
916
917/* Return the physical page corresponding to a virtual one. Use it
918 only for debugging because no protection checks are done. Return -1
919 if no page found. */
920target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
921
922#define CPU_LOG_TB_OUT_ASM (1 << 0)
923#define CPU_LOG_TB_IN_ASM (1 << 1)
924#define CPU_LOG_TB_OP (1 << 2)
925#define CPU_LOG_TB_OP_OPT (1 << 3)
926#define CPU_LOG_INT (1 << 4)
927#define CPU_LOG_EXEC (1 << 5)
928#define CPU_LOG_PCALL (1 << 6)
929#define CPU_LOG_IOPORT (1 << 7)
930#define CPU_LOG_TB_CPU (1 << 8)
931
932/* define log items */
933typedef struct CPULogItem {
934 int mask;
935 const char *name;
936 const char *help;
937} CPULogItem;
938
939extern CPULogItem cpu_log_items[];
940
941void cpu_set_log(int log_flags);
942void cpu_set_log_filename(const char *filename);
943int cpu_str_to_log_mask(const char *str);
944
945/* IO ports API */
946
947/* NOTE: as these functions may be even used when there is an isa
948 brige on non x86 targets, we always defined them */
949#ifndef NO_CPU_IO_DEFS
950void cpu_outb(CPUState *env, int addr, int val);
951void cpu_outw(CPUState *env, int addr, int val);
952void cpu_outl(CPUState *env, int addr, int val);
953int cpu_inb(CPUState *env, int addr);
954int cpu_inw(CPUState *env, int addr);
955int cpu_inl(CPUState *env, int addr);
956#endif
957
958/* memory API */
959
960#ifndef VBOX
961extern int phys_ram_size;
962extern int phys_ram_fd;
963#endif /* !VBOX */
964extern RTGCPHYS phys_ram_size;
965extern uint8_t *phys_ram_base;
966extern uint8_t *phys_ram_dirty;
967#ifdef VBOX
968/* This is required for bounds checking the phys_ram_dirty accesses. */
969extern uint32_t phys_ram_dirty_size;
970#endif /* VBOX */
971
972/* physical memory access */
973#define TLB_INVALID_MASK (1 << 3)
974#define IO_MEM_SHIFT 4
975#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
976
977#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
978#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
979#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
980#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
981/* acts like a ROM when read and like a device when written. As an
982 exception, the write memory callback gets the ram offset instead of
983 the physical address */
984#define IO_MEM_ROMD (1)
985
986typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
987typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
988
989void cpu_register_physical_memory(target_phys_addr_t start_addr,
990 unsigned long size,
991 unsigned long phys_offset);
992uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
993int cpu_register_io_memory(int io_index,
994 CPUReadMemoryFunc **mem_read,
995 CPUWriteMemoryFunc **mem_write,
996 void *opaque);
997CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
998CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
999
1000void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1001 int len, int is_write);
1002static inline void cpu_physical_memory_read(target_phys_addr_t addr,
1003 uint8_t *buf, int len)
1004{
1005 cpu_physical_memory_rw(addr, buf, len, 0);
1006}
1007static inline void cpu_physical_memory_write(target_phys_addr_t addr,
1008 const uint8_t *buf, int len)
1009{
1010 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
1011}
1012uint32_t ldub_phys(target_phys_addr_t addr);
1013uint32_t lduw_phys(target_phys_addr_t addr);
1014uint32_t ldl_phys(target_phys_addr_t addr);
1015uint64_t ldq_phys(target_phys_addr_t addr);
1016void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
1017void stb_phys(target_phys_addr_t addr, uint32_t val);
1018void stw_phys(target_phys_addr_t addr, uint32_t val);
1019void stl_phys(target_phys_addr_t addr, uint32_t val);
1020void stq_phys(target_phys_addr_t addr, uint64_t val);
1021
1022void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1023 const uint8_t *buf, int len);
1024int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1025 uint8_t *buf, int len, int is_write);
1026
1027#define VGA_DIRTY_FLAG 0x01
1028#define CODE_DIRTY_FLAG 0x02
1029
1030/* read dirty bit (return 0 or 1) */
1031static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1032{
1033#ifdef VBOX
1034 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1035 {
1036 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1037 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1038 return 0;
1039 }
1040#endif
1041 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
1042}
1043
1044static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
1045 int dirty_flags)
1046{
1047#ifdef VBOX
1048 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1049 {
1050 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1051 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1052 return 0xff & dirty_flags; /** @todo I don't think this is the right thing to return, fix! */
1053 }
1054#endif
1055 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1056}
1057
1058static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1059{
1060#ifdef VBOX
1061 if (RT_UNLIKELY((addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
1062 {
1063 Log(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));
1064 /*AssertMsgFailed(("cpu_physical_memory_is_dirty: %VGp\n", (RTGCPHYS)addr));*/
1065 return;
1066 }
1067#endif
1068 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1069}
1070
1071void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1072 int dirty_flags);
1073void cpu_tlb_update_dirty(CPUState *env);
1074
1075void dump_exec_info(FILE *f,
1076 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1077
1078/*******************************************/
1079/* host CPU ticks (if available) */
1080
1081#if defined(__powerpc__)
1082
1083static inline uint32_t get_tbl(void)
1084{
1085 uint32_t tbl;
1086 asm volatile("mftb %0" : "=r" (tbl));
1087 return tbl;
1088}
1089
1090static inline uint32_t get_tbu(void)
1091{
1092 uint32_t tbl;
1093 asm volatile("mftbu %0" : "=r" (tbl));
1094 return tbl;
1095}
1096
1097static inline int64_t cpu_get_real_ticks(void)
1098{
1099 uint32_t l, h, h1;
1100 /* NOTE: we test if wrapping has occurred */
1101 do {
1102 h = get_tbu();
1103 l = get_tbl();
1104 h1 = get_tbu();
1105 } while (h != h1);
1106 return ((int64_t)h << 32) | l;
1107}
1108
1109#elif defined(__i386__)
1110
1111static inline int64_t cpu_get_real_ticks(void)
1112{
1113 int64_t val;
1114 asm volatile ("rdtsc" : "=A" (val));
1115 return val;
1116}
1117
1118#elif defined(__x86_64__)
1119
1120static inline int64_t cpu_get_real_ticks(void)
1121{
1122 uint32_t low,high;
1123 int64_t val;
1124 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1125 val = high;
1126 val <<= 32;
1127 val |= low;
1128 return val;
1129}
1130
1131#elif defined(__ia64)
1132
1133static inline int64_t cpu_get_real_ticks(void)
1134{
1135 int64_t val;
1136 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1137 return val;
1138}
1139
1140#elif defined(__s390__)
1141
1142static inline int64_t cpu_get_real_ticks(void)
1143{
1144 int64_t val;
1145 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1146 return val;
1147}
1148
1149#elif defined(__sparc_v9__)
1150
1151static inline int64_t cpu_get_real_ticks (void)
1152{
1153#if defined(_LP64)
1154 uint64_t rval;
1155 asm volatile("rd %%tick,%0" : "=r"(rval));
1156 return rval;
1157#else
1158 union {
1159 uint64_t i64;
1160 struct {
1161 uint32_t high;
1162 uint32_t low;
1163 } i32;
1164 } rval;
1165 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1166 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1167 return rval.i64;
1168#endif
1169}
1170#else
1171/* The host CPU doesn't have an easily accessible cycle counter.
1172 Just return a monotonically increasing vlue. This will be totally wrong,
1173 but hopefully better than nothing. */
1174static inline int64_t cpu_get_real_ticks (void)
1175{
1176 static int64_t ticks = 0;
1177 return ticks++;
1178}
1179#endif
1180
1181/* profiling */
1182#ifdef CONFIG_PROFILER
1183static inline int64_t profile_getclock(void)
1184{
1185 return cpu_get_real_ticks();
1186}
1187
1188extern int64_t kqemu_time, kqemu_time_start;
1189extern int64_t qemu_time, qemu_time_start;
1190extern int64_t tlb_flush_time;
1191extern int64_t kqemu_exec_count;
1192extern int64_t dev_time;
1193extern int64_t kqemu_ret_int_count;
1194extern int64_t kqemu_ret_excp_count;
1195extern int64_t kqemu_ret_intr_count;
1196
1197#endif
1198
1199#ifdef VBOX
1200void tb_invalidate_virt(CPUState *env, uint32_t eip);
1201#endif /* VBOX */
1202
1203#endif /* CPU_ALL_H */
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