1 | /*
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2 | * internal execution defines for qemu
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3 | *
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4 | * Copyright (c) 2003 Fabrice Bellard
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5 | *
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6 | * This library is free software; you can redistribute it and/or
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7 | * modify it under the terms of the GNU Lesser General Public
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8 | * License as published by the Free Software Foundation; either
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9 | * version 2 of the License, or (at your option) any later version.
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10 | *
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11 | * This library is distributed in the hope that it will be useful,
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | * Lesser General Public License for more details.
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15 | *
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16 | * You should have received a copy of the GNU Lesser General Public
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17 | * License along with this library; if not, write to the Free Software
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18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | */
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20 |
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21 | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | #ifndef VBOX
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23 | #define DEBUG_DISAS
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24 | #endif
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25 |
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26 | #ifdef VBOX
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27 | # include <VBox/tm.h>
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28 | # include <VBox/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
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29 | # ifndef LOG_GROUP
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30 | # define LOG_GROUP LOG_GROUP_REM
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31 | # endif
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32 | # include <VBox/log.h>
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33 | # include "REMInternal.h"
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34 | # include <VBox/vm.h>
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35 | #endif /* VBOX */
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36 |
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37 | #ifndef glue
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38 | #define xglue(x, y) x ## y
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39 | #define glue(x, y) xglue(x, y)
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40 | #define stringify(s) tostring(s)
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41 | #define tostring(s) #s
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42 | #endif
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43 |
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44 | #if __GNUC__ < 3
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45 | #define __builtin_expect(x, n) (x)
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46 | #endif
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47 |
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48 | #ifdef __i386__
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49 | #define REGPARM(n) __attribute((regparm(n)))
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50 | #else
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51 | #define REGPARM(n)
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52 | #endif
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53 |
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54 | /* is_jmp field values */
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55 | #define DISAS_NEXT 0 /* next instruction can be analyzed */
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56 | #define DISAS_JUMP 1 /* only pc was modified dynamically */
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57 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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58 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */
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59 |
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60 | struct TranslationBlock;
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61 |
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62 | /* XXX: make safe guess about sizes */
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63 | #define MAX_OP_PER_INSTR 32
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64 | #define OPC_BUF_SIZE 512
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65 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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66 |
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67 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
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68 |
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69 | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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70 | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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71 | extern long gen_labels[OPC_BUF_SIZE];
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72 | extern int nb_gen_labels;
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73 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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74 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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75 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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76 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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77 | extern target_ulong gen_opc_jump_pc[2];
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78 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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79 |
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80 | typedef void (GenOpFunc)(void);
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81 | typedef void (GenOpFunc1)(long);
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82 | typedef void (GenOpFunc2)(long, long);
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83 | typedef void (GenOpFunc3)(long, long, long);
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84 |
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85 | #if defined(TARGET_I386)
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86 |
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87 | void optimize_flags_init(void);
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88 |
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89 | #endif
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90 |
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91 | extern FILE *logfile;
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92 | extern int loglevel;
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93 |
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94 | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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95 | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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96 | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
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97 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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98 | int max_code_size, int *gen_code_size_ptr);
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99 | int cpu_restore_state(struct TranslationBlock *tb,
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100 | CPUState *env, unsigned long searched_pc,
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101 | void *puc);
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102 | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
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103 | int max_code_size, int *gen_code_size_ptr);
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104 | int cpu_restore_state_copy(struct TranslationBlock *tb,
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105 | CPUState *env, unsigned long searched_pc,
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106 | void *puc);
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107 | void cpu_resume_from_signal(CPUState *env1, void *puc);
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108 | void cpu_exec_init(CPUState *env);
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109 | int page_unprotect(target_ulong address, unsigned long pc, void *puc);
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110 | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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111 | int is_cpu_write_access);
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112 | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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113 | void tlb_flush_page(CPUState *env, target_ulong addr);
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114 | void tlb_flush(CPUState *env, int flush_global);
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115 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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116 | target_phys_addr_t paddr, int prot,
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117 | int is_user, int is_softmmu);
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118 | static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
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119 | target_phys_addr_t paddr, int prot,
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120 | int is_user, int is_softmmu)
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121 | {
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122 | if (prot & PAGE_READ)
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123 | prot |= PAGE_EXEC;
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124 | return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
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125 | }
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126 |
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127 | #define CODE_GEN_MAX_SIZE 65536
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128 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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129 |
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130 | #define CODE_GEN_PHYS_HASH_BITS 15
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131 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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132 |
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133 | /* maximum total translate dcode allocated */
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134 |
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135 | /* NOTE: the translated code area cannot be too big because on some
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136 | archs the range of "fast" function calls is limited. Here is a
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137 | summary of the ranges:
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138 |
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139 | i386 : signed 32 bits
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140 | arm : signed 26 bits
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141 | ppc : signed 24 bits
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142 | sparc : signed 32 bits
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143 | alpha : signed 23 bits
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144 | */
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145 |
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146 | #if defined(__alpha__)
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147 | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
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148 | #elif defined(__ia64)
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149 | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
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150 | #elif defined(__powerpc__)
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151 | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
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152 | #else
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153 | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
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154 | #endif
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155 |
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156 | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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157 |
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158 | /* estimated block size for TB allocation */
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159 | /* XXX: use a per code average code fragment size and modulate it
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160 | according to the host CPU */
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161 | #if defined(CONFIG_SOFTMMU)
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162 | #define CODE_GEN_AVG_BLOCK_SIZE 128
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163 | #else
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164 | #define CODE_GEN_AVG_BLOCK_SIZE 64
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165 | #endif
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166 |
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167 | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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168 |
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169 | #if defined(__powerpc__)
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170 | #define USE_DIRECT_JUMP
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171 | #endif
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172 | #if defined(__i386__) && !defined(_WIN32)
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173 | #define USE_DIRECT_JUMP
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174 | #endif
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175 | #ifdef VBOX /* bird: not safe in next step because of threading & cpu_interrupt. */
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176 | #undef USE_DIRECT_JUMP
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177 | #endif /* VBOX */
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178 |
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179 | typedef struct TranslationBlock {
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180 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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181 | target_ulong cs_base; /* CS base for this block */
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182 | unsigned int flags; /* flags defining in which context the code was generated */
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183 | uint16_t size; /* size of target code for this block (1 <=
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184 | size <= TARGET_PAGE_SIZE) */
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185 | uint16_t cflags; /* compile flags */
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186 | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
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187 | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
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188 | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
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189 | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
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190 | #ifdef VBOX
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191 | #define CF_RAW_MODE 0x0010 /* block was generated in raw mode */
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192 | #endif
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193 |
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194 | uint8_t *tc_ptr; /* pointer to the translated code */
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195 | /* next matching tb for physical address. */
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196 | struct TranslationBlock *phys_hash_next;
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197 | /* first and second physical page containing code. The lower bit
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198 | of the pointer tells the index in page_next[] */
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199 | struct TranslationBlock *page_next[2];
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200 | target_ulong page_addr[2];
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201 |
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202 | /* the following data are used to directly call another TB from
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203 | the code of this one. */
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204 | uint16_t tb_next_offset[2]; /* offset of original jump target */
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205 | #ifdef USE_DIRECT_JUMP
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206 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
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207 | #else
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208 | # if defined(VBOX) && defined(__DARWIN__) && defined(__AMD64__)
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209 | # error "First 4GB aren't reachable. jmp dword [tb_next] wont work."
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210 | # endif
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211 | uint32_t tb_next[2]; /* address of jump generated code */
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212 | #endif
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213 | /* list of TBs jumping to this one. This is a circular list using
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214 | the two least significant bits of the pointers to tell what is
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215 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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216 | jmp_first */
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217 | struct TranslationBlock *jmp_next[2];
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218 | struct TranslationBlock *jmp_first;
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219 | } TranslationBlock;
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220 |
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221 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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222 | {
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223 | target_ulong tmp;
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224 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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225 | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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226 | }
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227 |
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228 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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229 | {
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230 | target_ulong tmp;
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231 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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232 | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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233 | (tmp & TB_JMP_ADDR_MASK));
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234 | }
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235 |
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236 | static inline unsigned int tb_phys_hash_func(unsigned long pc)
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237 | {
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238 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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239 | }
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240 |
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241 | TranslationBlock *tb_alloc(target_ulong pc);
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242 | void tb_flush(CPUState *env);
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243 | void tb_link_phys(TranslationBlock *tb,
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244 | target_ulong phys_pc, target_ulong phys_page2);
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245 |
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246 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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247 |
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248 | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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249 | extern uint8_t *code_gen_ptr;
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250 |
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251 | #if defined(USE_DIRECT_JUMP)
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252 |
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253 | #if defined(__powerpc__)
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254 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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255 | {
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256 | uint32_t val, *ptr;
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257 |
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258 | /* patch the branch destination */
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259 | ptr = (uint32_t *)jmp_addr;
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260 | val = *ptr;
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261 | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
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262 | *ptr = val;
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263 | /* flush icache */
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264 | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
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265 | asm volatile ("sync" : : : "memory");
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266 | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
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267 | asm volatile ("sync" : : : "memory");
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268 | asm volatile ("isync" : : : "memory");
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269 | }
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270 | #elif defined(__i386__)
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271 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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272 | {
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273 | /* patch the branch destination */
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274 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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275 | /* no need to flush icache explicitely */
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276 | }
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277 | #endif
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278 |
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279 | static inline void tb_set_jmp_target(TranslationBlock *tb,
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280 | int n, unsigned long addr)
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281 | {
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282 | unsigned long offset;
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283 |
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284 | offset = tb->tb_jmp_offset[n];
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285 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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286 | offset = tb->tb_jmp_offset[n + 2];
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287 | if (offset != 0xffff)
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288 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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289 | }
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290 |
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291 | #else
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292 |
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293 | /* set the jump target */
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294 | static inline void tb_set_jmp_target(TranslationBlock *tb,
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295 | int n, unsigned long addr)
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296 | {
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297 | tb->tb_next[n] = addr;
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298 | }
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299 |
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300 | #endif
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301 |
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302 | static inline void tb_add_jump(TranslationBlock *tb, int n,
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303 | TranslationBlock *tb_next)
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304 | {
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305 | /* NOTE: this test is only needed for thread safety */
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306 | if (!tb->jmp_next[n]) {
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307 | /* patch the native jump address */
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308 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
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309 |
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310 | /* add in TB jmp circular list */
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311 | tb->jmp_next[n] = tb_next->jmp_first;
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312 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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313 | }
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314 | }
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315 |
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316 | TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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317 |
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318 | #ifndef offsetof
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319 | #define offsetof(type, field) ((size_t) &((type *)0)->field)
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320 | #endif
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321 |
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322 | #if defined(_WIN32)
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323 | #define ASM_DATA_SECTION ".section \".data\"\n"
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324 | #define ASM_PREVIOUS_SECTION ".section .text\n"
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325 | #elif defined(__APPLE__)
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326 | #define ASM_DATA_SECTION ".data\n"
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327 | #define ASM_PREVIOUS_SECTION ".text\n"
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328 | #else
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329 | #define ASM_DATA_SECTION ".section \".data\"\n"
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330 | #define ASM_PREVIOUS_SECTION ".previous\n"
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331 | #endif
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332 |
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333 | #define ASM_OP_LABEL_NAME(n, opname) \
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334 | ASM_NAME(__op_label) #n "." ASM_NAME(opname)
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335 |
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336 | #if defined(__powerpc__)
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337 |
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338 | /* we patch the jump instruction directly */
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339 | #define GOTO_TB(opname, tbparam, n)\
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340 | do {\
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341 | asm volatile (ASM_DATA_SECTION\
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342 | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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343 | ".long 1f\n"\
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344 | ASM_PREVIOUS_SECTION \
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345 | "b " ASM_NAME(__op_jmp) #n "\n"\
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346 | "1:\n");\
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347 | } while (0)
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348 |
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349 | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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350 |
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351 | /* we patch the jump instruction directly */
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352 | #define GOTO_TB(opname, tbparam, n)\
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353 | do {\
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354 | asm volatile (".section .data\n"\
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355 | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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356 | ".long 1f\n"\
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357 | ASM_PREVIOUS_SECTION \
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358 | "jmp " ASM_NAME(__op_jmp) #n "\n"\
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359 | "1:\n");\
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360 | } while (0)
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361 |
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362 | #else
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363 |
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364 | /* jump to next block operations (more portable code, does not need
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365 | cache flushing, but slower because of indirect jump) */
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366 | # ifdef VBOX /* bird: GCC4 (and Ming 3.4.x?) will remove the two unused static
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367 | variables. I've added a dummy __asm__ statement which reference
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368 | the two variables to prevent this. */
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369 | # if __GNUC__ >= 4
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370 | # define GOTO_TB(opname, tbparam, n)\
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371 | do {\
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372 | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
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373 | static void __attribute__((unused)) *__op_label ## n \
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374 | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
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375 | __asm__ ("" : : "m" (__op_label ## n), "m" (dummy ## n));\
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376 | goto *(void *)(uintptr_t)(((TranslationBlock *)tbparam)->tb_next[n]);\
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377 | label ## n: ;\
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378 | dummy_label ## n: ;\
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379 | } while (0)
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380 | # else
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381 | # define GOTO_TB(opname, tbparam, n)\
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382 | do {\
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383 | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
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384 | static void __attribute__((unused)) *__op_label ## n \
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385 | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
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386 | goto *(void *)(uintptr_t)(((TranslationBlock *)tbparam)->tb_next[n]);\
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387 | label ## n: ;\
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388 | dummy_label ## n: ;\
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389 | } while (0)
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390 | # endif
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391 | # else /* !VBOX */
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392 | #define GOTO_TB(opname, tbparam, n)\
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393 | do {\
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394 | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
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395 | static void __attribute__((unused)) *__op_label ## n \
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396 | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
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397 | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
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398 | label ## n: ;\
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399 | dummy_label ## n: ;\
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400 | } while (0)
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401 | # endif /* !VBOX */
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402 |
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403 | #endif
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404 |
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405 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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406 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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407 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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408 |
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409 | #ifdef __powerpc__
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410 | static inline int testandset (int *p)
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411 | {
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412 | int ret;
|
---|
413 | __asm__ __volatile__ (
|
---|
414 | "0: lwarx %0,0,%1\n"
|
---|
415 | " xor. %0,%3,%0\n"
|
---|
416 | " bne 1f\n"
|
---|
417 | " stwcx. %2,0,%1\n"
|
---|
418 | " bne- 0b\n"
|
---|
419 | "1: "
|
---|
420 | : "=&r" (ret)
|
---|
421 | : "r" (p), "r" (1), "r" (0)
|
---|
422 | : "cr0", "memory");
|
---|
423 | return ret;
|
---|
424 | }
|
---|
425 | #endif
|
---|
426 |
|
---|
427 | #ifdef __i386__
|
---|
428 | static inline int testandset (int *p)
|
---|
429 | {
|
---|
430 | long int readval = 0;
|
---|
431 |
|
---|
432 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
---|
433 | : "+m" (*p), "+a" (readval)
|
---|
434 | : "r" (1)
|
---|
435 | : "cc");
|
---|
436 | return readval;
|
---|
437 | }
|
---|
438 | #endif
|
---|
439 |
|
---|
440 | #ifdef __x86_64__
|
---|
441 | static inline int testandset (int *p)
|
---|
442 | {
|
---|
443 | long int readval = 0;
|
---|
444 |
|
---|
445 | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
---|
446 | : "+m" (*p), "+a" (readval)
|
---|
447 | : "r" (1)
|
---|
448 | : "cc");
|
---|
449 | return readval;
|
---|
450 | }
|
---|
451 | #endif
|
---|
452 |
|
---|
453 | #ifdef __s390__
|
---|
454 | static inline int testandset (int *p)
|
---|
455 | {
|
---|
456 | int ret;
|
---|
457 |
|
---|
458 | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
---|
459 | " jl 0b"
|
---|
460 | : "=&d" (ret)
|
---|
461 | : "r" (1), "a" (p), "0" (*p)
|
---|
462 | : "cc", "memory" );
|
---|
463 | return ret;
|
---|
464 | }
|
---|
465 | #endif
|
---|
466 |
|
---|
467 | #ifdef __alpha__
|
---|
468 | static inline int testandset (int *p)
|
---|
469 | {
|
---|
470 | int ret;
|
---|
471 | unsigned long one;
|
---|
472 |
|
---|
473 | __asm__ __volatile__ ("0: mov 1,%2\n"
|
---|
474 | " ldl_l %0,%1\n"
|
---|
475 | " stl_c %2,%1\n"
|
---|
476 | " beq %2,1f\n"
|
---|
477 | ".subsection 2\n"
|
---|
478 | "1: br 0b\n"
|
---|
479 | ".previous"
|
---|
480 | : "=r" (ret), "=m" (*p), "=r" (one)
|
---|
481 | : "m" (*p));
|
---|
482 | return ret;
|
---|
483 | }
|
---|
484 | #endif
|
---|
485 |
|
---|
486 | #ifdef __sparc__
|
---|
487 | static inline int testandset (int *p)
|
---|
488 | {
|
---|
489 | int ret;
|
---|
490 |
|
---|
491 | __asm__ __volatile__("ldstub [%1], %0"
|
---|
492 | : "=r" (ret)
|
---|
493 | : "r" (p)
|
---|
494 | : "memory");
|
---|
495 |
|
---|
496 | return (ret ? 1 : 0);
|
---|
497 | }
|
---|
498 | #endif
|
---|
499 |
|
---|
500 | #ifdef __arm__
|
---|
501 | static inline int testandset (int *spinlock)
|
---|
502 | {
|
---|
503 | register unsigned int ret;
|
---|
504 | __asm__ __volatile__("swp %0, %1, [%2]"
|
---|
505 | : "=r"(ret)
|
---|
506 | : "0"(1), "r"(spinlock));
|
---|
507 |
|
---|
508 | return ret;
|
---|
509 | }
|
---|
510 | #endif
|
---|
511 |
|
---|
512 | #ifdef __mc68000
|
---|
513 | static inline int testandset (int *p)
|
---|
514 | {
|
---|
515 | char ret;
|
---|
516 | __asm__ __volatile__("tas %1; sne %0"
|
---|
517 | : "=r" (ret)
|
---|
518 | : "m" (p)
|
---|
519 | : "cc","memory");
|
---|
520 | return ret;
|
---|
521 | }
|
---|
522 | #endif
|
---|
523 |
|
---|
524 | #ifdef __ia64
|
---|
525 | #include <ia64intrin.h>
|
---|
526 |
|
---|
527 | static inline int testandset (int *p)
|
---|
528 | {
|
---|
529 | return __sync_lock_test_and_set (p, 1);
|
---|
530 | }
|
---|
531 | #endif
|
---|
532 |
|
---|
533 | typedef int spinlock_t;
|
---|
534 |
|
---|
535 | #define SPIN_LOCK_UNLOCKED 0
|
---|
536 |
|
---|
537 | #if defined(CONFIG_USER_ONLY)
|
---|
538 | static inline void spin_lock(spinlock_t *lock)
|
---|
539 | {
|
---|
540 | while (testandset(lock));
|
---|
541 | }
|
---|
542 |
|
---|
543 | static inline void spin_unlock(spinlock_t *lock)
|
---|
544 | {
|
---|
545 | *lock = 0;
|
---|
546 | }
|
---|
547 |
|
---|
548 | static inline int spin_trylock(spinlock_t *lock)
|
---|
549 | {
|
---|
550 | return !testandset(lock);
|
---|
551 | }
|
---|
552 | #else
|
---|
553 | static inline void spin_lock(spinlock_t *lock)
|
---|
554 | {
|
---|
555 | }
|
---|
556 |
|
---|
557 | static inline void spin_unlock(spinlock_t *lock)
|
---|
558 | {
|
---|
559 | }
|
---|
560 |
|
---|
561 | static inline int spin_trylock(spinlock_t *lock)
|
---|
562 | {
|
---|
563 | return 1;
|
---|
564 | }
|
---|
565 | #endif
|
---|
566 |
|
---|
567 | extern spinlock_t tb_lock;
|
---|
568 |
|
---|
569 | extern int tb_invalidated_flag;
|
---|
570 |
|
---|
571 | #if !defined(CONFIG_USER_ONLY)
|
---|
572 |
|
---|
573 | void tlb_fill(target_ulong addr, int is_write, int is_user,
|
---|
574 | void *retaddr);
|
---|
575 |
|
---|
576 | #define ACCESS_TYPE 3
|
---|
577 | #define MEMSUFFIX _code
|
---|
578 | #define env cpu_single_env
|
---|
579 |
|
---|
580 | #define DATA_SIZE 1
|
---|
581 | #include "softmmu_header.h"
|
---|
582 |
|
---|
583 | #define DATA_SIZE 2
|
---|
584 | #include "softmmu_header.h"
|
---|
585 |
|
---|
586 | #define DATA_SIZE 4
|
---|
587 | #include "softmmu_header.h"
|
---|
588 |
|
---|
589 | #define DATA_SIZE 8
|
---|
590 | #include "softmmu_header.h"
|
---|
591 |
|
---|
592 | #undef ACCESS_TYPE
|
---|
593 | #undef MEMSUFFIX
|
---|
594 | #undef env
|
---|
595 |
|
---|
596 | #endif
|
---|
597 |
|
---|
598 | #if defined(CONFIG_USER_ONLY)
|
---|
599 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
|
---|
600 | {
|
---|
601 | return addr;
|
---|
602 | }
|
---|
603 | #else
|
---|
604 | # ifdef VBOX
|
---|
605 | target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry);
|
---|
606 | # if defined(PGM_DYNAMIC_RAM_ALLOC) && !defined(REM_PHYS_ADDR_IN_TLB)
|
---|
607 | target_ulong remR3HCVirt2GCPhys(void *env, void *addr);
|
---|
608 | # endif
|
---|
609 | # endif
|
---|
610 | /* NOTE: this function can trigger an exception */
|
---|
611 | /* NOTE2: the returned address is not exactly the physical address: it
|
---|
612 | is the offset relative to phys_ram_base */
|
---|
613 | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
|
---|
614 | {
|
---|
615 | int is_user, index, pd;
|
---|
616 |
|
---|
617 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
---|
618 | #if defined(TARGET_I386)
|
---|
619 | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
---|
620 | #elif defined (TARGET_PPC)
|
---|
621 | is_user = msr_pr;
|
---|
622 | #elif defined (TARGET_MIPS)
|
---|
623 | is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
|
---|
624 | #elif defined (TARGET_SPARC)
|
---|
625 | is_user = (env->psrs == 0);
|
---|
626 | #elif defined (TARGET_ARM)
|
---|
627 | is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
|
---|
628 | #elif defined (TARGET_SH4)
|
---|
629 | is_user = ((env->sr & SR_MD) == 0);
|
---|
630 | #else
|
---|
631 | #error unimplemented CPU
|
---|
632 | #endif
|
---|
633 | if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
|
---|
634 | (addr & TARGET_PAGE_MASK), 0)) {
|
---|
635 | ldub_code(addr);
|
---|
636 | }
|
---|
637 | pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
|
---|
638 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
---|
639 | # ifdef VBOX
|
---|
640 | /* deal with non-MMIO access handlers. */
|
---|
641 | return remR3PhysGetPhysicalAddressCode(env, addr, &env->tlb_table[is_user][index]);
|
---|
642 | # else
|
---|
643 | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
|
---|
644 | # endif
|
---|
645 | }
|
---|
646 | # if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
|
---|
647 | return addr + env->tlb_table[is_user][index].addend;
|
---|
648 | # elif defined(VBOX) && defined(PGM_DYNAMIC_RAM_ALLOC)
|
---|
649 | return remR3HCVirt2GCPhys(env, (void *)(addr + env->tlb_table[is_user][index].addend));
|
---|
650 | # else
|
---|
651 | return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
|
---|
652 | # endif
|
---|
653 | }
|
---|
654 | #endif
|
---|
655 |
|
---|
656 |
|
---|
657 | #ifdef USE_KQEMU
|
---|
658 | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
|
---|
659 |
|
---|
660 | int kqemu_init(CPUState *env);
|
---|
661 | int kqemu_cpu_exec(CPUState *env);
|
---|
662 | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
---|
663 | void kqemu_flush(CPUState *env, int global);
|
---|
664 | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
---|
665 | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
---|
666 | void kqemu_cpu_interrupt(CPUState *env);
|
---|
667 | void kqemu_record_dump(void);
|
---|
668 |
|
---|
669 | static inline int kqemu_is_ok(CPUState *env)
|
---|
670 | {
|
---|
671 | return(env->kqemu_enabled &&
|
---|
672 | (env->cr[0] & CR0_PE_MASK) &&
|
---|
673 | !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
|
---|
674 | (env->eflags & IF_MASK) &&
|
---|
675 | !(env->eflags & VM_MASK) &&
|
---|
676 | (env->kqemu_enabled == 2 ||
|
---|
677 | ((env->hflags & HF_CPL_MASK) == 3 &&
|
---|
678 | (env->eflags & IOPL_MASK) != IOPL_MASK)));
|
---|
679 | }
|
---|
680 |
|
---|
681 | #endif
|
---|