VirtualBox

source: vbox/trunk/src/recompiler/dyngen.h@ 12245

Last change on this file since 12245 was 11982, checked in by vboxsync, 16 years ago

All: license header changes for 2.0 (OSE headers, add Sun GPL/LGPL disclaimer)
  • Property svn:eol-style set to native
File size: 13.5 KB
Line 
1/*
2 * dyngen helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29
30int __op_param1, __op_param2, __op_param3;
31#if defined(__sparc__) || defined(__arm__)
32 void __op_gen_label1(){}
33 void __op_gen_label2(){}
34 void __op_gen_label3(){}
35#else
36 int __op_gen_label1, __op_gen_label2, __op_gen_label3;
37#endif
38int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
39
40#ifdef __i386__
41static inline void flush_icache_range(unsigned long start, unsigned long stop)
42{
43}
44#endif
45
46#ifdef __x86_64__
47static inline void flush_icache_range(unsigned long start, unsigned long stop)
48{
49}
50#endif
51
52#ifdef __s390__
53static inline void flush_icache_range(unsigned long start, unsigned long stop)
54{
55}
56#endif
57
58#ifdef __ia64__
59static inline void flush_icache_range(unsigned long start, unsigned long stop)
60{
61 while (start < stop) {
62 asm volatile ("fc %0" :: "r"(start));
63 start += 32;
64 }
65 asm volatile (";;sync.i;;srlz.i;;");
66}
67#endif
68
69#ifdef __powerpc__
70
71#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
72
73static void inline flush_icache_range(unsigned long start, unsigned long stop)
74{
75 unsigned long p;
76
77 start &= ~(MIN_CACHE_LINE_SIZE - 1);
78 stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
79
80 for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
81 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
82 }
83 asm volatile ("sync" : : : "memory");
84 for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
85 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
86 }
87 asm volatile ("sync" : : : "memory");
88 asm volatile ("isync" : : : "memory");
89}
90#endif
91
92#ifdef __alpha__
93static inline void flush_icache_range(unsigned long start, unsigned long stop)
94{
95 asm ("imb");
96}
97#endif
98
99#ifdef __sparc__
100
101static void inline flush_icache_range(unsigned long start, unsigned long stop)
102{
103 unsigned long p;
104
105 p = start & ~(8UL - 1UL);
106 stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
107
108 for (; p < stop; p += 8)
109 __asm__ __volatile__("flush\t%0" : : "r" (p));
110}
111
112#endif
113
114#ifdef __arm__
115static inline void flush_icache_range(unsigned long start, unsigned long stop)
116{
117 register unsigned long _beg __asm ("a1") = start;
118 register unsigned long _end __asm ("a2") = stop;
119 register unsigned long _flg __asm ("a3") = 0;
120 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
121}
122#endif
123
124#ifdef __mc68000
125#include <asm/cachectl.h>
126static inline void flush_icache_range(unsigned long start, unsigned long stop)
127{
128 cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
129}
130#endif
131
132#ifdef __alpha__
133
134register int gp asm("$29");
135
136static inline void immediate_ldah(void *p, int val) {
137 uint32_t *dest = p;
138 long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff;
139
140 *dest &= ~0xffff;
141 *dest |= high;
142 *dest |= 31 << 16;
143}
144static inline void immediate_lda(void *dest, int val) {
145 *(uint16_t *) dest = val;
146}
147void fix_bsr(void *p, int offset) {
148 uint32_t *dest = p;
149 *dest &= ~((1 << 21) - 1);
150 *dest |= (offset >> 2) & ((1 << 21) - 1);
151}
152
153#endif /* __alpha__ */
154
155#ifdef __arm__
156
157#define ARM_LDR_TABLE_SIZE 1024
158
159typedef struct LDREntry {
160 uint8_t *ptr;
161 uint32_t *data_ptr;
162 unsigned type:2;
163} LDREntry;
164
165static LDREntry arm_ldr_table[1024];
166static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];
167
168extern char exec_loop;
169
170static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val)
171{
172 *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff);
173}
174
175static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
176 LDREntry *ldr_start, LDREntry *ldr_end,
177 uint32_t *data_start, uint32_t *data_end,
178 int gen_jmp)
179{
180 LDREntry *le;
181 uint32_t *ptr;
182 int offset, data_size, target;
183 uint8_t *data_ptr;
184 uint32_t insn;
185 uint32_t mask;
186
187 data_size = (data_end - data_start) << 2;
188
189 if (gen_jmp) {
190 /* generate branch to skip the data */
191 if (data_size == 0)
192 return gen_code_ptr;
193 target = (long)gen_code_ptr + data_size + 4;
194 arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
195 gen_code_ptr += 4;
196 }
197
198 /* copy the data */
199 data_ptr = gen_code_ptr;
200 memcpy(gen_code_ptr, data_start, data_size);
201 gen_code_ptr += data_size;
202
203 /* patch the ldr to point to the data */
204 for(le = ldr_start; le < ldr_end; le++) {
205 ptr = (uint32_t *)le->ptr;
206 offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +
207 (unsigned long)data_ptr -
208 (unsigned long)ptr - 8;
209 if (offset < 0) {
210 fprintf(stderr, "Negative constant pool offset\n");
211 abort();
212 }
213 switch (le->type) {
214 case 0: /* ldr */
215 mask = ~0x00800fff;
216 if (offset >= 4096) {
217 fprintf(stderr, "Bad ldr offset\n");
218 abort();
219 }
220 break;
221 case 1: /* ldc */
222 mask = ~0x008000ff;
223 if (offset >= 1024 ) {
224 fprintf(stderr, "Bad ldc offset\n");
225 abort();
226 }
227 break;
228 case 2: /* add */
229 mask = ~0xfff;
230 if (offset >= 1024 ) {
231 fprintf(stderr, "Bad add offset\n");
232 abort();
233 }
234 break;
235 default:
236 fprintf(stderr, "Bad pc relative fixup\n");
237 abort();
238 }
239 insn = *ptr & mask;
240 switch (le->type) {
241 case 0: /* ldr */
242 insn |= offset | 0x00800000;
243 break;
244 case 1: /* ldc */
245 insn |= (offset >> 2) | 0x00800000;
246 break;
247 case 2: /* add */
248 insn |= (offset >> 2) | 0xf00;
249 break;
250 }
251 *ptr = insn;
252 }
253 return gen_code_ptr;
254}
255
256#endif /* __arm__ */
257
258#ifdef __ia64
259
260
261/* Patch instruction with "val" where "mask" has 1 bits. */
262static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
263{
264 uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
265# define insn_mask ((1UL << 41) - 1)
266 unsigned long shift;
267
268 b0 = b[0]; b1 = b[1];
269 shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */
270 if (shift >= 64) {
271 m1 = mask << (shift - 64);
272 v1 = val << (shift - 64);
273 } else {
274 m0 = mask << shift; m1 = mask >> (64 - shift);
275 v0 = val << shift; v1 = val >> (64 - shift);
276 b[0] = (b0 & ~m0) | (v0 & m0);
277 }
278 b[1] = (b1 & ~m1) | (v1 & m1);
279}
280
281static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val)
282{
283 ia64_patch(insn_addr,
284 0x011ffffe000UL,
285 ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
286 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
287 ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
288}
289
290static inline void ia64_imm64 (void *insn, uint64_t val)
291{
292 /* Ignore the slot number of the relocation; GCC and Intel
293 toolchains differed for some time on whether IMM64 relocs are
294 against slot 1 (Intel) or slot 2 (GCC). */
295 uint64_t insn_addr = (uint64_t) insn & ~3UL;
296
297 ia64_patch(insn_addr + 2,
298 0x01fffefe000UL,
299 ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
300 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
301 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
302 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
303 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)
304 );
305 ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
306}
307
308static inline void ia64_imm60b (void *insn, uint64_t val)
309{
310 /* Ignore the slot number of the relocation; GCC and Intel
311 toolchains differed for some time on whether IMM64 relocs are
312 against slot 1 (Intel) or slot 2 (GCC). */
313 uint64_t insn_addr = (uint64_t) insn & ~3UL;
314
315 if (val + ((uint64_t) 1 << 59) >= (1UL << 60))
316 fprintf(stderr, "%s: value %ld out of IMM60 range\n",
317 __FUNCTION__, (int64_t) val);
318 ia64_patch_imm60(insn_addr + 2, val);
319}
320
321static inline void ia64_imm22 (void *insn, uint64_t val)
322{
323 if (val + (1 << 21) >= (1 << 22))
324 fprintf(stderr, "%s: value %li out of IMM22 range\n",
325 __FUNCTION__, (int64_t)val);
326 ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
327 ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
328 | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */
329 | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */
330 | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */));
331}
332
333/* Like ia64_imm22(), but also clear bits 20-21. For addl, this has
334 the effect of turning "addl rX=imm22,rY" into "addl
335 rX=imm22,r0". */
336static inline void ia64_imm22_r0 (void *insn, uint64_t val)
337{
338 if (val + (1 << 21) >= (1 << 22))
339 fprintf(stderr, "%s: value %li out of IMM22 range\n",
340 __FUNCTION__, (int64_t)val);
341 ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20),
342 ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
343 | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */
344 | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */
345 | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */));
346}
347
348static inline void ia64_imm21b (void *insn, uint64_t val)
349{
350 if (val + (1 << 20) >= (1 << 21))
351 fprintf(stderr, "%s: value %li out of IMM21b range\n",
352 __FUNCTION__, (int64_t)val);
353 ia64_patch((uint64_t) insn, 0x11ffffe000UL,
354 ( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */
355 | ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */));
356}
357
358static inline void ia64_nop_b (void *insn)
359{
360 ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37);
361}
362
363static inline void ia64_ldxmov(void *insn, uint64_t val)
364{
365 if (val + (1 << 21) < (1 << 22))
366 ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37);
367}
368
369static inline int ia64_patch_ltoff(void *insn, uint64_t val,
370 int relaxable)
371{
372 if (relaxable && (val + (1 << 21) < (1 << 22))) {
373 ia64_imm22_r0(insn, val);
374 return 0;
375 }
376 return 1;
377}
378
379struct ia64_fixup {
380 struct ia64_fixup *next;
381 void *addr; /* address that needs to be patched */
382 long value;
383};
384
385#define IA64_PLT(insn, plt_index) \
386do { \
387 struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \
388 fixup->next = plt_fixes; \
389 plt_fixes = fixup; \
390 fixup->addr = (insn); \
391 fixup->value = (plt_index); \
392 plt_offset[(plt_index)] = 1; \
393} while (0)
394
395#define IA64_LTOFF(insn, val, relaxable) \
396do { \
397 if (ia64_patch_ltoff(insn, val, relaxable)) { \
398 struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \
399 fixup->next = ltoff_fixes; \
400 ltoff_fixes = fixup; \
401 fixup->addr = (insn); \
402 fixup->value = (val); \
403 } \
404} while (0)
405
406static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
407 struct ia64_fixup *ltoff_fixes,
408 uint64_t gp,
409 struct ia64_fixup *plt_fixes,
410 int num_plts,
411 unsigned long *plt_target,
412 unsigned int *plt_offset)
413{
414 static const uint8_t plt_bundle[] = {
415 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */
416 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60,
417
418 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */
419 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
420 };
421 uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start, *vp;
422 struct ia64_fixup *fixup;
423 unsigned int offset = 0;
424 struct fdesc {
425 long ip;
426 long gp;
427 } *fdesc;
428 int i;
429
430 if (plt_fixes) {
431 plt_start = gen_code_ptr;
432
433 for (i = 0; i < num_plts; ++i) {
434 if (plt_offset[i]) {
435 plt_offset[i] = offset;
436 offset += sizeof(plt_bundle);
437
438 fdesc = (struct fdesc *) plt_target[i];
439 memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
440 ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
441 ia64_imm60b(gen_code_ptr + 0x12,
442 (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4);
443 gen_code_ptr += sizeof(plt_bundle);
444 }
445 }
446
447 for (fixup = plt_fixes; fixup; fixup = fixup->next)
448 ia64_imm21b(fixup->addr,
449 ((long) plt_start + plt_offset[fixup->value]
450 - ((long) fixup->addr & ~0xf)) >> 4);
451 }
452
453 got_start = gen_code_ptr;
454
455 /* First, create the GOT: */
456 for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
457 /* first check if we already have this value in the GOT: */
458 for (vp = got_start; vp < gen_code_ptr; ++vp)
459 if (*(uint64_t *) vp == fixup->value)
460 break;
461 if (vp == gen_code_ptr) {
462 /* Nope, we need to put the value in the GOT: */
463 *(uint64_t *) vp = fixup->value;
464 gen_code_ptr += 8;
465 }
466 ia64_imm22(fixup->addr, (long) vp - gp);
467 }
468 /* Keep code ptr aligned. */
469 if ((long) gen_code_ptr & 15)
470 gen_code_ptr += 8;
471 *gen_code_pp = gen_code_ptr;
472}
473
474#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette