VirtualBox

source: vbox/trunk/src/recompiler/cpu-defs.h@ 13832

Last change on this file since 13832 was 13375, checked in by vboxsync, 16 years ago

some (disabled) VMI bits

  • Property svn:eol-style set to native
File size: 6.1 KB
Line 
1/*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29#ifndef CPU_DEFS_H
30#define CPU_DEFS_H
31
32#include "config.h"
33#include <setjmp.h>
34#include <inttypes.h>
35#include "osdep.h"
36
37#ifndef TARGET_LONG_BITS
38#error TARGET_LONG_BITS must be defined before including this header
39#endif
40
41#ifndef TARGET_PHYS_ADDR_BITS
42#if TARGET_LONG_BITS >= HOST_LONG_BITS
43#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
44#else
45#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
46#endif
47#endif
48
49#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
50
51/* target_ulong is the type of a virtual address */
52#if TARGET_LONG_SIZE == 4
53typedef int32_t target_long;
54typedef uint32_t target_ulong;
55#define TARGET_FMT_lx "%08x"
56#elif TARGET_LONG_SIZE == 8
57typedef int64_t target_long;
58typedef uint64_t target_ulong;
59#define TARGET_FMT_lx "%016" PRIx64
60#else
61#error TARGET_LONG_SIZE undefined
62#endif
63
64/* target_phys_addr_t is the type of a physical address (its size can
65 be different from 'target_ulong'). We have sizeof(target_phys_addr)
66 = max(sizeof(unsigned long),
67 sizeof(size_of_target_physical_address)) because we must pass a
68 host pointer to memory operations in some cases */
69
70#if TARGET_PHYS_ADDR_BITS == 32
71typedef uint32_t target_phys_addr_t;
72#elif TARGET_PHYS_ADDR_BITS == 64
73typedef uint64_t target_phys_addr_t;
74#else
75#error TARGET_PHYS_ADDR_BITS undefined
76#endif
77
78/* address in the RAM (different from a physical address) */
79typedef unsigned long ram_addr_t;
80
81#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
82
83#define EXCP_INTERRUPT 0x10000 /* async interruption */
84#define EXCP_HLT 0x10001 /* hlt instruction reached */
85#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
86#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
87#if defined(VBOX)
88#define EXCP_EXECUTE_RAW 0x11024 /* execute raw mode. */
89#define EXCP_EXECUTE_HWACC 0x11025 /* execute hardware accelerated raw mode. */
90#define EXCP_SINGLE_INSTR 0x11026 /* executed single instruction. */
91#define EXCP_RC 0x11027 /* a EM rc was raised (VMR3Reset/Suspend/PowerOff). */
92#ifdef VBOX
93#define EXCP_PARAV_CALL 0x11028 /* VMI BIOS call */
94#endif
95#endif /* VBOX */
96#define MAX_BREAKPOINTS 32
97
98#define TB_JMP_CACHE_BITS 12
99#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
100
101/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
102 addresses on the same page. The top bits are the same. This allows
103 TLB invalidation to quickly clear a subset of the hash table. */
104#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
105#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
106#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
107#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
108
109#define CPU_TLB_BITS 8
110#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
111
112typedef struct CPUTLBEntry {
113 /* bit 31 to TARGET_PAGE_BITS : virtual address
114 bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
115 zone number
116 bit 3 : indicates that the entry is invalid
117 bit 2..0 : zero
118 */
119 target_ulong addr_read;
120 target_ulong addr_write;
121 target_ulong addr_code;
122 /* addend to virtual address to get physical address */
123 target_phys_addr_t addend;
124} CPUTLBEntry;
125
126#define CPU_COMMON \
127 struct TranslationBlock *current_tb; /* currently executing TB */ \
128 /* soft mmu support */ \
129 /* in order to avoid passing too many arguments to the memory \
130 write helpers, we store some rarely used information in the CPU \
131 context) */ \
132 unsigned long mem_write_pc; /* host pc at which the memory was \
133 written */ \
134 target_ulong mem_write_vaddr; /* target virtual addr at which the \
135 memory was written */ \
136 /* 0 = kernel, 1 = user */ \
137 CPUTLBEntry tlb_table[2][CPU_TLB_SIZE]; \
138 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
139 \
140 /* from this point: preserved by CPU reset */ \
141 /* ice debug support */ \
142 target_ulong breakpoints[MAX_BREAKPOINTS]; \
143 int nb_breakpoints; \
144 int singlestep_enabled; \
145 \
146 void *next_cpu; /* next CPU sharing TB cache */ \
147 int cpu_index; /* CPU index (informative) */ \
148 /* user data */ \
149 void *opaque;
150
151#endif
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