1 | #ifndef CPU_COMMON_H
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2 | #define CPU_COMMON_H 1
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3 |
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4 | /* CPU interfaces that are target indpendent. */
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5 |
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6 | #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
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7 | #define WORDS_ALIGNED
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8 | #endif
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9 |
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10 | #ifdef TARGET_PHYS_ADDR_BITS
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11 | #include "targphys.h"
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12 | #endif
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13 |
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14 | #ifndef NEED_CPU_H
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15 | #include "poison.h"
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16 | #endif
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17 |
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18 | #include "bswap.h"
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19 | #include "qemu-queue.h"
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20 |
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21 | #if !defined(CONFIG_USER_ONLY)
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22 |
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23 | /* address in the RAM (different from a physical address) */
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24 | typedef uintptr_t ram_addr_t;
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25 |
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26 | /* memory API */
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27 |
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28 | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
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29 | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
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30 |
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31 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
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32 | ram_addr_t size,
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33 | ram_addr_t phys_offset,
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34 | ram_addr_t region_offset);
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35 | static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
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36 | ram_addr_t size,
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37 | ram_addr_t phys_offset)
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38 | {
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39 | cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
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40 | }
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41 |
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42 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
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43 | #ifndef VBOX
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44 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
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45 | ram_addr_t size, void *host);
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46 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
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47 | void qemu_ram_free(ram_addr_t addr);
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48 | /* This should only be used for ram local to a device. */
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49 | void *qemu_get_ram_ptr(ram_addr_t addr);
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50 | /* This should not be used by devices. */
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51 | ram_addr_t qemu_ram_addr_from_host(void *ptr);
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52 | #endif /* !VBOX */
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53 |
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54 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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55 | CPUWriteMemoryFunc * const *mem_write,
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56 | void *opaque);
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57 | void cpu_unregister_io_memory(int table_address);
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58 |
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59 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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60 | int len, int is_write);
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61 | static inline void cpu_physical_memory_read(target_phys_addr_t addr,
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62 | uint8_t *buf, int len)
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63 | {
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64 | cpu_physical_memory_rw(addr, buf, len, 0);
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65 | }
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66 | static inline void cpu_physical_memory_write(target_phys_addr_t addr,
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67 | const uint8_t *buf, int len)
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68 | {
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69 | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
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70 | }
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71 | void *cpu_physical_memory_map(target_phys_addr_t addr,
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72 | target_phys_addr_t *plen,
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73 | int is_write);
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74 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
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75 | int is_write, target_phys_addr_t access_len);
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76 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
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77 | void cpu_unregister_map_client(void *cookie);
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78 |
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79 | struct CPUPhysMemoryClient;
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80 | typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
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81 | struct CPUPhysMemoryClient {
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82 | void (*set_memory)(struct CPUPhysMemoryClient *client,
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83 | target_phys_addr_t start_addr,
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84 | ram_addr_t size,
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85 | ram_addr_t phys_offset);
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86 | int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
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87 | target_phys_addr_t start_addr,
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88 | target_phys_addr_t end_addr);
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89 | int (*migration_log)(struct CPUPhysMemoryClient *client,
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90 | int enable);
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91 | QLIST_ENTRY(CPUPhysMemoryClient) list;
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92 | };
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93 |
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94 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
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95 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
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96 |
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97 | /* Coalesced MMIO regions are areas where write operations can be reordered.
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98 | * This usually implies that write operations are side-effect free. This allows
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99 | * batching which can make a major impact on performance when using
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100 | * virtualization.
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101 | */
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102 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
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103 |
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104 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
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105 |
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106 | void qemu_flush_coalesced_mmio_buffer(void);
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107 |
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108 | uint32_t ldub_phys(target_phys_addr_t addr);
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109 | uint32_t lduw_phys(target_phys_addr_t addr);
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110 | uint32_t ldl_phys(target_phys_addr_t addr);
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111 | uint64_t ldq_phys(target_phys_addr_t addr);
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112 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
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113 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
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114 | void stb_phys(target_phys_addr_t addr, uint32_t val);
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115 | void stw_phys(target_phys_addr_t addr, uint32_t val);
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116 | void stl_phys(target_phys_addr_t addr, uint32_t val);
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117 | void stq_phys(target_phys_addr_t addr, uint64_t val);
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118 |
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119 | void cpu_physical_memory_write_rom(target_phys_addr_t addr,
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120 | const uint8_t *buf, int len);
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121 |
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122 | #define IO_MEM_SHIFT 3
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123 |
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124 | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
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125 | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
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126 | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
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127 | #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
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128 |
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129 | /* Acts like a ROM when read and like a device when written. */
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130 | #define IO_MEM_ROMD (1)
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131 | #define IO_MEM_SUBPAGE (2)
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132 |
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133 | #endif
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134 |
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135 | #endif /* !CPU_COMMON_H */
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