1 | /*
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2 | * defines common to all virtual CPUs
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3 | *
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4 | * Copyright (c) 2003 Fabrice Bellard
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5 | *
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6 | * This library is free software; you can redistribute it and/or
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7 | * modify it under the terms of the GNU Lesser General Public
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8 | * License as published by the Free Software Foundation; either
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9 | * version 2 of the License, or (at your option) any later version.
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10 | *
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11 | * This library is distributed in the hope that it will be useful,
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | * Lesser General Public License for more details.
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15 | *
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16 | * You should have received a copy of the GNU Lesser General Public
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17 | * License along with this library; if not, write to the Free Software
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18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | */
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20 | #ifndef CPU_ALL_H
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21 | #define CPU_ALL_H
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22 |
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23 | #if defined(__arm__) || defined(__sparc__)
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24 | #define WORDS_ALIGNED
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25 | #endif
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26 |
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27 | /* some important defines:
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28 | *
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29 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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30 | * memory accesses.
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31 | *
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32 | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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33 | * otherwise little endian.
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34 | *
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35 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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36 | *
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37 | * TARGET_WORDS_BIGENDIAN : same for target cpu
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38 | */
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39 |
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40 | #include "bswap.h"
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41 |
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42 | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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43 | #define BSWAP_NEEDED
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44 | #endif
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45 |
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46 | #ifdef BSWAP_NEEDED
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47 |
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48 | static inline uint16_t tswap16(uint16_t s)
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49 | {
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50 | return bswap16(s);
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51 | }
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52 |
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53 | static inline uint32_t tswap32(uint32_t s)
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54 | {
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55 | return bswap32(s);
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56 | }
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57 |
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58 | static inline uint64_t tswap64(uint64_t s)
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59 | {
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60 | return bswap64(s);
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61 | }
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62 |
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63 | static inline void tswap16s(uint16_t *s)
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64 | {
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65 | *s = bswap16(*s);
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66 | }
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67 |
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68 | static inline void tswap32s(uint32_t *s)
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69 | {
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70 | *s = bswap32(*s);
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71 | }
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72 |
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73 | static inline void tswap64s(uint64_t *s)
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74 | {
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75 | *s = bswap64(*s);
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76 | }
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77 |
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78 | #else
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79 |
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80 | static inline uint16_t tswap16(uint16_t s)
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81 | {
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82 | return s;
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83 | }
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84 |
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85 | static inline uint32_t tswap32(uint32_t s)
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86 | {
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87 | return s;
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88 | }
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89 |
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90 | static inline uint64_t tswap64(uint64_t s)
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91 | {
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92 | return s;
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93 | }
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94 |
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95 | static inline void tswap16s(uint16_t *s)
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96 | {
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97 | }
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98 |
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99 | static inline void tswap32s(uint32_t *s)
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100 | {
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101 | }
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102 |
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103 | static inline void tswap64s(uint64_t *s)
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104 | {
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105 | }
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106 |
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107 | #endif
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108 |
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109 | #if TARGET_LONG_SIZE == 4
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110 | #define tswapl(s) tswap32(s)
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111 | #define tswapls(s) tswap32s((uint32_t *)(s))
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112 | #else
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113 | #define tswapl(s) tswap64(s)
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114 | #define tswapls(s) tswap64s((uint64_t *)(s))
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115 | #endif
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116 |
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117 | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
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118 | endian ! */
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119 | typedef union {
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120 | double d;
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121 | #if defined(WORDS_BIGENDIAN) || (defined(__arm__) && !defined(__VFP_FP__))
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122 | struct {
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123 | uint32_t upper;
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124 | uint32_t lower;
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125 | } l;
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126 | #else
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127 | struct {
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128 | uint32_t lower;
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129 | uint32_t upper;
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130 | } l;
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131 | #endif
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132 | uint64_t ll;
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133 | } CPU_DoubleU;
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134 |
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135 | /* CPU memory access without any memory or io remapping */
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136 |
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137 | /*
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138 | * the generic syntax for the memory accesses is:
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139 | *
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140 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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141 | *
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142 | * store: st{type}{size}{endian}_{access_type}(ptr, val)
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143 | *
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144 | * type is:
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145 | * (empty): integer access
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146 | * f : float access
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147 | *
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148 | * sign is:
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149 | * (empty): for floats or 32 bit size
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150 | * u : unsigned
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151 | * s : signed
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152 | *
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153 | * size is:
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154 | * b: 8 bits
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155 | * w: 16 bits
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156 | * l: 32 bits
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157 | * q: 64 bits
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158 | *
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159 | * endian is:
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160 | * (empty): target cpu endianness or 8 bit access
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161 | * r : reversed target cpu endianness (not implemented yet)
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162 | * be : big endian (not implemented yet)
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163 | * le : little endian (not implemented yet)
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164 | *
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165 | * access_type is:
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166 | * raw : host memory access
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167 | * user : user mode access using soft MMU
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168 | * kernel : kernel mode access using soft MMU
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169 | */
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170 | #ifdef VBOX
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171 |
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172 | #if !defined(REMR3PHYSREADWRITE_DEFINED)
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173 | #define REMR3PHYSREADWRITE_DEFINED
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174 | /* Header sharing between vbox & qemu is rather ugly. */
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175 | void remR3PhysReadBytes(uint8_t *pbSrcPhys, void *pvDst, unsigned cb);
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176 | uint8_t remR3PhysReadUByte(uint8_t *pbSrcPhys);
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177 | int8_t remR3PhysReadSByte(uint8_t *pbSrcPhys);
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178 | uint16_t remR3PhysReadUWord(uint8_t *pbSrcPhys);
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179 | int16_t remR3PhysReadSWord(uint8_t *pbSrcPhys);
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180 | uint32_t remR3PhysReadULong(uint8_t *pbSrcPhys);
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181 | int32_t remR3PhysReadSLong(uint8_t *pbSrcPhys);
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182 | void remR3PhysWriteBytes(uint8_t *pbDstPhys, const void *pvSrc, unsigned cb);
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183 | void remR3PhysWriteByte(uint8_t *pbDstPhys, uint8_t val);
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184 | void remR3PhysWriteWord(uint8_t *pbDstPhys, uint16_t val);
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185 | void remR3PhysWriteDword(uint8_t *pbDstPhys, uint32_t val);
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186 | void *remR3GCPhys2HCVirt(void *env, target_ulong addr);
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187 | target_ulong remR3HCVirt2GCPhys(void *env, void *addr);
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188 | void remR3GrowDynRange(unsigned long physaddr);
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189 | #endif
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190 |
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191 | static inline int ldub_p(void *ptr)
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192 | {
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193 | return remR3PhysReadUByte(ptr);
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194 | }
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195 |
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196 | static inline int ldsb_p(void *ptr)
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197 | {
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198 | return remR3PhysReadSByte(ptr);
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199 | }
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200 |
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201 | static inline void stb_p(void *ptr, int v)
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202 | {
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203 | remR3PhysWriteByte(ptr, v);
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204 | }
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205 |
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206 | #else
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207 | static inline int ldub_p(void *ptr)
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208 | {
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209 | return *(uint8_t *)ptr;
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210 | }
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211 |
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212 | static inline int ldsb_p(void *ptr)
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213 | {
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214 | return *(int8_t *)ptr;
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215 | }
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216 |
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217 | static inline void stb_p(void *ptr, int v)
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218 | {
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219 | *(uint8_t *)ptr = v;
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220 | }
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221 | #endif
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222 |
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223 | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
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224 | kernel handles unaligned load/stores may give better results, but
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225 | it is a system wide setting : bad */
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226 | #if !defined(TARGET_WORDS_BIGENDIAN) && (defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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227 | /* conservative code for little endian unaligned accesses */
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228 | static inline int lduw_p(void *ptr)
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229 | {
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230 | #ifdef __powerpc__
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231 | int val;
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232 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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233 | return val;
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234 | #else
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235 | uint8_t *p = ptr;
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236 | return p[0] | (p[1] << 8);
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237 | #endif
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238 | }
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239 |
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240 | static inline int ldsw_p(void *ptr)
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241 | {
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242 | #ifdef __powerpc__
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243 | int val;
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244 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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245 | return (int16_t)val;
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246 | #else
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247 | uint8_t *p = ptr;
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248 | return (int16_t)(p[0] | (p[1] << 8));
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249 | #endif
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250 | }
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251 |
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252 | static inline int ldl_p(void *ptr)
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253 | {
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254 | #ifdef __powerpc__
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255 | int val;
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256 | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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257 | return val;
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258 | #else
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259 | uint8_t *p = ptr;
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260 | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
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261 | #endif
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262 | }
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263 |
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264 | static inline uint64_t ldq_p(void *ptr)
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265 | {
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266 | uint8_t *p = ptr;
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267 | uint32_t v1, v2;
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268 | v1 = ldl_p(p);
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269 | v2 = ldl_p(p + 4);
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270 | return v1 | ((uint64_t)v2 << 32);
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271 | }
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272 |
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273 | static inline void stw_p(void *ptr, int v)
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274 | {
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275 | #ifdef __powerpc__
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276 | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
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277 | #else
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278 | uint8_t *p = ptr;
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279 | p[0] = v;
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280 | p[1] = v >> 8;
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281 | #endif
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282 | }
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283 |
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284 | static inline void stl_p(void *ptr, int v)
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285 | {
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286 | #ifdef __powerpc__
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287 | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
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288 | #else
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289 | uint8_t *p = ptr;
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290 | p[0] = v;
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291 | p[1] = v >> 8;
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292 | p[2] = v >> 16;
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293 | p[3] = v >> 24;
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294 | #endif
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295 | }
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296 |
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297 | static inline void stq_p(void *ptr, uint64_t v)
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298 | {
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299 | uint8_t *p = ptr;
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300 | stl_p(p, (uint32_t)v);
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301 | stl_p(p + 4, v >> 32);
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302 | }
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303 |
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304 | /* float access */
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305 |
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306 | static inline float ldfl_p(void *ptr)
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307 | {
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308 | union {
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309 | float f;
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310 | uint32_t i;
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311 | } u;
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312 | u.i = ldl_p(ptr);
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313 | return u.f;
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314 | }
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315 |
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316 | static inline void stfl_p(void *ptr, float v)
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317 | {
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318 | union {
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319 | float f;
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320 | uint32_t i;
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321 | } u;
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322 | u.f = v;
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323 | stl_p(ptr, u.i);
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324 | }
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325 |
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326 | static inline double ldfq_p(void *ptr)
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327 | {
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328 | CPU_DoubleU u;
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329 | u.l.lower = ldl_p(ptr);
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330 | u.l.upper = ldl_p(ptr + 4);
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331 | return u.d;
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332 | }
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333 |
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334 | static inline void stfq_p(void *ptr, double v)
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335 | {
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336 | CPU_DoubleU u;
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337 | u.d = v;
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338 | stl_p(ptr, u.l.lower);
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339 | stl_p(ptr + 4, u.l.upper);
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340 | }
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341 |
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342 | #elif defined(TARGET_WORDS_BIGENDIAN) && (!defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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343 | static inline int lduw_p(void *ptr)
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344 | {
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345 | #if defined(__i386__)
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346 | int val;
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347 | asm volatile ("movzwl %1, %0\n"
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348 | "xchgb %b0, %h0\n"
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349 | : "=q" (val)
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350 | : "m" (*(uint16_t *)ptr));
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351 | return val;
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352 | #else
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353 | uint8_t *b = (uint8_t *) ptr;
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354 | return ((b[0] << 8) | b[1]);
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355 | #endif
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356 | }
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357 |
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358 | static inline int ldsw_p(void *ptr)
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359 | {
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360 | #if defined(__i386__)
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361 | int val;
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362 | asm volatile ("movzwl %1, %0\n"
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363 | "xchgb %b0, %h0\n"
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364 | : "=q" (val)
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365 | : "m" (*(uint16_t *)ptr));
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366 | return (int16_t)val;
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367 | #else
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368 | uint8_t *b = (uint8_t *) ptr;
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369 | return (int16_t)((b[0] << 8) | b[1]);
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370 | #endif
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371 | }
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372 |
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373 | static inline int ldl_p(void *ptr)
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374 | {
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375 | #if defined(__i386__) || defined(__x86_64__)
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376 | int val;
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377 | asm volatile ("movl %1, %0\n"
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378 | "bswap %0\n"
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379 | : "=r" (val)
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380 | : "m" (*(uint32_t *)ptr));
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381 | return val;
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382 | #else
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383 | uint8_t *b = (uint8_t *) ptr;
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384 | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
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385 | #endif
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386 | }
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387 |
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388 | static inline uint64_t ldq_p(void *ptr)
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389 | {
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390 | uint32_t a,b;
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391 | a = ldl_p(ptr);
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392 | b = ldl_p(ptr+4);
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393 | return (((uint64_t)a<<32)|b);
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394 | }
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395 |
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396 | static inline void stw_p(void *ptr, int v)
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397 | {
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398 | #if defined(__i386__)
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399 | asm volatile ("xchgb %b0, %h0\n"
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400 | "movw %w0, %1\n"
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401 | : "=q" (v)
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402 | : "m" (*(uint16_t *)ptr), "0" (v));
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403 | #else
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404 | uint8_t *d = (uint8_t *) ptr;
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405 | d[0] = v >> 8;
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406 | d[1] = v;
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407 | #endif
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408 | }
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409 |
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410 | static inline void stl_p(void *ptr, int v)
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411 | {
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412 | #if defined(__i386__) || defined(__x86_64__)
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413 | asm volatile ("bswap %0\n"
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414 | "movl %0, %1\n"
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415 | : "=r" (v)
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416 | : "m" (*(uint32_t *)ptr), "0" (v));
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417 | #else
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418 | uint8_t *d = (uint8_t *) ptr;
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419 | d[0] = v >> 24;
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420 | d[1] = v >> 16;
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421 | d[2] = v >> 8;
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422 | d[3] = v;
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423 | #endif
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424 | }
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425 |
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426 | static inline void stq_p(void *ptr, uint64_t v)
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427 | {
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428 | stl_p(ptr, v >> 32);
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429 | stl_p(ptr + 4, v);
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430 | }
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431 |
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432 | /* float access */
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433 |
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434 | static inline float ldfl_p(void *ptr)
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435 | {
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436 | union {
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437 | float f;
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438 | uint32_t i;
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439 | } u;
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440 | u.i = ldl_p(ptr);
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441 | return u.f;
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442 | }
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443 |
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444 | static inline void stfl_p(void *ptr, float v)
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445 | {
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446 | union {
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447 | float f;
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448 | uint32_t i;
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449 | } u;
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450 | u.f = v;
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451 | stl_p(ptr, u.i);
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452 | }
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453 |
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454 | static inline double ldfq_p(void *ptr)
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455 | {
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456 | CPU_DoubleU u;
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457 | u.l.upper = ldl_p(ptr);
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458 | u.l.lower = ldl_p(ptr + 4);
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459 | return u.d;
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460 | }
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461 |
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462 | static inline void stfq_p(void *ptr, double v)
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463 | {
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464 | CPU_DoubleU u;
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465 | u.d = v;
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466 | stl_p(ptr, u.l.upper);
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467 | stl_p(ptr + 4, u.l.lower);
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468 | }
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469 |
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470 | #else
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471 |
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472 | #ifdef VBOX
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473 | static inline int lduw_p(void *ptr)
|
---|
474 | {
|
---|
475 | return remR3PhysReadUWord(ptr);
|
---|
476 | }
|
---|
477 |
|
---|
478 | static inline int ldsw_p(void *ptr)
|
---|
479 | {
|
---|
480 | return remR3PhysReadSWord(ptr);
|
---|
481 | }
|
---|
482 |
|
---|
483 | static inline int ldl_p(void *ptr)
|
---|
484 | {
|
---|
485 | return remR3PhysReadULong(ptr);
|
---|
486 | }
|
---|
487 |
|
---|
488 | static inline uint64_t ldq_p(void *ptr)
|
---|
489 | {
|
---|
490 | uint64_t val;
|
---|
491 |
|
---|
492 | remR3PhysReadBytes(ptr, &val, sizeof(val));
|
---|
493 | return val;
|
---|
494 | }
|
---|
495 |
|
---|
496 | static inline void stw_p(void *ptr, int v)
|
---|
497 | {
|
---|
498 | remR3PhysWriteWord(ptr, (uint16_t)v);
|
---|
499 | }
|
---|
500 |
|
---|
501 | static inline void stl_p(void *ptr, int v)
|
---|
502 | {
|
---|
503 | remR3PhysWriteDword(ptr, (uint32_t)v);
|
---|
504 | }
|
---|
505 |
|
---|
506 | static inline void stq_p(void *ptr, uint64_t v)
|
---|
507 | {
|
---|
508 | remR3PhysWriteBytes(ptr, &v, sizeof(v));
|
---|
509 | }
|
---|
510 |
|
---|
511 | /* float access */
|
---|
512 |
|
---|
513 | static inline float ldfl_p(void *ptr)
|
---|
514 | {
|
---|
515 | float val;
|
---|
516 |
|
---|
517 | remR3PhysReadBytes(ptr, &val, sizeof(val));
|
---|
518 | return val;
|
---|
519 | }
|
---|
520 |
|
---|
521 | static inline double ldfq_p(void *ptr)
|
---|
522 | {
|
---|
523 | double val;
|
---|
524 |
|
---|
525 | remR3PhysReadBytes(ptr, &val, sizeof(val));
|
---|
526 | return val;
|
---|
527 | }
|
---|
528 |
|
---|
529 | static inline void stfl_p(void *ptr, float v)
|
---|
530 | {
|
---|
531 | remR3PhysWriteBytes(ptr, &v, sizeof(v));
|
---|
532 | }
|
---|
533 |
|
---|
534 | static inline void stfq_p(void *ptr, double v)
|
---|
535 | {
|
---|
536 | remR3PhysWriteBytes(ptr, &v, sizeof(v));
|
---|
537 | }
|
---|
538 | #else
|
---|
539 | static inline int lduw_p(void *ptr)
|
---|
540 | {
|
---|
541 | return *(uint16_t *)ptr;
|
---|
542 | }
|
---|
543 |
|
---|
544 | static inline int ldsw_p(void *ptr)
|
---|
545 | {
|
---|
546 | return *(int16_t *)ptr;
|
---|
547 | }
|
---|
548 |
|
---|
549 | static inline int ldl_p(void *ptr)
|
---|
550 | {
|
---|
551 | return *(uint32_t *)ptr;
|
---|
552 | }
|
---|
553 |
|
---|
554 | static inline uint64_t ldq_p(void *ptr)
|
---|
555 | {
|
---|
556 | return *(uint64_t *)ptr;
|
---|
557 | }
|
---|
558 |
|
---|
559 | static inline void stw_p(void *ptr, int v)
|
---|
560 | {
|
---|
561 | *(uint16_t *)ptr = v;
|
---|
562 | }
|
---|
563 |
|
---|
564 | static inline void stl_p(void *ptr, int v)
|
---|
565 | {
|
---|
566 | *(uint32_t *)ptr = v;
|
---|
567 | }
|
---|
568 |
|
---|
569 | static inline void stq_p(void *ptr, uint64_t v)
|
---|
570 | {
|
---|
571 | *(uint64_t *)ptr = v;
|
---|
572 | }
|
---|
573 |
|
---|
574 | /* float access */
|
---|
575 |
|
---|
576 | static inline float ldfl_p(void *ptr)
|
---|
577 | {
|
---|
578 | return *(float *)ptr;
|
---|
579 | }
|
---|
580 |
|
---|
581 | static inline double ldfq_p(void *ptr)
|
---|
582 | {
|
---|
583 | return *(double *)ptr;
|
---|
584 | }
|
---|
585 |
|
---|
586 | static inline void stfl_p(void *ptr, float v)
|
---|
587 | {
|
---|
588 | *(float *)ptr = v;
|
---|
589 | }
|
---|
590 |
|
---|
591 | static inline void stfq_p(void *ptr, double v)
|
---|
592 | {
|
---|
593 | *(double *)ptr = v;
|
---|
594 | }
|
---|
595 | #endif /* VBOX */
|
---|
596 |
|
---|
597 | #endif
|
---|
598 |
|
---|
599 | /* MMU memory access macros */
|
---|
600 |
|
---|
601 | /* NOTE: we use double casts if pointers and target_ulong have
|
---|
602 | different sizes */
|
---|
603 | #define ldub_raw(p) ldub_p((uint8_t *)(long)(p))
|
---|
604 | #define ldsb_raw(p) ldsb_p((uint8_t *)(long)(p))
|
---|
605 | #define lduw_raw(p) lduw_p((uint8_t *)(long)(p))
|
---|
606 | #define ldsw_raw(p) ldsw_p((uint8_t *)(long)(p))
|
---|
607 | #define ldl_raw(p) ldl_p((uint8_t *)(long)(p))
|
---|
608 | #define ldq_raw(p) ldq_p((uint8_t *)(long)(p))
|
---|
609 | #define ldfl_raw(p) ldfl_p((uint8_t *)(long)(p))
|
---|
610 | #define ldfq_raw(p) ldfq_p((uint8_t *)(long)(p))
|
---|
611 | #define stb_raw(p, v) stb_p((uint8_t *)(long)(p), v)
|
---|
612 | #define stw_raw(p, v) stw_p((uint8_t *)(long)(p), v)
|
---|
613 | #define stl_raw(p, v) stl_p((uint8_t *)(long)(p), v)
|
---|
614 | #define stq_raw(p, v) stq_p((uint8_t *)(long)(p), v)
|
---|
615 | #define stfl_raw(p, v) stfl_p((uint8_t *)(long)(p), v)
|
---|
616 | #define stfq_raw(p, v) stfq_p((uint8_t *)(long)(p), v)
|
---|
617 |
|
---|
618 |
|
---|
619 | #if defined(CONFIG_USER_ONLY)
|
---|
620 |
|
---|
621 | /* if user mode, no other memory access functions */
|
---|
622 | #define ldub(p) ldub_raw(p)
|
---|
623 | #define ldsb(p) ldsb_raw(p)
|
---|
624 | #define lduw(p) lduw_raw(p)
|
---|
625 | #define ldsw(p) ldsw_raw(p)
|
---|
626 | #define ldl(p) ldl_raw(p)
|
---|
627 | #define ldq(p) ldq_raw(p)
|
---|
628 | #define ldfl(p) ldfl_raw(p)
|
---|
629 | #define ldfq(p) ldfq_raw(p)
|
---|
630 | #define stb(p, v) stb_raw(p, v)
|
---|
631 | #define stw(p, v) stw_raw(p, v)
|
---|
632 | #define stl(p, v) stl_raw(p, v)
|
---|
633 | #define stq(p, v) stq_raw(p, v)
|
---|
634 | #define stfl(p, v) stfl_raw(p, v)
|
---|
635 | #define stfq(p, v) stfq_raw(p, v)
|
---|
636 |
|
---|
637 | #define ldub_code(p) ldub_raw(p)
|
---|
638 | #define ldsb_code(p) ldsb_raw(p)
|
---|
639 | #define lduw_code(p) lduw_raw(p)
|
---|
640 | #define ldsw_code(p) ldsw_raw(p)
|
---|
641 | #define ldl_code(p) ldl_raw(p)
|
---|
642 |
|
---|
643 | #define ldub_kernel(p) ldub_raw(p)
|
---|
644 | #define ldsb_kernel(p) ldsb_raw(p)
|
---|
645 | #define lduw_kernel(p) lduw_raw(p)
|
---|
646 | #define ldsw_kernel(p) ldsw_raw(p)
|
---|
647 | #define ldl_kernel(p) ldl_raw(p)
|
---|
648 | #define ldfl_kernel(p) ldfl_raw(p)
|
---|
649 | #define ldfq_kernel(p) ldfq_raw(p)
|
---|
650 | #define stb_kernel(p, v) stb_raw(p, v)
|
---|
651 | #define stw_kernel(p, v) stw_raw(p, v)
|
---|
652 | #define stl_kernel(p, v) stl_raw(p, v)
|
---|
653 | #define stq_kernel(p, v) stq_raw(p, v)
|
---|
654 | #define stfl_kernel(p, v) stfl_raw(p, v)
|
---|
655 | #define stfq_kernel(p, vt) stfq_raw(p, v)
|
---|
656 |
|
---|
657 | #endif /* defined(CONFIG_USER_ONLY) */
|
---|
658 |
|
---|
659 | /* page related stuff */
|
---|
660 |
|
---|
661 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
|
---|
662 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
|
---|
663 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
|
---|
664 |
|
---|
665 | extern unsigned long qemu_real_host_page_size;
|
---|
666 | extern unsigned long qemu_host_page_bits;
|
---|
667 | extern unsigned long qemu_host_page_size;
|
---|
668 | extern unsigned long qemu_host_page_mask;
|
---|
669 |
|
---|
670 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
|
---|
671 |
|
---|
672 | /* same as PROT_xxx */
|
---|
673 | #define PAGE_READ 0x0001
|
---|
674 | #define PAGE_WRITE 0x0002
|
---|
675 | #define PAGE_EXEC 0x0004
|
---|
676 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
---|
677 | #define PAGE_VALID 0x0008
|
---|
678 | /* original state of the write flag (used when tracking self-modifying
|
---|
679 | code */
|
---|
680 | #define PAGE_WRITE_ORG 0x0010
|
---|
681 |
|
---|
682 | void page_dump(FILE *f);
|
---|
683 | int page_get_flags(unsigned long address);
|
---|
684 | void page_set_flags(unsigned long start, unsigned long end, int flags);
|
---|
685 | void page_unprotect_range(uint8_t *data, unsigned long data_size);
|
---|
686 |
|
---|
687 | #define SINGLE_CPU_DEFINES
|
---|
688 | #ifdef SINGLE_CPU_DEFINES
|
---|
689 |
|
---|
690 | #if defined(TARGET_I386)
|
---|
691 |
|
---|
692 | #define CPUState CPUX86State
|
---|
693 | #define cpu_init cpu_x86_init
|
---|
694 | #define cpu_exec cpu_x86_exec
|
---|
695 | #define cpu_gen_code cpu_x86_gen_code
|
---|
696 | #define cpu_signal_handler cpu_x86_signal_handler
|
---|
697 |
|
---|
698 | #elif defined(TARGET_ARM)
|
---|
699 |
|
---|
700 | #define CPUState CPUARMState
|
---|
701 | #define cpu_init cpu_arm_init
|
---|
702 | #define cpu_exec cpu_arm_exec
|
---|
703 | #define cpu_gen_code cpu_arm_gen_code
|
---|
704 | #define cpu_signal_handler cpu_arm_signal_handler
|
---|
705 |
|
---|
706 | #elif defined(TARGET_SPARC)
|
---|
707 |
|
---|
708 | #define CPUState CPUSPARCState
|
---|
709 | #define cpu_init cpu_sparc_init
|
---|
710 | #define cpu_exec cpu_sparc_exec
|
---|
711 | #define cpu_gen_code cpu_sparc_gen_code
|
---|
712 | #define cpu_signal_handler cpu_sparc_signal_handler
|
---|
713 |
|
---|
714 | #elif defined(TARGET_PPC)
|
---|
715 |
|
---|
716 | #define CPUState CPUPPCState
|
---|
717 | #define cpu_init cpu_ppc_init
|
---|
718 | #define cpu_exec cpu_ppc_exec
|
---|
719 | #define cpu_gen_code cpu_ppc_gen_code
|
---|
720 | #define cpu_signal_handler cpu_ppc_signal_handler
|
---|
721 |
|
---|
722 | #else
|
---|
723 |
|
---|
724 | #error unsupported target CPU
|
---|
725 |
|
---|
726 | #endif
|
---|
727 |
|
---|
728 | #endif /* SINGLE_CPU_DEFINES */
|
---|
729 |
|
---|
730 | void cpu_dump_state(CPUState *env, FILE *f,
|
---|
731 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
|
---|
732 | int flags);
|
---|
733 |
|
---|
734 | void cpu_abort(CPUState *env, const char *fmt, ...);
|
---|
735 | extern CPUState *cpu_single_env;
|
---|
736 | extern int code_copy_enabled;
|
---|
737 |
|
---|
738 | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
|
---|
739 | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
|
---|
740 | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
|
---|
741 | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
|
---|
742 | #ifdef VBOX
|
---|
743 | /** Executes a single instruction. cpu_exec() will normally return EXCP_SINGLE_INSTR. */
|
---|
744 | #define CPU_INTERRUPT_SINGLE_INSTR 0x0040
|
---|
745 | /** Executing a CPU_INTERRUPT_SINGLE_INSTR request, quit the cpu_loop. (for exceptions and suchlike) */
|
---|
746 | #define CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT 0x0080
|
---|
747 | /** VM execution was interrupted by VMR3Reset, VMR3Suspend or VMR3PowerOff. */
|
---|
748 | #define CPU_INTERRUPT_RC 0x0100
|
---|
749 | /** Exit current TB to process an external interrupt request (also in op.c!!) */
|
---|
750 | #define CPU_INTERRUPT_EXTERNAL_EXIT 0x0200
|
---|
751 | /** Exit current TB to process an external interrupt request (also in op.c!!) */
|
---|
752 | #define CPU_INTERRUPT_EXTERNAL_HARD 0x0400
|
---|
753 | /** Exit current TB to process an external interrupt request (also in op.c!!) */
|
---|
754 | #define CPU_INTERRUPT_EXTERNAL_TIMER 0x0800
|
---|
755 | /** Exit current TB to process an external interrupt request (also in op.c!!) */
|
---|
756 | #define CPU_INTERRUPT_EXTERNAL_DMA 0x1000
|
---|
757 | #endif /* VBOX */
|
---|
758 | void cpu_interrupt(CPUState *s, int mask);
|
---|
759 | void cpu_reset_interrupt(CPUState *env, int mask);
|
---|
760 |
|
---|
761 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
|
---|
762 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
|
---|
763 | void cpu_single_step(CPUState *env, int enabled);
|
---|
764 | void cpu_reset(CPUState *s);
|
---|
765 |
|
---|
766 | /* Return the physical page corresponding to a virtual one. Use it
|
---|
767 | only for debugging because no protection checks are done. Return -1
|
---|
768 | if no page found. */
|
---|
769 | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
|
---|
770 |
|
---|
771 | #define CPU_LOG_TB_OUT_ASM (1 << 0)
|
---|
772 | #define CPU_LOG_TB_IN_ASM (1 << 1)
|
---|
773 | #define CPU_LOG_TB_OP (1 << 2)
|
---|
774 | #define CPU_LOG_TB_OP_OPT (1 << 3)
|
---|
775 | #define CPU_LOG_INT (1 << 4)
|
---|
776 | #define CPU_LOG_EXEC (1 << 5)
|
---|
777 | #define CPU_LOG_PCALL (1 << 6)
|
---|
778 | #define CPU_LOG_IOPORT (1 << 7)
|
---|
779 | #define CPU_LOG_TB_CPU (1 << 8)
|
---|
780 |
|
---|
781 | /* define log items */
|
---|
782 | typedef struct CPULogItem {
|
---|
783 | int mask;
|
---|
784 | const char *name;
|
---|
785 | const char *help;
|
---|
786 | } CPULogItem;
|
---|
787 |
|
---|
788 | extern CPULogItem cpu_log_items[];
|
---|
789 |
|
---|
790 | void cpu_set_log(int log_flags);
|
---|
791 | void cpu_set_log_filename(const char *filename);
|
---|
792 | int cpu_str_to_log_mask(const char *str);
|
---|
793 |
|
---|
794 | /* IO ports API */
|
---|
795 |
|
---|
796 | /* NOTE: as these functions may be even used when there is an isa
|
---|
797 | brige on non x86 targets, we always defined them */
|
---|
798 | #ifndef NO_CPU_IO_DEFS
|
---|
799 | void cpu_outb(CPUState *env, int addr, int val);
|
---|
800 | void cpu_outw(CPUState *env, int addr, int val);
|
---|
801 | void cpu_outl(CPUState *env, int addr, int val);
|
---|
802 | int cpu_inb(CPUState *env, int addr);
|
---|
803 | int cpu_inw(CPUState *env, int addr);
|
---|
804 | int cpu_inl(CPUState *env, int addr);
|
---|
805 | #endif
|
---|
806 |
|
---|
807 | /* memory API */
|
---|
808 | extern uint32_t phys_ram_size;
|
---|
809 | #ifndef VBOX
|
---|
810 | extern int phys_ram_fd;
|
---|
811 | extern int phys_ram_size;
|
---|
812 | extern uint8_t *phys_ram_base;
|
---|
813 | #endif
|
---|
814 | extern uint8_t *phys_ram_dirty;
|
---|
815 |
|
---|
816 | /* physical memory access */
|
---|
817 | #define IO_MEM_NB_ENTRIES 256
|
---|
818 | #define TLB_INVALID_MASK (1 << 3)
|
---|
819 | #define IO_MEM_SHIFT 4
|
---|
820 |
|
---|
821 | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
|
---|
822 | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
|
---|
823 | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
|
---|
824 | #define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
|
---|
825 | #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
|
---|
826 | #ifdef VBOX
|
---|
827 | #define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
|
---|
828 | #endif
|
---|
829 |
|
---|
830 | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
|
---|
831 | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
|
---|
832 |
|
---|
833 | void cpu_register_physical_memory(target_phys_addr_t start_addr,
|
---|
834 | unsigned long size,
|
---|
835 | unsigned long phys_offset);
|
---|
836 | int cpu_register_io_memory(int io_index,
|
---|
837 | CPUReadMemoryFunc **mem_read,
|
---|
838 | CPUWriteMemoryFunc **mem_write,
|
---|
839 | void *opaque);
|
---|
840 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
|
---|
841 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
|
---|
842 |
|
---|
843 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
---|
844 | int len, int is_write);
|
---|
845 | static inline void cpu_physical_memory_read(target_phys_addr_t addr,
|
---|
846 | uint8_t *buf, int len)
|
---|
847 | {
|
---|
848 | cpu_physical_memory_rw(addr, buf, len, 0);
|
---|
849 | }
|
---|
850 | static inline void cpu_physical_memory_write(target_phys_addr_t addr,
|
---|
851 | const uint8_t *buf, int len)
|
---|
852 | {
|
---|
853 | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
|
---|
854 | }
|
---|
855 | uint32_t ldl_phys(target_phys_addr_t addr);
|
---|
856 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
|
---|
857 | void stl_phys(target_phys_addr_t addr, uint32_t val);
|
---|
858 |
|
---|
859 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
---|
860 | uint8_t *buf, int len, int is_write);
|
---|
861 |
|
---|
862 | /* read dirty bit (return 0 or 1) */
|
---|
863 | static inline int cpu_physical_memory_is_dirty(target_ulong addr)
|
---|
864 | {
|
---|
865 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS];
|
---|
866 | }
|
---|
867 |
|
---|
868 | static inline void cpu_physical_memory_set_dirty(target_ulong addr)
|
---|
869 | {
|
---|
870 | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 1;
|
---|
871 | }
|
---|
872 |
|
---|
873 | void cpu_physical_memory_reset_dirty(target_ulong start, target_ulong end);
|
---|
874 |
|
---|
875 | void dump_exec_info(FILE *f,
|
---|
876 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
|
---|
877 |
|
---|
878 |
|
---|
879 | #ifdef VBOX
|
---|
880 | void tb_invalidate_virt(CPUState *env, uint32_t eip);
|
---|
881 | #endif
|
---|
882 |
|
---|
883 | #endif /* CPU_ALL_H */
|
---|