VBoxRecompiler.c@ 1806

Last change on this file since 1806 was 1337, checked in by vboxsync, 18 years ago
Forbid execution of v86 code with IF=0.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 153.8 KB

Line
1	/** @file
2	*
3	* VBox Recompiler - QEMU.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include "vl.h"
27	#include "exec-all.h"
28
29	#include <VBox/rem.h>
30	#include <VBox/vmapi.h>
31	#include <VBox/tm.h>
32	#include <VBox/ssm.h>
33	#include <VBox/em.h>
34	#include <VBox/trpm.h>
35	#include <VBox/iom.h>
36	#include <VBox/mm.h>
37	#include <VBox/pgm.h>
38	#include <VBox/pdm.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/dbg.h>
41	#include <VBox/hwaccm.h>
42	#include <VBox/patm.h>
43	#include <VBox/csam.h>
44	#include "REMInternal.h"
45	#include <VBox/vm.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49	#define LOG_GROUP LOG_GROUP_REM
50	#include <VBox/log.h>
51	#include <iprt/semaphore.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/thread.h>
55	#include <iprt/string.h>
56
57
58	/* Don't wanna include everything. */
59	extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
60	extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
61	extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
62	extern void tlb_flush_page(CPUX86State *env, uint32_t addr);
63	extern void tlb_flush(CPUState *env, int flush_global);
64	extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
65	extern void sync_ldtr(CPUX86State *env1, int selector);
66	extern int sync_tr(CPUX86State *env1, int selector);
67
68	#ifdef VBOX_STRICT
69	unsigned long get_phys_page_offset(target_ulong addr);
70	#endif
71
72
73	/*******************************************************************************
74	* Defined Constants And Macros *
75	*******************************************************************************/
76
77	/** Copy 80-bit fpu register at pSrc to pDst.
78	* This is probably faster than calling memcpy.
79	*/
80	#define REM_COPY_FPU_REG(pDst, pSrc) \
81	do { (PX86FPUMMX)(pDst) = (const X86FPUMMX *)(pSrc); } while (0)
82
83
84	/*******************************************************************************
85	* Internal Functions *
86	*******************************************************************************/
87	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
88	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
89	static void remR3StateUpdate(PVM pVM);
90	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
91	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
92	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
93	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
94	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96
97	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
98	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
99	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
100	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
101	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103
104
105	/*******************************************************************************
106	* Global Variables *
107	*******************************************************************************/
108
109	/** The log level of the recompiler. */
110	#if 1
111	extern int loglevel;
112	#else
113	int loglevel = ~0;
114	FILE *logfile = NULL;
115	#endif
116
117
118	/** @todo Move stats to REM::s some rainy day we have nothing do to. */
119	#ifdef VBOX_WITH_STATISTICS
120	static STAMPROFILEADV gStatExecuteSingleInstr;
121	static STAMPROFILEADV gStatCompilationQEmu;
122	static STAMPROFILEADV gStatRunCodeQEmu;
123	static STAMPROFILEADV gStatTotalTimeQEmu;
124	static STAMPROFILEADV gStatTimers;
125	static STAMPROFILEADV gStatTBLookup;
126	static STAMPROFILEADV gStatIRQ;
127	static STAMPROFILEADV gStatRawCheck;
128	static STAMPROFILEADV gStatMemRead;
129	static STAMPROFILEADV gStatMemWrite;
130	static STAMCOUNTER gStatRefuseTFInhibit;
131	static STAMCOUNTER gStatRefuseVM86;
132	static STAMCOUNTER gStatRefusePaging;
133	static STAMCOUNTER gStatRefusePAE;
134	static STAMCOUNTER gStatRefuseIOPLNot0;
135	static STAMCOUNTER gStatRefuseIF0;
136	static STAMCOUNTER gStatRefuseCode16;
137	static STAMCOUNTER gStatRefuseWP0;
138	static STAMCOUNTER gStatRefuseRing1or2;
139	static STAMCOUNTER gStatRefuseCanExecute;
140	static STAMCOUNTER gStatREMGDTChange;
141	static STAMCOUNTER gStatREMIDTChange;
142	static STAMCOUNTER gStatREMLDTRChange;
143	static STAMCOUNTER gStatREMTRChange;
144	static STAMCOUNTER gStatSelOutOfSync[6];
145	static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
146	#endif
147
148	/*
149	* Global stuff.
150	*/
151
152	/** MMIO read callbacks. */
153	CPUReadMemoryFunc *g_apfnMMIORead[3] =
154	{
155	remR3MMIOReadU8,
156	remR3MMIOReadU16,
157	remR3MMIOReadU32
158	};
159
160	/** MMIO write callbacks. */
161	CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
162	{
163	remR3MMIOWriteU8,
164	remR3MMIOWriteU16,
165	remR3MMIOWriteU32
166	};
167
168	/** Handler read callbacks. */
169	CPUReadMemoryFunc *g_apfnHandlerRead[3] =
170	{
171	remR3HandlerReadU8,
172	remR3HandlerReadU16,
173	remR3HandlerReadU32
174	};
175
176	/** Handler write callbacks. */
177	CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
178	{
179	remR3HandlerWriteU8,
180	remR3HandlerWriteU16,
181	remR3HandlerWriteU32
182	};
183
184	#ifndef PGM_DYNAMIC_RAM_ALLOC
185	/* Guest physical RAM base. Not to be used in external code. */
186	static uint8_t *phys_ram_base;
187	#endif
188
189	/*
190	* Instance stuff.
191	*/
192	/** Pointer to the cpu state. */
193	CPUState *cpu_single_env;
194
195
196	#ifdef VBOX_WITH_DEBUGGER
197	/*
198	* Debugger commands.
199	*/
200	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
201
202	/** '.remstep' arguments. */
203	static const DBGCVARDESC g_aArgRemStep[] =
204	{
205	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
206	{ 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
207	};
208
209	/** Command descriptors. */
210	static const DBGCCMD g_aCmds[] =
211	{
212	{
213	.pszCmd ="remstep",
214	.cArgsMin = 0,
215	.cArgsMax = 1,
216	.paArgDescs = &g_aArgRemStep[0],
217	.cArgDescs = ELEMENTS(g_aArgRemStep),
218	.pResultDesc = NULL,
219	.fFlags = 0,
220	.pfnHandler = remR3CmdDisasEnableStepping,
221	.pszSyntax = "[on/off]",
222	.pszDescription = "Enable or disable the single stepping with logged disassembly. "
223	"If no arguments show the current state."
224	}
225	};
226	#endif
227
228
229	/*******************************************************************************
230	* Internal Functions *
231	*******************************************************************************/
232	static void remAbort(int rc, const char *pszTip);
233
234
235	/* Put them here to avoid unused variable warning. */
236	AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
237	//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
238	//AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
239
240	/**
241	* Initializes the REM.
242	*
243	* @returns VBox status code.
244	* @param pVM The VM to operate on.
245	*/
246	REMR3DECL(int) REMR3Init(PVM pVM)
247	{
248	uint32_t u32Dummy;
249	AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
250	//AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
251	AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
252	#if 0 /* not merged yet */
253	Assert(!testmath());
254	#endif
255
256	/*
257	* Init some internal data members.
258	*/
259	pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
260	pVM->rem.s.Env.pVM = pVM;
261	#ifdef CPU_RAW_MODE_INIT
262	pVM->rem.s.state \|= CPU_RAW_MODE_INIT;
263	#endif
264
265	/* ctx. */
266	int rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);
267	if (VBOX_FAILURE(rc))
268	{
269	AssertMsgFailed(("Failed to obtain guest ctx pointer. rc=%Vrc\n", rc));
270	return rc;
271	}
272	AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
273
274	/*
275	* Init the recompiler.
276	*/
277	if (!cpu_x86_init(&pVM->rem.s.Env))
278	{
279	AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
280	return VERR_GENERAL_FAILURE;
281	}
282	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
283
284	/* allocate code buffer for single instruction emulation. */
285	pVM->rem.s.Env.cbCodeBuffer = 4096;
286	pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
287	AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
288
289	/* finally, set the cpu_single_env global. */
290	cpu_single_env = &pVM->rem.s.Env;
291
292	/* Nothing is pending by default */
293	pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
294
295	#ifdef DEBUG_bird
296	//cpu_breakpoint_insert(&pVM->rem.s.Env, some-address);
297	#endif
298
299	/*
300	* Register ram types.
301	*/
302	pVM->rem.s.iMMIOMemType = cpu_register_io_memory(0, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
303	AssertReleaseMsg(pVM->rem.s.iMMIOMemType > 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
304	pVM->rem.s.iHandlerMemType = cpu_register_io_memory(0, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
305	AssertReleaseMsg(pVM->rem.s.iHandlerMemType > 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
306	Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
307
308	/*
309	* Register the saved state data unit.
310	*/
311	rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
312	NULL, remR3Save, NULL,
313	NULL, remR3Load, NULL);
314	if (VBOX_FAILURE(rc))
315	return rc;
316
317	#ifdef VBOX_WITH_DEBUGGER
318	/*
319	* Debugger commands.
320	*/
321	static bool fRegisteredCmds = false;
322	if (!fRegisteredCmds)
323	{
324	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
325	if (VBOX_SUCCESS(rc))
326	fRegisteredCmds = true;
327	}
328	#endif
329
330	#ifdef VBOX_WITH_STATISTICS
331	/*
332	* Statistics.
333	*/
334	STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
335	STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
336	STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
337	STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
338	STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
339	STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
340	STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
341	STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
342	STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
343	STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
344
345	STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
346	STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
347	STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
348	STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
349	STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
350	STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
351	STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
352	STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
353	STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
354	STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
355
356	STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
357	STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
358	STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
359	STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
360
361	STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
362	STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
363	STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
364	STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
365	STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
366	STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
367
368	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
369	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
370	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
371	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
372	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
373	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
374
375	#endif
376	return rc;
377	}
378
379
380	/**
381	* Terminates the REM.
382	*
383	* Termination means cleaning up and freeing all resources,
384	* the VM it self is at this point powered off or suspended.
385	*
386	* @returns VBox status code.
387	* @param pVM The VM to operate on.
388	*/
389	REMR3DECL(int) REMR3Term(PVM pVM)
390	{
391	return VINF_SUCCESS;
392	}
393
394
395	/**
396	* The VM is being reset.
397	*
398	* For the REM component this means to call the cpu_reset() and
399	* reinitialize some state variables.
400	*
401	* @param pVM VM handle.
402	*/
403	REMR3DECL(void) REMR3Reset(PVM pVM)
404	{
405	pVM->rem.s.fIgnoreCR3Load = true;
406	pVM->rem.s.fIgnoreInvlPg = true;
407	pVM->rem.s.fIgnoreCpuMode = true;
408
409	/*
410	* Reset the REM cpu.
411	*/
412	cpu_reset(&pVM->rem.s.Env);
413	pVM->rem.s.cInvalidatedPages = 0;
414
415	pVM->rem.s.fIgnoreCR3Load = false;
416	pVM->rem.s.fIgnoreInvlPg = false;
417	pVM->rem.s.fIgnoreCpuMode = false;
418	}
419
420
421	/**
422	* Execute state save operation.
423	*
424	* @returns VBox status code.
425	* @param pVM VM Handle.
426	* @param pSSM SSM operation handle.
427	*/
428	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
429	{
430	LogFlow(("remR3Save:\n"));
431
432	/*
433	* Save the required CPU Env bits.
434	* (Not much because we're never in REM when doing the save.)
435	*/
436	PREM pRem = &pVM->rem.s;
437	Assert(!pRem->fInREM);
438	SSMR3PutU32(pSSM, pRem->Env.hflags);
439	SSMR3PutMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
440	SSMR3PutU32(pSSM, ~0); /* separator */
441
442	/*
443	* Save the REM stuff.
444	*/
445	SSMR3PutUInt(pSSM, pRem->cInvalidatedPages);
446	unsigned i;
447	for (i = 0; i < pRem->cInvalidatedPages; i++)
448	SSMR3PutGCPtr(pSSM, pRem->aGCPtrInvalidatedPages[i]);
449
450	SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
451
452	return SSMR3PutU32(pSSM, ~0); /* terminator */
453	}
454
455
456	/**
457	* Execute state load operation.
458	*
459	* @returns VBox status code.
460	* @param pVM VM Handle.
461	* @param pSSM SSM operation handle.
462	* @param u32Version Data layout version.
463	*/
464	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
465	{
466	uint32_t u32Dummy;
467	LogFlow(("remR3Load:\n"));
468
469	/*
470	* Validate version.
471	*/
472	if (u32Version != REM_SAVED_STATE_VERSION)
473	{
474	Log(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
475	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
476	}
477
478	/*
479	* Do a reset to be on the safe side...
480	*/
481	REMR3Reset(pVM);
482
483	/*
484	* Ignore all ignorable notifications.
485	* Not doing this will cause big trouble.
486	*/
487	pVM->rem.s.fIgnoreCR3Load = true;
488	pVM->rem.s.fIgnoreInvlPg = true;
489	pVM->rem.s.fIgnoreCpuMode = true;
490
491	/*
492	* Load the required CPU Env bits.
493	* (Not much because we're never in REM when doing the save.)
494	*/
495	PREM pRem = &pVM->rem.s;
496	Assert(!pRem->fInREM);
497	SSMR3GetU32(pSSM, &pRem->Env.hflags);
498	SSMR3GetMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
499	uint32_t u32Sep;
500	int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
501	if (VBOX_FAILURE(rc))
502	return rc;
503	if (u32Sep != ~0)
504	{
505	AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
506	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
507	}
508
509	/*
510	* Load the REM stuff.
511	*/
512	rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
513	if (VBOX_FAILURE(rc))
514	return rc;
515	if (pRem->cInvalidatedPages > ELEMENTS(pRem->aGCPtrInvalidatedPages))
516	{
517	AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
518	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
519	}
520	unsigned i;
521	for (i = 0; i < pRem->cInvalidatedPages; i++)
522	SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
523
524	rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
525	if (VBOX_FAILURE(rc))
526	return rc;
527
528	/* check the terminator. */
529	rc = SSMR3GetU32(pSSM, &u32Sep);
530	if (VBOX_FAILURE(rc))
531	return rc;
532	if (u32Sep != ~0)
533	{
534	AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
535	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
536	}
537
538	/*
539	* Get the CPUID features.
540	*/
541	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
542
543	/*
544	* Sync the Load Flush the TLB
545	*/
546	tlb_flush(&pRem->Env, 1);
547
548	#if 0 /** @todo r=bird: this doesn't make sense. WHY? */
549	/*
550	* Clear all lazy flags (only FPU sync for now).
551	*/
552	CPUMGetAndClearFPUUsedREM(pVM);
553	#endif
554
555	/*
556	* Stop ignoring ignornable notifications.
557	*/
558	pVM->rem.s.fIgnoreCpuMode = false;
559	pVM->rem.s.fIgnoreInvlPg = false;
560	pVM->rem.s.fIgnoreCR3Load = false;
561
562	return VINF_SUCCESS;
563	}
564
565
566
567	#undef LOG_GROUP
568	#define LOG_GROUP LOG_GROUP_REM_RUN
569
570	/**
571	* Single steps an instruction in recompiled mode.
572	*
573	* Before calling this function the REM state needs to be in sync with
574	* the VM. Call REMR3State() to perform the sync. It's only necessary
575	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
576	* and after calling REMR3StateBack().
577	*
578	* @returns VBox status code.
579	*
580	* @param pVM VM Handle.
581	*/
582	REMR3DECL(int) REMR3Step(PVM pVM)
583	{
584	/*
585	* Lock the REM - we don't wanna have anyone interrupting us
586	* while stepping - and enabled single stepping. We also ignore
587	* pending interrupts and suchlike.
588	*/
589	int interrupt_request = pVM->rem.s.Env.interrupt_request;
590	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
591	pVM->rem.s.Env.interrupt_request = 0;
592	cpu_single_step(&pVM->rem.s.Env, 1);
593
594	/*
595	* If we're standing at a breakpoint, that have to be disabled before we start stepping.
596	*/
597	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
598	bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
599
600	/*
601	* Execute and handle the return code.
602	* We execute without enabling the cpu tick, so on success we'll
603	* just flip it on and off to make sure it moves
604	*/
605	int rc = cpu_exec(&pVM->rem.s.Env);
606	if (rc == EXCP_DEBUG)
607	{
608	TMCpuTickResume(pVM);
609	TMCpuTickPause(pVM);
610	TMVirtualResume(pVM);
611	TMVirtualPause(pVM);
612	rc = VINF_EM_DBG_STEPPED;
613	}
614	else
615	{
616	AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
617	switch (rc)
618	{
619	case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
620	case EXCP_HLT: rc = VINF_EM_HALT; break;
621	case EXCP_RC:
622	rc = pVM->rem.s.rc;
623	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
624	break;
625	default:
626	AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
627	rc = VERR_INTERNAL_ERROR;
628	break;
629	}
630	}
631
632	/*
633	* Restore the stuff we changed to prevent interruption.
634	* Unlock the REM.
635	*/
636	if (fBp)
637	{
638	int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
639	Assert(rc2 == 0); NOREF(rc2);
640	}
641	cpu_single_step(&pVM->rem.s.Env, 0);
642	pVM->rem.s.Env.interrupt_request = interrupt_request;
643
644	return rc;
645	}
646
647
648	/**
649	* Set a breakpoint using the REM facilities.
650	*
651	* @returns VBox status code.
652	* @param pVM The VM handle.
653	* @param Address The breakpoint address.
654	* @thread The emulation thread.
655	*/
656	REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
657	{
658	VM_ASSERT_EMT(pVM);
659	if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
660	{
661	LogFlow(("REMR3BreakpointSet: Address=%VGv\n", Address));
662	return VINF_SUCCESS;
663	}
664	LogFlow(("REMR3BreakpointSet: Address=%VGv - failed!\n", Address));
665	return VERR_REM_NO_MORE_BP_SLOTS;
666	}
667
668
669	/**
670	* Clears a breakpoint set by REMR3BreakpointSet().
671	*
672	* @returns VBox status code.
673	* @param pVM The VM handle.
674	* @param Address The breakpoint address.
675	* @thread The emulation thread.
676	*/
677	REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
678	{
679	VM_ASSERT_EMT(pVM);
680	if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
681	{
682	LogFlow(("REMR3BreakpointClear: Address=%VGv\n", Address));
683	return VINF_SUCCESS;
684	}
685	LogFlow(("REMR3BreakpointClear: Address=%VGv - not found!\n", Address));
686	return VERR_REM_BP_NOT_FOUND;
687	}
688
689
690	/**
691	* Emulate an instruction.
692	*
693	* This function executes one instruction without letting anyone
694	* interrupt it. This is intended for being called while being in
695	* raw mode and thus will take care of all the state syncing between
696	* REM and the rest.
697	*
698	* @returns VBox status code.
699	* @param pVM VM handle.
700	*/
701	REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
702	{
703	Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
704
705	/*
706	* Sync the state and enable single instruction / single stepping.
707	*/
708	int rc = REMR3State(pVM);
709	if (VBOX_SUCCESS(rc))
710	{
711	int interrupt_request = pVM->rem.s.Env.interrupt_request;
712	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
713	Assert(!pVM->rem.s.Env.singlestep_enabled);
714	#if 1
715
716	/*
717	* Now we set the execute single instruction flag and enter the cpu_exec loop.
718	*/
719	pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
720	rc = cpu_exec(&pVM->rem.s.Env);
721	switch (rc)
722	{
723	/*
724	* Executed without anything out of the way happening.
725	*/
726	case EXCP_SINGLE_INSTR:
727	rc = VINF_EM_RESCHEDULE;
728	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
729	break;
730
731	/*
732	* If we take a trap or start servicing a pending interrupt, we might end up here.
733	* (Timer thread or some other thread wishing EMT's attention.)
734	*/
735	case EXCP_INTERRUPT:
736	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
737	rc = VINF_EM_RESCHEDULE;
738	break;
739
740	/*
741	* Single step, we assume!
742	* If there was a breakpoint there we're fucked now.
743	*/
744	case EXCP_DEBUG:
745	{
746	/* breakpoint or single step? */
747	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
748	int iBP;
749	rc = VINF_EM_DBG_STEPPED;
750	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
751	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
752	{
753	rc = VINF_EM_DBG_BREAKPOINT;
754	break;
755	}
756	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
757	break;
758	}
759
760	/*
761	* hlt instruction.
762	*/
763	case EXCP_HLT:
764	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
765	rc = VINF_EM_HALT;
766	break;
767
768	/*
769	* Switch to RAW-mode.
770	*/
771	case EXCP_EXECUTE_RAW:
772	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
773	rc = VINF_EM_RESCHEDULE_RAW;
774	break;
775
776	/*
777	* Switch to hardware accelerated RAW-mode.
778	*/
779	case EXCP_EXECUTE_HWACC:
780	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
781	rc = VINF_EM_RESCHEDULE_HWACC;
782	break;
783
784	/*
785	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
786	*/
787	case EXCP_RC:
788	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
789	rc = pVM->rem.s.rc;
790	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
791	break;
792
793	/*
794	* Figure out the rest when they arrive....
795	*/
796	default:
797	AssertMsgFailed(("rc=%d\n", rc));
798	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
799	rc = VINF_EM_RESCHEDULE;
800	break;
801	}
802
803	/*
804	* Switch back the state.
805	*/
806	#else
807	pVM->rem.s.Env.interrupt_request = 0;
808	cpu_single_step(&pVM->rem.s.Env, 1);
809
810	/*
811	* Execute and handle the return code.
812	* We execute without enabling the cpu tick, so on success we'll
813	* just flip it on and off to make sure it moves.
814	*
815	* (We do not use emulate_single_instr() because that doesn't enter the
816	* right way in will cause serious trouble if a longjmp was attempted.)
817	*/
818	#ifdef DEBUG_bird
819	remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
820	#endif
821	int cTimesMax = 16384;
822	uint32_t eip = pVM->rem.s.Env.eip;
823	do
824	{
825	rc = cpu_exec(&pVM->rem.s.Env);
826	} while ( eip == pVM->rem.s.Env.eip
827	&& (rc == EXCP_DEBUG \|\| rc == EXCP_EXECUTE_RAW)
828	&& --cTimesMax > 0);
829	switch (rc)
830	{
831	/*
832	* Single step, we assume!
833	* If there was a breakpoint there we're fucked now.
834	*/
835	case EXCP_DEBUG:
836	{
837	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
838	rc = VINF_EM_RESCHEDULE;
839	break;
840	}
841
842	/*
843	* We cannot be interrupted!
844	*/
845	case EXCP_INTERRUPT:
846	AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
847	rc = VERR_INTERNAL_ERROR;
848	break;
849
850	/*
851	* hlt instruction.
852	*/
853	case EXCP_HLT:
854	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
855	rc = VINF_EM_HALT;
856	break;
857
858	/*
859	* Switch to RAW-mode.
860	*/
861	case EXCP_EXECUTE_RAW:
862	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
863	rc = VINF_EM_RESCHEDULE_RAW;
864	break;
865
866	/*
867	* Switch to hardware accelerated RAW-mode.
868	*/
869	case EXCP_EXECUTE_HWACC:
870	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
871	rc = VINF_EM_RESCHEDULE_HWACC;
872	break;
873
874	/*
875	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
876	*/
877	case EXCP_RC:
878	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
879	rc = pVM->rem.s.rc;
880	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
881	break;
882
883	/*
884	* Figure out the rest when they arrive....
885	*/
886	default:
887	AssertMsgFailed(("rc=%d\n", rc));
888	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
889	rc = VINF_SUCCESS;
890	break;
891	}
892
893	/*
894	* Switch back the state.
895	*/
896	cpu_single_step(&pVM->rem.s.Env, 0);
897	#endif
898	pVM->rem.s.Env.interrupt_request = interrupt_request;
899	int rc2 = REMR3StateBack(pVM);
900	AssertRC(rc2);
901	}
902
903	Log2(("REMR3EmulateInstruction: returns %Vrc (cs:eip=%04x:%08x)\n",
904	rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
905	return rc;
906	}
907
908
909	/**
910	* Runs code in recompiled mode.
911	*
912	* Before calling this function the REM state needs to be in sync with
913	* the VM. Call REMR3State() to perform the sync. It's only necessary
914	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
915	* and after calling REMR3StateBack().
916	*
917	* @returns VBox status code.
918	*
919	* @param pVM VM Handle.
920	*/
921	REMR3DECL(int) REMR3Run(PVM pVM)
922	{
923	Log2(("REMR3Run: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
924	Assert(pVM->rem.s.fInREM);
925	////Keyboard / tb stuff:
926	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0xf000
927	// && pVM->rem.s.Env.eip >= 0xe860
928	// && pVM->rem.s.Env.eip <= 0xe880)
929	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
930	////A20:
931	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x9020
932	// && pVM->rem.s.Env.eip >= 0x970
933	// && pVM->rem.s.Env.eip <= 0x9a0)
934	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
935	////Speaker (port 61h)
936	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x0010
937	// && ( (pVM->rem.s.Env.eip >= 0x90278c10 && pVM->rem.s.Env.eip <= 0x90278c30)
938	// \|\| (pVM->rem.s.Env.eip >= 0x9010e250 && pVM->rem.s.Env.eip <= 0x9010e260)
939	// )
940	// )
941	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
942	//DBGFR3InfoLog(pVM, "timers", NULL);
943
944
945	int rc = cpu_exec(&pVM->rem.s.Env);
946	switch (rc)
947	{
948	/*
949	* This happens when the execution was interrupted
950	* by an external event, like pending timers.
951	*/
952	case EXCP_INTERRUPT:
953	Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
954	rc = VINF_SUCCESS;
955	break;
956
957	/*
958	* hlt instruction.
959	*/
960	case EXCP_HLT:
961	Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
962	rc = VINF_EM_HALT;
963	break;
964
965	/*
966	* Breakpoint/single step.
967	*/
968	case EXCP_DEBUG:
969	{
970	#if 0//def DEBUG_bird
971	static int iBP = 0;
972	printf("howdy, breakpoint! iBP=%d\n", iBP);
973	switch (iBP)
974	{
975	case 0:
976	cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
977	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
978	//pVM->rem.s.Env.interrupt_request = 0;
979	//pVM->rem.s.Env.exception_index = -1;
980	//g_fInterruptDisabled = 1;
981	rc = VINF_SUCCESS;
982	asm("int3");
983	break;
984	default:
985	asm("int3");
986	break;
987	}
988	iBP++;
989	#else
990	/* breakpoint or single step? */
991	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
992	int iBP;
993	rc = VINF_EM_DBG_STEPPED;
994	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
995	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
996	{
997	rc = VINF_EM_DBG_BREAKPOINT;
998	break;
999	}
1000	Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
1001	#endif
1002	break;
1003	}
1004
1005	/*
1006	* Switch to RAW-mode.
1007	*/
1008	case EXCP_EXECUTE_RAW:
1009	Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1010	rc = VINF_EM_RESCHEDULE_RAW;
1011	break;
1012
1013	/*
1014	* Switch to hardware accelerated RAW-mode.
1015	*/
1016	case EXCP_EXECUTE_HWACC:
1017	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1018	rc = VINF_EM_RESCHEDULE_HWACC;
1019	break;
1020
1021	/*
1022	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
1023	*/
1024	case EXCP_RC:
1025	Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
1026	rc = pVM->rem.s.rc;
1027	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1028	break;
1029
1030	/*
1031	* Figure out the rest when they arrive....
1032	*/
1033	default:
1034	AssertMsgFailed(("rc=%d\n", rc));
1035	Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1036	rc = VINF_SUCCESS;
1037	break;
1038	}
1039
1040	Log2(("REMR3Run: returns %Vrc (cs:eip=%04x:%08x)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
1041	return rc;
1042	}
1043
1044
1045	/**
1046	* Check if the cpu state is suitable for Raw execution.
1047	*
1048	* @returns boolean
1049	* @param env The CPU env struct.
1050	* @param eip The EIP to check this for (might differ from env->eip).
1051	* @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1052	* @param pExceptionIndex Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1053	*
1054	* @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1055	*/
1056	bool remR3CanExecuteRaw(CPUState env, RTGCPTR eip, unsigned fFlags, uint32_t pExceptionIndex)
1057	{
1058	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1059	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1060	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1061
1062	/* Update counter. */
1063	env->pVM->rem.s.cCanExecuteRaw++;
1064
1065	if (HWACCMIsEnabled(env->pVM))
1066	{
1067	env->state \|= CPU_RAW_HWACC;
1068
1069	/*
1070	* Create partial context for HWACCMR3CanExecuteGuest
1071	*/
1072	CPUMCTX Ctx;
1073	Ctx.cr0 = env->cr[0];
1074	Ctx.cr3 = env->cr[3];
1075	Ctx.cr4 = env->cr[4];
1076
1077	Ctx.tr = env->tr.selector;
1078	Ctx.trHid.u32Base = (uint32_t)env->tr.base;
1079	Ctx.trHid.u32Limit = env->tr.limit;
1080	Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1081
1082	Ctx.idtr.cbIdt = env->idt.limit;
1083	Ctx.idtr.pIdt = (uint32_t)env->idt.base;
1084
1085	Ctx.eflags.u32 = env->eflags;
1086
1087	Ctx.cs = env->segs[R_CS].selector;
1088	Ctx.csHid.u32Base = (uint32_t)env->segs[R_CS].base;
1089	Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1090	Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1091
1092	Ctx.ss = env->segs[R_SS].selector;
1093	Ctx.ssHid.u32Base = (uint32_t)env->segs[R_SS].base;
1094	Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1095	Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1096
1097	/* Hardware accelerated raw-mode:
1098	*
1099	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1100	*/
1101	if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1102	{
1103	*pExceptionIndex = EXCP_EXECUTE_HWACC;
1104	return true;
1105	}
1106	return false;
1107	}
1108
1109	/*
1110	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1111	* or 32 bits protected mode ring 0 code
1112	*
1113	* The tests are ordered by the likelyhood of being true during normal execution.
1114	*/
1115	if (fFlags & (HF_TF_MASK \| HF_INHIBIT_IRQ_MASK))
1116	{
1117	STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1118	Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1119	return false;
1120	}
1121
1122	#ifndef VBOX_RAW_V86
1123	if (fFlags & VM_MASK) {
1124	STAM_COUNTER_INC(&gStatRefuseVM86);
1125	Log2(("raw mode refused: VM_MASK\n"));
1126	return false;
1127	}
1128	#endif
1129
1130	if (env->state & CPU_EMULATE_SINGLE_INSTR)
1131	{
1132	#ifndef DEBUG_bird
1133	Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1134	#endif
1135	return false;
1136	}
1137
1138	if (env->singlestep_enabled)
1139	{
1140	//Log2(("raw mode refused: Single step\n"));
1141	return false;
1142	}
1143
1144	if (env->nb_breakpoints > 0)
1145	{
1146	//Log2(("raw mode refused: Breakpoints\n"));
1147	return false;
1148	}
1149
1150	uint32_t u32CR0 = env->cr[0];
1151	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
1152	{
1153	STAM_COUNTER_INC(&gStatRefusePaging);
1154	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1155	return false;
1156	}
1157
1158	if (env->cr[4] & CR4_PAE_MASK)
1159	{
1160	STAM_COUNTER_INC(&gStatRefusePAE);
1161	//Log2(("raw mode refused: PAE\n"));
1162	return false;
1163	}
1164
1165	if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1166	{
1167	if (!EMIsRawRing3Enabled(env->pVM))
1168	return false;
1169
1170	if (!(env->eflags & IF_MASK))
1171	{
1172	STAM_COUNTER_INC(&gStatRefuseIF0);
1173	Log2(("raw mode refused: IF (RawR3)\n"));
1174	return false;
1175	}
1176
1177	if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1178	{
1179	STAM_COUNTER_INC(&gStatRefuseWP0);
1180	Log2(("raw mode refused: CR0.WP + RawR0\n"));
1181	return false;
1182	}
1183	}
1184	else
1185	{
1186	if (!EMIsRawRing0Enabled(env->pVM))
1187	return false;
1188
1189	// Let's start with pure 32 bits ring 0 code first
1190	if ((fFlags & (HF_SS32_MASK \| HF_CS32_MASK)) != (HF_SS32_MASK \| HF_CS32_MASK))
1191	{
1192	STAM_COUNTER_INC(&gStatRefuseCode16);
1193	Log2(("raw r0 mode refused: HF_[S\|C]S32_MASK fFlags=%#x\n", fFlags));
1194	return false;
1195	}
1196
1197	// Only R0
1198	if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1199	{
1200	STAM_COUNTER_INC(&gStatRefuseRing1or2);
1201	Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1202	return false;
1203	}
1204
1205	if (!(u32CR0 & CR0_WP_MASK))
1206	{
1207	STAM_COUNTER_INC(&gStatRefuseWP0);
1208	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1209	return false;
1210	}
1211
1212	if (PATMIsPatchGCAddr(env->pVM, eip))
1213	{
1214	Log2(("raw r0 mode forced: patch code\n"));
1215	*pExceptionIndex = EXCP_EXECUTE_RAW;
1216	return true;
1217	}
1218
1219	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1220	if (!(env->eflags & IF_MASK))
1221	{
1222	STAM_COUNTER_INC(&gStatRefuseIF0);
1223	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1224	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1225	return false;
1226	}
1227	#endif
1228
1229	env->state \|= CPU_RAW_RING0;
1230	}
1231
1232	/*
1233	* Don't reschedule the first time we're called, because there might be
1234	* special reasons why we're here that is not covered by the above checks.
1235	*/
1236	if (env->pVM->rem.s.cCanExecuteRaw == 1)
1237	{
1238	Log2(("raw mode refused: first scheduling\n"));
1239	STAM_COUNTER_INC(&gStatRefuseCanExecute);
1240	return false;
1241	}
1242
1243	Assert(PGMPhysIsA20Enabled(env->pVM));
1244	*pExceptionIndex = EXCP_EXECUTE_RAW;
1245	return true;
1246	}
1247
1248
1249	/**
1250	* Fetches a code byte.
1251	*
1252	* @returns Success indicator (bool) for ease of use.
1253	* @param env The CPU environment structure.
1254	* @param GCPtrInstr Where to fetch code.
1255	* @param pu8Byte Where to store the byte on success
1256	*/
1257	bool remR3GetOpcode(CPUState env, RTGCPTR GCPtrInstr, uint8_t pu8Byte)
1258	{
1259	int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1260	if (VBOX_SUCCESS(rc))
1261	return true;
1262	return false;
1263	}
1264
1265
1266	/**
1267	* Flush (or invalidate if you like) page table/dir entry.
1268	*
1269	* (invlpg instruction; tlb_flush_page)
1270	*
1271	* @param env Pointer to cpu environment.
1272	* @param GCPtr The virtual address which page table/dir entry should be invalidated.
1273	*/
1274	void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1275	{
1276	PVM pVM = env->pVM;
1277
1278	/*
1279	* When we're replaying invlpg instructions or restoring a saved
1280	* state we disable this path.
1281	*/
1282	if (pVM->rem.s.fIgnoreInvlPg)
1283	return;
1284	Log(("remR3FlushPage: GCPtr=%VGv\n", GCPtr));
1285
1286	//RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1287
1288	/*
1289	* Update the control registers before calling PGMFlushPage.
1290	*/
1291	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1292	pCtx->cr0 = env->cr[0];
1293	pCtx->cr3 = env->cr[3];
1294	pCtx->cr4 = env->cr[4];
1295
1296	/*
1297	* Let PGM do the rest.
1298	*/
1299	int rc = PGMInvalidatePage(pVM, GCPtr);
1300	if (VBOX_FAILURE(rc))
1301	{
1302	AssertMsgFailed(("remR3FlushPage %x %x %x %d failed!!\n", GCPtr));
1303	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1304	}
1305	//RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1306	}
1307
1308	/**
1309	* Set page table/dir entry. (called from tlb_set_page)
1310	*
1311	* @param env Pointer to cpu environment.
1312	*/
1313	void remR3SetPage(CPUState env, CPUTLBEntry pRead, CPUTLBEntry *pWrite, int prot, int is_user)
1314	{
1315	uint32_t virt_addr, addend;
1316
1317	Log2(("tlb_set_page_raw read (%x-%x) write (%x-%x) prot %x is_user %d\n", pRead->address, pRead->addend, pWrite->address, pWrite->addend, prot, is_user));
1318
1319	if (prot & PAGE_WRITE)
1320	{
1321	addend = pWrite->addend;
1322	virt_addr = pWrite->address;
1323	}
1324	else
1325	if (prot & PAGE_READ)
1326	{
1327	addend = pRead->addend;
1328	virt_addr = pRead->address;
1329	}
1330	else
1331	{
1332	// Should never happen!
1333	AssertMsgFailed(("tlb_set_page_raw unexpected protection flags %x\n", prot));
1334	return;
1335	}
1336
1337	// Clear IO_* flags (TODO: are they actually useful for us??)
1338	virt_addr &= ~0xFFF;
1339
1340	/*
1341	* Update the control registers before calling PGMFlushPage.
1342	*/
1343	PCPUMCTX pCtx = (PCPUMCTX)env->pVM->rem.s.pCtx;
1344	pCtx->cr0 = env->cr[0];
1345	pCtx->cr3 = env->cr[3];
1346	pCtx->cr4 = env->cr[4];
1347
1348	/*
1349	* Let PGM do the rest.
1350	*/
1351	int rc = PGMInvalidatePage(env->pVM, (RTGCPTR)virt_addr);
1352	if (VBOX_FAILURE(rc))
1353	{
1354	AssertMsgFailed(("RAWEx_SetPageEntry %x %x %d failed!!\n", virt_addr, prot, is_user));
1355	VM_FF_SET(env->pVM, VM_FF_PGM_SYNC_CR3);
1356	}
1357	}
1358
1359	/**
1360	* Called from tlb_protect_code in order to write monitor a code page.
1361	*
1362	* @param env Pointer to the CPU environment.
1363	* @param GCPtr Code page to monitor
1364	*/
1365	void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1366	{
1367	if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1368	&& !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1369	&& (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1370	&& !(env->eflags & VM_MASK) /* no V86 mode */
1371	&& !HWACCMIsEnabled(env->pVM))
1372	CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1373	}
1374
1375	/**
1376	* Called when the CPU is initialized, any of the CRx registers are changed or
1377	* when the A20 line is modified.
1378	*
1379	* @param env Pointer to the CPU environment.
1380	* @param fGlobal Set if the flush is global.
1381	*/
1382	void remR3FlushTLB(CPUState *env, bool fGlobal)
1383	{
1384	PVM pVM = env->pVM;
1385
1386	/*
1387	* When we're replaying invlpg instructions or restoring a saved
1388	* state we disable this path.
1389	*/
1390	if (pVM->rem.s.fIgnoreCR3Load)
1391	return;
1392
1393	/*
1394	* The caller doesn't check cr4, so we have to do that for ourselves.
1395	*/
1396	if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1397	fGlobal = true;
1398	Log(("remR3FlushTLB: CR0=%VGp CR3=%VGp CR4=%VGp %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1399
1400	/*
1401	* Update the control registers before calling PGMR3FlushTLB.
1402	*/
1403	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1404	pCtx->cr0 = env->cr[0];
1405	pCtx->cr3 = env->cr[3];
1406	pCtx->cr4 = env->cr[4];
1407
1408	/*
1409	* Let PGM do the rest.
1410	*/
1411	PGMFlushTLB(pVM, env->cr[3], fGlobal);
1412	}
1413
1414
1415	/**
1416	* Called when any of the cr0, cr4 or efer registers is updated.
1417	*
1418	* @param env Pointer to the CPU environment.
1419	*/
1420	void remR3ChangeCpuMode(CPUState *env)
1421	{
1422	int rc;
1423	PVM pVM = env->pVM;
1424
1425	/*
1426	* When we're replaying loads or restoring a saved
1427	* state this path is disabled.
1428	*/
1429	if (pVM->rem.s.fIgnoreCpuMode)
1430	return;
1431
1432	/*
1433	* Update the control registers before calling PGMR3ChangeMode()
1434	* as it may need to map whatever cr3 is pointing to.
1435	*/
1436	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1437	pCtx->cr0 = env->cr[0];
1438	pCtx->cr3 = env->cr[3];
1439	pCtx->cr4 = env->cr[4];
1440
1441	#ifdef TARGET_X86_64
1442	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1443	if (rc != VINF_SUCCESS)
1444	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], env->efer, rc);
1445	#else
1446	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1447	if (rc != VINF_SUCCESS)
1448	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], 0LL, rc);
1449	#endif
1450	}
1451
1452
1453	/**
1454	* Called from compiled code to run dma.
1455	*
1456	* @param env Pointer to the CPU environment.
1457	*/
1458	void remR3DmaRun(CPUState *env)
1459	{
1460	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1461	PDMR3DmaRun(env->pVM);
1462	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1463	}
1464
1465	/**
1466	* Called from compiled code to schedule pending timers in VMM
1467	*
1468	* @param env Pointer to the CPU environment.
1469	*/
1470	void remR3TimersRun(CPUState *env)
1471	{
1472	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1473	remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1474	TMR3TimerQueuesDo(env->pVM);
1475	remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1476	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1477	}
1478
1479	/**
1480	* Record trap occurance
1481	*
1482	* @returns VBox status code
1483	* @param env Pointer to the CPU environment.
1484	* @param uTrap Trap nr
1485	* @param uErrorCode Error code
1486	* @param pvNextEIP Next EIP
1487	*/
1488	int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1489	{
1490	PVM pVM = (PVM)env->pVM;
1491	#ifdef VBOX_WITH_STATISTICS
1492	static STAMCOUNTER aStatTrap[255];
1493	static bool aRegisters[ELEMENTS(aStatTrap)];
1494	#endif
1495
1496	#ifdef VBOX_WITH_STATISTICS
1497	if (uTrap < 255)
1498	{
1499	if (!aRegisters[uTrap])
1500	{
1501	aRegisters[uTrap] = true;
1502	char szStatName[64];
1503	RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1504	STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1505	}
1506	STAM_COUNTER_INC(&aStatTrap[uTrap]);
1507	}
1508	#endif
1509	Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1510	if(uTrap < 0x20)
1511	{
1512	remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1513
1514	if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 128)
1515	{
1516	LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1517	remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1518	return VERR_REM_TOO_MANY_TRAPS;
1519	}
1520	if(pVM->rem.s.uPendingException != uTrap \|\| pVM->rem.s.uPendingExcptEIP != env->eip \|\| pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1521	pVM->rem.s.cPendingExceptions = 1;
1522	pVM->rem.s.uPendingException = uTrap;
1523	pVM->rem.s.uPendingExcptEIP = env->eip;
1524	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1525	}
1526	else
1527	{
1528	pVM->rem.s.cPendingExceptions = 0;
1529	pVM->rem.s.uPendingException = uTrap;
1530	pVM->rem.s.uPendingExcptEIP = env->eip;
1531	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1532	}
1533	return VINF_SUCCESS;
1534	}
1535
1536	/*
1537	* Clear current active trap
1538	*
1539	* @param pVM VM Handle.
1540	*/
1541	void remR3TrapClear(PVM pVM)
1542	{
1543	pVM->rem.s.cPendingExceptions = 0;
1544	pVM->rem.s.uPendingException = 0;
1545	pVM->rem.s.uPendingExcptEIP = 0;
1546	pVM->rem.s.uPendingExcptCR2 = 0;
1547	}
1548
1549
1550	/**
1551	* Syncs the internal REM state with the VM.
1552	*
1553	* This must be called before REMR3Run() is invoked whenever when the REM
1554	* state is not up to date. Calling it several times in a row is not
1555	* permitted.
1556	*
1557	* @returns VBox status code.
1558	*
1559	* @param pVM VM Handle.
1560	*
1561	* @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1562	* no do this since the majority of the callers don't want any unnecessary of events
1563	* pending that would immediatly interrupt execution.
1564	*/
1565	REMR3DECL(int) REMR3State(PVM pVM)
1566	{
1567	Assert(!pVM->rem.s.fInREM);
1568	Log2(("REMR3State:\n"));
1569	STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1570	register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1571	register unsigned fFlags;
1572
1573	/*
1574	* Copy the registers which requires no special handling.
1575	*/
1576	Assert(R_EAX == 0);
1577	pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1578	Assert(R_ECX == 1);
1579	pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1580	Assert(R_EDX == 2);
1581	pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1582	Assert(R_EBX == 3);
1583	pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1584	Assert(R_ESP == 4);
1585	pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1586	Assert(R_EBP == 5);
1587	pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1588	Assert(R_ESI == 6);
1589	pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1590	Assert(R_EDI == 7);
1591	pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1592	pVM->rem.s.Env.eip = pCtx->eip;
1593
1594	pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1595
1596	pVM->rem.s.Env.cr[2] = pCtx->cr2;
1597
1598	/** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1599	pVM->rem.s.Env.dr[0] = pCtx->dr0;
1600	pVM->rem.s.Env.dr[1] = pCtx->dr1;
1601	pVM->rem.s.Env.dr[2] = pCtx->dr2;
1602	pVM->rem.s.Env.dr[3] = pCtx->dr3;
1603	pVM->rem.s.Env.dr[4] = pCtx->dr4;
1604	pVM->rem.s.Env.dr[5] = pCtx->dr5;
1605	pVM->rem.s.Env.dr[6] = pCtx->dr6;
1606	pVM->rem.s.Env.dr[7] = pCtx->dr7;
1607
1608	/*
1609	* Replay invlpg?
1610	*/
1611	if (pVM->rem.s.cInvalidatedPages)
1612	{
1613	pVM->rem.s.fIgnoreInvlPg = true;
1614	RTUINT i;
1615	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1616	{
1617	Log2(("REMR3State: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1618	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1619	}
1620	pVM->rem.s.fIgnoreInvlPg = false;
1621	pVM->rem.s.cInvalidatedPages = 0;
1622	}
1623
1624	/*
1625	* Registers which are seldomly changed and require special handling / order when changed.
1626	*/
1627	fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1628	if (fFlags & ( CPUM_CHANGED_CR4 \| CPUM_CHANGED_CR3 \| CPUM_CHANGED_CR0
1629	\| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_TR
1630	\| CPUM_CHANGED_FPU_REM \| CPUM_CHANGED_SYSENTER_MSR))
1631	{
1632	if (fFlags & CPUM_CHANGED_FPU_REM)
1633	save_raw_fp_state(&pVM->rem.s.Env, (uint8_t )&pCtx->fpu); / 'save' is an excellent name. */
1634
1635	if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1636	{
1637	pVM->rem.s.fIgnoreCR3Load = true;
1638	tlb_flush(&pVM->rem.s.Env, true);
1639	pVM->rem.s.fIgnoreCR3Load = false;
1640	}
1641
1642	if (fFlags & CPUM_CHANGED_CR4)
1643	{
1644	pVM->rem.s.fIgnoreCR3Load = true;
1645	pVM->rem.s.fIgnoreCpuMode = true;
1646	cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1647	pVM->rem.s.fIgnoreCpuMode = false;
1648	pVM->rem.s.fIgnoreCR3Load = false;
1649	}
1650
1651	if (fFlags & CPUM_CHANGED_CR0)
1652	{
1653	pVM->rem.s.fIgnoreCR3Load = true;
1654	pVM->rem.s.fIgnoreCpuMode = true;
1655	cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1656	pVM->rem.s.fIgnoreCpuMode = false;
1657	pVM->rem.s.fIgnoreCR3Load = false;
1658	}
1659
1660	if (fFlags & CPUM_CHANGED_CR3)
1661	{
1662	pVM->rem.s.fIgnoreCR3Load = true;
1663	cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1664	pVM->rem.s.fIgnoreCR3Load = false;
1665	}
1666
1667	if (fFlags & CPUM_CHANGED_GDTR)
1668	{
1669	pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1670	pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1671	}
1672
1673	if (fFlags & CPUM_CHANGED_IDTR)
1674	{
1675	pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1676	pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1677	}
1678
1679	if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1680	{
1681	pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1682	pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1683	pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1684	}
1685
1686	if (fFlags & CPUM_CHANGED_LDTR)
1687	{
1688	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1689	{
1690	pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1691	pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u32Base;
1692	pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1693	pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1694	}
1695	else
1696	sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1697	}
1698
1699	if (fFlags & CPUM_CHANGED_TR)
1700	{
1701	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1702	{
1703	pVM->rem.s.Env.tr.selector = pCtx->tr;
1704	pVM->rem.s.Env.tr.base = pCtx->trHid.u32Base;
1705	pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1706	pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1707	}
1708	else
1709	sync_tr(&pVM->rem.s.Env, pCtx->tr);
1710
1711	/** @note do_interrupt will fault if the busy flag is still set.... */
1712	pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1713	}
1714	}
1715
1716	/*
1717	* Update selector registers.
1718	* This must be done after we've synced gdt, ldt and crX registers
1719	* since we're reading the GDT/LDT om sync_seg. This will happen with
1720	* saved state which takes a quick dip into rawmode for instance.
1721	*/
1722	/*
1723	* Stack; Note first check this one as the CPL might have changed. The
1724	* wrong CPL can cause QEmu to raise an exception in sync_seg!!
1725	*/
1726
1727	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1728	{
1729	/* The hidden selector registers are valid in the CPU context. */
1730	/** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1731
1732	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1733	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1734	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1735	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1736	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1737	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1738
1739	/* Set current CPL. */
1740	if (pCtx->eflags.Bits.u1VM == 1)
1741	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1742	else
1743	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1744	}
1745	else
1746	{
1747	/* In 'normal' raw mode we don't have access to the hidden selector registers. */
1748	if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1749	{
1750	Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1751
1752	cpu_x86_set_cpl(&pVM->rem.s.Env, (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & 3));
1753	sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1754	#ifdef VBOX_WITH_STATISTICS
1755	if (pVM->rem.s.Env.segs[R_SS].newselector)
1756	{
1757	STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1758	}
1759	#endif
1760	}
1761	else
1762	pVM->rem.s.Env.segs[R_SS].newselector = 0;
1763
1764	if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1765	{
1766	Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1767	sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1768	#ifdef VBOX_WITH_STATISTICS
1769	if (pVM->rem.s.Env.segs[R_ES].newselector)
1770	{
1771	STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1772	}
1773	#endif
1774	}
1775	else
1776	pVM->rem.s.Env.segs[R_ES].newselector = 0;
1777
1778	if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1779	{
1780	Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1781	sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1782	#ifdef VBOX_WITH_STATISTICS
1783	if (pVM->rem.s.Env.segs[R_CS].newselector)
1784	{
1785	STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1786	}
1787	#endif
1788	}
1789	else
1790	pVM->rem.s.Env.segs[R_CS].newselector = 0;
1791
1792	if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1793	{
1794	Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1795	sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1796	#ifdef VBOX_WITH_STATISTICS
1797	if (pVM->rem.s.Env.segs[R_DS].newselector)
1798	{
1799	STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1800	}
1801	#endif
1802	}
1803	else
1804	pVM->rem.s.Env.segs[R_DS].newselector = 0;
1805
1806	/** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1807	* be the same but not the base/limit. */
1808	if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1809	{
1810	Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1811	sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1812	#ifdef VBOX_WITH_STATISTICS
1813	if (pVM->rem.s.Env.segs[R_FS].newselector)
1814	{
1815	STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1816	}
1817	#endif
1818	}
1819	else
1820	pVM->rem.s.Env.segs[R_FS].newselector = 0;
1821
1822	if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1823	{
1824	Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1825	sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1826	#ifdef VBOX_WITH_STATISTICS
1827	if (pVM->rem.s.Env.segs[R_GS].newselector)
1828	{
1829	STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1830	}
1831	#endif
1832	}
1833	else
1834	pVM->rem.s.Env.segs[R_GS].newselector = 0;
1835	}
1836
1837	/*
1838	* Check for traps.
1839	*/
1840	pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
1841	bool fIsSoftwareInterrupt;
1842	uint8_t u8TrapNo;
1843	int rc = TRPMQueryTrap(pVM, &u8TrapNo, &fIsSoftwareInterrupt);
1844	if (VBOX_SUCCESS(rc))
1845	{
1846	#ifdef DEBUG
1847	if (u8TrapNo == 0x80)
1848	{
1849	remR3DumpLnxSyscall(pVM);
1850	remR3DumpOBsdSyscall(pVM);
1851	}
1852	#endif
1853
1854	pVM->rem.s.Env.exception_index = u8TrapNo;
1855	if (!fIsSoftwareInterrupt)
1856	{
1857	pVM->rem.s.Env.exception_is_int = 0;
1858	pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
1859	}
1860	else
1861	{
1862	/*
1863	* The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
1864	* We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
1865	* for int03 and into.
1866	*/
1867	pVM->rem.s.Env.exception_is_int = 1;
1868	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 2;
1869	/* int 3 may be generated by one-byte 0xcc */
1870	if (u8TrapNo == 3)
1871	{
1872	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xcc)
1873	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1874	}
1875	/* int 4 may be generated by one-byte 0xce */
1876	else if (u8TrapNo == 4)
1877	{
1878	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xce)
1879	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1880	}
1881	}
1882
1883	/* get error code and cr2 if needed. */
1884	switch (u8TrapNo)
1885	{
1886	case 0x0e:
1887	pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
1888	/* fallthru */
1889	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
1890	pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
1891	break;
1892
1893	case 0x11: case 0x08:
1894	default:
1895	pVM->rem.s.Env.error_code = 0;
1896	break;
1897	}
1898
1899	/*
1900	* We can now reset the active trap since the recompiler is gonna have a go at it.
1901	*/
1902	rc = TRPMResetTrap(pVM);
1903	AssertRC(rc);
1904	Log2(("REMR3State: trap=%02x errcd=%VGv cr2=%VGv nexteip=%VGv%s\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.error_code,
1905	pVM->rem.s.Env.cr[2], pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
1906	}
1907
1908	/*
1909	* Clear old interrupt request flags; Check for pending hardware interrupts.
1910	* (See @remark for why we don't check for other FFs.)
1911	*/
1912	pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER);
1913	if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
1914	\|\| VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
1915	pVM->rem.s.Env.interrupt_request \|= CPU_INTERRUPT_HARD;
1916
1917	/*
1918	* We're now in REM mode.
1919	*/
1920	pVM->rem.s.fInREM = true;
1921	pVM->rem.s.cCanExecuteRaw = 0;
1922	STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
1923	Log2(("REMR3State: returns VINF_SUCCESS\n"));
1924	return VINF_SUCCESS;
1925	}
1926
1927
1928	/**
1929	* Syncs back changes in the REM state to the the VM state.
1930	*
1931	* This must be called after invoking REMR3Run().
1932	* Calling it several times in a row is not permitted.
1933	*
1934	* @returns VBox status code.
1935	*
1936	* @param pVM VM Handle.
1937	*/
1938	REMR3DECL(int) REMR3StateBack(PVM pVM)
1939	{
1940	Log2(("REMR3StateBack:\n"));
1941	Assert(pVM->rem.s.fInREM);
1942	STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
1943	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
1944
1945	/*
1946	* Copy back the registers.
1947	* This is done in the order they are declared in the CPUMCTX structure.
1948	*/
1949
1950	/** @todo FOP */
1951	/** @todo FPUIP */
1952	/** @todo CS */
1953	/** @todo FPUDP */
1954	/** @todo DS */
1955	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
1956	pCtx->fpu.MXCSR = 0;
1957	pCtx->fpu.MXCSR_MASK = 0;
1958
1959	/** @todo check if FPU/XMM was actually used in the recompiler */
1960	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
1961	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
1962
1963	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
1964	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
1965	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
1966	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
1967	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
1968	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
1969	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
1970
1971	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
1972	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
1973
1974	#ifdef VBOX_WITH_STATISTICS
1975	if (pVM->rem.s.Env.segs[R_SS].newselector)
1976	{
1977	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
1978	}
1979	if (pVM->rem.s.Env.segs[R_GS].newselector)
1980	{
1981	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
1982	}
1983	if (pVM->rem.s.Env.segs[R_FS].newselector)
1984	{
1985	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
1986	}
1987	if (pVM->rem.s.Env.segs[R_ES].newselector)
1988	{
1989	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
1990	}
1991	if (pVM->rem.s.Env.segs[R_DS].newselector)
1992	{
1993	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
1994	}
1995	if (pVM->rem.s.Env.segs[R_CS].newselector)
1996	{
1997	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
1998	}
1999	#endif
2000	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2001	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2002	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2003	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2004	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2005
2006	pCtx->eip = pVM->rem.s.Env.eip;
2007	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2008
2009	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2010	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2011	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2012	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2013
2014	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2015	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2016	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2017	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2018	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2019	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2020	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2021	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2022
2023	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2024	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2025	{
2026	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2027	STAM_COUNTER_INC(&gStatREMGDTChange);
2028	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2029	}
2030
2031	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2032	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2033	{
2034	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2035	STAM_COUNTER_INC(&gStatREMIDTChange);
2036	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2037	}
2038
2039	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2040	{
2041	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2042	STAM_COUNTER_INC(&gStatREMLDTRChange);
2043	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2044	}
2045	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2046	{
2047	pCtx->tr = pVM->rem.s.Env.tr.selector;
2048	STAM_COUNTER_INC(&gStatREMTRChange);
2049	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2050	}
2051
2052	/** @todo These values could still be out of sync! */
2053	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2054	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2055	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2056	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2057
2058	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2059	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2060	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2061
2062	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2063	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2064	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2065
2066	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2067	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2068	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2069
2070	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2071	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2072	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2073
2074	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2075	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2076	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2077
2078	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2079	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2080	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2081
2082	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2083	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2084	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2085
2086	/* Sysenter MSR */
2087	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2088	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2089	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2090
2091	remR3TrapClear(pVM);
2092
2093	/*
2094	* Check for traps.
2095	*/
2096	if ( pVM->rem.s.Env.exception_index >= 0
2097	&& pVM->rem.s.Env.exception_index < 256)
2098	{
2099	Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2100	int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int);
2101	AssertRC(rc);
2102	switch (pVM->rem.s.Env.exception_index)
2103	{
2104	case 0x0e:
2105	TRPMSetFaultAddress(pVM, pCtx->cr2);
2106	/* fallthru */
2107	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2108	case 0x11: case 0x08: /* 0 */
2109	TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2110	break;
2111	}
2112
2113	}
2114
2115	/*
2116	* We're not longer in REM mode.
2117	*/
2118	pVM->rem.s.fInREM = false;
2119	STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2120	Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2121	return VINF_SUCCESS;
2122	}
2123
2124
2125	/**
2126	* This is called by the disassembler when it wants to update the cpu state
2127	* before for instance doing a register dump.
2128	*/
2129	static void remR3StateUpdate(PVM pVM)
2130	{
2131	Assert(pVM->rem.s.fInREM);
2132	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2133
2134	/*
2135	* Copy back the registers.
2136	* This is done in the order they are declared in the CPUMCTX structure.
2137	*/
2138
2139	/** @todo FOP */
2140	/** @todo FPUIP */
2141	/** @todo CS */
2142	/** @todo FPUDP */
2143	/** @todo DS */
2144	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2145	pCtx->fpu.MXCSR = 0;
2146	pCtx->fpu.MXCSR_MASK = 0;
2147
2148	/** @todo check if FPU/XMM was actually used in the recompiler */
2149	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2150	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2151
2152	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2153	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2154	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2155	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2156	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2157	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2158	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2159
2160	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2161	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2162
2163	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2164	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2165	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2166	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2167	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2168
2169	pCtx->eip = pVM->rem.s.Env.eip;
2170	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2171
2172	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2173	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2174	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2175	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2176
2177	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2178	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2179	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2180	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2181	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2182	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2183	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2184	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2185
2186	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2187	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2188	{
2189	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2190	STAM_COUNTER_INC(&gStatREMGDTChange);
2191	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2192	}
2193
2194	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2195	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2196	{
2197	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2198	STAM_COUNTER_INC(&gStatREMIDTChange);
2199	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2200	}
2201
2202	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2203	{
2204	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2205	STAM_COUNTER_INC(&gStatREMLDTRChange);
2206	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2207	}
2208	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2209	{
2210	pCtx->tr = pVM->rem.s.Env.tr.selector;
2211	STAM_COUNTER_INC(&gStatREMTRChange);
2212	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2213	}
2214
2215	/** @todo These values could still be out of sync! */
2216	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2217	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2218	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2219	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2220
2221	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2222	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2223	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2224
2225	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2226	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2227	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2228
2229	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2230	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2231	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2232
2233	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2234	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2235	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2236
2237	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2238	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2239	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2240
2241	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2242	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2243	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2244
2245	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2246	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2247	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2248
2249	/* Sysenter MSR */
2250	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2251	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2252	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2253	}
2254
2255
2256	/**
2257	* Update the VMM state information if we're currently in REM.
2258	*
2259	* This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2260	* we're currently executing in REM and the VMM state is invalid. This method will of
2261	* course check that we're executing in REM before syncing any data over to the VMM.
2262	*
2263	* @param pVM The VM handle.
2264	*/
2265	REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2266	{
2267	if (pVM->rem.s.fInREM)
2268	remR3StateUpdate(pVM);
2269	}
2270
2271
2272	#undef LOG_GROUP
2273	#define LOG_GROUP LOG_GROUP_REM
2274
2275
2276	/**
2277	* Notify the recompiler about Address Gate 20 state change.
2278	*
2279	* This notification is required since A20 gate changes are
2280	* initialized from a device driver and the VM might just as
2281	* well be in REM mode as in RAW mode.
2282	*
2283	* @param pVM VM handle.
2284	* @param fEnable True if the gate should be enabled.
2285	* False if the gate should be disabled.
2286	*/
2287	REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2288	{
2289	LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2290	VM_ASSERT_EMT(pVM);
2291	cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2292	}
2293
2294
2295	/**
2296	* Replays the invalidated recorded pages.
2297	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2298	*
2299	* @param pVM VM handle.
2300	*/
2301	REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2302	{
2303	VM_ASSERT_EMT(pVM);
2304
2305	/*
2306	* Sync the required registers.
2307	*/
2308	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2309	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2310	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2311	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2312
2313	/*
2314	* Replay the flushes.
2315	*/
2316	pVM->rem.s.fIgnoreInvlPg = true;
2317	RTUINT i;
2318	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2319	{
2320	Log2(("REMR3ReplayInvalidatedPages: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2321	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2322	}
2323	pVM->rem.s.fIgnoreInvlPg = false;
2324	pVM->rem.s.cInvalidatedPages = 0;
2325	}
2326
2327
2328	/**
2329	* Replays the invalidated recorded pages.
2330	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2331	*
2332	* @param pVM VM handle.
2333	*/
2334	REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2335	{
2336	LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2337	VM_ASSERT_EMT(pVM);
2338
2339	/*
2340	* Replay the flushes.
2341	*/
2342	RTUINT i;
2343	const RTUINT c = pVM->rem.s.cHandlerNotifications;
2344	pVM->rem.s.cHandlerNotifications = 0;
2345	for (i = 0; i < c; i++)
2346	{
2347	PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2348	switch (pRec->enmKind)
2349	{
2350	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2351	REMR3NotifyHandlerPhysicalRegister(pVM,
2352	pRec->u.PhysicalRegister.enmType,
2353	pRec->u.PhysicalRegister.GCPhys,
2354	pRec->u.PhysicalRegister.cb,
2355	pRec->u.PhysicalRegister.fHasHCHandler);
2356	break;
2357
2358	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2359	REMR3NotifyHandlerPhysicalDeregister(pVM,
2360	pRec->u.PhysicalDeregister.enmType,
2361	pRec->u.PhysicalDeregister.GCPhys,
2362	pRec->u.PhysicalDeregister.cb,
2363	pRec->u.PhysicalDeregister.fHasHCHandler,
2364	pRec->u.PhysicalDeregister.pvHCPtr);
2365	break;
2366
2367	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2368	REMR3NotifyHandlerPhysicalModify(pVM,
2369	pRec->u.PhysicalModify.enmType,
2370	pRec->u.PhysicalModify.GCPhysOld,
2371	pRec->u.PhysicalModify.GCPhysNew,
2372	pRec->u.PhysicalModify.cb,
2373	pRec->u.PhysicalModify.fHasHCHandler,
2374	pRec->u.PhysicalModify.pvHCPtr);
2375	break;
2376
2377	default:
2378	AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2379	break;
2380	}
2381	}
2382	}
2383
2384
2385	/**
2386	* Notify REM about changed code page.
2387	*
2388	* @returns VBox status code.
2389	* @param pVM VM handle.
2390	* @param pvCodePage Code page address
2391	*/
2392	REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2393	{
2394	int rc;
2395	RTGCPHYS PhysGC;
2396	uint64_t flags;
2397
2398	VM_ASSERT_EMT(pVM);
2399
2400	/*
2401	* Get the physical page address.
2402	*/
2403	rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2404	if (rc == VINF_SUCCESS)
2405	{
2406	/*
2407	* Sync the required registers and flush the whole page.
2408	* (Easier to do the whole page than notifying it about each physical
2409	* byte that was changed.
2410	*/
2411	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2412	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2413	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2414	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2415
2416	tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2417	}
2418	return VINF_SUCCESS;
2419	}
2420
2421	/**
2422	* Notification about a successful MMR3PhysRegister() call.
2423	*
2424	* @param pVM VM handle.
2425	* @param GCPhys The physical address the RAM.
2426	* @param cb Size of the memory.
2427	* @param pvRam The HC address of the RAM.
2428	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2429	*/
2430	REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
2431	{
2432	Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2433	VM_ASSERT_EMT(pVM);
2434
2435	/*
2436	* Validate input - we trust the caller.
2437	*/
2438	Assert(!GCPhys \|\| pvRam);
2439	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2440	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2441	Assert(cb);
2442	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2443
2444	/*
2445	* Base ram?
2446	*/
2447	if (!GCPhys)
2448	{
2449	#ifndef PGM_DYNAMIC_RAM_ALLOC
2450	AssertRelease(!phys_ram_base);
2451	phys_ram_base = pvRam;
2452	#endif
2453	phys_ram_size = cb;
2454	phys_ram_dirty = MMR3HeapAllocZ(pVM, MM_TAG_REM, cb >> PAGE_SHIFT);
2455	AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", cb >> PAGE_SHIFT));
2456	}
2457	#ifndef PGM_DYNAMIC_RAM_ALLOC
2458	AssertRelease(phys_ram_base);
2459	#endif
2460
2461	/*
2462	* Register the ram.
2463	*/
2464	#ifdef PGM_DYNAMIC_RAM_ALLOC
2465	if (!GCPhys)
2466	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_RAM_MISSING);
2467	else
2468	{
2469	uint32_t i;
2470
2471	cpu_register_physical_memory(GCPhys, cb, GCPhys \| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2472
2473	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2474	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2475	{
2476	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2477	{
2478	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2479	pVM->rem.s.aPhysReg[i].cb = cb;
2480	break;
2481	}
2482	}
2483	if (i == pVM->rem.s.cPhysRegistrations)
2484	{
2485	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2486	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2487	pVM->rem.s.aPhysReg[i].cb = cb;
2488	pVM->rem.s.cPhysRegistrations++;
2489	}
2490	}
2491	#else
2492	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvRam - (uintptr_t)phys_ram_base)
2493	\| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2494	#endif
2495	}
2496
2497
2498	/**
2499	* Notification about a successful PGMR3PhysRegisterChunk() call.
2500	*
2501	* @param pVM VM handle.
2502	* @param GCPhys The physical address the RAM.
2503	* @param cb Size of the memory.
2504	* @param pvRam The HC address of the RAM.
2505	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2506	*/
2507	REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2508	{
2509	uint32_t idx;
2510
2511	Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2512	VM_ASSERT_EMT(pVM);
2513
2514	/*
2515	* Validate input - we trust the caller.
2516	*/
2517	Assert(pvRam);
2518	Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2519	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2520	Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2521	Assert(fFlags == 0 /* normal RAM */);
2522
2523	if (!pVM->rem.s.paHCVirtToGCPhys)
2524	{
2525	uint32_t size = (_4G >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(REMCHUNKINFO);
2526
2527	Assert(phys_ram_size);
2528
2529	pVM->rem.s.paHCVirtToGCPhys = (PREMCHUNKINFO)MMR3HeapAllocZ(pVM, MM_TAG_REM, size);
2530	pVM->rem.s.paGCPhysToHCVirt = (RTHCPTR)MMR3HeapAllocZ(pVM, MM_TAG_REM, (phys_ram_size >> PGM_DYNAMIC_CHUNK_SHIFT)*sizeof(RTHCPTR));
2531	}
2532	pVM->rem.s.paGCPhysToHCVirt[GCPhys >> PGM_DYNAMIC_CHUNK_SHIFT] = pvRam;
2533
2534	idx = (pvRam >> PGM_DYNAMIC_CHUNK_SHIFT);
2535	if (!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1)
2536	{
2537	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1 = pvRam;
2538	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 = GCPhys;
2539	}
2540	else
2541	{
2542	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2);
2543	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2 = pvRam;
2544	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 = GCPhys;
2545	}
2546	/* Does the region spawn two chunks? */
2547	if (pvRam & PGM_DYNAMIC_CHUNK_OFFSET_MASK)
2548	{
2549	if (!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1)
2550	{
2551	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1 = pvRam;
2552	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys1 = GCPhys;
2553	}
2554	else
2555	{
2556	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2);
2557	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2 = pvRam;
2558	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys2 = GCPhys;
2559	}
2560	}
2561	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2562	}
2563
2564	/**
2565	* Convert GC physical address to HC virt
2566	*
2567	* @returns The HC virt address corresponding to addr.
2568	* @param env The cpu environment.
2569	* @param addr The physical address.
2570	*/
2571	void remR3GCPhys2HCVirt(void env, target_ulong addr)
2572	{
2573	#ifdef PGM_DYNAMIC_RAM_ALLOC
2574	PVM pVM = ((CPUState *)env)->pVM;
2575	uint32_t i;
2576
2577	/* lookup in pVM->rem.s.aPhysReg array first (for ROM range(s) inside the guest's RAM) */
2578	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2579	{
2580	uint32_t off = addr - pVM->rem.s.aPhysReg[i].GCPhys;
2581	if (off < pVM->rem.s.aPhysReg[i].cb)
2582	{
2583	Log2(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].HCVirt + off));
2584	return (void *)(pVM->rem.s.aPhysReg[i].HCVirt + off);
2585	}
2586	}
2587	AssertMsg(addr < phys_ram_size, ("remR3GCPhys2HCVirt: unknown physical address %x\n", addr));
2588	Log2(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK)));
2589	return (void *)(pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2590	#else
2591	return phys_ram_base + addr;
2592	#endif
2593	}
2594
2595	/**
2596	* Convert GC physical address to HC virt
2597	*
2598	* @returns The HC virt address corresponding to addr.
2599	* @param env The cpu environment.
2600	* @param addr The physical address.
2601	*/
2602	target_ulong remR3HCVirt2GCPhys(void env, void addr)
2603	{
2604	#ifdef PGM_DYNAMIC_RAM_ALLOC
2605	PVM pVM = ((CPUState *)env)->pVM;
2606	RTHCUINTPTR HCVirt = (RTHCUINTPTR)addr;
2607	uint32_t idx = (HCVirt >> PGM_DYNAMIC_CHUNK_SHIFT);
2608	RTHCUINTPTR off;
2609	RTUINT i;
2610
2611	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1;
2612
2613	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1
2614	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2615	{
2616	Log2(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off));
2617	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off;
2618	}
2619
2620	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2;
2621	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2
2622	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2623	{
2624	Log2(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off));
2625	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off;
2626	}
2627
2628	/* Must be externally registered RAM/ROM range */
2629	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2630	{
2631	uint32_t off = HCVirt - pVM->rem.s.aPhysReg[i].HCVirt;
2632	if (off < pVM->rem.s.aPhysReg[i].cb)
2633	{
2634	Log2(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].GCPhys + off));
2635	return pVM->rem.s.aPhysReg[i].GCPhys + off;
2636	}
2637	}
2638	AssertReleaseMsgFailed(("No translation for physical address %VHv???\n", addr));
2639	return 0;
2640	#else
2641	return (target_ulong)addr - (target_ulong)phys_ram_base;
2642	#endif
2643	}
2644
2645	/**
2646	* Grows dynamically allocated guest RAM.
2647	* Will raise a fatal error if the operation fails.
2648	*
2649	* @param physaddr The physical address.
2650	*/
2651	void remR3GrowDynRange(unsigned long physaddr)
2652	{
2653	int rc;
2654	PVM pVM = cpu_single_env->pVM;
2655
2656	Log(("remR3GrowDynRange %VGp\n", physaddr));
2657	rc = PGM3PhysGrowRange(pVM, (RTGCPHYS)physaddr);
2658	if (VBOX_SUCCESS(rc))
2659	return;
2660
2661	LogRel(("\nUnable to allocate guest RAM chunk at %VGp\n", physaddr));
2662	cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %VGp\n", physaddr);
2663	AssertFatalFailed();
2664	}
2665
2666	/**
2667	* Notification about a successful MMR3PhysRomRegister() call.
2668	*
2669	* @param pVM VM handle.
2670	* @param GCPhys The physical address of the ROM.
2671	* @param cb The size of the ROM.
2672	* @param pvCopy Pointer to the ROM copy.
2673	*/
2674	REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy)
2675	{
2676	#ifdef PGM_DYNAMIC_RAM_ALLOC
2677	uint32_t i;
2678	#endif
2679	Log(("REMR3NotifyPhysRomRegister: GCPhys=%VGp cb=%d pvCopy=%p\n", GCPhys, cb, pvCopy));
2680	VM_ASSERT_EMT(pVM);
2681
2682	/*
2683	* Validate input - we trust the caller.
2684	*/
2685	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2686	Assert(cb);
2687	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2688	Assert(pvCopy);
2689	Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2690
2691	/*
2692	* Register the rom.
2693	*/
2694	#ifdef PGM_DYNAMIC_RAM_ALLOC
2695	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_ROM);
2696	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2697	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2698	{
2699	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2700	{
2701	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2702	pVM->rem.s.aPhysReg[i].cb = cb;
2703	break;
2704	}
2705	}
2706	if (i == pVM->rem.s.cPhysRegistrations)
2707	{
2708	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2709	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2710	pVM->rem.s.aPhysReg[i].cb = cb;
2711	pVM->rem.s.cPhysRegistrations++;
2712	}
2713	#else
2714	AssertRelease(phys_ram_base);
2715	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvCopy - (uintptr_t)phys_ram_base) \| IO_MEM_ROM);
2716	#endif
2717	Log2(("%.64Vhxd\n", (char *)pvCopy + cb - 64));
2718	}
2719
2720
2721	/**
2722	* Notification about a successful MMR3PhysRegister() call.
2723	*
2724	* @param pVM VM Handle.
2725	* @param GCPhys Start physical address.
2726	* @param cb The size of the range.
2727	*/
2728	REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2729	{
2730	LogFlow(("REMR3NotifyPhysReserve: GCPhys=%VGp cb=%d\n", GCPhys, cb));
2731	VM_ASSERT_EMT(pVM);
2732
2733	/*
2734	* Validate input - we trust the caller.
2735	*/
2736	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2737	Assert(cb);
2738	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2739
2740	/*
2741	* Unassigning the memory.
2742	*/
2743	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2744	}
2745
2746
2747	/**
2748	* Notification about a successful PGMR3HandlerPhysicalRegister() call.
2749	*
2750	* @param pVM VM Handle.
2751	* @param enmType Handler type.
2752	* @param GCPhys Handler range address.
2753	* @param cb Size of the handler range.
2754	* @param fHasHCHandler Set if the handler has a HC callback function.
2755	*
2756	* @remark MMR3PhysRomRegister assumes that this function will not apply the
2757	* Handler memory type to memory which has no HC handler.
2758	*/
2759	REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2760	{
2761	LogFlow(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d\n",
2762	enmType, GCPhys, cb, fHasHCHandler));
2763	VM_ASSERT_EMT(pVM);
2764	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2765	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2766
2767	if (pVM->rem.s.cHandlerNotifications)
2768	REMR3ReplayHandlerNotifications(pVM);
2769
2770	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2771	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2772	else if (fHasHCHandler)
2773	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2774	}
2775
2776
2777	/**
2778	* Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2779	*
2780	* @param pVM VM Handle.
2781	* @param enmType Handler type.
2782	* @param GCPhys Handler range address.
2783	* @param cb Size of the handler range.
2784	* @param fHasHCHandler Set if the handler has a HC callback function.
2785	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2786	*/
2787	REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2788	{
2789	LogFlow(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p RAM=%08x\n",
2790	enmType, GCPhys, cb, fHasHCHandler, pvHCPtr, MMR3PhysGetRamSize(pVM)));
2791	VM_ASSERT_EMT(pVM);
2792
2793	if (pVM->rem.s.cHandlerNotifications)
2794	REMR3ReplayHandlerNotifications(pVM);
2795
2796	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2797	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2798	else if (fHasHCHandler)
2799	{
2800	if (!pvHCPtr)
2801	{
2802	Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2803	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2804	}
2805	else
2806	{
2807	/* This is not prefect, but it'll do for PD monitoring... */
2808	Assert(cb == PAGE_SIZE);
2809	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2810	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2811	#ifdef PGM_DYNAMIC_RAM_ALLOC
2812	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2813	#else
2814	cpu_register_physical_memory(GCPhys, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2815	#endif
2816	}
2817	}
2818	}
2819
2820
2821	/**
2822	* Notification about a successful PGMR3HandlerPhysicalModify() call.
2823	*
2824	* @param pVM VM Handle.
2825	* @param enmType Handler type.
2826	* @param GCPhysOld Old handler range address.
2827	* @param GCPhysNew New handler range address.
2828	* @param cb Size of the handler range.
2829	* @param fHasHCHandler Set if the handler has a HC callback function.
2830	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2831	*/
2832	REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2833	{
2834	LogFlow(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%VGp GCPhysNew=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p\n",
2835	enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, pvHCPtr));
2836	VM_ASSERT_EMT(pVM);
2837	AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2838
2839	if (pVM->rem.s.cHandlerNotifications)
2840	REMR3ReplayHandlerNotifications(pVM);
2841
2842	if (fHasHCHandler)
2843	{
2844	/*
2845	* Reset the old page.
2846	*/
2847	if (!pvHCPtr)
2848	cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2849	else
2850	{
2851	/* This is not prefect, but it'll do for PD monitoring... */
2852	Assert(cb == PAGE_SIZE);
2853	Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2854	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2855	#ifdef PGM_DYNAMIC_RAM_ALLOC
2856	cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2857	#else
2858	cpu_register_physical_memory(GCPhysOld, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2859	#endif
2860	}
2861
2862	/*
2863	* Update the new page.
2864	*/
2865	Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2866	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2867	cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2868	}
2869	}
2870
2871
2872	/**
2873	* Checks if we're handling access to this page or not.
2874	*
2875	* @returns true if we're trapping access.
2876	* @returns false if we aren't.
2877	* @param pVM The VM handle.
2878	* @param GCPhys The physical address.
2879	*
2880	* @remark This function will only work correctly in VBOX_STRICT builds!
2881	*/
2882	REMDECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
2883	{
2884	#ifdef VBOX_STRICT
2885	if (pVM->rem.s.cHandlerNotifications)
2886	REMR3ReplayHandlerNotifications(pVM);
2887
2888	unsigned long off = get_phys_page_offset(GCPhys);
2889	return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
2890	\|\| (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
2891	\|\| (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
2892	#else
2893	return false;
2894	#endif
2895	}
2896
2897
2898	/**
2899	* Deals with a rare case in get_phys_addr_code where the code
2900	* is being monitored.
2901	*
2902	* It could also be an MMIO page, in which case we will raise a fatal error.
2903	*
2904	* @returns The physical address corresponding to addr.
2905	* @param env The cpu environment.
2906	* @param addr The virtual address.
2907	* @param pTLBEntry The TLB entry.
2908	*/
2909	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry)
2910	{
2911	PVM pVM = env->pVM;
2912	if ((pTLBEntry->address & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
2913	{
2914	target_ulong ret = pTLBEntry->addend + addr;
2915	AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%VGv address=%VGv addend=%VGp ret=%VGp\n",
2916	(RTGCPTR)addr, (RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, ret);
2917	return ret;
2918	}
2919	LogRel(("\nTrying to execute code with memory type address=%VGv addend=%VGp at %VGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
2920	"*** handlers\n",
2921	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
2922	DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
2923	LogRel(("*** mmio\n"));
2924	DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
2925	LogRel(("*** phys\n"));
2926	DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
2927	cpu_abort(env, "Trying to execute code with memory type address=%VGv addend=%VGp at %VGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
2928	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
2929	AssertFatalFailed();
2930	}
2931
2932	/**
2933	* Read guest RAM and ROM.
2934	*
2935	* @param pbSrcPhys The source address. Relative to guest RAM.
2936	* @param pvDst The destination address.
2937	* @param cb Number of bytes
2938	*/
2939	void remR3PhysReadBytes(uint8_t pbSrcPhys, void pvDst, unsigned cb)
2940	{
2941	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2942
2943	/*
2944	* Calc the physical address ('off') and check that it's within the RAM.
2945	* ROM is accessed this way, even if it's not part of the RAM.
2946	*/
2947	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2948	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2949	if (off < (uintptr_t)phys_ram_size)
2950	PGMPhysRead(cpu_single_env->pVM, (RTGCPHYS)off, pvDst, cb);
2951	else
2952	{
2953	/* ROM range outside physical RAM, HC address passed directly */
2954	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2955	memcpy(pvDst, pbSrcPhys, cb);
2956	}
2957	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2958	}
2959
2960	/** @todo r=bird: s/Byte/U8/ s/Word/U16/ s/Dword/U32/, see MMIO and other functions.
2961	* It could be an idea to inline these wrapper functions... */
2962
2963	/**
2964	* Read guest RAM and ROM.
2965	*
2966	* @param pbSrcPhys The source address. Relative to guest RAM.
2967	*/
2968	uint8_t remR3PhysReadUByte(uint8_t *pbSrcPhys)
2969	{
2970	uint8_t val;
2971
2972	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2973
2974	/*
2975	* Calc the physical address ('off') and check that it's within the RAM.
2976	* ROM is accessed this way, even if it's not part of the RAM.
2977	*/
2978	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2979	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2980	if (off < (uintptr_t)phys_ram_size)
2981	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
2982	else
2983	{
2984	/* ROM range outside physical RAM, HC address passed directly */
2985	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2986	val = *pbSrcPhys;
2987	}
2988	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2989	return val;
2990	}
2991
2992	/**
2993	* Read guest RAM and ROM.
2994	*
2995	* @param pbSrcPhys The source address. Relative to guest RAM.
2996	*/
2997	int8_t remR3PhysReadSByte(uint8_t *pbSrcPhys)
2998	{
2999	int8_t val;
3000
3001	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3002
3003	/*
3004	* Calc the physical address ('off') and check that it's within the RAM.
3005	* ROM is accessed this way, even if it's not part of the RAM.
3006	*/
3007	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3008	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3009	if (off < (uintptr_t)phys_ram_size)
3010	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3011	else
3012	{
3013	/* ROM range outside physical RAM, HC address passed directly */
3014	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3015	val = (int8_t )pbSrcPhys;
3016	}
3017	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3018	return val;
3019	}
3020
3021	/**
3022	* Read guest RAM and ROM.
3023	*
3024	* @param pbSrcPhys The source address. Relative to guest RAM.
3025	*/
3026	uint16_t remR3PhysReadUWord(uint8_t *pbSrcPhys)
3027	{
3028	uint16_t val;
3029
3030	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3031
3032	/*
3033	* Calc the physical address ('off') and check that it's within the RAM.
3034	* ROM is accessed this way, even if it's not part of the RAM.
3035	*/
3036	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3037	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3038	if (off < (uintptr_t)phys_ram_size)
3039	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3040	else
3041	{
3042	/* ROM range outside physical RAM, HC address passed directly */
3043	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3044	val = (uint16_t )pbSrcPhys;
3045	}
3046	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3047	return val;
3048	}
3049
3050	/**
3051	* Read guest RAM and ROM.
3052	*
3053	* @param pbSrcPhys The source address. Relative to guest RAM.
3054	*/
3055	int16_t remR3PhysReadSWord(uint8_t *pbSrcPhys)
3056	{
3057	int16_t val;
3058
3059	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3060
3061	/*
3062	* Calc the physical address ('off') and check that it's within the RAM.
3063	* ROM is accessed this way, even if it's not part of the RAM.
3064	*/
3065	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3066	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3067	if (off < (uintptr_t)phys_ram_size)
3068	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3069	else
3070	{
3071	/* ROM range outside physical RAM, HC address passed directly */
3072	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3073	val = (int16_t )pbSrcPhys;
3074	}
3075	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3076	return val;
3077	}
3078
3079	/**
3080	* Read guest RAM and ROM.
3081	*
3082	* @param pbSrcPhys The source address. Relative to guest RAM.
3083	*/
3084	uint32_t remR3PhysReadULong(uint8_t *pbSrcPhys)
3085	{
3086	uint32_t val;
3087
3088	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3089
3090	/*
3091	* Calc the physical address ('off') and check that it's within the RAM.
3092	* ROM is accessed this way, even if it's not part of the RAM.
3093	*/
3094	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3095	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3096	if (off < (uintptr_t)phys_ram_size)
3097	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3098	else
3099	{
3100	/* ROM range outside physical RAM, HC address passed directly */
3101	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3102	val = (uint32_t )pbSrcPhys;
3103	}
3104	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3105	return val;
3106	}
3107
3108	/**
3109	* Read guest RAM and ROM.
3110	*
3111	* @param pbSrcPhys The source address. Relative to guest RAM.
3112	*/
3113	int32_t remR3PhysReadSLong(uint8_t *pbSrcPhys)
3114	{
3115	int32_t val;
3116
3117	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3118
3119	/*
3120	* Calc the physical address ('off') and check that it's within the RAM.
3121	* ROM is accessed this way, even if it's not part of the RAM.
3122	*/
3123	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3124	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3125	if (off < (uintptr_t)phys_ram_size)
3126	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3127	else
3128	{
3129	/* ROM range outside physical RAM, HC address passed directly */
3130	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3131	val = (int32_t )pbSrcPhys;
3132	}
3133	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3134	return val;
3135	}
3136
3137	/**
3138	* Write guest RAM.
3139	*
3140	* @param pbDstPhys The destination address. Relative to guest RAM.
3141	* @param pvSrc The source address.
3142	* @param cb Number of bytes to write
3143	*/
3144	void remR3PhysWriteBytes(uint8_t pbDstPhys, const void pvSrc, unsigned cb)
3145	{
3146	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3147	/*
3148	* Calc the physical address ('off') and check that it's within the RAM.
3149	*/
3150	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3151	if (off < (uintptr_t)phys_ram_size)
3152	PGMPhysWrite(cpu_single_env->pVM, (RTGCPHYS)off, pvSrc, cb);
3153	else
3154	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, cb));
3155	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3156	}
3157
3158
3159	/**
3160	* Write guest RAM.
3161	*
3162	* @param pbDstPhys The destination address. Relative to guest RAM.
3163	* @param val Value
3164	*/
3165	void remR3PhysWriteByte(uint8_t *pbDstPhys, uint8_t val)
3166	{
3167	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3168	/*
3169	* Calc the physical address ('off') and check that it's within the RAM.
3170	*/
3171	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3172	if (off < (uintptr_t)phys_ram_size)
3173	PGMR3PhysWriteByte(cpu_single_env->pVM, (RTGCPHYS)off, val);
3174	else
3175	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 1));
3176	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3177	}
3178
3179	/**
3180	* Write guest RAM.
3181	*
3182	* @param pbDstPhys The destination address. Relative to guest RAM.
3183	* @param val Value
3184	*/
3185	void remR3PhysWriteWord(uint8_t *pbDstPhys, uint16_t val)
3186	{
3187	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3188	/*
3189	* Calc the physical address ('off') and check that it's within the RAM.
3190	*/
3191	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3192	if (off < (uintptr_t)phys_ram_size)
3193	PGMR3PhysWriteWord(cpu_single_env->pVM, (RTGCPHYS)off, val);
3194	else
3195	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 2));
3196	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3197	}
3198
3199	/**
3200	* Write guest RAM.
3201	*
3202	* @param pbDstPhys The destination address. Relative to guest RAM.
3203	* @param val Value
3204	*/
3205	void remR3PhysWriteDword(uint8_t *pbDstPhys, uint32_t val)
3206	{
3207	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3208	/*
3209	* Calc the physical address ('off') and check that it's within the RAM.
3210	*/
3211	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3212	if (off < (uintptr_t)phys_ram_size)
3213	PGMR3PhysWriteDword(cpu_single_env->pVM, (RTGCPHYS)off, val);
3214	else
3215	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 4));
3216	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3217	}
3218
3219
3220
3221	#undef LOG_GROUP
3222	#define LOG_GROUP LOG_GROUP_REM_MMIO
3223
3224	/** Read MMIO memory. */
3225	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3226	{
3227	uint32_t u32 = 0;
3228	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3229	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3230	Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32));
3231	return u32;
3232	}
3233
3234	/** Read MMIO memory. */
3235	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3236	{
3237	uint32_t u32 = 0;
3238	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3239	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3240	Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32));
3241	return u32;
3242	}
3243
3244	/** Read MMIO memory. */
3245	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3246	{
3247	uint32_t u32 = 0;
3248	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3249	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3250	Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32));
3251	return u32;
3252	}
3253
3254	/** Write to MMIO memory. */
3255	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3256	{
3257	Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3258	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3259	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3260	}
3261
3262	/** Write to MMIO memory. */
3263	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3264	{
3265	Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3266	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3267	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3268	}
3269
3270	/** Write to MMIO memory. */
3271	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3272	{
3273	Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3274	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3275	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3276	}
3277
3278
3279	#undef LOG_GROUP
3280	#define LOG_GROUP LOG_GROUP_REM_HANDLER
3281
3282	/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3283
3284	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3285	{
3286	Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys));
3287	uint8_t u8;
3288	PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3289	return u8;
3290	}
3291
3292	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3293	{
3294	Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys));
3295	uint16_t u16;
3296	PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3297	return u16;
3298	}
3299
3300	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3301	{
3302	Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys));
3303	uint32_t u32;
3304	PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3305	return u32;
3306	}
3307
3308	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3309	{
3310	Log2(("remR3HandlerWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3311	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3312	}
3313
3314	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3315	{
3316	Log2(("remR3HandlerWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3317	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3318	}
3319
3320	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3321	{
3322	Log2(("remR3HandlerWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3323	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3324	}
3325
3326	/* -+- disassembly -+- */
3327
3328	#undef LOG_GROUP
3329	#define LOG_GROUP LOG_GROUP_REM_DISAS
3330
3331
3332	/**
3333	* Enables or disables singled stepped disassembly.
3334	*
3335	* @returns VBox status code.
3336	* @param pVM VM handle.
3337	* @param fEnable To enable set this flag, to disable clear it.
3338	*/
3339	static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3340	{
3341	LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3342	VM_ASSERT_EMT(pVM);
3343
3344	if (fEnable)
3345	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
3346	else
3347	pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3348	return VINF_SUCCESS;
3349	}
3350
3351
3352	/**
3353	* Enables or disables singled stepped disassembly.
3354	*
3355	* @returns VBox status code.
3356	* @param pVM VM handle.
3357	* @param fEnable To enable set this flag, to disable clear it.
3358	*/
3359	REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3360	{
3361	PVMREQ pReq;
3362	int rc;
3363
3364	LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3365	if (VM_IS_EMT(pVM))
3366	return remR3DisasEnableStepping(pVM, fEnable);
3367
3368	rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3369	AssertRC(rc);
3370	if (VBOX_SUCCESS(rc))
3371	rc = pReq->iStatus;
3372	VMR3ReqFree(pReq);
3373	return rc;
3374	}
3375
3376
3377	#ifdef VBOX_WITH_DEBUGGER
3378	/**
3379	* External Debugger Command: .remstep [on\|off\|1\|0]
3380	*/
3381	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3382	{
3383	bool fEnable;
3384	int rc;
3385
3386	/* print status */
3387	if (cArgs == 0)
3388	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3389	pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3390
3391	/* convert the argument and change the mode. */
3392	rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3393	if (VBOX_FAILURE(rc))
3394	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3395	rc = REMR3DisasEnableStepping(pVM, fEnable);
3396	if (VBOX_FAILURE(rc))
3397	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3398	return rc;
3399	}
3400	#endif
3401
3402
3403	/**
3404	* Disassembles n instructions and prints them to the log.
3405	*
3406	* @returns Success indicator.
3407	* @param env Pointer to the recompiler CPU structure.
3408	* @param f32BitCode Indicates that whether or not the code should
3409	* be disassembled as 16 or 32 bit. If -1 the CS
3410	* selector will be inspected.
3411	* @param nrInstructions Nr of instructions to disassemble
3412	* @param pszPrefix
3413	* @remark not currently used for anything but ad-hoc debugging.
3414	*/
3415	bool remR3DisasBlock(CPUState env, int f32BitCode, int nrInstructions, char pszPrefix)
3416	{
3417	int i;
3418
3419	/*
3420	* Determin 16/32 bit mode.
3421	*/
3422	if (f32BitCode == -1)
3423	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3424
3425	/*
3426	* Convert cs:eip to host context address.
3427	* We don't care to much about cross page correctness presently.
3428	*/
3429	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3430	void *pvPC;
3431	if (f32BitCode && (env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3432	{
3433	/* convert eip to physical address. */
3434	int rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,
3435	GCPtrPC,
3436	env->cr[3],
3437	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE), /** @todo add longmode flag */
3438	&pvPC);
3439	if (VBOX_FAILURE(rc))
3440	{
3441	if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3442	return false;
3443	pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3444	+ (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3445	}
3446	}
3447	else
3448	{
3449	/* physical address */
3450	int rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions*16, &pvPC);
3451	if (VBOX_FAILURE(rc))
3452	return false;
3453	}
3454
3455	/*
3456	* Disassemble.
3457	*/
3458	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3459	DISCPUSTATE Cpu;
3460	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3461	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3462	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3463	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3464	//Cpu.dwUserData[2] = GCPtrPC;
3465
3466	for (i=0;i<nrInstructions;i++)
3467	{
3468	char szOutput[256];
3469	uint32_t cbOp;
3470	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3471	return false;
3472	if (pszPrefix)
3473	Log(("%s: %s", pszPrefix, szOutput));
3474	else
3475	Log(("%s", szOutput));
3476
3477	pvPC += cbOp;
3478	}
3479	return true;
3480	}
3481
3482
3483	/** @todo need to test the new code, using the old code in the mean while. */
3484	#define USE_OLD_DUMP_AND_DISASSEMBLY
3485
3486	/**
3487	* Disassembles one instruction and prints it to the log.
3488	*
3489	* @returns Success indicator.
3490	* @param env Pointer to the recompiler CPU structure.
3491	* @param f32BitCode Indicates that whether or not the code should
3492	* be disassembled as 16 or 32 bit. If -1 the CS
3493	* selector will be inspected.
3494	* @param pszPrefix
3495	*/
3496	bool remR3DisasInstr(CPUState env, int f32BitCode, char pszPrefix)
3497	{
3498	#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3499	PVM pVM = env->pVM;
3500
3501	/*
3502	* Determin 16/32 bit mode.
3503	*/
3504	if (f32BitCode == -1)
3505	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3506
3507	/*
3508	* Log registers
3509	*/
3510	if (LogIs2Enabled())
3511	{
3512	remR3StateUpdate(pVM);
3513	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3514	}
3515
3516	/*
3517	* Convert cs:eip to host context address.
3518	* We don't care to much about cross page correctness presently.
3519	*/
3520	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3521	void *pvPC;
3522	if ((env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3523	{
3524	/* convert eip to physical address. */
3525	int rc = PGMPhysGCPtr2HCPtrByGstCR3(pVM,
3526	GCPtrPC,
3527	env->cr[3],
3528	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE),
3529	&pvPC);
3530	if (VBOX_FAILURE(rc))
3531	{
3532	if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3533	return false;
3534	pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3535	+ (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3536	}
3537	}
3538	else
3539	{
3540
3541	/* physical address */
3542	int rc = PGMPhysGCPhys2HCPtr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3543	if (VBOX_FAILURE(rc))
3544	return false;
3545	}
3546
3547	/*
3548	* Disassemble.
3549	*/
3550	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3551	DISCPUSTATE Cpu;
3552	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3553	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3554	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3555	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3556	//Cpu.dwUserData[2] = GCPtrPC;
3557	char szOutput[256];
3558	uint32_t cbOp;
3559	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3560	return false;
3561
3562	if (!f32BitCode)
3563	{
3564	if (pszPrefix)
3565	Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3566	else
3567	Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3568	}
3569	else
3570	{
3571	if (pszPrefix)
3572	Log(("%s: %s", pszPrefix, szOutput));
3573	else
3574	Log(("%s", szOutput));
3575	}
3576	return true;
3577
3578	#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3579	PVM pVM = env->pVM;
3580	const bool fLog = LogIsEnabled();
3581	const bool fLog2 = LogIs2Enabled();
3582	int rc = VINF_SUCCESS;
3583
3584	/*
3585	* Don't bother if there ain't any log output to do.
3586	*/
3587	if (!fLog && !fLog2)
3588	return true;
3589
3590	/*
3591	* Update the state so DBGF reads the correct register values.
3592	*/
3593	remR3StateUpdate(pVM);
3594
3595	/*
3596	* Log registers if requested.
3597	*/
3598	if (!fLog2)
3599	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3600
3601	/*
3602	* Disassemble to log.
3603	*/
3604	if (fLog)
3605	rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3606
3607	return VBOX_SUCCESS(rc);
3608	#endif
3609	}
3610
3611
3612	/**
3613	* Disassemble recompiled code.
3614	*
3615	* @param phFileIgnored Ignored, logfile usually.
3616	* @param pvCode Pointer to the code block.
3617	* @param cb Size of the code block.
3618	*/
3619	void disas(FILE phFileIgnored, void pvCode, unsigned long cb)
3620	{
3621	if (LogIs2Enabled())
3622	{
3623	unsigned off = 0;
3624	char szOutput[256];
3625	DISCPUSTATE Cpu = {0};
3626	Cpu.mode = CPUMODE_32BIT;
3627
3628	RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3629	while (off < cb)
3630	{
3631	uint32_t cbInstr;
3632	if (DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput))
3633	RTLogPrintf("%s", szOutput);
3634	else
3635	{
3636	RTLogPrintf("disas error\n");
3637	cbInstr = 1;
3638	}
3639	off += cbInstr;
3640	}
3641	}
3642	NOREF(phFileIgnored);
3643	}
3644
3645
3646	/**
3647	* Disassemble guest code.
3648	*
3649	* @param phFileIgnored Ignored, logfile usually.
3650	* @param uCode The guest address of the code to disassemble. (flat?)
3651	* @param cb Number of bytes to disassemble.
3652	* @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3653	*/
3654	void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3655	{
3656	if (LogIs2Enabled())
3657	{
3658	PVM pVM = cpu_single_env->pVM;
3659
3660	/*
3661	* Update the state so DBGF reads the correct register values (flags).
3662	*/
3663	remR3StateUpdate(pVM);
3664
3665	/*
3666	* Do the disassembling.
3667	*/
3668	RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3669	RTSEL cs = cpu_single_env->segs[R_CS].selector;
3670	RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3671	for (;;)
3672	{
3673	char szBuf[256];
3674	size_t cbInstr;
3675	int rc = DBGFR3DisasInstrEx(pVM,
3676	cs,
3677	eip,
3678	0,
3679	szBuf, sizeof(szBuf),
3680	&cbInstr);
3681	if (VBOX_SUCCESS(rc))
3682	RTLogPrintf("%VGp %s\n", uCode, szBuf);
3683	else
3684	{
3685	RTLogPrintf("%VGp %04x:%VGp: %s\n", uCode, cs, eip, szBuf);
3686	cbInstr = 1;
3687	}
3688
3689	/* next */
3690	if (cb <= cbInstr)
3691	break;
3692	cb -= cbInstr;
3693	uCode += cbInstr;
3694	eip += cbInstr;
3695	}
3696	}
3697	NOREF(phFileIgnored);
3698	}
3699
3700
3701	/**
3702	* Looks up a guest symbol.
3703	*
3704	* @returns Pointer to symbol name. This is a static buffer.
3705	* @param orig_addr The address in question.
3706	*/
3707	const char *lookup_symbol(target_ulong orig_addr)
3708	{
3709	RTGCINTPTR off = 0;
3710	DBGFSYMBOL Sym;
3711	PVM pVM = cpu_single_env->pVM;
3712	int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3713	if (VBOX_SUCCESS(rc))
3714	{
3715	static char szSym[sizeof(Sym.szName) + 48];
3716	if (!off)
3717	RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3718	else if (off > 0)
3719	RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3720	else
3721	RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3722	return szSym;
3723	}
3724	return "<N/A>";
3725	}
3726
3727
3728	#undef LOG_GROUP
3729	#define LOG_GROUP LOG_GROUP_REM
3730
3731
3732	/* -+- FF notifications -+- */
3733
3734
3735	/**
3736	* Notification about a pending interrupt.
3737	*
3738	* @param pVM VM Handle.
3739	* @param u8Interrupt Interrupt
3740	* @thread The emulation thread.
3741	*/
3742	REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3743	{
3744	Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3745	pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3746	}
3747
3748	/**
3749	* Notification about a pending interrupt.
3750	*
3751	* @returns Pending interrupt or REM_NO_PENDING_IRQ
3752	* @param pVM VM Handle.
3753	* @thread The emulation thread.
3754	*/
3755	REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3756	{
3757	return pVM->rem.s.u32PendingInterrupt;
3758	}
3759
3760	/**
3761	* Notification about the interrupt FF being set.
3762	*
3763	* @param pVM VM Handle.
3764	* @thread The emulation thread.
3765	*/
3766	REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3767	{
3768	LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3769	(pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3770	if (pVM->rem.s.fInREM)
3771	{
3772	if (VM_IS_EMT(pVM))
3773	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3774	else
3775	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3776	}
3777	}
3778
3779
3780	/**
3781	* Notification about the interrupt FF being set.
3782	*
3783	* @param pVM VM Handle.
3784	* @thread The emulation thread.
3785	*/
3786	REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3787	{
3788	LogFlow(("REMR3NotifyInterruptClear:\n"));
3789	VM_ASSERT_EMT(pVM);
3790	if (pVM->rem.s.fInREM)
3791	cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3792	}
3793
3794
3795	/**
3796	* Notification about pending timer(s).
3797	*
3798	* @param pVM VM Handle.
3799	* @thread Any.
3800	*/
3801	REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3802	{
3803	#ifndef DEBUG_bird
3804	LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3805	#endif
3806	if (pVM->rem.s.fInREM)
3807	{
3808	if (VM_IS_EMT(pVM))
3809	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3810	else
3811	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3812	}
3813	}
3814
3815
3816	/**
3817	* Notification about pending DMA transfers.
3818	*
3819	* @param pVM VM Handle.
3820	* @thread Any.
3821	*/
3822	REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3823	{
3824	LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3825	if (pVM->rem.s.fInREM)
3826	{
3827	if (VM_IS_EMT(pVM))
3828	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3829	else
3830	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3831	}
3832	}
3833
3834
3835	/**
3836	* Notification about pending timer(s).
3837	*
3838	* @param pVM VM Handle.
3839	* @thread Any.
3840	*/
3841	REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3842	{
3843	LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3844	if (pVM->rem.s.fInREM)
3845	{
3846	if (VM_IS_EMT(pVM))
3847	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3848	else
3849	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3850	}
3851	}
3852
3853
3854	/**
3855	* Notification about pending FF set by an external thread.
3856	*
3857	* @param pVM VM handle.
3858	* @thread Any.
3859	*/
3860	REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3861	{
3862	LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3863	if (pVM->rem.s.fInREM)
3864	{
3865	if (VM_IS_EMT(pVM))
3866	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3867	else
3868	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3869	}
3870	}
3871
3872
3873	#ifdef VBOX_WITH_STATISTICS
3874	void remR3ProfileStart(int statcode)
3875	{
3876	STAMPROFILEADV *pStat;
3877	switch(statcode)
3878	{
3879	case STATS_EMULATE_SINGLE_INSTR:
3880	pStat = &gStatExecuteSingleInstr;
3881	break;
3882	case STATS_QEMU_COMPILATION:
3883	pStat = &gStatCompilationQEmu;
3884	break;
3885	case STATS_QEMU_RUN_EMULATED_CODE:
3886	pStat = &gStatRunCodeQEmu;
3887	break;
3888	case STATS_QEMU_TOTAL:
3889	pStat = &gStatTotalTimeQEmu;
3890	break;
3891	case STATS_QEMU_RUN_TIMERS:
3892	pStat = &gStatTimers;
3893	break;
3894	case STATS_TLB_LOOKUP:
3895	pStat= &gStatTBLookup;
3896	break;
3897	case STATS_IRQ_HANDLING:
3898	pStat= &gStatIRQ;
3899	break;
3900	case STATS_RAW_CHECK:
3901	pStat = &gStatRawCheck;
3902	break;
3903
3904	default:
3905	AssertMsgFailed(("unknown stat %d\n", statcode));
3906	return;
3907	}
3908	STAM_PROFILE_ADV_START(pStat, a);
3909	}
3910
3911
3912	void remR3ProfileStop(int statcode)
3913	{
3914	STAMPROFILEADV *pStat;
3915	switch(statcode)
3916	{
3917	case STATS_EMULATE_SINGLE_INSTR:
3918	pStat = &gStatExecuteSingleInstr;
3919	break;
3920	case STATS_QEMU_COMPILATION:
3921	pStat = &gStatCompilationQEmu;
3922	break;
3923	case STATS_QEMU_RUN_EMULATED_CODE:
3924	pStat = &gStatRunCodeQEmu;
3925	break;
3926	case STATS_QEMU_TOTAL:
3927	pStat = &gStatTotalTimeQEmu;
3928	break;
3929	case STATS_QEMU_RUN_TIMERS:
3930	pStat = &gStatTimers;
3931	break;
3932	case STATS_TLB_LOOKUP:
3933	pStat= &gStatTBLookup;
3934	break;
3935	case STATS_IRQ_HANDLING:
3936	pStat= &gStatIRQ;
3937	break;
3938	case STATS_RAW_CHECK:
3939	pStat = &gStatRawCheck;
3940	break;
3941	default:
3942	AssertMsgFailed(("unknown stat %d\n", statcode));
3943	return;
3944	}
3945	STAM_PROFILE_ADV_STOP(pStat, a);
3946	}
3947	#endif
3948
3949	/**
3950	* Raise an RC, force rem exit.
3951	*
3952	* @param pVM VM handle.
3953	* @param rc The rc.
3954	*/
3955	void remR3RaiseRC(PVM pVM, int rc)
3956	{
3957	Log(("remR3RaiseRC: rc=%Vrc\n", rc));
3958	Assert(pVM->rem.s.fInREM);
3959	VM_ASSERT_EMT(pVM);
3960	pVM->rem.s.rc = rc;
3961	cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
3962	}
3963
3964
3965	/* -+- timers -+- */
3966
3967	uint64_t cpu_get_tsc(CPUX86State *env)
3968	{
3969	return TMCpuTickGet(env->pVM);
3970	}
3971
3972
3973	/* -+- interrupts -+- */
3974
3975	void cpu_set_ferr(CPUX86State *env)
3976	{
3977	int rc = PDMIsaSetIrq(env->pVM, 13, 1);
3978	LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
3979	}
3980
3981	int cpu_get_pic_interrupt(CPUState *env)
3982	{
3983	uint8_t u8Interrupt;
3984	int rc;
3985
3986	/* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
3987	* In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
3988	* with the (a)pic.
3989	*/
3990	/** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
3991	/** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
3992	* if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
3993	* remove this kludge. */
3994	if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
3995	{
3996	rc = VINF_SUCCESS;
3997	Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
3998	u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
3999	env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4000	}
4001	else
4002	rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
4003
4004	LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Vrc\n", u8Interrupt, rc));
4005	if (VBOX_SUCCESS(rc))
4006	{
4007	if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
4008	env->interrupt_request \|= CPU_INTERRUPT_HARD;
4009	return u8Interrupt;
4010	}
4011	return -1;
4012	}
4013
4014
4015	/* -+- local apic -+- */
4016
4017	void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4018	{
4019	int rc = PDMApicSetBase(env->pVM, val);
4020	LogFlow(("cpu_set_apic_base: val=%#llx rc=%Vrc\n", val, rc)); NOREF(rc);
4021	}
4022
4023	uint64_t cpu_get_apic_base(CPUX86State *env)
4024	{
4025	uint64_t u64;
4026	int rc = PDMApicGetBase(env->pVM, &u64);
4027	if (VBOX_SUCCESS(rc))
4028	{
4029	LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4030	return u64;
4031	}
4032	LogFlow(("cpu_get_apic_base: returns 0 (rc=%Vrc)\n", rc));
4033	return 0;
4034	}
4035
4036	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4037	{
4038	int rc = PDMApicSetTPR(env->pVM, val);
4039	LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Vrc\n", val, rc)); NOREF(rc);
4040	}
4041
4042	uint8_t cpu_get_apic_tpr(CPUX86State *env)
4043	{
4044	uint8_t u8;
4045	int rc = PDMApicGetTPR(env->pVM, &u8);
4046	if (VBOX_SUCCESS(rc))
4047	{
4048	LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4049	return u8;
4050	}
4051	LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Vrc)\n", rc));
4052	return 0;
4053	}
4054
4055
4056	/* -+- I/O Ports -+- */
4057
4058	#undef LOG_GROUP
4059	#define LOG_GROUP LOG_GROUP_REM_IOPORT
4060
4061	void cpu_outb(CPUState *env, int addr, int val)
4062	{
4063	if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4064	Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4065
4066	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4067	if (rc == VINF_SUCCESS)
4068	return;
4069	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4070	{
4071	Log(("cpu_outb: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4072	remR3RaiseRC(env->pVM, rc);
4073	return;
4074	}
4075	remAbort(rc, __FUNCTION__);
4076	}
4077
4078	void cpu_outw(CPUState *env, int addr, int val)
4079	{
4080	//Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4081	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4082	if (rc == VINF_SUCCESS)
4083	return;
4084	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4085	{
4086	Log(("cpu_outw: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4087	remR3RaiseRC(env->pVM, rc);
4088	return;
4089	}
4090	remAbort(rc, __FUNCTION__);
4091	}
4092
4093	void cpu_outl(CPUState *env, int addr, int val)
4094	{
4095	Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4096	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4097	if (rc == VINF_SUCCESS)
4098	return;
4099	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4100	{
4101	Log(("cpu_outl: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4102	remR3RaiseRC(env->pVM, rc);
4103	return;
4104	}
4105	remAbort(rc, __FUNCTION__);
4106	}
4107
4108	int cpu_inb(CPUState *env, int addr)
4109	{
4110	uint32_t u32 = 0;
4111	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4112	if (rc == VINF_SUCCESS)
4113	{
4114	if (/addr != 0x61 && /addr != 0x71)
4115	Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4116	return (int)u32;
4117	}
4118	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4119	{
4120	Log(("cpu_inb: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4121	remR3RaiseRC(env->pVM, rc);
4122	return (int)u32;
4123	}
4124	remAbort(rc, __FUNCTION__);
4125	return 0xff;
4126	}
4127
4128	int cpu_inw(CPUState *env, int addr)
4129	{
4130	uint32_t u32 = 0;
4131	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4132	if (rc == VINF_SUCCESS)
4133	{
4134	Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4135	return (int)u32;
4136	}
4137	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4138	{
4139	Log(("cpu_inw: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4140	remR3RaiseRC(env->pVM, rc);
4141	return (int)u32;
4142	}
4143	remAbort(rc, __FUNCTION__);
4144	return 0xffff;
4145	}
4146
4147	int cpu_inl(CPUState *env, int addr)
4148	{
4149	uint32_t u32 = 0;
4150	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4151	if (rc == VINF_SUCCESS)
4152	{
4153	//if (addr==0x01f0 && u32 == 0x6b6d)
4154	// loglevel = ~0;
4155	Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4156	return (int)u32;
4157	}
4158	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4159	{
4160	Log(("cpu_inl: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4161	remR3RaiseRC(env->pVM, rc);
4162	return (int)u32;
4163	}
4164	remAbort(rc, __FUNCTION__);
4165	return 0xffffffff;
4166	}
4167
4168	#undef LOG_GROUP
4169	#define LOG_GROUP LOG_GROUP_REM
4170
4171
4172	/* -+- helpers and misc other interfaces -+- */
4173
4174	/**
4175	* Perform the CPUID instruction.
4176	*
4177	* ASMCpuId cannot be invoked from some source files where this is used because of global
4178	* register allocations.
4179	*
4180	* @param env Pointer to the recompiler CPU structure.
4181	* @param uOperator CPUID operation (eax).
4182	* @param pvEAX Where to store eax.
4183	* @param pvEBX Where to store ebx.
4184	* @param pvECX Where to store ecx.
4185	* @param pvEDX Where to store edx.
4186	*/
4187	void remR3CpuId(CPUState env, unsigned uOperator, void pvEAX, void pvEBX, void pvECX, void *pvEDX)
4188	{
4189	CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t )pvEAX, (uint32_t )pvEBX, (uint32_t )pvECX, (uint32_t )pvEDX);
4190	}
4191
4192
4193	#if 0 /* not used */
4194	/**
4195	* Interface for qemu hardware to report back fatal errors.
4196	*/
4197	void hw_error(const char *pszFormat, ...)
4198	{
4199	/*
4200	* Bitch about it.
4201	*/
4202	/** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4203	* this in my Odin32 tree at home! */
4204	va_list args;
4205	va_start(args, pszFormat);
4206	RTLogPrintf("fatal error in virtual hardware:");
4207	RTLogPrintfV(pszFormat, args);
4208	va_end(args);
4209	AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4210
4211	/*
4212	* If we're in REM context we'll sync back the state before 'jumping' to
4213	* the EMs failure handling.
4214	*/
4215	PVM pVM = cpu_single_env->pVM;
4216	if (pVM->rem.s.fInREM)
4217	REMR3StateBack(pVM);
4218	EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4219	AssertMsgFailed(("EMR3FatalError returned!\n"));
4220	}
4221	#endif
4222
4223	/**
4224	* Interface for the qemu cpu to report unhandled situation
4225	* raising a fatal VM error.
4226	*/
4227	void cpu_abort(CPUState env, const char pszFormat, ...)
4228	{
4229	/*
4230	* Bitch about it.
4231	*/
4232	RTLogFlags(NULL, "nodisabled nobuffered");
4233	va_list args;
4234	va_start(args, pszFormat);
4235	RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4236	va_end(args);
4237	va_start(args, pszFormat);
4238	AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4239	va_end(args);
4240
4241	/*
4242	* If we're in REM context we'll sync back the state before 'jumping' to
4243	* the EMs failure handling.
4244	*/
4245	PVM pVM = cpu_single_env->pVM;
4246	if (pVM->rem.s.fInREM)
4247	REMR3StateBack(pVM);
4248	EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4249	AssertMsgFailed(("EMR3FatalError returned!\n"));
4250	}
4251
4252
4253	/**
4254	* Aborts the VM.
4255	*
4256	* @param rc VBox error code.
4257	* @param pszTip Hint about why/when this happend.
4258	*/
4259	static void remAbort(int rc, const char *pszTip)
4260	{
4261	/*
4262	* Bitch about it.
4263	*/
4264	RTLogPrintf("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip);
4265	AssertReleaseMsgFailed(("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip));
4266
4267	/*
4268	* Jump back to where we entered the recompiler.
4269	*/
4270	PVM pVM = cpu_single_env->pVM;
4271	if (pVM->rem.s.fInREM)
4272	REMR3StateBack(pVM);
4273	EMR3FatalError(pVM, rc);
4274	AssertMsgFailed(("EMR3FatalError returned!\n"));
4275	}
4276
4277
4278	/**
4279	* Dumps a linux system call.
4280	* @param pVM VM handle.
4281	*/
4282	void remR3DumpLnxSyscall(PVM pVM)
4283	{
4284	static const char *apsz[] =
4285	{
4286	"sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4287	"sys_exit",
4288	"sys_fork",
4289	"sys_read",
4290	"sys_write",
4291	"sys_open", /* 5 */
4292	"sys_close",
4293	"sys_waitpid",
4294	"sys_creat",
4295	"sys_link",
4296	"sys_unlink", /* 10 */
4297	"sys_execve",
4298	"sys_chdir",
4299	"sys_time",
4300	"sys_mknod",
4301	"sys_chmod", /* 15 */
4302	"sys_lchown16",
4303	"sys_ni_syscall", /* old break syscall holder */
4304	"sys_stat",
4305	"sys_lseek",
4306	"sys_getpid", /* 20 */
4307	"sys_mount",
4308	"sys_oldumount",
4309	"sys_setuid16",
4310	"sys_getuid16",
4311	"sys_stime", /* 25 */
4312	"sys_ptrace",
4313	"sys_alarm",
4314	"sys_fstat",
4315	"sys_pause",
4316	"sys_utime", /* 30 */
4317	"sys_ni_syscall", /* old stty syscall holder */
4318	"sys_ni_syscall", /* old gtty syscall holder */
4319	"sys_access",
4320	"sys_nice",
4321	"sys_ni_syscall", /* 35 - old ftime syscall holder */
4322	"sys_sync",
4323	"sys_kill",
4324	"sys_rename",
4325	"sys_mkdir",
4326	"sys_rmdir", /* 40 */
4327	"sys_dup",
4328	"sys_pipe",
4329	"sys_times",
4330	"sys_ni_syscall", /* old prof syscall holder */
4331	"sys_brk", /* 45 */
4332	"sys_setgid16",
4333	"sys_getgid16",
4334	"sys_signal",
4335	"sys_geteuid16",
4336	"sys_getegid16", /* 50 */
4337	"sys_acct",
4338	"sys_umount", /* recycled never used phys() */
4339	"sys_ni_syscall", /* old lock syscall holder */
4340	"sys_ioctl",
4341	"sys_fcntl", /* 55 */
4342	"sys_ni_syscall", /* old mpx syscall holder */
4343	"sys_setpgid",
4344	"sys_ni_syscall", /* old ulimit syscall holder */
4345	"sys_olduname",
4346	"sys_umask", /* 60 */
4347	"sys_chroot",
4348	"sys_ustat",
4349	"sys_dup2",
4350	"sys_getppid",
4351	"sys_getpgrp", /* 65 */
4352	"sys_setsid",
4353	"sys_sigaction",
4354	"sys_sgetmask",
4355	"sys_ssetmask",
4356	"sys_setreuid16", /* 70 */
4357	"sys_setregid16",
4358	"sys_sigsuspend",
4359	"sys_sigpending",
4360	"sys_sethostname",
4361	"sys_setrlimit", /* 75 */
4362	"sys_old_getrlimit",
4363	"sys_getrusage",
4364	"sys_gettimeofday",
4365	"sys_settimeofday",
4366	"sys_getgroups16", /* 80 */
4367	"sys_setgroups16",
4368	"old_select",
4369	"sys_symlink",
4370	"sys_lstat",
4371	"sys_readlink", /* 85 */
4372	"sys_uselib",
4373	"sys_swapon",
4374	"sys_reboot",
4375	"old_readdir",
4376	"old_mmap", /* 90 */
4377	"sys_munmap",
4378	"sys_truncate",
4379	"sys_ftruncate",
4380	"sys_fchmod",
4381	"sys_fchown16", /* 95 */
4382	"sys_getpriority",
4383	"sys_setpriority",
4384	"sys_ni_syscall", /* old profil syscall holder */
4385	"sys_statfs",
4386	"sys_fstatfs", /* 100 */
4387	"sys_ioperm",
4388	"sys_socketcall",
4389	"sys_syslog",
4390	"sys_setitimer",
4391	"sys_getitimer", /* 105 */
4392	"sys_newstat",
4393	"sys_newlstat",
4394	"sys_newfstat",
4395	"sys_uname",
4396	"sys_iopl", /* 110 */
4397	"sys_vhangup",
4398	"sys_ni_syscall", /* old "idle" system call */
4399	"sys_vm86old",
4400	"sys_wait4",
4401	"sys_swapoff", /* 115 */
4402	"sys_sysinfo",
4403	"sys_ipc",
4404	"sys_fsync",
4405	"sys_sigreturn",
4406	"sys_clone", /* 120 */
4407	"sys_setdomainname",
4408	"sys_newuname",
4409	"sys_modify_ldt",
4410	"sys_adjtimex",
4411	"sys_mprotect", /* 125 */
4412	"sys_sigprocmask",
4413	"sys_ni_syscall", /* old "create_module" */
4414	"sys_init_module",
4415	"sys_delete_module",
4416	"sys_ni_syscall", /* 130: old "get_kernel_syms" */
4417	"sys_quotactl",
4418	"sys_getpgid",
4419	"sys_fchdir",
4420	"sys_bdflush",
4421	"sys_sysfs", /* 135 */
4422	"sys_personality",
4423	"sys_ni_syscall", /* reserved for afs_syscall */
4424	"sys_setfsuid16",
4425	"sys_setfsgid16",
4426	"sys_llseek", /* 140 */
4427	"sys_getdents",
4428	"sys_select",
4429	"sys_flock",
4430	"sys_msync",
4431	"sys_readv", /* 145 */
4432	"sys_writev",
4433	"sys_getsid",
4434	"sys_fdatasync",
4435	"sys_sysctl",
4436	"sys_mlock", /* 150 */
4437	"sys_munlock",
4438	"sys_mlockall",
4439	"sys_munlockall",
4440	"sys_sched_setparam",
4441	"sys_sched_getparam", /* 155 */
4442	"sys_sched_setscheduler",
4443	"sys_sched_getscheduler",
4444	"sys_sched_yield",
4445	"sys_sched_get_priority_max",
4446	"sys_sched_get_priority_min", /* 160 */
4447	"sys_sched_rr_get_interval",
4448	"sys_nanosleep",
4449	"sys_mremap",
4450	"sys_setresuid16",
4451	"sys_getresuid16", /* 165 */
4452	"sys_vm86",
4453	"sys_ni_syscall", /* Old sys_query_module */
4454	"sys_poll",
4455	"sys_nfsservctl",
4456	"sys_setresgid16", /* 170 */
4457	"sys_getresgid16",
4458	"sys_prctl",
4459	"sys_rt_sigreturn",
4460	"sys_rt_sigaction",
4461	"sys_rt_sigprocmask", /* 175 */
4462	"sys_rt_sigpending",
4463	"sys_rt_sigtimedwait",
4464	"sys_rt_sigqueueinfo",
4465	"sys_rt_sigsuspend",
4466	"sys_pread64", /* 180 */
4467	"sys_pwrite64",
4468	"sys_chown16",
4469	"sys_getcwd",
4470	"sys_capget",
4471	"sys_capset", /* 185 */
4472	"sys_sigaltstack",
4473	"sys_sendfile",
4474	"sys_ni_syscall", /* reserved for streams1 */
4475	"sys_ni_syscall", /* reserved for streams2 */
4476	"sys_vfork", /* 190 */
4477	"sys_getrlimit",
4478	"sys_mmap2",
4479	"sys_truncate64",
4480	"sys_ftruncate64",
4481	"sys_stat64", /* 195 */
4482	"sys_lstat64",
4483	"sys_fstat64",
4484	"sys_lchown",
4485	"sys_getuid",
4486	"sys_getgid", /* 200 */
4487	"sys_geteuid",
4488	"sys_getegid",
4489	"sys_setreuid",
4490	"sys_setregid",
4491	"sys_getgroups", /* 205 */
4492	"sys_setgroups",
4493	"sys_fchown",
4494	"sys_setresuid",
4495	"sys_getresuid",
4496	"sys_setresgid", /* 210 */
4497	"sys_getresgid",
4498	"sys_chown",
4499	"sys_setuid",
4500	"sys_setgid",
4501	"sys_setfsuid", /* 215 */
4502	"sys_setfsgid",
4503	"sys_pivot_root",
4504	"sys_mincore",
4505	"sys_madvise",
4506	"sys_getdents64", /* 220 */
4507	"sys_fcntl64",
4508	"sys_ni_syscall", /* reserved for TUX */
4509	"sys_ni_syscall",
4510	"sys_gettid",
4511	"sys_readahead", /* 225 */
4512	"sys_setxattr",
4513	"sys_lsetxattr",
4514	"sys_fsetxattr",
4515	"sys_getxattr",
4516	"sys_lgetxattr", /* 230 */
4517	"sys_fgetxattr",
4518	"sys_listxattr",
4519	"sys_llistxattr",
4520	"sys_flistxattr",
4521	"sys_removexattr", /* 235 */
4522	"sys_lremovexattr",
4523	"sys_fremovexattr",
4524	"sys_tkill",
4525	"sys_sendfile64",
4526	"sys_futex", /* 240 */
4527	"sys_sched_setaffinity",
4528	"sys_sched_getaffinity",
4529	"sys_set_thread_area",
4530	"sys_get_thread_area",
4531	"sys_io_setup", /* 245 */
4532	"sys_io_destroy",
4533	"sys_io_getevents",
4534	"sys_io_submit",
4535	"sys_io_cancel",
4536	"sys_fadvise64", /* 250 */
4537	"sys_ni_syscall",
4538	"sys_exit_group",
4539	"sys_lookup_dcookie",
4540	"sys_epoll_create",
4541	"sys_epoll_ctl", /* 255 */
4542	"sys_epoll_wait",
4543	"sys_remap_file_pages",
4544	"sys_set_tid_address",
4545	"sys_timer_create",
4546	"sys_timer_settime", /* 260 */
4547	"sys_timer_gettime",
4548	"sys_timer_getoverrun",
4549	"sys_timer_delete",
4550	"sys_clock_settime",
4551	"sys_clock_gettime", /* 265 */
4552	"sys_clock_getres",
4553	"sys_clock_nanosleep",
4554	"sys_statfs64",
4555	"sys_fstatfs64",
4556	"sys_tgkill", /* 270 */
4557	"sys_utimes",
4558	"sys_fadvise64_64",
4559	"sys_ni_syscall" /* sys_vserver */
4560	};
4561
4562	uint32_t uEAX = CPUMGetGuestEAX(pVM);
4563	switch (uEAX)
4564	{
4565	default:
4566	if (uEAX < ELEMENTS(apsz))
4567	Log(("REM: linux syscall %3d: %s (eip=%VGv ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4568	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4569	CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4570	else
4571	Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4572	break;
4573
4574	}
4575	}
4576
4577
4578	/**
4579	* Dumps an OpenBSD system call.
4580	* @param pVM VM handle.
4581	*/
4582	void remR3DumpOBsdSyscall(PVM pVM)
4583	{
4584	static const char *apsz[] =
4585	{
4586	"SYS_syscall", //0
4587	"SYS_exit", //1
4588	"SYS_fork", //2
4589	"SYS_read", //3
4590	"SYS_write", //4
4591	"SYS_open", //5
4592	"SYS_close", //6
4593	"SYS_wait4", //7
4594	"SYS_8",
4595	"SYS_link", //9
4596	"SYS_unlink", //10
4597	"SYS_11",
4598	"SYS_chdir", //12
4599	"SYS_fchdir", //13
4600	"SYS_mknod", //14
4601	"SYS_chmod", //15
4602	"SYS_chown", //16
4603	"SYS_break", //17
4604	"SYS_18",
4605	"SYS_19",
4606	"SYS_getpid", //20
4607	"SYS_mount", //21
4608	"SYS_unmount", //22
4609	"SYS_setuid", //23
4610	"SYS_getuid", //24
4611	"SYS_geteuid", //25
4612	"SYS_ptrace", //26
4613	"SYS_recvmsg", //27
4614	"SYS_sendmsg", //28
4615	"SYS_recvfrom", //29
4616	"SYS_accept", //30
4617	"SYS_getpeername", //31
4618	"SYS_getsockname", //32
4619	"SYS_access", //33
4620	"SYS_chflags", //34
4621	"SYS_fchflags", //35
4622	"SYS_sync", //36
4623	"SYS_kill", //37
4624	"SYS_38",
4625	"SYS_getppid", //39
4626	"SYS_40",
4627	"SYS_dup", //41
4628	"SYS_opipe", //42
4629	"SYS_getegid", //43
4630	"SYS_profil", //44
4631	"SYS_ktrace", //45
4632	"SYS_sigaction", //46
4633	"SYS_getgid", //47
4634	"SYS_sigprocmask", //48
4635	"SYS_getlogin", //49
4636	"SYS_setlogin", //50
4637	"SYS_acct", //51
4638	"SYS_sigpending", //52
4639	"SYS_osigaltstack", //53
4640	"SYS_ioctl", //54
4641	"SYS_reboot", //55
4642	"SYS_revoke", //56
4643	"SYS_symlink", //57
4644	"SYS_readlink", //58
4645	"SYS_execve", //59
4646	"SYS_umask", //60
4647	"SYS_chroot", //61
4648	"SYS_62",
4649	"SYS_63",
4650	"SYS_64",
4651	"SYS_65",
4652	"SYS_vfork", //66
4653	"SYS_67",
4654	"SYS_68",
4655	"SYS_sbrk", //69
4656	"SYS_sstk", //70
4657	"SYS_61",
4658	"SYS_vadvise", //72
4659	"SYS_munmap", //73
4660	"SYS_mprotect", //74
4661	"SYS_madvise", //75
4662	"SYS_76",
4663	"SYS_77",
4664	"SYS_mincore", //78
4665	"SYS_getgroups", //79
4666	"SYS_setgroups", //80
4667	"SYS_getpgrp", //81
4668	"SYS_setpgid", //82
4669	"SYS_setitimer", //83
4670	"SYS_84",
4671	"SYS_85",
4672	"SYS_getitimer", //86
4673	"SYS_87",
4674	"SYS_88",
4675	"SYS_89",
4676	"SYS_dup2", //90
4677	"SYS_91",
4678	"SYS_fcntl", //92
4679	"SYS_select", //93
4680	"SYS_94",
4681	"SYS_fsync", //95
4682	"SYS_setpriority", //96
4683	"SYS_socket", //97
4684	"SYS_connect", //98
4685	"SYS_99",
4686	"SYS_getpriority", //100
4687	"SYS_101",
4688	"SYS_102",
4689	"SYS_sigreturn", //103
4690	"SYS_bind", //104
4691	"SYS_setsockopt", //105
4692	"SYS_listen", //106
4693	"SYS_107",
4694	"SYS_108",
4695	"SYS_109",
4696	"SYS_110",
4697	"SYS_sigsuspend", //111
4698	"SYS_112",
4699	"SYS_113",
4700	"SYS_114",
4701	"SYS_115",
4702	"SYS_gettimeofday", //116
4703	"SYS_getrusage", //117
4704	"SYS_getsockopt", //118
4705	"SYS_119",
4706	"SYS_readv", //120
4707	"SYS_writev", //121
4708	"SYS_settimeofday", //122
4709	"SYS_fchown", //123
4710	"SYS_fchmod", //124
4711	"SYS_125",
4712	"SYS_setreuid", //126
4713	"SYS_setregid", //127
4714	"SYS_rename", //128
4715	"SYS_129",
4716	"SYS_130",
4717	"SYS_flock", //131
4718	"SYS_mkfifo", //132
4719	"SYS_sendto", //133
4720	"SYS_shutdown", //134
4721	"SYS_socketpair", //135
4722	"SYS_mkdir", //136
4723	"SYS_rmdir", //137
4724	"SYS_utimes", //138
4725	"SYS_139",
4726	"SYS_adjtime", //140
4727	"SYS_141",
4728	"SYS_142",
4729	"SYS_143",
4730	"SYS_144",
4731	"SYS_145",
4732	"SYS_146",
4733	"SYS_setsid", //147
4734	"SYS_quotactl", //148
4735	"SYS_149",
4736	"SYS_150",
4737	"SYS_151",
4738	"SYS_152",
4739	"SYS_153",
4740	"SYS_154",
4741	"SYS_nfssvc", //155
4742	"SYS_156",
4743	"SYS_157",
4744	"SYS_158",
4745	"SYS_159",
4746	"SYS_160",
4747	"SYS_getfh", //161
4748	"SYS_162",
4749	"SYS_163",
4750	"SYS_164",
4751	"SYS_sysarch", //165
4752	"SYS_166",
4753	"SYS_167",
4754	"SYS_168",
4755	"SYS_169",
4756	"SYS_170",
4757	"SYS_171",
4758	"SYS_172",
4759	"SYS_pread", //173
4760	"SYS_pwrite", //174
4761	"SYS_175",
4762	"SYS_176",
4763	"SYS_177",
4764	"SYS_178",
4765	"SYS_179",
4766	"SYS_180",
4767	"SYS_setgid", //181
4768	"SYS_setegid", //182
4769	"SYS_seteuid", //183
4770	"SYS_lfs_bmapv", //184
4771	"SYS_lfs_markv", //185
4772	"SYS_lfs_segclean", //186
4773	"SYS_lfs_segwait", //187
4774	"SYS_188",
4775	"SYS_189",
4776	"SYS_190",
4777	"SYS_pathconf", //191
4778	"SYS_fpathconf", //192
4779	"SYS_swapctl", //193
4780	"SYS_getrlimit", //194
4781	"SYS_setrlimit", //195
4782	"SYS_getdirentries", //196
4783	"SYS_mmap", //197
4784	"SYS___syscall", //198
4785	"SYS_lseek", //199
4786	"SYS_truncate", //200
4787	"SYS_ftruncate", //201
4788	"SYS___sysctl", //202
4789	"SYS_mlock", //203
4790	"SYS_munlock", //204
4791	"SYS_205",
4792	"SYS_futimes", //206
4793	"SYS_getpgid", //207
4794	"SYS_xfspioctl", //208
4795	"SYS_209",
4796	"SYS_210",
4797	"SYS_211",
4798	"SYS_212",
4799	"SYS_213",
4800	"SYS_214",
4801	"SYS_215",
4802	"SYS_216",
4803	"SYS_217",
4804	"SYS_218",
4805	"SYS_219",
4806	"SYS_220",
4807	"SYS_semget", //221
4808	"SYS_222",
4809	"SYS_223",
4810	"SYS_224",
4811	"SYS_msgget", //225
4812	"SYS_msgsnd", //226
4813	"SYS_msgrcv", //227
4814	"SYS_shmat", //228
4815	"SYS_229",
4816	"SYS_shmdt", //230
4817	"SYS_231",
4818	"SYS_clock_gettime", //232
4819	"SYS_clock_settime", //233
4820	"SYS_clock_getres", //234
4821	"SYS_235",
4822	"SYS_236",
4823	"SYS_237",
4824	"SYS_238",
4825	"SYS_239",
4826	"SYS_nanosleep", //240
4827	"SYS_241",
4828	"SYS_242",
4829	"SYS_243",
4830	"SYS_244",
4831	"SYS_245",
4832	"SYS_246",
4833	"SYS_247",
4834	"SYS_248",
4835	"SYS_249",
4836	"SYS_minherit", //250
4837	"SYS_rfork", //251
4838	"SYS_poll", //252
4839	"SYS_issetugid", //253
4840	"SYS_lchown", //254
4841	"SYS_getsid", //255
4842	"SYS_msync", //256
4843	"SYS_257",
4844	"SYS_258",
4845	"SYS_259",
4846	"SYS_getfsstat", //260
4847	"SYS_statfs", //261
4848	"SYS_fstatfs", //262
4849	"SYS_pipe", //263
4850	"SYS_fhopen", //264
4851	"SYS_265",
4852	"SYS_fhstatfs", //266
4853	"SYS_preadv", //267
4854	"SYS_pwritev", //268
4855	"SYS_kqueue", //269
4856	"SYS_kevent", //270
4857	"SYS_mlockall", //271
4858	"SYS_munlockall", //272
4859	"SYS_getpeereid", //273
4860	"SYS_274",
4861	"SYS_275",
4862	"SYS_276",
4863	"SYS_277",
4864	"SYS_278",
4865	"SYS_279",
4866	"SYS_280",
4867	"SYS_getresuid", //281
4868	"SYS_setresuid", //282
4869	"SYS_getresgid", //283
4870	"SYS_setresgid", //284
4871	"SYS_285",
4872	"SYS_mquery", //286
4873	"SYS_closefrom", //287
4874	"SYS_sigaltstack", //288
4875	"SYS_shmget", //289
4876	"SYS_semop", //290
4877	"SYS_stat", //291
4878	"SYS_fstat", //292
4879	"SYS_lstat", //293
4880	"SYS_fhstat", //294
4881	"SYS___semctl", //295
4882	"SYS_shmctl", //296
4883	"SYS_msgctl", //297
4884	"SYS_MAXSYSCALL", //298
4885	//299
4886	//300
4887	};
4888	uint32_t uEAX;
4889	#ifndef DEBUG_bird
4890	if (!LogIsEnabled())
4891	return;
4892	#endif
4893	uEAX = CPUMGetGuestEAX(pVM);
4894	switch (uEAX)
4895	{
4896	default:
4897	if (uEAX < ELEMENTS(apsz))
4898	{
4899	uint32_t au32Args[8] = {0};
4900	PGMPhysReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4901	RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4902	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4903	au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4904	}
4905	else
4906	RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4907	break;
4908	}
4909	}

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source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 1806

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