VirtualBox

source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 16933

Last change on this file since 16933 was 16128, checked in by vboxsync, 16 years ago

REM: sync the FPU state after CR4 and CPUID or we'll get the wrong format.

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1/* $Id: VBoxRecompiler.c 16128 2009-01-21 11:15:09Z vboxsync $ */
2/** @file
3 * VBox Recompiler - QEMU.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_REM
27#include "vl.h"
28#include "exec-all.h"
29
30#include <VBox/rem.h>
31#include <VBox/vmapi.h>
32#include <VBox/tm.h>
33#include <VBox/ssm.h>
34#include <VBox/em.h>
35#include <VBox/trpm.h>
36#include <VBox/iom.h>
37#include <VBox/mm.h>
38#include <VBox/pgm.h>
39#include <VBox/pdm.h>
40#include <VBox/dbgf.h>
41#include <VBox/dbg.h>
42#include <VBox/hwaccm.h>
43#include <VBox/patm.h>
44#include <VBox/csam.h>
45#include "REMInternal.h"
46#include <VBox/vm.h>
47#include <VBox/param.h>
48#include <VBox/err.h>
49
50#include <VBox/log.h>
51#include <iprt/semaphore.h>
52#include <iprt/asm.h>
53#include <iprt/assert.h>
54#include <iprt/thread.h>
55#include <iprt/string.h>
56
57/* Don't wanna include everything. */
58extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
59extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
60extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
61extern void tlb_flush_page(CPUX86State *env, target_ulong addr);
62extern void tlb_flush(CPUState *env, int flush_global);
63extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
64extern void sync_ldtr(CPUX86State *env1, int selector);
65extern int sync_tr(CPUX86State *env1, int selector);
66
67#ifdef VBOX_STRICT
68unsigned long get_phys_page_offset(target_ulong addr);
69#endif
70
71
72/*******************************************************************************
73* Defined Constants And Macros *
74*******************************************************************************/
75
76/** Copy 80-bit fpu register at pSrc to pDst.
77 * This is probably faster than *calling* memcpy.
78 */
79#define REM_COPY_FPU_REG(pDst, pSrc) \
80 do { *(PX86FPUMMX)(pDst) = *(const X86FPUMMX *)(pSrc); } while (0)
81
82
83/*******************************************************************************
84* Internal Functions *
85*******************************************************************************/
86static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
87static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
88static void remR3StateUpdate(PVM pVM);
89
90static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
91static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
92static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
93static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
94static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96
97static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
98static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
99static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
100static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
101static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103
104
105/*******************************************************************************
106* Global Variables *
107*******************************************************************************/
108
109/** @todo Move stats to REM::s some rainy day we have nothing do to. */
110#ifdef VBOX_WITH_STATISTICS
111static STAMPROFILEADV gStatExecuteSingleInstr;
112static STAMPROFILEADV gStatCompilationQEmu;
113static STAMPROFILEADV gStatRunCodeQEmu;
114static STAMPROFILEADV gStatTotalTimeQEmu;
115static STAMPROFILEADV gStatTimers;
116static STAMPROFILEADV gStatTBLookup;
117static STAMPROFILEADV gStatIRQ;
118static STAMPROFILEADV gStatRawCheck;
119static STAMPROFILEADV gStatMemRead;
120static STAMPROFILEADV gStatMemWrite;
121static STAMPROFILE gStatGCPhys2HCVirt;
122static STAMPROFILE gStatHCVirt2GCPhys;
123static STAMCOUNTER gStatCpuGetTSC;
124static STAMCOUNTER gStatRefuseTFInhibit;
125static STAMCOUNTER gStatRefuseVM86;
126static STAMCOUNTER gStatRefusePaging;
127static STAMCOUNTER gStatRefusePAE;
128static STAMCOUNTER gStatRefuseIOPLNot0;
129static STAMCOUNTER gStatRefuseIF0;
130static STAMCOUNTER gStatRefuseCode16;
131static STAMCOUNTER gStatRefuseWP0;
132static STAMCOUNTER gStatRefuseRing1or2;
133static STAMCOUNTER gStatRefuseCanExecute;
134static STAMCOUNTER gStatREMGDTChange;
135static STAMCOUNTER gStatREMIDTChange;
136static STAMCOUNTER gStatREMLDTRChange;
137static STAMCOUNTER gStatREMTRChange;
138static STAMCOUNTER gStatSelOutOfSync[6];
139static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
140static STAMCOUNTER gStatFlushTBs;
141/* in exec.c */
142extern uint32_t tlb_flush_count;
143extern uint32_t tb_flush_count;
144extern uint32_t tb_phys_invalidate_count;
145#endif
146
147/*
148 * Global stuff.
149 */
150
151/** MMIO read callbacks. */
152CPUReadMemoryFunc *g_apfnMMIORead[3] =
153{
154 remR3MMIOReadU8,
155 remR3MMIOReadU16,
156 remR3MMIOReadU32
157};
158
159/** MMIO write callbacks. */
160CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
161{
162 remR3MMIOWriteU8,
163 remR3MMIOWriteU16,
164 remR3MMIOWriteU32
165};
166
167/** Handler read callbacks. */
168CPUReadMemoryFunc *g_apfnHandlerRead[3] =
169{
170 remR3HandlerReadU8,
171 remR3HandlerReadU16,
172 remR3HandlerReadU32
173};
174
175/** Handler write callbacks. */
176CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
177{
178 remR3HandlerWriteU8,
179 remR3HandlerWriteU16,
180 remR3HandlerWriteU32
181};
182
183
184#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
185/*
186 * Debugger commands.
187 */
188static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
189
190/** '.remstep' arguments. */
191static const DBGCVARDESC g_aArgRemStep[] =
192{
193 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
194 { 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
195};
196
197/** Command descriptors. */
198static const DBGCCMD g_aCmds[] =
199{
200 {
201 .pszCmd ="remstep",
202 .cArgsMin = 0,
203 .cArgsMax = 1,
204 .paArgDescs = &g_aArgRemStep[0],
205 .cArgDescs = RT_ELEMENTS(g_aArgRemStep),
206 .pResultDesc = NULL,
207 .fFlags = 0,
208 .pfnHandler = remR3CmdDisasEnableStepping,
209 .pszSyntax = "[on/off]",
210 .pszDescription = "Enable or disable the single stepping with logged disassembly. "
211 "If no arguments show the current state."
212 }
213};
214#endif
215
216
217/* Instantiate the structure signatures. */
218#define REM_STRUCT_OP 0
219#include "Sun/structs.h"
220
221
222
223/*******************************************************************************
224* Internal Functions *
225*******************************************************************************/
226static void remAbort(int rc, const char *pszTip);
227extern int testmath(void);
228
229/* Put them here to avoid unused variable warning. */
230AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
231#if !defined(IPRT_NO_CRT) && (defined(RT_OS_LINUX) || defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS))
232//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
233/* Why did this have to be identical?? */
234AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
235#else
236AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
237#endif
238
239
240/**
241 * Initializes the REM.
242 *
243 * @returns VBox status code.
244 * @param pVM The VM to operate on.
245 */
246REMR3DECL(int) REMR3Init(PVM pVM)
247{
248 uint32_t u32Dummy;
249 unsigned i;
250
251 /*
252 * Assert sanity.
253 */
254 AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
255 AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
256 AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
257#if defined(DEBUG) && !defined(RT_OS_SOLARIS) /// @todo fix the solaris math stuff.
258 Assert(!testmath());
259#endif
260 ASSERT_STRUCT_TABLE(Misc);
261 ASSERT_STRUCT_TABLE(TLB);
262 ASSERT_STRUCT_TABLE(SegmentCache);
263 ASSERT_STRUCT_TABLE(XMMReg);
264 ASSERT_STRUCT_TABLE(MMXReg);
265 ASSERT_STRUCT_TABLE(float_status);
266 ASSERT_STRUCT_TABLE(float32u);
267 ASSERT_STRUCT_TABLE(float64u);
268 ASSERT_STRUCT_TABLE(floatx80u);
269 ASSERT_STRUCT_TABLE(CPUState);
270
271 /*
272 * Init some internal data members.
273 */
274 pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
275 pVM->rem.s.Env.pVM = pVM;
276#ifdef CPU_RAW_MODE_INIT
277 pVM->rem.s.state |= CPU_RAW_MODE_INIT;
278#endif
279
280 /* ctx. */
281 pVM->rem.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
282 AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
283
284 /* ignore all notifications */
285 pVM->rem.s.fIgnoreAll = true;
286
287 /*
288 * Init the recompiler.
289 */
290 if (!cpu_x86_init(&pVM->rem.s.Env))
291 {
292 AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
293 return VERR_GENERAL_FAILURE;
294 }
295 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
296 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext3_features, &pVM->rem.s.Env.cpuid_ext2_features);
297
298 /* allocate code buffer for single instruction emulation. */
299 pVM->rem.s.Env.cbCodeBuffer = 4096;
300 pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
301 AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
302
303 /* finally, set the cpu_single_env global. */
304 cpu_single_env = &pVM->rem.s.Env;
305
306 /* Nothing is pending by default */
307 pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
308
309 /*
310 * Register ram types.
311 */
312 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(-1, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
313 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
314 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(-1, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
315 AssertReleaseMsg(pVM->rem.s.iHandlerMemType >= 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
316 Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
317
318 /* stop ignoring. */
319 pVM->rem.s.fIgnoreAll = false;
320
321 /*
322 * Register the saved state data unit.
323 */
324 int rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
325 NULL, remR3Save, NULL,
326 NULL, remR3Load, NULL);
327 if (RT_FAILURE(rc))
328 return rc;
329
330#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
331 /*
332 * Debugger commands.
333 */
334 static bool fRegisteredCmds = false;
335 if (!fRegisteredCmds)
336 {
337 int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
338 if (RT_SUCCESS(rc))
339 fRegisteredCmds = true;
340 }
341#endif
342
343#ifdef VBOX_WITH_STATISTICS
344 /*
345 * Statistics.
346 */
347 STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
348 STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
349 STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
350 STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
351 STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
352 STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
353 STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
354 STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
355 STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
356 STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
357 STAM_REG(pVM, &gStatHCVirt2GCPhys, STAMTYPE_PROFILE, "/PROF/REM/HCVirt2GCPhys", STAMUNIT_TICKS_PER_CALL, "Profiling memory convertion.");
358 STAM_REG(pVM, &gStatGCPhys2HCVirt, STAMTYPE_PROFILE, "/PROF/REM/GCPhys2HCVirt", STAMUNIT_TICKS_PER_CALL, "Profiling memory convertion.");
359
360 STAM_REG(pVM, &gStatCpuGetTSC, STAMTYPE_COUNTER, "/REM/CpuGetTSC", STAMUNIT_OCCURENCES, "cpu_get_tsc calls");
361
362 STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
363 STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
364 STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
365 STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
366 STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
367 STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
368 STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
369 STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
370 STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
371 STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
372 STAM_REG(pVM, &gStatFlushTBs, STAMTYPE_COUNTER, "/REM/FlushTB", STAMUNIT_OCCURENCES, "Number of TB flushes");
373
374 STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
375 STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
376 STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
377 STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
378
379 STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
380 STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
381 STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
382 STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
383 STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
384 STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
385
386 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
387 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
388 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
389 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
390 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
391 STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
392
393 STAM_REG(pVM, &tb_flush_count, STAMTYPE_U32_RESET, "/REM/TbFlushCount", STAMUNIT_OCCURENCES, "tb_flush() calls");
394 STAM_REG(pVM, &tb_phys_invalidate_count,STAMTYPE_U32_RESET, "/REM/TbPhysInvldCount", STAMUNIT_OCCURENCES, "tb_phys_invalidate() calls");
395 STAM_REG(pVM, &tlb_flush_count, STAMTYPE_U32_RESET, "/REM/TlbFlushCount", STAMUNIT_OCCURENCES, "tlb_flush() calls");
396
397
398#endif
399
400#ifdef DEBUG_ALL_LOGGING
401 loglevel = ~0;
402#endif
403
404 return rc;
405}
406
407
408/**
409 * Terminates the REM.
410 *
411 * Termination means cleaning up and freeing all resources,
412 * the VM it self is at this point powered off or suspended.
413 *
414 * @returns VBox status code.
415 * @param pVM The VM to operate on.
416 */
417REMR3DECL(int) REMR3Term(PVM pVM)
418{
419 return VINF_SUCCESS;
420}
421
422
423/**
424 * The VM is being reset.
425 *
426 * For the REM component this means to call the cpu_reset() and
427 * reinitialize some state variables.
428 *
429 * @param pVM VM handle.
430 */
431REMR3DECL(void) REMR3Reset(PVM pVM)
432{
433 /*
434 * Reset the REM cpu.
435 */
436 pVM->rem.s.fIgnoreAll = true;
437 cpu_reset(&pVM->rem.s.Env);
438 pVM->rem.s.cInvalidatedPages = 0;
439 pVM->rem.s.fIgnoreAll = false;
440
441 /* Clear raw ring 0 init state */
442 pVM->rem.s.Env.state &= ~CPU_RAW_RING0;
443
444 /* Flush the TBs the next time we execute code here. */
445 pVM->rem.s.fFlushTBs = true;
446}
447
448
449/**
450 * Execute state save operation.
451 *
452 * @returns VBox status code.
453 * @param pVM VM Handle.
454 * @param pSSM SSM operation handle.
455 */
456static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
457{
458 LogFlow(("remR3Save:\n"));
459
460 /*
461 * Save the required CPU Env bits.
462 * (Not much because we're never in REM when doing the save.)
463 */
464 PREM pRem = &pVM->rem.s;
465 Assert(!pRem->fInREM);
466 SSMR3PutU32(pSSM, pRem->Env.hflags);
467 SSMR3PutU32(pSSM, ~0); /* separator */
468
469 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
470 SSMR3PutU32(pSSM, !!(pRem->Env.state & CPU_RAW_RING0));
471 SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
472
473 return SSMR3PutU32(pSSM, ~0); /* terminator */
474}
475
476
477/**
478 * Execute state load operation.
479 *
480 * @returns VBox status code.
481 * @param pVM VM Handle.
482 * @param pSSM SSM operation handle.
483 * @param u32Version Data layout version.
484 */
485static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
486{
487 uint32_t u32Dummy;
488 uint32_t fRawRing0 = false;
489 LogFlow(("remR3Load:\n"));
490
491 /*
492 * Validate version.
493 */
494 if ( u32Version != REM_SAVED_STATE_VERSION
495 && u32Version != REM_SAVED_STATE_VERSION_VER1_6)
496 {
497 AssertMsgFailed(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
498 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
499 }
500
501 /*
502 * Do a reset to be on the safe side...
503 */
504 REMR3Reset(pVM);
505
506 /*
507 * Ignore all ignorable notifications.
508 * (Not doing this will cause serious trouble.)
509 */
510 pVM->rem.s.fIgnoreAll = true;
511
512 /*
513 * Load the required CPU Env bits.
514 * (Not much because we're never in REM when doing the save.)
515 */
516 PREM pRem = &pVM->rem.s;
517 Assert(!pRem->fInREM);
518 SSMR3GetU32(pSSM, &pRem->Env.hflags);
519 if (u32Version == REM_SAVED_STATE_VERSION_VER1_6)
520 {
521 /* Redundant REM CPU state has to be loaded, but can be ignored. */
522 CPUX86State_Ver16 temp;
523 SSMR3GetMem(pSSM, &temp, RT_OFFSETOF(CPUX86State_Ver16, jmp_env));
524 }
525
526 uint32_t u32Sep;
527 int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
528 if (RT_FAILURE(rc))
529 return rc;
530 if (u32Sep != ~0U)
531 {
532 AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
533 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
534 }
535
536 /* Remember if we've entered raw mode (vital for ring 1 checks in e.g. iret emulation). */
537 SSMR3GetUInt(pSSM, &fRawRing0);
538 if (fRawRing0)
539 pRem->Env.state |= CPU_RAW_RING0;
540
541 if (u32Version == REM_SAVED_STATE_VERSION_VER1_6)
542 {
543 /*
544 * Load the REM stuff.
545 */
546 rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
547 if (RT_FAILURE(rc))
548 return rc;
549 if (pRem->cInvalidatedPages > RT_ELEMENTS(pRem->aGCPtrInvalidatedPages))
550 {
551 AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
552 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
553 }
554 unsigned i;
555 for (i = 0; i < pRem->cInvalidatedPages; i++)
556 SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
557 }
558
559 rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
560 if (RT_FAILURE(rc))
561 return rc;
562
563 /* check the terminator. */
564 rc = SSMR3GetU32(pSSM, &u32Sep);
565 if (RT_FAILURE(rc))
566 return rc;
567 if (u32Sep != ~0U)
568 {
569 AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
570 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
571 }
572
573 /*
574 * Get the CPUID features.
575 */
576 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
577 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
578
579 /*
580 * Sync the Load Flush the TLB
581 */
582 tlb_flush(&pRem->Env, 1);
583
584 /*
585 * Stop ignoring ignornable notifications.
586 */
587 pVM->rem.s.fIgnoreAll = false;
588
589 /*
590 * Sync the whole CPU state when executing code in the recompiler.
591 */
592 CPUMSetChangedFlags(pVM, CPUM_CHANGED_ALL);
593 return VINF_SUCCESS;
594}
595
596
597
598#undef LOG_GROUP
599#define LOG_GROUP LOG_GROUP_REM_RUN
600
601/**
602 * Single steps an instruction in recompiled mode.
603 *
604 * Before calling this function the REM state needs to be in sync with
605 * the VM. Call REMR3State() to perform the sync. It's only necessary
606 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
607 * and after calling REMR3StateBack().
608 *
609 * @returns VBox status code.
610 *
611 * @param pVM VM Handle.
612 */
613REMR3DECL(int) REMR3Step(PVM pVM)
614{
615 /*
616 * Lock the REM - we don't wanna have anyone interrupting us
617 * while stepping - and enabled single stepping. We also ignore
618 * pending interrupts and suchlike.
619 */
620 int interrupt_request = pVM->rem.s.Env.interrupt_request;
621 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER)));
622 pVM->rem.s.Env.interrupt_request = 0;
623 cpu_single_step(&pVM->rem.s.Env, 1);
624
625 /*
626 * If we're standing at a breakpoint, that have to be disabled before we start stepping.
627 */
628 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
629 bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
630
631 /*
632 * Execute and handle the return code.
633 * We execute without enabling the cpu tick, so on success we'll
634 * just flip it on and off to make sure it moves
635 */
636 int rc = cpu_exec(&pVM->rem.s.Env);
637 if (rc == EXCP_DEBUG)
638 {
639 TMCpuTickResume(pVM);
640 TMCpuTickPause(pVM);
641 TMVirtualResume(pVM);
642 TMVirtualPause(pVM);
643 rc = VINF_EM_DBG_STEPPED;
644 }
645 else
646 {
647 AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
648 switch (rc)
649 {
650 case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
651 case EXCP_HLT:
652 case EXCP_HALTED: rc = VINF_EM_HALT; break;
653 case EXCP_RC:
654 rc = pVM->rem.s.rc;
655 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
656 break;
657 default:
658 AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
659 rc = VERR_INTERNAL_ERROR;
660 break;
661 }
662 }
663
664 /*
665 * Restore the stuff we changed to prevent interruption.
666 * Unlock the REM.
667 */
668 if (fBp)
669 {
670 int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
671 Assert(rc2 == 0); NOREF(rc2);
672 }
673 cpu_single_step(&pVM->rem.s.Env, 0);
674 pVM->rem.s.Env.interrupt_request = interrupt_request;
675
676 return rc;
677}
678
679
680/**
681 * Set a breakpoint using the REM facilities.
682 *
683 * @returns VBox status code.
684 * @param pVM The VM handle.
685 * @param Address The breakpoint address.
686 * @thread The emulation thread.
687 */
688REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
689{
690 VM_ASSERT_EMT(pVM);
691 if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
692 {
693 LogFlow(("REMR3BreakpointSet: Address=%RGv\n", Address));
694 return VINF_SUCCESS;
695 }
696 LogFlow(("REMR3BreakpointSet: Address=%RGv - failed!\n", Address));
697 return VERR_REM_NO_MORE_BP_SLOTS;
698}
699
700
701/**
702 * Clears a breakpoint set by REMR3BreakpointSet().
703 *
704 * @returns VBox status code.
705 * @param pVM The VM handle.
706 * @param Address The breakpoint address.
707 * @thread The emulation thread.
708 */
709REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
710{
711 VM_ASSERT_EMT(pVM);
712 if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
713 {
714 LogFlow(("REMR3BreakpointClear: Address=%RGv\n", Address));
715 return VINF_SUCCESS;
716 }
717 LogFlow(("REMR3BreakpointClear: Address=%RGv - not found!\n", Address));
718 return VERR_REM_BP_NOT_FOUND;
719}
720
721
722/**
723 * Emulate an instruction.
724 *
725 * This function executes one instruction without letting anyone
726 * interrupt it. This is intended for being called while being in
727 * raw mode and thus will take care of all the state syncing between
728 * REM and the rest.
729 *
730 * @returns VBox status code.
731 * @param pVM VM handle.
732 */
733REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
734{
735 bool fFlushTBs;
736
737 Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
738
739 /* Make sure this flag is set; we might never execute remR3CanExecuteRaw in the AMD-V case.
740 * CPU_RAW_HWACC makes sure we never execute interrupt handlers in the recompiler.
741 */
742 if (HWACCMIsEnabled(pVM))
743 pVM->rem.s.Env.state |= CPU_RAW_HWACC;
744
745 /* Skip the TB flush as that's rather expensive and not necessary for single instruction emulation. */
746 fFlushTBs = pVM->rem.s.fFlushTBs;
747 pVM->rem.s.fFlushTBs = false;
748
749 /*
750 * Sync the state and enable single instruction / single stepping.
751 */
752 int rc = REMR3State(pVM);
753 pVM->rem.s.fFlushTBs = fFlushTBs;
754 if (RT_SUCCESS(rc))
755 {
756 int interrupt_request = pVM->rem.s.Env.interrupt_request;
757 Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER | CPU_INTERRUPT_EXTERNAL_HARD | CPU_INTERRUPT_EXTERNAL_EXIT | CPU_INTERRUPT_EXTERNAL_TIMER)));
758 Assert(!pVM->rem.s.Env.singlestep_enabled);
759#if 1
760
761 /*
762 * Now we set the execute single instruction flag and enter the cpu_exec loop.
763 */
764 TMNotifyStartOfExecution(pVM);
765 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
766 rc = cpu_exec(&pVM->rem.s.Env);
767 TMNotifyEndOfExecution(pVM);
768 switch (rc)
769 {
770 /*
771 * Executed without anything out of the way happening.
772 */
773 case EXCP_SINGLE_INSTR:
774 rc = VINF_EM_RESCHEDULE;
775 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
776 break;
777
778 /*
779 * If we take a trap or start servicing a pending interrupt, we might end up here.
780 * (Timer thread or some other thread wishing EMT's attention.)
781 */
782 case EXCP_INTERRUPT:
783 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
784 rc = VINF_EM_RESCHEDULE;
785 break;
786
787 /*
788 * Single step, we assume!
789 * If there was a breakpoint there we're fucked now.
790 */
791 case EXCP_DEBUG:
792 {
793 /* breakpoint or single step? */
794 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
795 int iBP;
796 rc = VINF_EM_DBG_STEPPED;
797 for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
798 if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
799 {
800 rc = VINF_EM_DBG_BREAKPOINT;
801 break;
802 }
803 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc iBP=%d GCPtrPC=%RGv\n", rc, iBP, GCPtrPC));
804 break;
805 }
806
807 /*
808 * hlt instruction.
809 */
810 case EXCP_HLT:
811 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
812 rc = VINF_EM_HALT;
813 break;
814
815 /*
816 * The VM has halted.
817 */
818 case EXCP_HALTED:
819 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
820 rc = VINF_EM_HALT;
821 break;
822
823 /*
824 * Switch to RAW-mode.
825 */
826 case EXCP_EXECUTE_RAW:
827 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
828 rc = VINF_EM_RESCHEDULE_RAW;
829 break;
830
831 /*
832 * Switch to hardware accelerated RAW-mode.
833 */
834 case EXCP_EXECUTE_HWACC:
835 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
836 rc = VINF_EM_RESCHEDULE_HWACC;
837 break;
838
839 /*
840 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
841 */
842 case EXCP_RC:
843 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
844 rc = pVM->rem.s.rc;
845 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
846 break;
847
848 /*
849 * Figure out the rest when they arrive....
850 */
851 default:
852 AssertMsgFailed(("rc=%d\n", rc));
853 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
854 rc = VINF_EM_RESCHEDULE;
855 break;
856 }
857
858 /*
859 * Switch back the state.
860 */
861#else
862 pVM->rem.s.Env.interrupt_request = 0;
863 cpu_single_step(&pVM->rem.s.Env, 1);
864
865 /*
866 * Execute and handle the return code.
867 * We execute without enabling the cpu tick, so on success we'll
868 * just flip it on and off to make sure it moves.
869 *
870 * (We do not use emulate_single_instr() because that doesn't enter the
871 * right way in will cause serious trouble if a longjmp was attempted.)
872 */
873# ifdef DEBUG_bird
874 remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
875# endif
876 TMNotifyStartOfExecution(pVM);
877 int cTimesMax = 16384;
878 uint32_t eip = pVM->rem.s.Env.eip;
879 do
880 {
881 rc = cpu_exec(&pVM->rem.s.Env);
882
883 } while ( eip == pVM->rem.s.Env.eip
884 && (rc == EXCP_DEBUG || rc == EXCP_EXECUTE_RAW)
885 && --cTimesMax > 0);
886 TMNotifyEndOfExecution(pVM);
887 switch (rc)
888 {
889 /*
890 * Single step, we assume!
891 * If there was a breakpoint there we're fucked now.
892 */
893 case EXCP_DEBUG:
894 {
895 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
896 rc = VINF_EM_RESCHEDULE;
897 break;
898 }
899
900 /*
901 * We cannot be interrupted!
902 */
903 case EXCP_INTERRUPT:
904 AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
905 rc = VERR_INTERNAL_ERROR;
906 break;
907
908 /*
909 * hlt instruction.
910 */
911 case EXCP_HLT:
912 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
913 rc = VINF_EM_HALT;
914 break;
915
916 /*
917 * The VM has halted.
918 */
919 case EXCP_HALTED:
920 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HALTED\n"));
921 rc = VINF_EM_HALT;
922 break;
923
924 /*
925 * Switch to RAW-mode.
926 */
927 case EXCP_EXECUTE_RAW:
928 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
929 rc = VINF_EM_RESCHEDULE_RAW;
930 break;
931
932 /*
933 * Switch to hardware accelerated RAW-mode.
934 */
935 case EXCP_EXECUTE_HWACC:
936 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
937 rc = VINF_EM_RESCHEDULE_HWACC;
938 break;
939
940 /*
941 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
942 */
943 case EXCP_RC:
944 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
945 rc = pVM->rem.s.rc;
946 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
947 break;
948
949 /*
950 * Figure out the rest when they arrive....
951 */
952 default:
953 AssertMsgFailed(("rc=%d\n", rc));
954 Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
955 rc = VINF_SUCCESS;
956 break;
957 }
958
959 /*
960 * Switch back the state.
961 */
962 cpu_single_step(&pVM->rem.s.Env, 0);
963#endif
964 pVM->rem.s.Env.interrupt_request = interrupt_request;
965 int rc2 = REMR3StateBack(pVM);
966 AssertRC(rc2);
967 }
968
969 Log2(("REMR3EmulateInstruction: returns %Rrc (cs:eip=%04x:%RGv)\n",
970 rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
971 return rc;
972}
973
974
975/**
976 * Runs code in recompiled mode.
977 *
978 * Before calling this function the REM state needs to be in sync with
979 * the VM. Call REMR3State() to perform the sync. It's only necessary
980 * (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
981 * and after calling REMR3StateBack().
982 *
983 * @returns VBox status code.
984 *
985 * @param pVM VM Handle.
986 */
987REMR3DECL(int) REMR3Run(PVM pVM)
988{
989 Log2(("REMR3Run: (cs:eip=%04x:%RGv)\n", pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
990 Assert(pVM->rem.s.fInREM);
991
992 TMNotifyStartOfExecution(pVM);
993 int rc = cpu_exec(&pVM->rem.s.Env);
994 TMNotifyEndOfExecution(pVM);
995 switch (rc)
996 {
997 /*
998 * This happens when the execution was interrupted
999 * by an external event, like pending timers.
1000 */
1001 case EXCP_INTERRUPT:
1002 Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
1003 rc = VINF_SUCCESS;
1004 break;
1005
1006 /*
1007 * hlt instruction.
1008 */
1009 case EXCP_HLT:
1010 Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
1011 rc = VINF_EM_HALT;
1012 break;
1013
1014 /*
1015 * The VM has halted.
1016 */
1017 case EXCP_HALTED:
1018 Log2(("REMR3Run: cpu_exec -> EXCP_HALTED\n"));
1019 rc = VINF_EM_HALT;
1020 break;
1021
1022 /*
1023 * Breakpoint/single step.
1024 */
1025 case EXCP_DEBUG:
1026 {
1027#if 0//def DEBUG_bird
1028 static int iBP = 0;
1029 printf("howdy, breakpoint! iBP=%d\n", iBP);
1030 switch (iBP)
1031 {
1032 case 0:
1033 cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
1034 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
1035 //pVM->rem.s.Env.interrupt_request = 0;
1036 //pVM->rem.s.Env.exception_index = -1;
1037 //g_fInterruptDisabled = 1;
1038 rc = VINF_SUCCESS;
1039 asm("int3");
1040 break;
1041 default:
1042 asm("int3");
1043 break;
1044 }
1045 iBP++;
1046#else
1047 /* breakpoint or single step? */
1048 RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
1049 int iBP;
1050 rc = VINF_EM_DBG_STEPPED;
1051 for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
1052 if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
1053 {
1054 rc = VINF_EM_DBG_BREAKPOINT;
1055 break;
1056 }
1057 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc iBP=%d GCPtrPC=%RGv\n", rc, iBP, GCPtrPC));
1058#endif
1059 break;
1060 }
1061
1062 /*
1063 * Switch to RAW-mode.
1064 */
1065 case EXCP_EXECUTE_RAW:
1066 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1067 rc = VINF_EM_RESCHEDULE_RAW;
1068 break;
1069
1070 /*
1071 * Switch to hardware accelerated RAW-mode.
1072 */
1073 case EXCP_EXECUTE_HWACC:
1074 Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1075 rc = VINF_EM_RESCHEDULE_HWACC;
1076 break;
1077
1078#ifdef VBOX_WITH_VMI
1079 /*
1080 *
1081 */
1082 case EXCP_PARAV_CALL:
1083 Log2(("REMR3Run: cpu_exec -> EXCP_PARAV_CALL\n"));
1084 rc = VINF_EM_RESCHEDULE_PARAV;
1085 break;
1086#endif
1087
1088 /*
1089 * An EM RC was raised (VMR3Reset/Suspend/PowerOff/some-fatal-error).
1090 */
1091 case EXCP_RC:
1092 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc));
1093 rc = pVM->rem.s.rc;
1094 pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1095 break;
1096
1097 /*
1098 * Figure out the rest when they arrive....
1099 */
1100 default:
1101 AssertMsgFailed(("rc=%d\n", rc));
1102 Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1103 rc = VINF_SUCCESS;
1104 break;
1105 }
1106
1107 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%RGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, (RTGCPTR)pVM->rem.s.Env.eip));
1108 return rc;
1109}
1110
1111
1112/**
1113 * Check if the cpu state is suitable for Raw execution.
1114 *
1115 * @returns boolean
1116 * @param env The CPU env struct.
1117 * @param eip The EIP to check this for (might differ from env->eip).
1118 * @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1119 * @param piException Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1120 *
1121 * @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1122 */
1123bool remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, int *piException)
1124{
1125 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1126 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1127 /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1128
1129 /* Update counter. */
1130 env->pVM->rem.s.cCanExecuteRaw++;
1131
1132 if (HWACCMIsEnabled(env->pVM))
1133 {
1134 env->state |= CPU_RAW_HWACC;
1135
1136 /*
1137 * Create partial context for HWACCMR3CanExecuteGuest
1138 */
1139 CPUMCTX Ctx;
1140 Ctx.cr0 = env->cr[0];
1141 Ctx.cr3 = env->cr[3];
1142 Ctx.cr4 = env->cr[4];
1143
1144 Ctx.tr = env->tr.selector;
1145 Ctx.trHid.u64Base = env->tr.base;
1146 Ctx.trHid.u32Limit = env->tr.limit;
1147 Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1148
1149 Ctx.idtr.cbIdt = env->idt.limit;
1150 Ctx.idtr.pIdt = env->idt.base;
1151
1152 Ctx.eflags.u32 = env->eflags;
1153
1154 Ctx.cs = env->segs[R_CS].selector;
1155 Ctx.csHid.u64Base = env->segs[R_CS].base;
1156 Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1157 Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1158
1159 Ctx.ds = env->segs[R_DS].selector;
1160 Ctx.dsHid.u64Base = env->segs[R_DS].base;
1161 Ctx.dsHid.u32Limit = env->segs[R_DS].limit;
1162 Ctx.dsHid.Attr.u = (env->segs[R_DS].flags >> 8) & 0xF0FF;
1163
1164 Ctx.es = env->segs[R_ES].selector;
1165 Ctx.esHid.u64Base = env->segs[R_ES].base;
1166 Ctx.esHid.u32Limit = env->segs[R_ES].limit;
1167 Ctx.esHid.Attr.u = (env->segs[R_ES].flags >> 8) & 0xF0FF;
1168
1169 Ctx.fs = env->segs[R_FS].selector;
1170 Ctx.fsHid.u64Base = env->segs[R_FS].base;
1171 Ctx.fsHid.u32Limit = env->segs[R_FS].limit;
1172 Ctx.fsHid.Attr.u = (env->segs[R_FS].flags >> 8) & 0xF0FF;
1173
1174 Ctx.gs = env->segs[R_GS].selector;
1175 Ctx.gsHid.u64Base = env->segs[R_GS].base;
1176 Ctx.gsHid.u32Limit = env->segs[R_GS].limit;
1177 Ctx.gsHid.Attr.u = (env->segs[R_GS].flags >> 8) & 0xF0FF;
1178
1179 Ctx.ss = env->segs[R_SS].selector;
1180 Ctx.ssHid.u64Base = env->segs[R_SS].base;
1181 Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1182 Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1183
1184 Ctx.msrEFER = env->efer;
1185
1186 /* Hardware accelerated raw-mode:
1187 *
1188 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1189 */
1190 if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1191 {
1192 *piException = EXCP_EXECUTE_HWACC;
1193 return true;
1194 }
1195 return false;
1196 }
1197
1198 /*
1199 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1200 * or 32 bits protected mode ring 0 code
1201 *
1202 * The tests are ordered by the likelyhood of being true during normal execution.
1203 */
1204 if (fFlags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))
1205 {
1206 STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1207 Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1208 return false;
1209 }
1210
1211#ifndef VBOX_RAW_V86
1212 if (fFlags & VM_MASK) {
1213 STAM_COUNTER_INC(&gStatRefuseVM86);
1214 Log2(("raw mode refused: VM_MASK\n"));
1215 return false;
1216 }
1217#endif
1218
1219 if (env->state & CPU_EMULATE_SINGLE_INSTR)
1220 {
1221#ifndef DEBUG_bird
1222 Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1223#endif
1224 return false;
1225 }
1226
1227 if (env->singlestep_enabled)
1228 {
1229 //Log2(("raw mode refused: Single step\n"));
1230 return false;
1231 }
1232
1233 if (env->nb_breakpoints > 0)
1234 {
1235 //Log2(("raw mode refused: Breakpoints\n"));
1236 return false;
1237 }
1238
1239 uint32_t u32CR0 = env->cr[0];
1240 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1241 {
1242 STAM_COUNTER_INC(&gStatRefusePaging);
1243 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1244 return false;
1245 }
1246
1247 if (env->cr[4] & CR4_PAE_MASK)
1248 {
1249 if (!(env->cpuid_features & X86_CPUID_FEATURE_EDX_PAE))
1250 {
1251 STAM_COUNTER_INC(&gStatRefusePAE);
1252 return false;
1253 }
1254 }
1255
1256 if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1257 {
1258 if (!EMIsRawRing3Enabled(env->pVM))
1259 return false;
1260
1261 if (!(env->eflags & IF_MASK))
1262 {
1263 STAM_COUNTER_INC(&gStatRefuseIF0);
1264 Log2(("raw mode refused: IF (RawR3)\n"));
1265 return false;
1266 }
1267
1268 if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1269 {
1270 STAM_COUNTER_INC(&gStatRefuseWP0);
1271 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1272 return false;
1273 }
1274 }
1275 else
1276 {
1277 if (!EMIsRawRing0Enabled(env->pVM))
1278 return false;
1279
1280 // Let's start with pure 32 bits ring 0 code first
1281 if ((fFlags & (HF_SS32_MASK | HF_CS32_MASK)) != (HF_SS32_MASK | HF_CS32_MASK))
1282 {
1283 STAM_COUNTER_INC(&gStatRefuseCode16);
1284 Log2(("raw r0 mode refused: HF_[S|C]S32_MASK fFlags=%#x\n", fFlags));
1285 return false;
1286 }
1287
1288 // Only R0
1289 if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1290 {
1291 STAM_COUNTER_INC(&gStatRefuseRing1or2);
1292 Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1293 return false;
1294 }
1295
1296 if (!(u32CR0 & CR0_WP_MASK))
1297 {
1298 STAM_COUNTER_INC(&gStatRefuseWP0);
1299 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1300 return false;
1301 }
1302
1303 if (PATMIsPatchGCAddr(env->pVM, eip))
1304 {
1305 Log2(("raw r0 mode forced: patch code\n"));
1306 *piException = EXCP_EXECUTE_RAW;
1307 return true;
1308 }
1309
1310#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1311 if (!(env->eflags & IF_MASK))
1312 {
1313 STAM_COUNTER_INC(&gStatRefuseIF0);
1314 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1315 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1316 return false;
1317 }
1318#endif
1319
1320 env->state |= CPU_RAW_RING0;
1321 }
1322
1323 /*
1324 * Don't reschedule the first time we're called, because there might be
1325 * special reasons why we're here that is not covered by the above checks.
1326 */
1327 if (env->pVM->rem.s.cCanExecuteRaw == 1)
1328 {
1329 Log2(("raw mode refused: first scheduling\n"));
1330 STAM_COUNTER_INC(&gStatRefuseCanExecute);
1331 return false;
1332 }
1333
1334 Assert(PGMPhysIsA20Enabled(env->pVM));
1335 *piException = EXCP_EXECUTE_RAW;
1336 return true;
1337}
1338
1339
1340/**
1341 * Fetches a code byte.
1342 *
1343 * @returns Success indicator (bool) for ease of use.
1344 * @param env The CPU environment structure.
1345 * @param GCPtrInstr Where to fetch code.
1346 * @param pu8Byte Where to store the byte on success
1347 */
1348bool remR3GetOpcode(CPUState *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte)
1349{
1350 int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1351 if (RT_SUCCESS(rc))
1352 return true;
1353 return false;
1354}
1355
1356
1357/**
1358 * Flush (or invalidate if you like) page table/dir entry.
1359 *
1360 * (invlpg instruction; tlb_flush_page)
1361 *
1362 * @param env Pointer to cpu environment.
1363 * @param GCPtr The virtual address which page table/dir entry should be invalidated.
1364 */
1365void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1366{
1367 PVM pVM = env->pVM;
1368
1369 /*
1370 * When we're replaying invlpg instructions or restoring a saved
1371 * state we disable this path.
1372 */
1373 if (pVM->rem.s.fIgnoreInvlPg || pVM->rem.s.fIgnoreAll)
1374 return;
1375 Log(("remR3FlushPage: GCPtr=%RGv\n", GCPtr));
1376 Assert(pVM->rem.s.fInREM || pVM->rem.s.fInStateSync);
1377
1378 //RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1379
1380 /*
1381 * Update the control registers before calling PGMFlushPage.
1382 */
1383 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1384 pCtx->cr0 = env->cr[0];
1385 pCtx->cr3 = env->cr[3];
1386 pCtx->cr4 = env->cr[4];
1387
1388 /*
1389 * Let PGM do the rest.
1390 */
1391 int rc = PGMInvalidatePage(pVM, GCPtr);
1392 if (RT_FAILURE(rc))
1393 {
1394 AssertMsgFailed(("remR3FlushPage %RGv failed with %d!!\n", GCPtr, rc));
1395 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1396 }
1397 //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1398}
1399
1400
1401/**
1402 * Called from tlb_protect_code in order to write monitor a code page.
1403 *
1404 * @param env Pointer to the CPU environment.
1405 * @param GCPtr Code page to monitor
1406 */
1407void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1408{
1409#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1410 Assert(env->pVM->rem.s.fInREM);
1411 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1412 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1413 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1414 && !(env->eflags & VM_MASK) /* no V86 mode */
1415 && !HWACCMIsEnabled(env->pVM))
1416 CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1417#endif
1418}
1419
1420/**
1421 * Called from tlb_unprotect_code in order to clear write monitoring for a code page.
1422 *
1423 * @param env Pointer to the CPU environment.
1424 * @param GCPtr Code page to monitor
1425 */
1426void remR3UnprotectCode(CPUState *env, RTGCPTR GCPtr)
1427{
1428 Assert(env->pVM->rem.s.fInREM);
1429#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
1430 if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1431 && !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1432 && (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1433 && !(env->eflags & VM_MASK) /* no V86 mode */
1434 && !HWACCMIsEnabled(env->pVM))
1435 CSAMR3UnmonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1436#endif
1437}
1438
1439
1440/**
1441 * Called when the CPU is initialized, any of the CRx registers are changed or
1442 * when the A20 line is modified.
1443 *
1444 * @param env Pointer to the CPU environment.
1445 * @param fGlobal Set if the flush is global.
1446 */
1447void remR3FlushTLB(CPUState *env, bool fGlobal)
1448{
1449 PVM pVM = env->pVM;
1450
1451 /*
1452 * When we're replaying invlpg instructions or restoring a saved
1453 * state we disable this path.
1454 */
1455 if (pVM->rem.s.fIgnoreCR3Load || pVM->rem.s.fIgnoreAll)
1456 return;
1457 Assert(pVM->rem.s.fInREM);
1458
1459 /*
1460 * The caller doesn't check cr4, so we have to do that for ourselves.
1461 */
1462 if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1463 fGlobal = true;
1464 Log(("remR3FlushTLB: CR0=%RGr CR3=%RGr CR4=%RGr %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1465
1466 /*
1467 * Update the control registers before calling PGMR3FlushTLB.
1468 */
1469 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1470 pCtx->cr0 = env->cr[0];
1471 pCtx->cr3 = env->cr[3];
1472 pCtx->cr4 = env->cr[4];
1473
1474 /*
1475 * Let PGM do the rest.
1476 */
1477 PGMFlushTLB(pVM, env->cr[3], fGlobal);
1478}
1479
1480
1481/**
1482 * Called when any of the cr0, cr4 or efer registers is updated.
1483 *
1484 * @param env Pointer to the CPU environment.
1485 */
1486void remR3ChangeCpuMode(CPUState *env)
1487{
1488 int rc;
1489 PVM pVM = env->pVM;
1490
1491 /*
1492 * When we're replaying loads or restoring a saved
1493 * state this path is disabled.
1494 */
1495 if (pVM->rem.s.fIgnoreCpuMode || pVM->rem.s.fIgnoreAll)
1496 return;
1497 Assert(pVM->rem.s.fInREM);
1498
1499 /*
1500 * Update the control registers before calling PGMChangeMode()
1501 * as it may need to map whatever cr3 is pointing to.
1502 */
1503 PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1504 pCtx->cr0 = env->cr[0];
1505 pCtx->cr3 = env->cr[3];
1506 pCtx->cr4 = env->cr[4];
1507
1508#ifdef TARGET_X86_64
1509 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1510 if (rc != VINF_SUCCESS)
1511 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], env->efer, rc);
1512#else
1513 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1514 if (rc != VINF_SUCCESS)
1515 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], 0LL, rc);
1516#endif
1517}
1518
1519
1520/**
1521 * Called from compiled code to run dma.
1522 *
1523 * @param env Pointer to the CPU environment.
1524 */
1525void remR3DmaRun(CPUState *env)
1526{
1527 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1528 PDMR3DmaRun(env->pVM);
1529 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1530}
1531
1532
1533/**
1534 * Called from compiled code to schedule pending timers in VMM
1535 *
1536 * @param env Pointer to the CPU environment.
1537 */
1538void remR3TimersRun(CPUState *env)
1539{
1540 remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1541 remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1542 TMR3TimerQueuesDo(env->pVM);
1543 remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1544 remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1545}
1546
1547
1548/**
1549 * Record trap occurance
1550 *
1551 * @returns VBox status code
1552 * @param env Pointer to the CPU environment.
1553 * @param uTrap Trap nr
1554 * @param uErrorCode Error code
1555 * @param pvNextEIP Next EIP
1556 */
1557int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1558{
1559 PVM pVM = env->pVM;
1560#ifdef VBOX_WITH_STATISTICS
1561 static STAMCOUNTER s_aStatTrap[255];
1562 static bool s_aRegisters[RT_ELEMENTS(s_aStatTrap)];
1563#endif
1564
1565#ifdef VBOX_WITH_STATISTICS
1566 if (uTrap < 255)
1567 {
1568 if (!s_aRegisters[uTrap])
1569 {
1570 s_aRegisters[uTrap] = true;
1571 char szStatName[64];
1572 RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1573 STAM_REG(env->pVM, &s_aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1574 }
1575 STAM_COUNTER_INC(&s_aStatTrap[uTrap]);
1576 }
1577#endif
1578 Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, (RTGCPTR)pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
1579 if( uTrap < 0x20
1580 && (env->cr[0] & X86_CR0_PE)
1581 && !(env->eflags & X86_EFL_VM))
1582 {
1583#ifdef DEBUG
1584 remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1585#endif
1586 if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 512)
1587 {
1588 LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%RGv eip=%RGv cr2=%RGv\n", uTrap, uErrorCode, (RTGCPTR)pvNextEIP, (RTGCPTR)env->eip, (RTGCPTR)env->cr[2]));
1589 remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1590 return VERR_REM_TOO_MANY_TRAPS;
1591 }
1592 if(pVM->rem.s.uPendingException != uTrap || pVM->rem.s.uPendingExcptEIP != env->eip || pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1593 pVM->rem.s.cPendingExceptions = 1;
1594 pVM->rem.s.uPendingException = uTrap;
1595 pVM->rem.s.uPendingExcptEIP = env->eip;
1596 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1597 }
1598 else
1599 {
1600 pVM->rem.s.cPendingExceptions = 0;
1601 pVM->rem.s.uPendingException = uTrap;
1602 pVM->rem.s.uPendingExcptEIP = env->eip;
1603 pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1604 }
1605 return VINF_SUCCESS;
1606}
1607
1608
1609/*
1610 * Clear current active trap
1611 *
1612 * @param pVM VM Handle.
1613 */
1614void remR3TrapClear(PVM pVM)
1615{
1616 pVM->rem.s.cPendingExceptions = 0;
1617 pVM->rem.s.uPendingException = 0;
1618 pVM->rem.s.uPendingExcptEIP = 0;
1619 pVM->rem.s.uPendingExcptCR2 = 0;
1620}
1621
1622
1623/*
1624 * Record previous call instruction addresses
1625 *
1626 * @param env Pointer to the CPU environment.
1627 */
1628void remR3RecordCall(CPUState *env)
1629{
1630 CSAMR3RecordCallAddress(env->pVM, env->eip);
1631}
1632
1633
1634/**
1635 * Syncs the internal REM state with the VM.
1636 *
1637 * This must be called before REMR3Run() is invoked whenever when the REM
1638 * state is not up to date. Calling it several times in a row is not
1639 * permitted.
1640 *
1641 * @returns VBox status code.
1642 *
1643 * @param pVM VM Handle.
1644 *
1645 * @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1646 * no do this since the majority of the callers don't want any unnecessary of events
1647 * pending that would immediatly interrupt execution.
1648 */
1649REMR3DECL(int) REMR3State(PVM pVM)
1650{
1651 Log2(("REMR3State:\n"));
1652 STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1653 register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1654 register unsigned fFlags;
1655 bool fHiddenSelRegsValid = CPUMAreHiddenSelRegsValid(pVM);
1656 unsigned i;
1657
1658 Assert(!pVM->rem.s.fInREM);
1659 pVM->rem.s.fInStateSync = true;
1660
1661 /*
1662 * If we have to flush TBs, do that immediately.
1663 */
1664 if (pVM->rem.s.fFlushTBs)
1665 {
1666 STAM_COUNTER_INC(&gStatFlushTBs);
1667 tb_flush(&pVM->rem.s.Env);
1668 pVM->rem.s.fFlushTBs = false;
1669 }
1670
1671 /*
1672 * Copy the registers which require no special handling.
1673 */
1674#ifdef TARGET_X86_64
1675 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
1676 Assert(R_EAX == 0);
1677 pVM->rem.s.Env.regs[R_EAX] = pCtx->rax;
1678 Assert(R_ECX == 1);
1679 pVM->rem.s.Env.regs[R_ECX] = pCtx->rcx;
1680 Assert(R_EDX == 2);
1681 pVM->rem.s.Env.regs[R_EDX] = pCtx->rdx;
1682 Assert(R_EBX == 3);
1683 pVM->rem.s.Env.regs[R_EBX] = pCtx->rbx;
1684 Assert(R_ESP == 4);
1685 pVM->rem.s.Env.regs[R_ESP] = pCtx->rsp;
1686 Assert(R_EBP == 5);
1687 pVM->rem.s.Env.regs[R_EBP] = pCtx->rbp;
1688 Assert(R_ESI == 6);
1689 pVM->rem.s.Env.regs[R_ESI] = pCtx->rsi;
1690 Assert(R_EDI == 7);
1691 pVM->rem.s.Env.regs[R_EDI] = pCtx->rdi;
1692 pVM->rem.s.Env.regs[8] = pCtx->r8;
1693 pVM->rem.s.Env.regs[9] = pCtx->r9;
1694 pVM->rem.s.Env.regs[10] = pCtx->r10;
1695 pVM->rem.s.Env.regs[11] = pCtx->r11;
1696 pVM->rem.s.Env.regs[12] = pCtx->r12;
1697 pVM->rem.s.Env.regs[13] = pCtx->r13;
1698 pVM->rem.s.Env.regs[14] = pCtx->r14;
1699 pVM->rem.s.Env.regs[15] = pCtx->r15;
1700
1701 pVM->rem.s.Env.eip = pCtx->rip;
1702
1703 pVM->rem.s.Env.eflags = pCtx->rflags.u64;
1704#else
1705 Assert(R_EAX == 0);
1706 pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1707 Assert(R_ECX == 1);
1708 pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1709 Assert(R_EDX == 2);
1710 pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1711 Assert(R_EBX == 3);
1712 pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1713 Assert(R_ESP == 4);
1714 pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1715 Assert(R_EBP == 5);
1716 pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1717 Assert(R_ESI == 6);
1718 pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1719 Assert(R_EDI == 7);
1720 pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1721 pVM->rem.s.Env.eip = pCtx->eip;
1722
1723 pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1724#endif
1725
1726 pVM->rem.s.Env.cr[2] = pCtx->cr2;
1727
1728 /** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1729 for (i=0;i<8;i++)
1730 pVM->rem.s.Env.dr[i] = pCtx->dr[i];
1731
1732 /*
1733 * Clear the halted hidden flag (the interrupt waking up the CPU can
1734 * have been dispatched in raw mode).
1735 */
1736 pVM->rem.s.Env.hflags &= ~HF_HALTED_MASK;
1737
1738 /*
1739 * Replay invlpg?
1740 */
1741 if (pVM->rem.s.cInvalidatedPages)
1742 {
1743 pVM->rem.s.fIgnoreInvlPg = true;
1744 RTUINT i;
1745 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1746 {
1747 Log2(("REMR3State: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1748 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1749 }
1750 pVM->rem.s.fIgnoreInvlPg = false;
1751 pVM->rem.s.cInvalidatedPages = 0;
1752 }
1753
1754 /* Replay notification changes? */
1755 if (pVM->rem.s.cHandlerNotifications)
1756 REMR3ReplayHandlerNotifications(pVM);
1757
1758 /* Update MSRs; before CRx registers! */
1759 pVM->rem.s.Env.efer = pCtx->msrEFER;
1760 pVM->rem.s.Env.star = pCtx->msrSTAR;
1761 pVM->rem.s.Env.pat = pCtx->msrPAT;
1762#ifdef TARGET_X86_64
1763 pVM->rem.s.Env.lstar = pCtx->msrLSTAR;
1764 pVM->rem.s.Env.cstar = pCtx->msrCSTAR;
1765 pVM->rem.s.Env.fmask = pCtx->msrSFMASK;
1766 pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
1767
1768 /* Update the internal long mode activate flag according to the new EFER value. */
1769 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1770 pVM->rem.s.Env.hflags |= HF_LMA_MASK;
1771 else
1772 pVM->rem.s.Env.hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
1773#endif
1774
1775 /*
1776 * Registers which are rarely changed and require special handling / order when changed.
1777 */
1778 fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1779 LogFlow(("CPUMGetAndClearChangedFlagsREM %x\n", fFlags));
1780 if (fFlags & ( CPUM_CHANGED_CR4 | CPUM_CHANGED_CR3 | CPUM_CHANGED_CR0
1781 | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_LDTR | CPUM_CHANGED_TR
1782 | CPUM_CHANGED_FPU_REM | CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_CPUID))
1783 {
1784 if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1785 {
1786 pVM->rem.s.fIgnoreCR3Load = true;
1787 tlb_flush(&pVM->rem.s.Env, true);
1788 pVM->rem.s.fIgnoreCR3Load = false;
1789 }
1790
1791 /* CR4 before CR0! */
1792 if (fFlags & CPUM_CHANGED_CR4)
1793 {
1794 pVM->rem.s.fIgnoreCR3Load = true;
1795 pVM->rem.s.fIgnoreCpuMode = true;
1796 cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1797 pVM->rem.s.fIgnoreCpuMode = false;
1798 pVM->rem.s.fIgnoreCR3Load = false;
1799 }
1800
1801 if (fFlags & CPUM_CHANGED_CR0)
1802 {
1803 pVM->rem.s.fIgnoreCR3Load = true;
1804 pVM->rem.s.fIgnoreCpuMode = true;
1805 cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1806 pVM->rem.s.fIgnoreCpuMode = false;
1807 pVM->rem.s.fIgnoreCR3Load = false;
1808 }
1809
1810 if (fFlags & CPUM_CHANGED_CR3)
1811 {
1812 pVM->rem.s.fIgnoreCR3Load = true;
1813 cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1814 pVM->rem.s.fIgnoreCR3Load = false;
1815 }
1816
1817 if (fFlags & CPUM_CHANGED_GDTR)
1818 {
1819 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1820 pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1821 }
1822
1823 if (fFlags & CPUM_CHANGED_IDTR)
1824 {
1825 pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1826 pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1827 }
1828
1829 if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1830 {
1831 pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1832 pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1833 pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1834 }
1835
1836 if (fFlags & CPUM_CHANGED_LDTR)
1837 {
1838 if (fHiddenSelRegsValid)
1839 {
1840 pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1841 pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u64Base;
1842 pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1843 pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1844 }
1845 else
1846 sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1847 }
1848
1849 if (fFlags & CPUM_CHANGED_TR)
1850 {
1851 if (fHiddenSelRegsValid)
1852 {
1853 pVM->rem.s.Env.tr.selector = pCtx->tr;
1854 pVM->rem.s.Env.tr.base = pCtx->trHid.u64Base;
1855 pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1856 pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1857 }
1858 else
1859 sync_tr(&pVM->rem.s.Env, pCtx->tr);
1860
1861 /** @note do_interrupt will fault if the busy flag is still set.... */
1862 pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1863 }
1864
1865 if (fFlags & CPUM_CHANGED_CPUID)
1866 {
1867 uint32_t u32Dummy;
1868
1869 /*
1870 * Get the CPUID features.
1871 */
1872 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
1873 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext2_features);
1874 }
1875
1876 /* Sync FPU state after CR4 and CPUID. */
1877 if (fFlags & CPUM_CHANGED_FPU_REM)
1878 save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu); /* 'save' is an excellent name. */
1879 }
1880
1881 /*
1882 * Update selector registers.
1883 * This must be done *after* we've synced gdt, ldt and crX registers
1884 * since we're reading the GDT/LDT om sync_seg. This will happen with
1885 * saved state which takes a quick dip into rawmode for instance.
1886 */
1887 /*
1888 * Stack; Note first check this one as the CPL might have changed. The
1889 * wrong CPL can cause QEmu to raise an exception in sync_seg!!
1890 */
1891
1892 if (fHiddenSelRegsValid)
1893 {
1894 /* The hidden selector registers are valid in the CPU context. */
1895 /** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1896
1897 /* Set current CPL */
1898 cpu_x86_set_cpl(&pVM->rem.s.Env, CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)));
1899
1900 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1901 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1902 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1903 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1904 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1905 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1906 }
1907 else
1908 {
1909 /* In 'normal' raw mode we don't have access to the hidden selector registers. */
1910 if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1911 {
1912 Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1913
1914 cpu_x86_set_cpl(&pVM->rem.s.Env, CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)));
1915 sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1916#ifdef VBOX_WITH_STATISTICS
1917 if (pVM->rem.s.Env.segs[R_SS].newselector)
1918 {
1919 STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1920 }
1921#endif
1922 }
1923 else
1924 pVM->rem.s.Env.segs[R_SS].newselector = 0;
1925
1926 if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1927 {
1928 Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1929 sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1930#ifdef VBOX_WITH_STATISTICS
1931 if (pVM->rem.s.Env.segs[R_ES].newselector)
1932 {
1933 STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1934 }
1935#endif
1936 }
1937 else
1938 pVM->rem.s.Env.segs[R_ES].newselector = 0;
1939
1940 if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1941 {
1942 Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1943 sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1944#ifdef VBOX_WITH_STATISTICS
1945 if (pVM->rem.s.Env.segs[R_CS].newselector)
1946 {
1947 STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1948 }
1949#endif
1950 }
1951 else
1952 pVM->rem.s.Env.segs[R_CS].newselector = 0;
1953
1954 if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1955 {
1956 Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1957 sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1958#ifdef VBOX_WITH_STATISTICS
1959 if (pVM->rem.s.Env.segs[R_DS].newselector)
1960 {
1961 STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1962 }
1963#endif
1964 }
1965 else
1966 pVM->rem.s.Env.segs[R_DS].newselector = 0;
1967
1968 /** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1969 * be the same but not the base/limit. */
1970 if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1971 {
1972 Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1973 sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1974#ifdef VBOX_WITH_STATISTICS
1975 if (pVM->rem.s.Env.segs[R_FS].newselector)
1976 {
1977 STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1978 }
1979#endif
1980 }
1981 else
1982 pVM->rem.s.Env.segs[R_FS].newselector = 0;
1983
1984 if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1985 {
1986 Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1987 sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1988#ifdef VBOX_WITH_STATISTICS
1989 if (pVM->rem.s.Env.segs[R_GS].newselector)
1990 {
1991 STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1992 }
1993#endif
1994 }
1995 else
1996 pVM->rem.s.Env.segs[R_GS].newselector = 0;
1997 }
1998
1999 /*
2000 * Check for traps.
2001 */
2002 pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
2003 TRPMEVENT enmType;
2004 uint8_t u8TrapNo;
2005 int rc = TRPMQueryTrap(pVM, &u8TrapNo, &enmType);
2006 if (RT_SUCCESS(rc))
2007 {
2008#ifdef DEBUG
2009 if (u8TrapNo == 0x80)
2010 {
2011 remR3DumpLnxSyscall(pVM);
2012 remR3DumpOBsdSyscall(pVM);
2013 }
2014#endif
2015
2016 pVM->rem.s.Env.exception_index = u8TrapNo;
2017 if (enmType != TRPM_SOFTWARE_INT)
2018 {
2019 pVM->rem.s.Env.exception_is_int = 0;
2020 pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
2021 }
2022 else
2023 {
2024 /*
2025 * The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
2026 * We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
2027 * for int03 and into.
2028 */
2029 pVM->rem.s.Env.exception_is_int = 1;
2030 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 2;
2031 /* int 3 may be generated by one-byte 0xcc */
2032 if (u8TrapNo == 3)
2033 {
2034 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xcc)
2035 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2036 }
2037 /* int 4 may be generated by one-byte 0xce */
2038 else if (u8TrapNo == 4)
2039 {
2040 if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->rip) == 0xce)
2041 pVM->rem.s.Env.exception_next_eip = pCtx->rip + 1;
2042 }
2043 }
2044
2045 /* get error code and cr2 if needed. */
2046 switch (u8TrapNo)
2047 {
2048 case 0x0e:
2049 pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
2050 /* fallthru */
2051 case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2052 pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
2053 break;
2054
2055 case 0x11: case 0x08:
2056 default:
2057 pVM->rem.s.Env.error_code = 0;
2058 break;
2059 }
2060
2061 /*
2062 * We can now reset the active trap since the recompiler is gonna have a go at it.
2063 */
2064 rc = TRPMResetTrap(pVM);
2065 AssertRC(rc);
2066 Log2(("REMR3State: trap=%02x errcd=%RGv cr2=%RGv nexteip=%RGv%s\n", pVM->rem.s.Env.exception_index, (RTGCPTR)pVM->rem.s.Env.error_code,
2067 (RTGCPTR)pVM->rem.s.Env.cr[2], (RTGCPTR)pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
2068 }
2069
2070 /*
2071 * Clear old interrupt request flags; Check for pending hardware interrupts.
2072 * (See @remark for why we don't check for other FFs.)
2073 */
2074 pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT | CPU_INTERRUPT_EXITTB | CPU_INTERRUPT_TIMER);
2075 if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
2076 || VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
2077 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD;
2078
2079 /*
2080 * We're now in REM mode.
2081 */
2082 pVM->rem.s.fInREM = true;
2083 pVM->rem.s.fInStateSync = false;
2084 pVM->rem.s.cCanExecuteRaw = 0;
2085 STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
2086 Log2(("REMR3State: returns VINF_SUCCESS\n"));
2087 return VINF_SUCCESS;
2088}
2089
2090
2091/**
2092 * Syncs back changes in the REM state to the the VM state.
2093 *
2094 * This must be called after invoking REMR3Run().
2095 * Calling it several times in a row is not permitted.
2096 *
2097 * @returns VBox status code.
2098 *
2099 * @param pVM VM Handle.
2100 */
2101REMR3DECL(int) REMR3StateBack(PVM pVM)
2102{
2103 Log2(("REMR3StateBack:\n"));
2104 Assert(pVM->rem.s.fInREM);
2105 STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
2106 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2107 unsigned i;
2108
2109 /*
2110 * Copy back the registers.
2111 * This is done in the order they are declared in the CPUMCTX structure.
2112 */
2113
2114 /** @todo FOP */
2115 /** @todo FPUIP */
2116 /** @todo CS */
2117 /** @todo FPUDP */
2118 /** @todo DS */
2119 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2120 pCtx->fpu.MXCSR = 0;
2121 pCtx->fpu.MXCSR_MASK = 0;
2122
2123 /** @todo check if FPU/XMM was actually used in the recompiler */
2124 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2125//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2126
2127#ifdef TARGET_X86_64
2128 /* Note that the high dwords of 64 bits registers are undefined in 32 bits mode and are undefined after a mode change. */
2129 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2130 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2131 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2132 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2133 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2134 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2135 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2136 pCtx->r8 = pVM->rem.s.Env.regs[8];
2137 pCtx->r9 = pVM->rem.s.Env.regs[9];
2138 pCtx->r10 = pVM->rem.s.Env.regs[10];
2139 pCtx->r11 = pVM->rem.s.Env.regs[11];
2140 pCtx->r12 = pVM->rem.s.Env.regs[12];
2141 pCtx->r13 = pVM->rem.s.Env.regs[13];
2142 pCtx->r14 = pVM->rem.s.Env.regs[14];
2143 pCtx->r15 = pVM->rem.s.Env.regs[15];
2144
2145 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2146
2147#else
2148 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2149 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2150 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2151 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2152 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2153 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2154 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2155
2156 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2157#endif
2158
2159 pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2160
2161#ifdef VBOX_WITH_STATISTICS
2162 if (pVM->rem.s.Env.segs[R_SS].newselector)
2163 {
2164 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
2165 }
2166 if (pVM->rem.s.Env.segs[R_GS].newselector)
2167 {
2168 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
2169 }
2170 if (pVM->rem.s.Env.segs[R_FS].newselector)
2171 {
2172 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
2173 }
2174 if (pVM->rem.s.Env.segs[R_ES].newselector)
2175 {
2176 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
2177 }
2178 if (pVM->rem.s.Env.segs[R_DS].newselector)
2179 {
2180 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2181 }
2182 if (pVM->rem.s.Env.segs[R_CS].newselector)
2183 {
2184 STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2185 }
2186#endif
2187 pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2188 pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2189 pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2190 pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2191 pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2192
2193#ifdef TARGET_X86_64
2194 pCtx->rip = pVM->rem.s.Env.eip;
2195 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2196#else
2197 pCtx->eip = pVM->rem.s.Env.eip;
2198 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2199#endif
2200
2201 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2202 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2203 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2204 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2205
2206 for (i=0;i<8;i++)
2207 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2208
2209 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2210 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base)
2211 {
2212 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base;
2213 STAM_COUNTER_INC(&gStatREMGDTChange);
2214 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2215 }
2216
2217 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2218 if (pCtx->idtr.pIdt != pVM->rem.s.Env.idt.base)
2219 {
2220 pCtx->idtr.pIdt = pVM->rem.s.Env.idt.base;
2221 STAM_COUNTER_INC(&gStatREMIDTChange);
2222 VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2223 }
2224
2225 if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2226 {
2227 pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2228 STAM_COUNTER_INC(&gStatREMLDTRChange);
2229 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2230 }
2231 if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2232 {
2233 pCtx->tr = pVM->rem.s.Env.tr.selector;
2234 STAM_COUNTER_INC(&gStatREMTRChange);
2235 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2236 }
2237
2238 /** @todo These values could still be out of sync! */
2239 pCtx->csHid.u64Base = pVM->rem.s.Env.segs[R_CS].base;
2240 pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2241 /** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2242 pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2243
2244 pCtx->dsHid.u64Base = pVM->rem.s.Env.segs[R_DS].base;
2245 pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2246 pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2247
2248 pCtx->esHid.u64Base = pVM->rem.s.Env.segs[R_ES].base;
2249 pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2250 pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2251
2252 pCtx->fsHid.u64Base = pVM->rem.s.Env.segs[R_FS].base;
2253 pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2254 pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2255
2256 pCtx->gsHid.u64Base = pVM->rem.s.Env.segs[R_GS].base;
2257 pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2258 pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2259
2260 pCtx->ssHid.u64Base = pVM->rem.s.Env.segs[R_SS].base;
2261 pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2262 pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2263
2264 pCtx->ldtrHid.u64Base = pVM->rem.s.Env.ldt.base;
2265 pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2266 pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2267
2268 pCtx->trHid.u64Base = pVM->rem.s.Env.tr.base;
2269 pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2270 pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2271
2272 /* Sysenter MSR */
2273 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2274 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2275 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2276
2277 /* System MSRs. */
2278 pCtx->msrEFER = pVM->rem.s.Env.efer;
2279 pCtx->msrSTAR = pVM->rem.s.Env.star;
2280 pCtx->msrPAT = pVM->rem.s.Env.pat;
2281#ifdef TARGET_X86_64
2282 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2283 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2284 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2285 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2286#endif
2287
2288 remR3TrapClear(pVM);
2289
2290 /*
2291 * Check for traps.
2292 */
2293 if ( pVM->rem.s.Env.exception_index >= 0
2294 && pVM->rem.s.Env.exception_index < 256)
2295 {
2296 Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2297 int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, (pVM->rem.s.Env.exception_is_int) ? TRPM_SOFTWARE_INT : TRPM_HARDWARE_INT);
2298 AssertRC(rc);
2299 switch (pVM->rem.s.Env.exception_index)
2300 {
2301 case 0x0e:
2302 TRPMSetFaultAddress(pVM, pCtx->cr2);
2303 /* fallthru */
2304 case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2305 case 0x11: case 0x08: /* 0 */
2306 TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2307 break;
2308 }
2309
2310 }
2311
2312 /*
2313 * We're not longer in REM mode.
2314 */
2315 pVM->rem.s.fInREM = false;
2316 STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2317 Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2318 return VINF_SUCCESS;
2319}
2320
2321
2322/**
2323 * This is called by the disassembler when it wants to update the cpu state
2324 * before for instance doing a register dump.
2325 */
2326static void remR3StateUpdate(PVM pVM)
2327{
2328 Assert(pVM->rem.s.fInREM);
2329 register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2330 unsigned i;
2331
2332 /*
2333 * Copy back the registers.
2334 * This is done in the order they are declared in the CPUMCTX structure.
2335 */
2336
2337 /** @todo FOP */
2338 /** @todo FPUIP */
2339 /** @todo CS */
2340 /** @todo FPUDP */
2341 /** @todo DS */
2342 /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2343 pCtx->fpu.MXCSR = 0;
2344 pCtx->fpu.MXCSR_MASK = 0;
2345
2346 /** @todo check if FPU/XMM was actually used in the recompiler */
2347 restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2348//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2349
2350#ifdef TARGET_X86_64
2351 pCtx->rdi = pVM->rem.s.Env.regs[R_EDI];
2352 pCtx->rsi = pVM->rem.s.Env.regs[R_ESI];
2353 pCtx->rbp = pVM->rem.s.Env.regs[R_EBP];
2354 pCtx->rax = pVM->rem.s.Env.regs[R_EAX];
2355 pCtx->rbx = pVM->rem.s.Env.regs[R_EBX];
2356 pCtx->rdx = pVM->rem.s.Env.regs[R_EDX];
2357 pCtx->rcx = pVM->rem.s.Env.regs[R_ECX];
2358 pCtx->r8 = pVM->rem.s.Env.regs[8];
2359 pCtx->r9 = pVM->rem.s.Env.regs[9];
2360 pCtx->r10 = pVM->rem.s.Env.regs[10];
2361 pCtx->r11 = pVM->rem.s.Env.regs[11];
2362 pCtx->r12 = pVM->rem.s.Env.regs[12];
2363 pCtx->r13 = pVM->rem.s.Env.regs[13];
2364 pCtx->r14 = pVM->rem.s.Env.regs[14];
2365 pCtx->r15 = pVM->rem.s.Env.regs[15];
2366
2367 pCtx->rsp = pVM->rem.s.Env.regs[R_ESP];
2368#else
2369 pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2370 pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2371 pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2372 pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2373 pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2374 pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2375 pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2376
2377 pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2378#endif
2379
2380 pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2381
2382 pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2383 pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2384 pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2385 pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2386 pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2387
2388#ifdef TARGET_X86_64
2389 pCtx->rip = pVM->rem.s.Env.eip;
2390 pCtx->rflags.u64 = pVM->rem.s.Env.eflags;
2391#else
2392 pCtx->eip = pVM->rem.s.Env.eip;
2393 pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2394#endif
2395
2396 pCtx->cr0 = pVM->rem.s.Env.cr[0];
2397 pCtx->cr2 = pVM->rem.s.Env.cr[2];
2398 pCtx->cr3 = pVM->rem.s.Env.cr[3];
2399 pCtx->cr4 = pVM->rem.s.Env.cr[4];
2400
2401 for (i=0;i<8;i++)
2402 pCtx->dr[i] = pVM->rem.s.Env.dr[i];
2403
2404 pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2405 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base)
2406 {
2407 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
2408 STAM_COUNTER_INC(&gStatREMGDTChange);
2409 VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2410 }
2411
2412 pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2413 if (pCtx->idtr.pIdt != (RTGCPTR)pVM->rem.s.Env.idt.base)
2414 {
2415 pCtx->idtr.pIdt = (RTGCPTR)pVM->rem.s.Env.idt.base;
2416 STAM_COUNTER_INC(&gStatREMIDTChange);
2417 VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2418 }
2419
2420 if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2421 {
2422 pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2423 STAM_COUNTER_INC(&gStatREMLDTRChange);
2424 VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2425 }
2426 if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2427 {
2428 pCtx->tr = pVM->rem.s.Env.tr.selector;
2429 STAM_COUNTER_INC(&gStatREMTRChange);
2430 VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2431 }
2432
2433 /** @todo These values could still be out of sync! */
2434 pCtx->csHid.u64Base = pVM->rem.s.Env.segs[R_CS].base;
2435 pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2436 /** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2437 pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2438
2439 pCtx->dsHid.u64Base = pVM->rem.s.Env.segs[R_DS].base;
2440 pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2441 pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2442
2443 pCtx->esHid.u64Base = pVM->rem.s.Env.segs[R_ES].base;
2444 pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2445 pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2446
2447 pCtx->fsHid.u64Base = pVM->rem.s.Env.segs[R_FS].base;
2448 pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2449 pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2450
2451 pCtx->gsHid.u64Base = pVM->rem.s.Env.segs[R_GS].base;
2452 pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2453 pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2454
2455 pCtx->ssHid.u64Base = pVM->rem.s.Env.segs[R_SS].base;
2456 pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2457 pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2458
2459 pCtx->ldtrHid.u64Base = pVM->rem.s.Env.ldt.base;
2460 pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2461 pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2462
2463 pCtx->trHid.u64Base = pVM->rem.s.Env.tr.base;
2464 pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2465 pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2466
2467 /* Sysenter MSR */
2468 pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2469 pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2470 pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2471
2472 /* System MSRs. */
2473 pCtx->msrEFER = pVM->rem.s.Env.efer;
2474 pCtx->msrSTAR = pVM->rem.s.Env.star;
2475 pCtx->msrPAT = pVM->rem.s.Env.pat;
2476#ifdef TARGET_X86_64
2477 pCtx->msrLSTAR = pVM->rem.s.Env.lstar;
2478 pCtx->msrCSTAR = pVM->rem.s.Env.cstar;
2479 pCtx->msrSFMASK = pVM->rem.s.Env.fmask;
2480 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase;
2481#endif
2482
2483}
2484
2485
2486/**
2487 * Update the VMM state information if we're currently in REM.
2488 *
2489 * This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2490 * we're currently executing in REM and the VMM state is invalid. This method will of
2491 * course check that we're executing in REM before syncing any data over to the VMM.
2492 *
2493 * @param pVM The VM handle.
2494 */
2495REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2496{
2497 if (pVM->rem.s.fInREM)
2498 remR3StateUpdate(pVM);
2499}
2500
2501
2502#undef LOG_GROUP
2503#define LOG_GROUP LOG_GROUP_REM
2504
2505
2506/**
2507 * Notify the recompiler about Address Gate 20 state change.
2508 *
2509 * This notification is required since A20 gate changes are
2510 * initialized from a device driver and the VM might just as
2511 * well be in REM mode as in RAW mode.
2512 *
2513 * @param pVM VM handle.
2514 * @param fEnable True if the gate should be enabled.
2515 * False if the gate should be disabled.
2516 */
2517REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2518{
2519 LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2520 VM_ASSERT_EMT(pVM);
2521
2522 bool fSaved = pVM->rem.s.fIgnoreAll; /* just in case. */
2523 pVM->rem.s.fIgnoreAll = fSaved || !pVM->rem.s.fInREM;
2524
2525 cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2526
2527 pVM->rem.s.fIgnoreAll = fSaved;
2528}
2529
2530
2531/**
2532 * Replays the invalidated recorded pages.
2533 * Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2534 *
2535 * @param pVM VM handle.
2536 */
2537REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2538{
2539 VM_ASSERT_EMT(pVM);
2540
2541 /*
2542 * Sync the required registers.
2543 */
2544 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2545 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2546 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2547 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2548
2549 /*
2550 * Replay the flushes.
2551 */
2552 pVM->rem.s.fIgnoreInvlPg = true;
2553 RTUINT i;
2554 for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2555 {
2556 Log2(("REMR3ReplayInvalidatedPages: invlpg %RGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2557 tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2558 }
2559 pVM->rem.s.fIgnoreInvlPg = false;
2560 pVM->rem.s.cInvalidatedPages = 0;
2561}
2562
2563
2564/**
2565 * Replays the handler notification changes
2566 * Called in response to VM_FF_REM_HANDLER_NOTIFY from the RAW execution loop.
2567 *
2568 * @param pVM VM handle.
2569 */
2570REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2571{
2572 LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2573 VM_ASSERT_EMT(pVM);
2574
2575 /*
2576 * Replay the flushes.
2577 */
2578 RTUINT i;
2579 const RTUINT c = pVM->rem.s.cHandlerNotifications;
2580 pVM->rem.s.cHandlerNotifications = 0;
2581 for (i = 0; i < c; i++)
2582 {
2583 PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2584 switch (pRec->enmKind)
2585 {
2586 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2587 REMR3NotifyHandlerPhysicalRegister(pVM,
2588 pRec->u.PhysicalRegister.enmType,
2589 pRec->u.PhysicalRegister.GCPhys,
2590 pRec->u.PhysicalRegister.cb,
2591 pRec->u.PhysicalRegister.fHasHCHandler);
2592 break;
2593
2594 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2595 REMR3NotifyHandlerPhysicalDeregister(pVM,
2596 pRec->u.PhysicalDeregister.enmType,
2597 pRec->u.PhysicalDeregister.GCPhys,
2598 pRec->u.PhysicalDeregister.cb,
2599 pRec->u.PhysicalDeregister.fHasHCHandler,
2600 pRec->u.PhysicalDeregister.fRestoreAsRAM);
2601 break;
2602
2603 case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2604 REMR3NotifyHandlerPhysicalModify(pVM,
2605 pRec->u.PhysicalModify.enmType,
2606 pRec->u.PhysicalModify.GCPhysOld,
2607 pRec->u.PhysicalModify.GCPhysNew,
2608 pRec->u.PhysicalModify.cb,
2609 pRec->u.PhysicalModify.fHasHCHandler,
2610 pRec->u.PhysicalModify.fRestoreAsRAM);
2611 break;
2612
2613 default:
2614 AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2615 break;
2616 }
2617 }
2618 VM_FF_CLEAR(pVM, VM_FF_REM_HANDLER_NOTIFY);
2619}
2620
2621
2622/**
2623 * Notify REM about changed code page.
2624 *
2625 * @returns VBox status code.
2626 * @param pVM VM handle.
2627 * @param pvCodePage Code page address
2628 */
2629REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2630{
2631#ifdef VBOX_REM_PROTECT_PAGES_FROM_SMC
2632 int rc;
2633 RTGCPHYS PhysGC;
2634 uint64_t flags;
2635
2636 VM_ASSERT_EMT(pVM);
2637
2638 /*
2639 * Get the physical page address.
2640 */
2641 rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2642 if (rc == VINF_SUCCESS)
2643 {
2644 /*
2645 * Sync the required registers and flush the whole page.
2646 * (Easier to do the whole page than notifying it about each physical
2647 * byte that was changed.
2648 */
2649 pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2650 pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2651 pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2652 pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2653
2654 tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2655 }
2656#endif
2657 return VINF_SUCCESS;
2658}
2659
2660
2661/**
2662 * Notification about a successful MMR3PhysRegister() call.
2663 *
2664 * @param pVM VM handle.
2665 * @param GCPhys The physical address the RAM.
2666 * @param cb Size of the memory.
2667 * @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2668 */
2669REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, unsigned fFlags)
2670{
2671 Log(("REMR3NotifyPhysRamRegister: GCPhys=%RGp cb=%d fFlags=%d\n", GCPhys, cb, fFlags));
2672 VM_ASSERT_EMT(pVM);
2673
2674 /*
2675 * Validate input - we trust the caller.
2676 */
2677 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2678 Assert(cb);
2679 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2680
2681 /*
2682 * Base ram?
2683 */
2684 if (!GCPhys)
2685 {
2686 phys_ram_size = cb;
2687 phys_ram_dirty_size = cb >> PAGE_SHIFT;
2688#ifndef VBOX_STRICT
2689 phys_ram_dirty = MMR3HeapAlloc(pVM, MM_TAG_REM, phys_ram_dirty_size);
2690 AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", phys_ram_dirty_size));
2691#else /* VBOX_STRICT: allocate a full map and make the out of bounds pages invalid. */
2692 phys_ram_dirty = RTMemPageAlloc(_4G >> PAGE_SHIFT);
2693 AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", _4G >> PAGE_SHIFT));
2694 uint32_t cbBitmap = RT_ALIGN_32(phys_ram_dirty_size, PAGE_SIZE);
2695 int rc = RTMemProtect(phys_ram_dirty + cbBitmap, (_4G >> PAGE_SHIFT) - cbBitmap, RTMEM_PROT_NONE);
2696 AssertRC(rc);
2697 phys_ram_dirty += cbBitmap - phys_ram_dirty_size;
2698#endif
2699 memset(phys_ram_dirty, 0xff, phys_ram_dirty_size);
2700 }
2701
2702 /*
2703 * Register the ram.
2704 */
2705 Assert(!pVM->rem.s.fIgnoreAll);
2706 pVM->rem.s.fIgnoreAll = true;
2707
2708#ifdef VBOX_WITH_NEW_PHYS_CODE
2709 if (fFlags & MM_RAM_FLAGS_RESERVED)
2710 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2711 else
2712 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2713#else
2714 if (!GCPhys)
2715 cpu_register_physical_memory(GCPhys, cb, GCPhys | IO_MEM_RAM_MISSING);
2716 else
2717 {
2718 if (fFlags & MM_RAM_FLAGS_RESERVED)
2719 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2720 else
2721 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2722 }
2723#endif
2724 Assert(pVM->rem.s.fIgnoreAll);
2725 pVM->rem.s.fIgnoreAll = false;
2726}
2727
2728#ifndef VBOX_WITH_NEW_PHYS_CODE
2729
2730/**
2731 * Notification about a successful PGMR3PhysRegisterChunk() call.
2732 *
2733 * @param pVM VM handle.
2734 * @param GCPhys The physical address the RAM.
2735 * @param cb Size of the memory.
2736 * @param pvRam The HC address of the RAM.
2737 * @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2738 */
2739REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2740{
2741 Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%RGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2742 VM_ASSERT_EMT(pVM);
2743
2744 /*
2745 * Validate input - we trust the caller.
2746 */
2747 Assert(pvRam);
2748 Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2749 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2750 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2751 Assert(fFlags == 0 /* normal RAM */);
2752 Assert(!pVM->rem.s.fIgnoreAll);
2753 pVM->rem.s.fIgnoreAll = true;
2754
2755 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2756
2757 Assert(pVM->rem.s.fIgnoreAll);
2758 pVM->rem.s.fIgnoreAll = false;
2759}
2760
2761
2762/**
2763 * Grows dynamically allocated guest RAM.
2764 * Will raise a fatal error if the operation fails.
2765 *
2766 * @param physaddr The physical address.
2767 */
2768void remR3GrowDynRange(unsigned long physaddr)
2769{
2770 int rc;
2771 PVM pVM = cpu_single_env->pVM;
2772
2773 LogFlow(("remR3GrowDynRange %RGp\n", (RTGCPHYS)physaddr));
2774 const RTGCPHYS GCPhys = physaddr;
2775 rc = PGM3PhysGrowRange(pVM, &GCPhys);
2776 if (RT_SUCCESS(rc))
2777 return;
2778
2779 LogRel(("\nUnable to allocate guest RAM chunk at %RGp\n", (RTGCPHYS)physaddr));
2780 cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %RGp\n", (RTGCPHYS)physaddr);
2781 AssertFatalFailed();
2782}
2783
2784#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2785
2786/**
2787 * Notification about a successful MMR3PhysRomRegister() call.
2788 *
2789 * @param pVM VM handle.
2790 * @param GCPhys The physical address of the ROM.
2791 * @param cb The size of the ROM.
2792 * @param pvCopy Pointer to the ROM copy.
2793 * @param fShadow Whether it's currently writable shadow ROM or normal readonly ROM.
2794 * This function will be called when ever the protection of the
2795 * shadow ROM changes (at reset and end of POST).
2796 */
2797REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)
2798{
2799 Log(("REMR3NotifyPhysRomRegister: GCPhys=%RGp cb=%d pvCopy=%p fShadow=%RTbool\n", GCPhys, cb, pvCopy, fShadow));
2800 VM_ASSERT_EMT(pVM);
2801
2802 /*
2803 * Validate input - we trust the caller.
2804 */
2805 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2806 Assert(cb);
2807 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2808 Assert(pvCopy);
2809 Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2810
2811 /*
2812 * Register the rom.
2813 */
2814 Assert(!pVM->rem.s.fIgnoreAll);
2815 pVM->rem.s.fIgnoreAll = true;
2816
2817 cpu_register_physical_memory(GCPhys, cb, GCPhys | (fShadow ? 0 : IO_MEM_ROM));
2818
2819 Log2(("%.64Rhxd\n", (char *)pvCopy + cb - 64));
2820
2821 Assert(pVM->rem.s.fIgnoreAll);
2822 pVM->rem.s.fIgnoreAll = false;
2823}
2824
2825
2826/**
2827 * Notification about a successful memory deregistration or reservation.
2828 *
2829 * @param pVM VM Handle.
2830 * @param GCPhys Start physical address.
2831 * @param cb The size of the range.
2832 * @todo Rename to REMR3NotifyPhysRamDeregister (for MMIO2) as we won't
2833 * reserve any memory soon.
2834 */
2835REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2836{
2837 Log(("REMR3NotifyPhysReserve: GCPhys=%RGp cb=%d\n", GCPhys, cb));
2838 VM_ASSERT_EMT(pVM);
2839
2840 /*
2841 * Validate input - we trust the caller.
2842 */
2843 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2844 Assert(cb);
2845 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2846
2847 /*
2848 * Unassigning the memory.
2849 */
2850 Assert(!pVM->rem.s.fIgnoreAll);
2851 pVM->rem.s.fIgnoreAll = true;
2852
2853 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2854
2855 Assert(pVM->rem.s.fIgnoreAll);
2856 pVM->rem.s.fIgnoreAll = false;
2857}
2858
2859
2860/**
2861 * Notification about a successful PGMR3HandlerPhysicalRegister() call.
2862 *
2863 * @param pVM VM Handle.
2864 * @param enmType Handler type.
2865 * @param GCPhys Handler range address.
2866 * @param cb Size of the handler range.
2867 * @param fHasHCHandler Set if the handler has a HC callback function.
2868 *
2869 * @remark MMR3PhysRomRegister assumes that this function will not apply the
2870 * Handler memory type to memory which has no HC handler.
2871 */
2872REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2873{
2874 Log(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%d\n",
2875 enmType, GCPhys, cb, fHasHCHandler));
2876 VM_ASSERT_EMT(pVM);
2877 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2878 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2879
2880 if (pVM->rem.s.cHandlerNotifications)
2881 REMR3ReplayHandlerNotifications(pVM);
2882
2883 Assert(!pVM->rem.s.fIgnoreAll);
2884 pVM->rem.s.fIgnoreAll = true;
2885
2886 if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2887 cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2888 else if (fHasHCHandler)
2889 cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2890
2891 Assert(pVM->rem.s.fIgnoreAll);
2892 pVM->rem.s.fIgnoreAll = false;
2893}
2894
2895
2896/**
2897 * Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2898 *
2899 * @param pVM VM Handle.
2900 * @param enmType Handler type.
2901 * @param GCPhys Handler range address.
2902 * @param cb Size of the handler range.
2903 * @param fHasHCHandler Set if the handler has a HC callback function.
2904 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
2905 */
2906REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
2907{
2908 Log(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool RAM=%08x\n",
2909 enmType, GCPhys, cb, fHasHCHandler, fRestoreAsRAM, MMR3PhysGetRamSize(pVM)));
2910 VM_ASSERT_EMT(pVM);
2911
2912 if (pVM->rem.s.cHandlerNotifications)
2913 REMR3ReplayHandlerNotifications(pVM);
2914
2915 Assert(!pVM->rem.s.fIgnoreAll);
2916 pVM->rem.s.fIgnoreAll = true;
2917
2918/** @todo this isn't right, MMIO can (in theory) be restored as RAM. */
2919 if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2920 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2921 else if (fHasHCHandler)
2922 {
2923 if (!fRestoreAsRAM)
2924 {
2925 Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2926 cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2927 }
2928 else
2929 {
2930 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2931 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2932 cpu_register_physical_memory(GCPhys, cb, GCPhys);
2933 }
2934 }
2935
2936 Assert(pVM->rem.s.fIgnoreAll);
2937 pVM->rem.s.fIgnoreAll = false;
2938}
2939
2940
2941/**
2942 * Notification about a successful PGMR3HandlerPhysicalModify() call.
2943 *
2944 * @param pVM VM Handle.
2945 * @param enmType Handler type.
2946 * @param GCPhysOld Old handler range address.
2947 * @param GCPhysNew New handler range address.
2948 * @param cb Size of the handler range.
2949 * @param fHasHCHandler Set if the handler has a HC callback function.
2950 * @param fRestoreAsRAM Whether the to restore it as normal RAM or as unassigned memory.
2951 */
2952REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM)
2953{
2954 Log(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%RGp GCPhysNew=%RGp cb=%RGp fHasHCHandler=%RTbool fRestoreAsRAM=%RTbool\n",
2955 enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, fRestoreAsRAM));
2956 VM_ASSERT_EMT(pVM);
2957 AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2958
2959 if (pVM->rem.s.cHandlerNotifications)
2960 REMR3ReplayHandlerNotifications(pVM);
2961
2962 if (fHasHCHandler)
2963 {
2964 Assert(!pVM->rem.s.fIgnoreAll);
2965 pVM->rem.s.fIgnoreAll = true;
2966
2967 /*
2968 * Reset the old page.
2969 */
2970 if (!fRestoreAsRAM)
2971 cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2972 else
2973 {
2974 /* This is not perfect, but it'll do for PD monitoring... */
2975 Assert(cb == PAGE_SIZE);
2976 Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2977 cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2978 }
2979
2980 /*
2981 * Update the new page.
2982 */
2983 Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2984 Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2985 cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2986
2987 Assert(pVM->rem.s.fIgnoreAll);
2988 pVM->rem.s.fIgnoreAll = false;
2989 }
2990}
2991
2992
2993/**
2994 * Checks if we're handling access to this page or not.
2995 *
2996 * @returns true if we're trapping access.
2997 * @returns false if we aren't.
2998 * @param pVM The VM handle.
2999 * @param GCPhys The physical address.
3000 *
3001 * @remark This function will only work correctly in VBOX_STRICT builds!
3002 */
3003REMR3DECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
3004{
3005#ifdef VBOX_STRICT
3006 if (pVM->rem.s.cHandlerNotifications)
3007 REMR3ReplayHandlerNotifications(pVM);
3008
3009 unsigned long off = get_phys_page_offset(GCPhys);
3010 return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
3011 || (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
3012 || (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
3013#else
3014 return false;
3015#endif
3016}
3017
3018
3019/**
3020 * Deals with a rare case in get_phys_addr_code where the code
3021 * is being monitored.
3022 *
3023 * It could also be an MMIO page, in which case we will raise a fatal error.
3024 *
3025 * @returns The physical address corresponding to addr.
3026 * @param env The cpu environment.
3027 * @param addr The virtual address.
3028 * @param pTLBEntry The TLB entry.
3029 */
3030target_ulong remR3PhysGetPhysicalAddressCode(CPUState *env, target_ulong addr, CPUTLBEntry *pTLBEntry)
3031{
3032 PVM pVM = env->pVM;
3033 if ((pTLBEntry->addr_code & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
3034 {
3035 target_ulong ret = pTLBEntry->addend + addr;
3036 AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%RGv addr_code=%RGv addend=%RGp ret=%RGp\n",
3037 (RTGCPTR)addr, (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPHYS)ret);
3038 return ret;
3039 }
3040 LogRel(("\nTrying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
3041 "*** handlers\n",
3042 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
3043 DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
3044 LogRel(("*** mmio\n"));
3045 DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
3046 LogRel(("*** phys\n"));
3047 DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
3048 cpu_abort(env, "Trying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
3049 (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
3050 AssertFatalFailed();
3051}
3052
3053
3054/** Validate the physical address passed to the read functions.
3055 * Useful for finding non-guest-ram reads/writes. */
3056#if 0 //1 /* disable if it becomes bothersome... */
3057# define VBOX_CHECK_ADDR(GCPhys) AssertMsg(PGMPhysIsGCPhysValid(cpu_single_env->pVM, (GCPhys)), ("%RGp\n", (GCPhys)))
3058#else
3059# define VBOX_CHECK_ADDR(GCPhys) do { } while (0)
3060#endif
3061
3062/**
3063 * Read guest RAM and ROM.
3064 *
3065 * @param SrcGCPhys The source address (guest physical).
3066 * @param pvDst The destination address.
3067 * @param cb Number of bytes
3068 */
3069void remR3PhysRead(RTGCPHYS SrcGCPhys, void *pvDst, unsigned cb)
3070{
3071 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3072 VBOX_CHECK_ADDR(SrcGCPhys);
3073 PGMPhysRead(cpu_single_env->pVM, SrcGCPhys, pvDst, cb);
3074 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3075}
3076
3077
3078/**
3079 * Read guest RAM and ROM, unsigned 8-bit.
3080 *
3081 * @param SrcGCPhys The source address (guest physical).
3082 */
3083uint8_t remR3PhysReadU8(RTGCPHYS SrcGCPhys)
3084{
3085 uint8_t val;
3086 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3087 VBOX_CHECK_ADDR(SrcGCPhys);
3088 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys);
3089 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3090 return val;
3091}
3092
3093
3094/**
3095 * Read guest RAM and ROM, signed 8-bit.
3096 *
3097 * @param SrcGCPhys The source address (guest physical).
3098 */
3099int8_t remR3PhysReadS8(RTGCPHYS SrcGCPhys)
3100{
3101 int8_t val;
3102 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3103 VBOX_CHECK_ADDR(SrcGCPhys);
3104 val = PGMR3PhysReadU8(cpu_single_env->pVM, SrcGCPhys);
3105 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3106 return val;
3107}
3108
3109
3110/**
3111 * Read guest RAM and ROM, unsigned 16-bit.
3112 *
3113 * @param SrcGCPhys The source address (guest physical).
3114 */
3115uint16_t remR3PhysReadU16(RTGCPHYS SrcGCPhys)
3116{
3117 uint16_t val;
3118 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3119 VBOX_CHECK_ADDR(SrcGCPhys);
3120 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys);
3121 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3122 return val;
3123}
3124
3125
3126/**
3127 * Read guest RAM and ROM, signed 16-bit.
3128 *
3129 * @param SrcGCPhys The source address (guest physical).
3130 */
3131int16_t remR3PhysReadS16(RTGCPHYS SrcGCPhys)
3132{
3133 uint16_t val;
3134 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3135 VBOX_CHECK_ADDR(SrcGCPhys);
3136 val = PGMR3PhysReadU16(cpu_single_env->pVM, SrcGCPhys);
3137 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3138 return val;
3139}
3140
3141
3142/**
3143 * Read guest RAM and ROM, unsigned 32-bit.
3144 *
3145 * @param SrcGCPhys The source address (guest physical).
3146 */
3147uint32_t remR3PhysReadU32(RTGCPHYS SrcGCPhys)
3148{
3149 uint32_t val;
3150 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3151 VBOX_CHECK_ADDR(SrcGCPhys);
3152 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys);
3153 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3154 return val;
3155}
3156
3157
3158/**
3159 * Read guest RAM and ROM, signed 32-bit.
3160 *
3161 * @param SrcGCPhys The source address (guest physical).
3162 */
3163int32_t remR3PhysReadS32(RTGCPHYS SrcGCPhys)
3164{
3165 int32_t val;
3166 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3167 VBOX_CHECK_ADDR(SrcGCPhys);
3168 val = PGMR3PhysReadU32(cpu_single_env->pVM, SrcGCPhys);
3169 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3170 return val;
3171}
3172
3173
3174/**
3175 * Read guest RAM and ROM, unsigned 64-bit.
3176 *
3177 * @param SrcGCPhys The source address (guest physical).
3178 */
3179uint64_t remR3PhysReadU64(RTGCPHYS SrcGCPhys)
3180{
3181 uint64_t val;
3182 STAM_PROFILE_ADV_START(&gStatMemRead, a);
3183 VBOX_CHECK_ADDR(SrcGCPhys);
3184 val = PGMR3PhysReadU64(cpu_single_env->pVM, SrcGCPhys);
3185 STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3186 return val;
3187}
3188
3189
3190/**
3191 * Write guest RAM.
3192 *
3193 * @param DstGCPhys The destination address (guest physical).
3194 * @param pvSrc The source address.
3195 * @param cb Number of bytes to write
3196 */
3197void remR3PhysWrite(RTGCPHYS DstGCPhys, const void *pvSrc, unsigned cb)
3198{
3199 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3200 VBOX_CHECK_ADDR(DstGCPhys);
3201 PGMPhysWrite(cpu_single_env->pVM, DstGCPhys, pvSrc, cb);
3202 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3203}
3204
3205
3206/**
3207 * Write guest RAM, unsigned 8-bit.
3208 *
3209 * @param DstGCPhys The destination address (guest physical).
3210 * @param val Value
3211 */
3212void remR3PhysWriteU8(RTGCPHYS DstGCPhys, uint8_t val)
3213{
3214 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3215 VBOX_CHECK_ADDR(DstGCPhys);
3216 PGMR3PhysWriteU8(cpu_single_env->pVM, DstGCPhys, val);
3217 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3218}
3219
3220
3221/**
3222 * Write guest RAM, unsigned 8-bit.
3223 *
3224 * @param DstGCPhys The destination address (guest physical).
3225 * @param val Value
3226 */
3227void remR3PhysWriteU16(RTGCPHYS DstGCPhys, uint16_t val)
3228{
3229 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3230 VBOX_CHECK_ADDR(DstGCPhys);
3231 PGMR3PhysWriteU16(cpu_single_env->pVM, DstGCPhys, val);
3232 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3233}
3234
3235
3236/**
3237 * Write guest RAM, unsigned 32-bit.
3238 *
3239 * @param DstGCPhys The destination address (guest physical).
3240 * @param val Value
3241 */
3242void remR3PhysWriteU32(RTGCPHYS DstGCPhys, uint32_t val)
3243{
3244 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3245 VBOX_CHECK_ADDR(DstGCPhys);
3246 PGMR3PhysWriteU32(cpu_single_env->pVM, DstGCPhys, val);
3247 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3248}
3249
3250
3251/**
3252 * Write guest RAM, unsigned 64-bit.
3253 *
3254 * @param DstGCPhys The destination address (guest physical).
3255 * @param val Value
3256 */
3257void remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val)
3258{
3259 STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3260 VBOX_CHECK_ADDR(DstGCPhys);
3261 PGMR3PhysWriteU64(cpu_single_env->pVM, DstGCPhys, val);
3262 STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3263}
3264
3265#undef LOG_GROUP
3266#define LOG_GROUP LOG_GROUP_REM_MMIO
3267
3268/** Read MMIO memory. */
3269static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3270{
3271 uint32_t u32 = 0;
3272 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3273 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3274 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", GCPhys, u32));
3275 return u32;
3276}
3277
3278/** Read MMIO memory. */
3279static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3280{
3281 uint32_t u32 = 0;
3282 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3283 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3284 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", GCPhys, u32));
3285 return u32;
3286}
3287
3288/** Read MMIO memory. */
3289static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3290{
3291 uint32_t u32 = 0;
3292 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3293 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3294 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", GCPhys, u32));
3295 return u32;
3296}
3297
3298/** Write to MMIO memory. */
3299static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3300{
3301 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3302 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3303 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3304}
3305
3306/** Write to MMIO memory. */
3307static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3308{
3309 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3310 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3311 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3312}
3313
3314/** Write to MMIO memory. */
3315static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3316{
3317 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3318 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3319 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc);
3320}
3321
3322
3323#undef LOG_GROUP
3324#define LOG_GROUP LOG_GROUP_REM_HANDLER
3325
3326/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3327
3328static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3329{
3330 Log2(("remR3HandlerReadU8: GCPhys=%RGp\n", GCPhys));
3331 uint8_t u8;
3332 PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3333 return u8;
3334}
3335
3336static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3337{
3338 Log2(("remR3HandlerReadU16: GCPhys=%RGp\n", GCPhys));
3339 uint16_t u16;
3340 PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3341 return u16;
3342}
3343
3344static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3345{
3346 Log2(("remR3HandlerReadU32: GCPhys=%RGp\n", GCPhys));
3347 uint32_t u32;
3348 PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3349 return u32;
3350}
3351
3352static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3353{
3354 Log2(("remR3HandlerWriteU8: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3355 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3356}
3357
3358static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3359{
3360 Log2(("remR3HandlerWriteU16: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3361 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3362}
3363
3364static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3365{
3366 Log2(("remR3HandlerWriteU32: GCPhys=%RGp u32=%#x\n", GCPhys, u32));
3367 PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3368}
3369
3370/* -+- disassembly -+- */
3371
3372#undef LOG_GROUP
3373#define LOG_GROUP LOG_GROUP_REM_DISAS
3374
3375
3376/**
3377 * Enables or disables singled stepped disassembly.
3378 *
3379 * @returns VBox status code.
3380 * @param pVM VM handle.
3381 * @param fEnable To enable set this flag, to disable clear it.
3382 */
3383static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3384{
3385 LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3386 VM_ASSERT_EMT(pVM);
3387
3388 if (fEnable)
3389 pVM->rem.s.Env.state |= CPU_EMULATE_SINGLE_STEP;
3390 else
3391 pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3392 return VINF_SUCCESS;
3393}
3394
3395
3396/**
3397 * Enables or disables singled stepped disassembly.
3398 *
3399 * @returns VBox status code.
3400 * @param pVM VM handle.
3401 * @param fEnable To enable set this flag, to disable clear it.
3402 */
3403REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3404{
3405 PVMREQ pReq;
3406 int rc;
3407
3408 LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3409 if (VM_IS_EMT(pVM))
3410 return remR3DisasEnableStepping(pVM, fEnable);
3411
3412 rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3413 AssertRC(rc);
3414 if (RT_SUCCESS(rc))
3415 rc = pReq->iStatus;
3416 VMR3ReqFree(pReq);
3417 return rc;
3418}
3419
3420
3421#if defined(VBOX_WITH_DEBUGGER) && !(defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64))
3422/**
3423 * External Debugger Command: .remstep [on|off|1|0]
3424 */
3425static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3426{
3427 bool fEnable;
3428 int rc;
3429
3430 /* print status */
3431 if (cArgs == 0)
3432 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3433 pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3434
3435 /* convert the argument and change the mode. */
3436 rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3437 if (RT_FAILURE(rc))
3438 return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3439 rc = REMR3DisasEnableStepping(pVM, fEnable);
3440 if (RT_FAILURE(rc))
3441 return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3442 return rc;
3443}
3444#endif
3445
3446
3447/**
3448 * Disassembles n instructions and prints them to the log.
3449 *
3450 * @returns Success indicator.
3451 * @param env Pointer to the recompiler CPU structure.
3452 * @param f32BitCode Indicates that whether or not the code should
3453 * be disassembled as 16 or 32 bit. If -1 the CS
3454 * selector will be inspected.
3455 * @param nrInstructions Nr of instructions to disassemble
3456 * @param pszPrefix
3457 * @remark not currently used for anything but ad-hoc debugging.
3458 */
3459bool remR3DisasBlock(CPUState *env, int f32BitCode, int nrInstructions, char *pszPrefix)
3460{
3461 int i;
3462
3463 /*
3464 * Determin 16/32 bit mode.
3465 */
3466 if (f32BitCode == -1)
3467 f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3468
3469 /*
3470 * Convert cs:eip to host context address.
3471 * We don't care to much about cross page correctness presently.
3472 */
3473 RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3474 void *pvPC;
3475 if (f32BitCode && (env->cr[0] & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG))
3476 {
3477 Assert(PGMGetGuestMode(env->pVM) < PGMMODE_AMD64);
3478
3479 /* convert eip to physical address. */
3480 int rc = PGMPhysGCPtr2R3PtrByGstCR3(env->pVM,
3481 GCPtrPC,
3482 env->cr[3],
3483 env->cr[4] & (X86_CR4_PSE | X86_CR4_PAE), /** @todo add longmode flag */
3484 &pvPC);
3485 if (RT_FAILURE(rc))
3486 {
3487 if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3488 return false;
3489 pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3490 + (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3491 }
3492 }
3493 else
3494 {
3495 /* physical address */
3496 int rc = PGMPhysGCPhys2R3Ptr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions * 16, &pvPC);
3497 if (RT_FAILURE(rc))
3498 return false;
3499 }
3500
3501 /*
3502 * Disassemble.
3503 */
3504 RTINTPTR off = env->eip - (RTGCUINTPTR)pvPC;
3505 DISCPUSTATE Cpu;
3506 Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3507 Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3508 //Cpu.dwUserData[0] = (uintptr_t)pVM;
3509 //Cpu.dwUserData[1] = (uintptr_t)pvPC;
3510 //Cpu.dwUserData[2] = GCPtrPC;
3511
3512 for (i=0;i<nrInstructions;i++)
3513 {
3514 char szOutput[256];
3515 uint32_t cbOp;
3516 if (RT_FAILURE(DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0])))
3517 return false;
3518 if (pszPrefix)
3519 Log(("%s: %s", pszPrefix, szOutput));
3520 else
3521 Log(("%s", szOutput));
3522
3523 pvPC += cbOp;
3524 }
3525 return true;
3526}
3527
3528
3529/** @todo need to test the new code, using the old code in the mean while. */
3530#define USE_OLD_DUMP_AND_DISASSEMBLY
3531
3532/**
3533 * Disassembles one instruction and prints it to the log.
3534 *
3535 * @returns Success indicator.
3536 * @param env Pointer to the recompiler CPU structure.
3537 * @param f32BitCode Indicates that whether or not the code should
3538 * be disassembled as 16 or 32 bit. If -1 the CS
3539 * selector will be inspected.
3540 * @param pszPrefix
3541 */
3542bool remR3DisasInstr(CPUState *env, int f32BitCode, char *pszPrefix)
3543{
3544#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3545 PVM pVM = env->pVM;
3546
3547 /* Doesn't work in long mode. */
3548 if (env->hflags & HF_LMA_MASK)
3549 return false;
3550
3551 /*
3552 * Determin 16/32 bit mode.
3553 */
3554 if (f32BitCode == -1)
3555 f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3556
3557 /*
3558 * Log registers
3559 */
3560 if (LogIs2Enabled())
3561 {
3562 remR3StateUpdate(pVM);
3563 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3564 }
3565
3566 /*
3567 * Convert cs:eip to host context address.
3568 * We don't care to much about cross page correctness presently.
3569 */
3570 RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3571 void *pvPC;
3572 if ((env->cr[0] & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG))
3573 {
3574 /* convert eip to physical address. */
3575 int rc = PGMPhysGCPtr2R3PtrByGstCR3(pVM,
3576 GCPtrPC,
3577 env->cr[3],
3578 env->cr[4] & (X86_CR4_PSE | X86_CR4_PAE),
3579 &pvPC);
3580 if (RT_FAILURE(rc))
3581 {
3582 if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3583 return false;
3584 pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3585 + (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3586 }
3587 }
3588 else
3589 {
3590
3591 /* physical address */
3592 int rc = PGMPhysGCPhys2R3Ptr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3593 if (RT_FAILURE(rc))
3594 return false;
3595 }
3596
3597 /*
3598 * Disassemble.
3599 */
3600 RTINTPTR off = env->eip - (RTGCUINTPTR)pvPC;
3601 DISCPUSTATE Cpu;
3602 Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3603 Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3604 //Cpu.dwUserData[0] = (uintptr_t)pVM;
3605 //Cpu.dwUserData[1] = (uintptr_t)pvPC;
3606 //Cpu.dwUserData[2] = GCPtrPC;
3607 char szOutput[256];
3608 uint32_t cbOp;
3609 if (RT_FAILURE(DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0])))
3610 return false;
3611
3612 if (!f32BitCode)
3613 {
3614 if (pszPrefix)
3615 Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3616 else
3617 Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3618 }
3619 else
3620 {
3621 if (pszPrefix)
3622 Log(("%s: %s", pszPrefix, szOutput));
3623 else
3624 Log(("%s", szOutput));
3625 }
3626 return true;
3627
3628#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3629 PVM pVM = env->pVM;
3630 const bool fLog = LogIsEnabled();
3631 const bool fLog2 = LogIs2Enabled();
3632 int rc = VINF_SUCCESS;
3633
3634 /*
3635 * Don't bother if there ain't any log output to do.
3636 */
3637 if (!fLog && !fLog2)
3638 return true;
3639
3640 /*
3641 * Update the state so DBGF reads the correct register values.
3642 */
3643 remR3StateUpdate(pVM);
3644
3645 /*
3646 * Log registers if requested.
3647 */
3648 if (!fLog2)
3649 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3650
3651 /*
3652 * Disassemble to log.
3653 */
3654 if (fLog)
3655 rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3656
3657 return RT_SUCCESS(rc);
3658#endif
3659}
3660
3661
3662/**
3663 * Disassemble recompiled code.
3664 *
3665 * @param phFileIgnored Ignored, logfile usually.
3666 * @param pvCode Pointer to the code block.
3667 * @param cb Size of the code block.
3668 */
3669void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
3670{
3671 if (LogIs2Enabled())
3672 {
3673 unsigned off = 0;
3674 char szOutput[256];
3675 DISCPUSTATE Cpu;
3676
3677 memset(&Cpu, 0, sizeof(Cpu));
3678#ifdef RT_ARCH_X86
3679 Cpu.mode = CPUMODE_32BIT;
3680#else
3681 Cpu.mode = CPUMODE_64BIT;
3682#endif
3683
3684 RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3685 while (off < cb)
3686 {
3687 uint32_t cbInstr;
3688 if (RT_SUCCESS(DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput)))
3689 RTLogPrintf("%s", szOutput);
3690 else
3691 {
3692 RTLogPrintf("disas error\n");
3693 cbInstr = 1;
3694#ifdef RT_ARCH_AMD64 /** @todo remove when DISInstr starts supporing 64-bit code. */
3695 break;
3696#endif
3697 }
3698 off += cbInstr;
3699 }
3700 }
3701 NOREF(phFileIgnored);
3702}
3703
3704
3705/**
3706 * Disassemble guest code.
3707 *
3708 * @param phFileIgnored Ignored, logfile usually.
3709 * @param uCode The guest address of the code to disassemble. (flat?)
3710 * @param cb Number of bytes to disassemble.
3711 * @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3712 */
3713void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3714{
3715 if (LogIs2Enabled())
3716 {
3717 PVM pVM = cpu_single_env->pVM;
3718
3719 /*
3720 * Update the state so DBGF reads the correct register values (flags).
3721 */
3722 remR3StateUpdate(pVM);
3723
3724 /*
3725 * Do the disassembling.
3726 */
3727 RTLogPrintf("Guest Code: PC=%RGp %#RGp (%RGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3728 RTSEL cs = cpu_single_env->segs[R_CS].selector;
3729 RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3730 for (;;)
3731 {
3732 char szBuf[256];
3733 uint32_t cbInstr;
3734 int rc = DBGFR3DisasInstrEx(pVM,
3735 cs,
3736 eip,
3737 0,
3738 szBuf, sizeof(szBuf),
3739 &cbInstr);
3740 if (RT_SUCCESS(rc))
3741 RTLogPrintf("%RGp %s\n", uCode, szBuf);
3742 else
3743 {
3744 RTLogPrintf("%RGp %04x:%RGv: %s\n", uCode, cs, eip, szBuf);
3745 cbInstr = 1;
3746 }
3747
3748 /* next */
3749 if (cb <= cbInstr)
3750 break;
3751 cb -= cbInstr;
3752 uCode += cbInstr;
3753 eip += cbInstr;
3754 }
3755 }
3756 NOREF(phFileIgnored);
3757}
3758
3759
3760/**
3761 * Looks up a guest symbol.
3762 *
3763 * @returns Pointer to symbol name. This is a static buffer.
3764 * @param orig_addr The address in question.
3765 */
3766const char *lookup_symbol(target_ulong orig_addr)
3767{
3768 RTGCINTPTR off = 0;
3769 DBGFSYMBOL Sym;
3770 PVM pVM = cpu_single_env->pVM;
3771 int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3772 if (RT_SUCCESS(rc))
3773 {
3774 static char szSym[sizeof(Sym.szName) + 48];
3775 if (!off)
3776 RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3777 else if (off > 0)
3778 RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3779 else
3780 RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3781 return szSym;
3782 }
3783 return "<N/A>";
3784}
3785
3786
3787#undef LOG_GROUP
3788#define LOG_GROUP LOG_GROUP_REM
3789
3790
3791/* -+- FF notifications -+- */
3792
3793
3794/**
3795 * Notification about a pending interrupt.
3796 *
3797 * @param pVM VM Handle.
3798 * @param u8Interrupt Interrupt
3799 * @thread The emulation thread.
3800 */
3801REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3802{
3803 Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3804 pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3805}
3806
3807/**
3808 * Notification about a pending interrupt.
3809 *
3810 * @returns Pending interrupt or REM_NO_PENDING_IRQ
3811 * @param pVM VM Handle.
3812 * @thread The emulation thread.
3813 */
3814REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3815{
3816 return pVM->rem.s.u32PendingInterrupt;
3817}
3818
3819/**
3820 * Notification about the interrupt FF being set.
3821 *
3822 * @param pVM VM Handle.
3823 * @thread The emulation thread.
3824 */
3825REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3826{
3827 LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3828 (pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3829 if (pVM->rem.s.fInREM)
3830 {
3831 if (VM_IS_EMT(pVM))
3832 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3833 else
3834 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3835 }
3836}
3837
3838
3839/**
3840 * Notification about the interrupt FF being set.
3841 *
3842 * @param pVM VM Handle.
3843 * @thread Any.
3844 */
3845REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3846{
3847 LogFlow(("REMR3NotifyInterruptClear:\n"));
3848 if (pVM->rem.s.fInREM)
3849 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3850}
3851
3852
3853/**
3854 * Notification about pending timer(s).
3855 *
3856 * @param pVM VM Handle.
3857 * @thread Any.
3858 */
3859REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3860{
3861#ifndef DEBUG_bird
3862 LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3863#endif
3864 if (pVM->rem.s.fInREM)
3865 {
3866 if (VM_IS_EMT(pVM))
3867 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3868 else
3869 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3870 }
3871}
3872
3873
3874/**
3875 * Notification about pending DMA transfers.
3876 *
3877 * @param pVM VM Handle.
3878 * @thread Any.
3879 */
3880REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3881{
3882 LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3883 if (pVM->rem.s.fInREM)
3884 {
3885 if (VM_IS_EMT(pVM))
3886 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3887 else
3888 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3889 }
3890}
3891
3892
3893/**
3894 * Notification about pending timer(s).
3895 *
3896 * @param pVM VM Handle.
3897 * @thread Any.
3898 */
3899REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3900{
3901 LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3902 if (pVM->rem.s.fInREM)
3903 {
3904 if (VM_IS_EMT(pVM))
3905 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3906 else
3907 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3908 }
3909}
3910
3911
3912/**
3913 * Notification about pending FF set by an external thread.
3914 *
3915 * @param pVM VM handle.
3916 * @thread Any.
3917 */
3918REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3919{
3920 LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3921 if (pVM->rem.s.fInREM)
3922 {
3923 if (VM_IS_EMT(pVM))
3924 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3925 else
3926 ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3927 }
3928}
3929
3930
3931#ifdef VBOX_WITH_STATISTICS
3932void remR3ProfileStart(int statcode)
3933{
3934 STAMPROFILEADV *pStat;
3935 switch(statcode)
3936 {
3937 case STATS_EMULATE_SINGLE_INSTR:
3938 pStat = &gStatExecuteSingleInstr;
3939 break;
3940 case STATS_QEMU_COMPILATION:
3941 pStat = &gStatCompilationQEmu;
3942 break;
3943 case STATS_QEMU_RUN_EMULATED_CODE:
3944 pStat = &gStatRunCodeQEmu;
3945 break;
3946 case STATS_QEMU_TOTAL:
3947 pStat = &gStatTotalTimeQEmu;
3948 break;
3949 case STATS_QEMU_RUN_TIMERS:
3950 pStat = &gStatTimers;
3951 break;
3952 case STATS_TLB_LOOKUP:
3953 pStat= &gStatTBLookup;
3954 break;
3955 case STATS_IRQ_HANDLING:
3956 pStat= &gStatIRQ;
3957 break;
3958 case STATS_RAW_CHECK:
3959 pStat = &gStatRawCheck;
3960 break;
3961
3962 default:
3963 AssertMsgFailed(("unknown stat %d\n", statcode));
3964 return;
3965 }
3966 STAM_PROFILE_ADV_START(pStat, a);
3967}
3968
3969
3970void remR3ProfileStop(int statcode)
3971{
3972 STAMPROFILEADV *pStat;
3973 switch(statcode)
3974 {
3975 case STATS_EMULATE_SINGLE_INSTR:
3976 pStat = &gStatExecuteSingleInstr;
3977 break;
3978 case STATS_QEMU_COMPILATION:
3979 pStat = &gStatCompilationQEmu;
3980 break;
3981 case STATS_QEMU_RUN_EMULATED_CODE:
3982 pStat = &gStatRunCodeQEmu;
3983 break;
3984 case STATS_QEMU_TOTAL:
3985 pStat = &gStatTotalTimeQEmu;
3986 break;
3987 case STATS_QEMU_RUN_TIMERS:
3988 pStat = &gStatTimers;
3989 break;
3990 case STATS_TLB_LOOKUP:
3991 pStat= &gStatTBLookup;
3992 break;
3993 case STATS_IRQ_HANDLING:
3994 pStat= &gStatIRQ;
3995 break;
3996 case STATS_RAW_CHECK:
3997 pStat = &gStatRawCheck;
3998 break;
3999 default:
4000 AssertMsgFailed(("unknown stat %d\n", statcode));
4001 return;
4002 }
4003 STAM_PROFILE_ADV_STOP(pStat, a);
4004}
4005#endif
4006
4007/**
4008 * Raise an RC, force rem exit.
4009 *
4010 * @param pVM VM handle.
4011 * @param rc The rc.
4012 */
4013void remR3RaiseRC(PVM pVM, int rc)
4014{
4015 Log(("remR3RaiseRC: rc=%Rrc\n", rc));
4016 Assert(pVM->rem.s.fInREM);
4017 VM_ASSERT_EMT(pVM);
4018 pVM->rem.s.rc = rc;
4019 cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
4020}
4021
4022
4023/* -+- timers -+- */
4024
4025uint64_t cpu_get_tsc(CPUX86State *env)
4026{
4027 STAM_COUNTER_INC(&gStatCpuGetTSC);
4028 return TMCpuTickGet(env->pVM);
4029}
4030
4031
4032/* -+- interrupts -+- */
4033
4034void cpu_set_ferr(CPUX86State *env)
4035{
4036 int rc = PDMIsaSetIrq(env->pVM, 13, 1);
4037 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
4038}
4039
4040int cpu_get_pic_interrupt(CPUState *env)
4041{
4042 uint8_t u8Interrupt;
4043 int rc;
4044
4045 /* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
4046 * In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
4047 * with the (a)pic.
4048 */
4049 /** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
4050 /** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
4051 * if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4052 * remove this kludge. */
4053 if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4054 {
4055 rc = VINF_SUCCESS;
4056 Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
4057 u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4058 env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4059 }
4060 else
4061 rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
4062
4063 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Rrc\n", u8Interrupt, rc));
4064 if (RT_SUCCESS(rc))
4065 {
4066 if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
4067 env->interrupt_request |= CPU_INTERRUPT_HARD;
4068 return u8Interrupt;
4069 }
4070 return -1;
4071}
4072
4073
4074/* -+- local apic -+- */
4075
4076void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4077{
4078 int rc = PDMApicSetBase(env->pVM, val);
4079 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Rrc\n", val, rc)); NOREF(rc);
4080}
4081
4082uint64_t cpu_get_apic_base(CPUX86State *env)
4083{
4084 uint64_t u64;
4085 int rc = PDMApicGetBase(env->pVM, &u64);
4086 if (RT_SUCCESS(rc))
4087 {
4088 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4089 return u64;
4090 }
4091 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", rc));
4092 return 0;
4093}
4094
4095void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4096{
4097 int rc = PDMApicSetTPR(env->pVM, val);
4098 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Rrc\n", val, rc)); NOREF(rc);
4099}
4100
4101uint8_t cpu_get_apic_tpr(CPUX86State *env)
4102{
4103 uint8_t u8;
4104 int rc = PDMApicGetTPR(env->pVM, &u8, NULL);
4105 if (RT_SUCCESS(rc))
4106 {
4107 LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4108 return u8;
4109 }
4110 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Rrc)\n", rc));
4111 return 0;
4112}
4113
4114
4115uint64_t cpu_apic_rdmsr(CPUX86State *env, uint32_t reg)
4116{
4117 uint64_t value;
4118 int rc = PDMApicReadMSR(env->pVM, 0/* cpu */, reg, &value);
4119 if (RT_SUCCESS(rc))
4120 {
4121 LogFlow(("cpu_apic_rdms returns %#x\n", value));
4122 return value;
4123 }
4124 /** @todo: exception ? */
4125 LogFlow(("cpu_apic_rdms returns 0 (rc=%Rrc)\n", rc));
4126 return value;
4127}
4128
4129void cpu_apic_wrmsr(CPUX86State *env, uint32_t reg, uint64_t value)
4130{
4131 int rc = PDMApicWriteMSR(env->pVM, 0 /* cpu */, reg, value);
4132 /** @todo: exception if error ? */
4133 LogFlow(("cpu_apic_wrmsr: rc=%Rrc\n", rc)); NOREF(rc);
4134}
4135
4136uint64_t cpu_rdmsr(CPUX86State *env, uint32_t msr)
4137{
4138 return CPUMGetGuestMsr(env->pVM, msr);
4139}
4140
4141void cpu_wrmsr(CPUX86State *env, uint32_t msr, uint64_t val)
4142{
4143 CPUMSetGuestMsr(env->pVM, msr, val);
4144}
4145
4146/* -+- I/O Ports -+- */
4147
4148#undef LOG_GROUP
4149#define LOG_GROUP LOG_GROUP_REM_IOPORT
4150
4151void cpu_outb(CPUState *env, int addr, int val)
4152{
4153 if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4154 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4155
4156 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4157 if (RT_LIKELY(rc == VINF_SUCCESS))
4158 return;
4159 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4160 {
4161 Log(("cpu_outb: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4162 remR3RaiseRC(env->pVM, rc);
4163 return;
4164 }
4165 remAbort(rc, __FUNCTION__);
4166}
4167
4168void cpu_outw(CPUState *env, int addr, int val)
4169{
4170 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4171 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4172 if (RT_LIKELY(rc == VINF_SUCCESS))
4173 return;
4174 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4175 {
4176 Log(("cpu_outw: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4177 remR3RaiseRC(env->pVM, rc);
4178 return;
4179 }
4180 remAbort(rc, __FUNCTION__);
4181}
4182
4183void cpu_outl(CPUState *env, int addr, int val)
4184{
4185 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4186 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4187 if (RT_LIKELY(rc == VINF_SUCCESS))
4188 return;
4189 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4190 {
4191 Log(("cpu_outl: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc));
4192 remR3RaiseRC(env->pVM, rc);
4193 return;
4194 }
4195 remAbort(rc, __FUNCTION__);
4196}
4197
4198int cpu_inb(CPUState *env, int addr)
4199{
4200 uint32_t u32 = 0;
4201 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4202 if (RT_LIKELY(rc == VINF_SUCCESS))
4203 {
4204 if (/*addr != 0x61 && */addr != 0x71)
4205 Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4206 return (int)u32;
4207 }
4208 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4209 {
4210 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4211 remR3RaiseRC(env->pVM, rc);
4212 return (int)u32;
4213 }
4214 remAbort(rc, __FUNCTION__);
4215 return 0xff;
4216}
4217
4218int cpu_inw(CPUState *env, int addr)
4219{
4220 uint32_t u32 = 0;
4221 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4222 if (RT_LIKELY(rc == VINF_SUCCESS))
4223 {
4224 Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4225 return (int)u32;
4226 }
4227 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4228 {
4229 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4230 remR3RaiseRC(env->pVM, rc);
4231 return (int)u32;
4232 }
4233 remAbort(rc, __FUNCTION__);
4234 return 0xffff;
4235}
4236
4237int cpu_inl(CPUState *env, int addr)
4238{
4239 uint32_t u32 = 0;
4240 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4241 if (RT_LIKELY(rc == VINF_SUCCESS))
4242 {
4243//if (addr==0x01f0 && u32 == 0x6b6d)
4244// loglevel = ~0;
4245 Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4246 return (int)u32;
4247 }
4248 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4249 {
4250 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc));
4251 remR3RaiseRC(env->pVM, rc);
4252 return (int)u32;
4253 }
4254 remAbort(rc, __FUNCTION__);
4255 return 0xffffffff;
4256}
4257
4258#undef LOG_GROUP
4259#define LOG_GROUP LOG_GROUP_REM
4260
4261
4262/* -+- helpers and misc other interfaces -+- */
4263
4264/**
4265 * Perform the CPUID instruction.
4266 *
4267 * ASMCpuId cannot be invoked from some source files where this is used because of global
4268 * register allocations.
4269 *
4270 * @param env Pointer to the recompiler CPU structure.
4271 * @param uOperator CPUID operation (eax).
4272 * @param pvEAX Where to store eax.
4273 * @param pvEBX Where to store ebx.
4274 * @param pvECX Where to store ecx.
4275 * @param pvEDX Where to store edx.
4276 */
4277void remR3CpuId(CPUState *env, unsigned uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
4278{
4279 CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t *)pvEAX, (uint32_t *)pvEBX, (uint32_t *)pvECX, (uint32_t *)pvEDX);
4280}
4281
4282
4283#if 0 /* not used */
4284/**
4285 * Interface for qemu hardware to report back fatal errors.
4286 */
4287void hw_error(const char *pszFormat, ...)
4288{
4289 /*
4290 * Bitch about it.
4291 */
4292 /** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4293 * this in my Odin32 tree at home! */
4294 va_list args;
4295 va_start(args, pszFormat);
4296 RTLogPrintf("fatal error in virtual hardware:");
4297 RTLogPrintfV(pszFormat, args);
4298 va_end(args);
4299 AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4300
4301 /*
4302 * If we're in REM context we'll sync back the state before 'jumping' to
4303 * the EMs failure handling.
4304 */
4305 PVM pVM = cpu_single_env->pVM;
4306 if (pVM->rem.s.fInREM)
4307 REMR3StateBack(pVM);
4308 EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4309 AssertMsgFailed(("EMR3FatalError returned!\n"));
4310}
4311#endif
4312
4313/**
4314 * Interface for the qemu cpu to report unhandled situation
4315 * raising a fatal VM error.
4316 */
4317void cpu_abort(CPUState *env, const char *pszFormat, ...)
4318{
4319 /*
4320 * Bitch about it.
4321 */
4322 RTLogFlags(NULL, "nodisabled nobuffered");
4323 va_list args;
4324 va_start(args, pszFormat);
4325 RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4326 va_end(args);
4327 va_start(args, pszFormat);
4328 AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4329 va_end(args);
4330
4331 /*
4332 * If we're in REM context we'll sync back the state before 'jumping' to
4333 * the EMs failure handling.
4334 */
4335 PVM pVM = cpu_single_env->pVM;
4336 if (pVM->rem.s.fInREM)
4337 REMR3StateBack(pVM);
4338 EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4339 AssertMsgFailed(("EMR3FatalError returned!\n"));
4340}
4341
4342
4343/**
4344 * Aborts the VM.
4345 *
4346 * @param rc VBox error code.
4347 * @param pszTip Hint about why/when this happend.
4348 */
4349static void remAbort(int rc, const char *pszTip)
4350{
4351 /*
4352 * Bitch about it.
4353 */
4354 RTLogPrintf("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip);
4355 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip));
4356
4357 /*
4358 * Jump back to where we entered the recompiler.
4359 */
4360 PVM pVM = cpu_single_env->pVM;
4361 if (pVM->rem.s.fInREM)
4362 REMR3StateBack(pVM);
4363 EMR3FatalError(pVM, rc);
4364 AssertMsgFailed(("EMR3FatalError returned!\n"));
4365}
4366
4367
4368/**
4369 * Dumps a linux system call.
4370 * @param pVM VM handle.
4371 */
4372void remR3DumpLnxSyscall(PVM pVM)
4373{
4374 static const char *apsz[] =
4375 {
4376 "sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4377 "sys_exit",
4378 "sys_fork",
4379 "sys_read",
4380 "sys_write",
4381 "sys_open", /* 5 */
4382 "sys_close",
4383 "sys_waitpid",
4384 "sys_creat",
4385 "sys_link",
4386 "sys_unlink", /* 10 */
4387 "sys_execve",
4388 "sys_chdir",
4389 "sys_time",
4390 "sys_mknod",
4391 "sys_chmod", /* 15 */
4392 "sys_lchown16",
4393 "sys_ni_syscall", /* old break syscall holder */
4394 "sys_stat",
4395 "sys_lseek",
4396 "sys_getpid", /* 20 */
4397 "sys_mount",
4398 "sys_oldumount",
4399 "sys_setuid16",
4400 "sys_getuid16",
4401 "sys_stime", /* 25 */
4402 "sys_ptrace",
4403 "sys_alarm",
4404 "sys_fstat",
4405 "sys_pause",
4406 "sys_utime", /* 30 */
4407 "sys_ni_syscall", /* old stty syscall holder */
4408 "sys_ni_syscall", /* old gtty syscall holder */
4409 "sys_access",
4410 "sys_nice",
4411 "sys_ni_syscall", /* 35 - old ftime syscall holder */
4412 "sys_sync",
4413 "sys_kill",
4414 "sys_rename",
4415 "sys_mkdir",
4416 "sys_rmdir", /* 40 */
4417 "sys_dup",
4418 "sys_pipe",
4419 "sys_times",
4420 "sys_ni_syscall", /* old prof syscall holder */
4421 "sys_brk", /* 45 */
4422 "sys_setgid16",
4423 "sys_getgid16",
4424 "sys_signal",
4425 "sys_geteuid16",
4426 "sys_getegid16", /* 50 */
4427 "sys_acct",
4428 "sys_umount", /* recycled never used phys() */
4429 "sys_ni_syscall", /* old lock syscall holder */
4430 "sys_ioctl",
4431 "sys_fcntl", /* 55 */
4432 "sys_ni_syscall", /* old mpx syscall holder */
4433 "sys_setpgid",
4434 "sys_ni_syscall", /* old ulimit syscall holder */
4435 "sys_olduname",
4436 "sys_umask", /* 60 */
4437 "sys_chroot",
4438 "sys_ustat",
4439 "sys_dup2",
4440 "sys_getppid",
4441 "sys_getpgrp", /* 65 */
4442 "sys_setsid",
4443 "sys_sigaction",
4444 "sys_sgetmask",
4445 "sys_ssetmask",
4446 "sys_setreuid16", /* 70 */
4447 "sys_setregid16",
4448 "sys_sigsuspend",
4449 "sys_sigpending",
4450 "sys_sethostname",
4451 "sys_setrlimit", /* 75 */
4452 "sys_old_getrlimit",
4453 "sys_getrusage",
4454 "sys_gettimeofday",
4455 "sys_settimeofday",
4456 "sys_getgroups16", /* 80 */
4457 "sys_setgroups16",
4458 "old_select",
4459 "sys_symlink",
4460 "sys_lstat",
4461 "sys_readlink", /* 85 */
4462 "sys_uselib",
4463 "sys_swapon",
4464 "sys_reboot",
4465 "old_readdir",
4466 "old_mmap", /* 90 */
4467 "sys_munmap",
4468 "sys_truncate",
4469 "sys_ftruncate",
4470 "sys_fchmod",
4471 "sys_fchown16", /* 95 */
4472 "sys_getpriority",
4473 "sys_setpriority",
4474 "sys_ni_syscall", /* old profil syscall holder */
4475 "sys_statfs",
4476 "sys_fstatfs", /* 100 */
4477 "sys_ioperm",
4478 "sys_socketcall",
4479 "sys_syslog",
4480 "sys_setitimer",
4481 "sys_getitimer", /* 105 */
4482 "sys_newstat",
4483 "sys_newlstat",
4484 "sys_newfstat",
4485 "sys_uname",
4486 "sys_iopl", /* 110 */
4487 "sys_vhangup",
4488 "sys_ni_syscall", /* old "idle" system call */
4489 "sys_vm86old",
4490 "sys_wait4",
4491 "sys_swapoff", /* 115 */
4492 "sys_sysinfo",
4493 "sys_ipc",
4494 "sys_fsync",
4495 "sys_sigreturn",
4496 "sys_clone", /* 120 */
4497 "sys_setdomainname",
4498 "sys_newuname",
4499 "sys_modify_ldt",
4500 "sys_adjtimex",
4501 "sys_mprotect", /* 125 */
4502 "sys_sigprocmask",
4503 "sys_ni_syscall", /* old "create_module" */
4504 "sys_init_module",
4505 "sys_delete_module",
4506 "sys_ni_syscall", /* 130: old "get_kernel_syms" */
4507 "sys_quotactl",
4508 "sys_getpgid",
4509 "sys_fchdir",
4510 "sys_bdflush",
4511 "sys_sysfs", /* 135 */
4512 "sys_personality",
4513 "sys_ni_syscall", /* reserved for afs_syscall */
4514 "sys_setfsuid16",
4515 "sys_setfsgid16",
4516 "sys_llseek", /* 140 */
4517 "sys_getdents",
4518 "sys_select",
4519 "sys_flock",
4520 "sys_msync",
4521 "sys_readv", /* 145 */
4522 "sys_writev",
4523 "sys_getsid",
4524 "sys_fdatasync",
4525 "sys_sysctl",
4526 "sys_mlock", /* 150 */
4527 "sys_munlock",
4528 "sys_mlockall",
4529 "sys_munlockall",
4530 "sys_sched_setparam",
4531 "sys_sched_getparam", /* 155 */
4532 "sys_sched_setscheduler",
4533 "sys_sched_getscheduler",
4534 "sys_sched_yield",
4535 "sys_sched_get_priority_max",
4536 "sys_sched_get_priority_min", /* 160 */
4537 "sys_sched_rr_get_interval",
4538 "sys_nanosleep",
4539 "sys_mremap",
4540 "sys_setresuid16",
4541 "sys_getresuid16", /* 165 */
4542 "sys_vm86",
4543 "sys_ni_syscall", /* Old sys_query_module */
4544 "sys_poll",
4545 "sys_nfsservctl",
4546 "sys_setresgid16", /* 170 */
4547 "sys_getresgid16",
4548 "sys_prctl",
4549 "sys_rt_sigreturn",
4550 "sys_rt_sigaction",
4551 "sys_rt_sigprocmask", /* 175 */
4552 "sys_rt_sigpending",
4553 "sys_rt_sigtimedwait",
4554 "sys_rt_sigqueueinfo",
4555 "sys_rt_sigsuspend",
4556 "sys_pread64", /* 180 */
4557 "sys_pwrite64",
4558 "sys_chown16",
4559 "sys_getcwd",
4560 "sys_capget",
4561 "sys_capset", /* 185 */
4562 "sys_sigaltstack",
4563 "sys_sendfile",
4564 "sys_ni_syscall", /* reserved for streams1 */
4565 "sys_ni_syscall", /* reserved for streams2 */
4566 "sys_vfork", /* 190 */
4567 "sys_getrlimit",
4568 "sys_mmap2",
4569 "sys_truncate64",
4570 "sys_ftruncate64",
4571 "sys_stat64", /* 195 */
4572 "sys_lstat64",
4573 "sys_fstat64",
4574 "sys_lchown",
4575 "sys_getuid",
4576 "sys_getgid", /* 200 */
4577 "sys_geteuid",
4578 "sys_getegid",
4579 "sys_setreuid",
4580 "sys_setregid",
4581 "sys_getgroups", /* 205 */
4582 "sys_setgroups",
4583 "sys_fchown",
4584 "sys_setresuid",
4585 "sys_getresuid",
4586 "sys_setresgid", /* 210 */
4587 "sys_getresgid",
4588 "sys_chown",
4589 "sys_setuid",
4590 "sys_setgid",
4591 "sys_setfsuid", /* 215 */
4592 "sys_setfsgid",
4593 "sys_pivot_root",
4594 "sys_mincore",
4595 "sys_madvise",
4596 "sys_getdents64", /* 220 */
4597 "sys_fcntl64",
4598 "sys_ni_syscall", /* reserved for TUX */
4599 "sys_ni_syscall",
4600 "sys_gettid",
4601 "sys_readahead", /* 225 */
4602 "sys_setxattr",
4603 "sys_lsetxattr",
4604 "sys_fsetxattr",
4605 "sys_getxattr",
4606 "sys_lgetxattr", /* 230 */
4607 "sys_fgetxattr",
4608 "sys_listxattr",
4609 "sys_llistxattr",
4610 "sys_flistxattr",
4611 "sys_removexattr", /* 235 */
4612 "sys_lremovexattr",
4613 "sys_fremovexattr",
4614 "sys_tkill",
4615 "sys_sendfile64",
4616 "sys_futex", /* 240 */
4617 "sys_sched_setaffinity",
4618 "sys_sched_getaffinity",
4619 "sys_set_thread_area",
4620 "sys_get_thread_area",
4621 "sys_io_setup", /* 245 */
4622 "sys_io_destroy",
4623 "sys_io_getevents",
4624 "sys_io_submit",
4625 "sys_io_cancel",
4626 "sys_fadvise64", /* 250 */
4627 "sys_ni_syscall",
4628 "sys_exit_group",
4629 "sys_lookup_dcookie",
4630 "sys_epoll_create",
4631 "sys_epoll_ctl", /* 255 */
4632 "sys_epoll_wait",
4633 "sys_remap_file_pages",
4634 "sys_set_tid_address",
4635 "sys_timer_create",
4636 "sys_timer_settime", /* 260 */
4637 "sys_timer_gettime",
4638 "sys_timer_getoverrun",
4639 "sys_timer_delete",
4640 "sys_clock_settime",
4641 "sys_clock_gettime", /* 265 */
4642 "sys_clock_getres",
4643 "sys_clock_nanosleep",
4644 "sys_statfs64",
4645 "sys_fstatfs64",
4646 "sys_tgkill", /* 270 */
4647 "sys_utimes",
4648 "sys_fadvise64_64",
4649 "sys_ni_syscall" /* sys_vserver */
4650 };
4651
4652 uint32_t uEAX = CPUMGetGuestEAX(pVM);
4653 switch (uEAX)
4654 {
4655 default:
4656 if (uEAX < RT_ELEMENTS(apsz))
4657 Log(("REM: linux syscall %3d: %s (eip=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4658 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4659 CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4660 else
4661 Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4662 break;
4663
4664 }
4665}
4666
4667
4668/**
4669 * Dumps an OpenBSD system call.
4670 * @param pVM VM handle.
4671 */
4672void remR3DumpOBsdSyscall(PVM pVM)
4673{
4674 static const char *apsz[] =
4675 {
4676 "SYS_syscall", //0
4677 "SYS_exit", //1
4678 "SYS_fork", //2
4679 "SYS_read", //3
4680 "SYS_write", //4
4681 "SYS_open", //5
4682 "SYS_close", //6
4683 "SYS_wait4", //7
4684 "SYS_8",
4685 "SYS_link", //9
4686 "SYS_unlink", //10
4687 "SYS_11",
4688 "SYS_chdir", //12
4689 "SYS_fchdir", //13
4690 "SYS_mknod", //14
4691 "SYS_chmod", //15
4692 "SYS_chown", //16
4693 "SYS_break", //17
4694 "SYS_18",
4695 "SYS_19",
4696 "SYS_getpid", //20
4697 "SYS_mount", //21
4698 "SYS_unmount", //22
4699 "SYS_setuid", //23
4700 "SYS_getuid", //24
4701 "SYS_geteuid", //25
4702 "SYS_ptrace", //26
4703 "SYS_recvmsg", //27
4704 "SYS_sendmsg", //28
4705 "SYS_recvfrom", //29
4706 "SYS_accept", //30
4707 "SYS_getpeername", //31
4708 "SYS_getsockname", //32
4709 "SYS_access", //33
4710 "SYS_chflags", //34
4711 "SYS_fchflags", //35
4712 "SYS_sync", //36
4713 "SYS_kill", //37
4714 "SYS_38",
4715 "SYS_getppid", //39
4716 "SYS_40",
4717 "SYS_dup", //41
4718 "SYS_opipe", //42
4719 "SYS_getegid", //43
4720 "SYS_profil", //44
4721 "SYS_ktrace", //45
4722 "SYS_sigaction", //46
4723 "SYS_getgid", //47
4724 "SYS_sigprocmask", //48
4725 "SYS_getlogin", //49
4726 "SYS_setlogin", //50
4727 "SYS_acct", //51
4728 "SYS_sigpending", //52
4729 "SYS_osigaltstack", //53
4730 "SYS_ioctl", //54
4731 "SYS_reboot", //55
4732 "SYS_revoke", //56
4733 "SYS_symlink", //57
4734 "SYS_readlink", //58
4735 "SYS_execve", //59
4736 "SYS_umask", //60
4737 "SYS_chroot", //61
4738 "SYS_62",
4739 "SYS_63",
4740 "SYS_64",
4741 "SYS_65",
4742 "SYS_vfork", //66
4743 "SYS_67",
4744 "SYS_68",
4745 "SYS_sbrk", //69
4746 "SYS_sstk", //70
4747 "SYS_61",
4748 "SYS_vadvise", //72
4749 "SYS_munmap", //73
4750 "SYS_mprotect", //74
4751 "SYS_madvise", //75
4752 "SYS_76",
4753 "SYS_77",
4754 "SYS_mincore", //78
4755 "SYS_getgroups", //79
4756 "SYS_setgroups", //80
4757 "SYS_getpgrp", //81
4758 "SYS_setpgid", //82
4759 "SYS_setitimer", //83
4760 "SYS_84",
4761 "SYS_85",
4762 "SYS_getitimer", //86
4763 "SYS_87",
4764 "SYS_88",
4765 "SYS_89",
4766 "SYS_dup2", //90
4767 "SYS_91",
4768 "SYS_fcntl", //92
4769 "SYS_select", //93
4770 "SYS_94",
4771 "SYS_fsync", //95
4772 "SYS_setpriority", //96
4773 "SYS_socket", //97
4774 "SYS_connect", //98
4775 "SYS_99",
4776 "SYS_getpriority", //100
4777 "SYS_101",
4778 "SYS_102",
4779 "SYS_sigreturn", //103
4780 "SYS_bind", //104
4781 "SYS_setsockopt", //105
4782 "SYS_listen", //106
4783 "SYS_107",
4784 "SYS_108",
4785 "SYS_109",
4786 "SYS_110",
4787 "SYS_sigsuspend", //111
4788 "SYS_112",
4789 "SYS_113",
4790 "SYS_114",
4791 "SYS_115",
4792 "SYS_gettimeofday", //116
4793 "SYS_getrusage", //117
4794 "SYS_getsockopt", //118
4795 "SYS_119",
4796 "SYS_readv", //120
4797 "SYS_writev", //121
4798 "SYS_settimeofday", //122
4799 "SYS_fchown", //123
4800 "SYS_fchmod", //124
4801 "SYS_125",
4802 "SYS_setreuid", //126
4803 "SYS_setregid", //127
4804 "SYS_rename", //128
4805 "SYS_129",
4806 "SYS_130",
4807 "SYS_flock", //131
4808 "SYS_mkfifo", //132
4809 "SYS_sendto", //133
4810 "SYS_shutdown", //134
4811 "SYS_socketpair", //135
4812 "SYS_mkdir", //136
4813 "SYS_rmdir", //137
4814 "SYS_utimes", //138
4815 "SYS_139",
4816 "SYS_adjtime", //140
4817 "SYS_141",
4818 "SYS_142",
4819 "SYS_143",
4820 "SYS_144",
4821 "SYS_145",
4822 "SYS_146",
4823 "SYS_setsid", //147
4824 "SYS_quotactl", //148
4825 "SYS_149",
4826 "SYS_150",
4827 "SYS_151",
4828 "SYS_152",
4829 "SYS_153",
4830 "SYS_154",
4831 "SYS_nfssvc", //155
4832 "SYS_156",
4833 "SYS_157",
4834 "SYS_158",
4835 "SYS_159",
4836 "SYS_160",
4837 "SYS_getfh", //161
4838 "SYS_162",
4839 "SYS_163",
4840 "SYS_164",
4841 "SYS_sysarch", //165
4842 "SYS_166",
4843 "SYS_167",
4844 "SYS_168",
4845 "SYS_169",
4846 "SYS_170",
4847 "SYS_171",
4848 "SYS_172",
4849 "SYS_pread", //173
4850 "SYS_pwrite", //174
4851 "SYS_175",
4852 "SYS_176",
4853 "SYS_177",
4854 "SYS_178",
4855 "SYS_179",
4856 "SYS_180",
4857 "SYS_setgid", //181
4858 "SYS_setegid", //182
4859 "SYS_seteuid", //183
4860 "SYS_lfs_bmapv", //184
4861 "SYS_lfs_markv", //185
4862 "SYS_lfs_segclean", //186
4863 "SYS_lfs_segwait", //187
4864 "SYS_188",
4865 "SYS_189",
4866 "SYS_190",
4867 "SYS_pathconf", //191
4868 "SYS_fpathconf", //192
4869 "SYS_swapctl", //193
4870 "SYS_getrlimit", //194
4871 "SYS_setrlimit", //195
4872 "SYS_getdirentries", //196
4873 "SYS_mmap", //197
4874 "SYS___syscall", //198
4875 "SYS_lseek", //199
4876 "SYS_truncate", //200
4877 "SYS_ftruncate", //201
4878 "SYS___sysctl", //202
4879 "SYS_mlock", //203
4880 "SYS_munlock", //204
4881 "SYS_205",
4882 "SYS_futimes", //206
4883 "SYS_getpgid", //207
4884 "SYS_xfspioctl", //208
4885 "SYS_209",
4886 "SYS_210",
4887 "SYS_211",
4888 "SYS_212",
4889 "SYS_213",
4890 "SYS_214",
4891 "SYS_215",
4892 "SYS_216",
4893 "SYS_217",
4894 "SYS_218",
4895 "SYS_219",
4896 "SYS_220",
4897 "SYS_semget", //221
4898 "SYS_222",
4899 "SYS_223",
4900 "SYS_224",
4901 "SYS_msgget", //225
4902 "SYS_msgsnd", //226
4903 "SYS_msgrcv", //227
4904 "SYS_shmat", //228
4905 "SYS_229",
4906 "SYS_shmdt", //230
4907 "SYS_231",
4908 "SYS_clock_gettime", //232
4909 "SYS_clock_settime", //233
4910 "SYS_clock_getres", //234
4911 "SYS_235",
4912 "SYS_236",
4913 "SYS_237",
4914 "SYS_238",
4915 "SYS_239",
4916 "SYS_nanosleep", //240
4917 "SYS_241",
4918 "SYS_242",
4919 "SYS_243",
4920 "SYS_244",
4921 "SYS_245",
4922 "SYS_246",
4923 "SYS_247",
4924 "SYS_248",
4925 "SYS_249",
4926 "SYS_minherit", //250
4927 "SYS_rfork", //251
4928 "SYS_poll", //252
4929 "SYS_issetugid", //253
4930 "SYS_lchown", //254
4931 "SYS_getsid", //255
4932 "SYS_msync", //256
4933 "SYS_257",
4934 "SYS_258",
4935 "SYS_259",
4936 "SYS_getfsstat", //260
4937 "SYS_statfs", //261
4938 "SYS_fstatfs", //262
4939 "SYS_pipe", //263
4940 "SYS_fhopen", //264
4941 "SYS_265",
4942 "SYS_fhstatfs", //266
4943 "SYS_preadv", //267
4944 "SYS_pwritev", //268
4945 "SYS_kqueue", //269
4946 "SYS_kevent", //270
4947 "SYS_mlockall", //271
4948 "SYS_munlockall", //272
4949 "SYS_getpeereid", //273
4950 "SYS_274",
4951 "SYS_275",
4952 "SYS_276",
4953 "SYS_277",
4954 "SYS_278",
4955 "SYS_279",
4956 "SYS_280",
4957 "SYS_getresuid", //281
4958 "SYS_setresuid", //282
4959 "SYS_getresgid", //283
4960 "SYS_setresgid", //284
4961 "SYS_285",
4962 "SYS_mquery", //286
4963 "SYS_closefrom", //287
4964 "SYS_sigaltstack", //288
4965 "SYS_shmget", //289
4966 "SYS_semop", //290
4967 "SYS_stat", //291
4968 "SYS_fstat", //292
4969 "SYS_lstat", //293
4970 "SYS_fhstat", //294
4971 "SYS___semctl", //295
4972 "SYS_shmctl", //296
4973 "SYS_msgctl", //297
4974 "SYS_MAXSYSCALL", //298
4975 //299
4976 //300
4977 };
4978 uint32_t uEAX;
4979 if (!LogIsEnabled())
4980 return;
4981 uEAX = CPUMGetGuestEAX(pVM);
4982 switch (uEAX)
4983 {
4984 default:
4985 if (uEAX < RT_ELEMENTS(apsz))
4986 {
4987 uint32_t au32Args[8] = {0};
4988 PGMPhysSimpleReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4989 RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4990 uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4991 au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4992 }
4993 else
4994 RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4995 break;
4996 }
4997}
4998
4999
5000#if defined(IPRT_NO_CRT) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
5001/**
5002 * The Dll main entry point (stub).
5003 */
5004bool __stdcall _DllMainCRTStartup(void *hModule, uint32_t dwReason, void *pvReserved)
5005{
5006 return true;
5007}
5008
5009void *memcpy(void *dst, const void *src, size_t size)
5010{
5011 uint8_t*pbDst = dst, *pbSrc = src;
5012 while (size-- > 0)
5013 *pbDst++ = *pbSrc++;
5014 return dst;
5015}
5016
5017#endif
5018
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