VBoxRecompiler.c@ 1125

Last change on this file since 1125 was 1078, checked in by vboxsync, 18 years ago
Fixes for V86 segment syncing. (+ cleanup)
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 154.1 KB

Line
1	/** @file
2	*
3	* VBox Recompiler - QEMU.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include "vl.h"
27	#include "exec-all.h"
28
29	#include <VBox/rem.h>
30	#include <VBox/vmapi.h>
31	#include <VBox/tm.h>
32	#include <VBox/ssm.h>
33	#include <VBox/em.h>
34	#include <VBox/trpm.h>
35	#include <VBox/iom.h>
36	#include <VBox/mm.h>
37	#include <VBox/pgm.h>
38	#include <VBox/pdm.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/dbg.h>
41	#include <VBox/hwaccm.h>
42	#include <VBox/patm.h>
43	#include <VBox/csam.h>
44	#include "REMInternal.h"
45	#include <VBox/vm.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49	#define LOG_GROUP LOG_GROUP_REM
50	#include <VBox/log.h>
51	#include <iprt/semaphore.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/thread.h>
55	#include <iprt/string.h>
56
57
58	/* Don't wanna include everything. */
59	extern void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
60	extern void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
61	extern void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
62	extern void tlb_flush_page(CPUX86State *env, uint32_t addr);
63	extern void tlb_flush(CPUState *env, int flush_global);
64	extern void sync_seg(CPUX86State *env1, int seg_reg, int selector);
65	extern void sync_ldtr(CPUX86State *env1, int selector);
66	extern int sync_tr(CPUX86State *env1, int selector);
67
68	#ifdef VBOX_STRICT
69	unsigned long get_phys_page_offset(target_ulong addr);
70	#endif
71
72
73	/*******************************************************************************
74	* Defined Constants And Macros *
75	*******************************************************************************/
76
77	/** Copy 80-bit fpu register at pSrc to pDst.
78	* This is probably faster than calling memcpy.
79	*/
80	#define REM_COPY_FPU_REG(pDst, pSrc) \
81	do { (PX86FPUMMX)(pDst) = (const X86FPUMMX *)(pSrc); } while (0)
82
83
84	/*******************************************************************************
85	* Internal Functions *
86	*******************************************************************************/
87	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM);
88	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
89	static void remR3StateUpdate(PVM pVM);
90	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys);
91	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys);
92	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys);
93	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
94	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
95	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
96
97	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys);
98	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys);
99	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys);
100	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
101	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
102	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32);
103
104
105	/*******************************************************************************
106	* Global Variables *
107	*******************************************************************************/
108
109	/** The log level of the recompiler. */
110	#if 1
111	extern int loglevel;
112	#else
113	int loglevel = ~0;
114	FILE *logfile = NULL;
115	#endif
116
117
118	/** @todo Move stats to REM::s some rainy day we have nothing do to. */
119	#ifdef VBOX_WITH_STATISTICS
120	static STAMPROFILEADV gStatExecuteSingleInstr;
121	static STAMPROFILEADV gStatCompilationQEmu;
122	static STAMPROFILEADV gStatRunCodeQEmu;
123	static STAMPROFILEADV gStatTotalTimeQEmu;
124	static STAMPROFILEADV gStatTimers;
125	static STAMPROFILEADV gStatTBLookup;
126	static STAMPROFILEADV gStatIRQ;
127	static STAMPROFILEADV gStatRawCheck;
128	static STAMPROFILEADV gStatMemRead;
129	static STAMPROFILEADV gStatMemWrite;
130	static STAMCOUNTER gStatRefuseTFInhibit;
131	static STAMCOUNTER gStatRefuseVM86;
132	static STAMCOUNTER gStatRefusePaging;
133	static STAMCOUNTER gStatRefusePAE;
134	static STAMCOUNTER gStatRefuseIOPLNot0;
135	static STAMCOUNTER gStatRefuseIF0;
136	static STAMCOUNTER gStatRefuseCode16;
137	static STAMCOUNTER gStatRefuseWP0;
138	static STAMCOUNTER gStatRefuseRing1or2;
139	static STAMCOUNTER gStatRefuseCanExecute;
140	static STAMCOUNTER gStatREMGDTChange;
141	static STAMCOUNTER gStatREMIDTChange;
142	static STAMCOUNTER gStatREMLDTRChange;
143	static STAMCOUNTER gStatREMTRChange;
144	static STAMCOUNTER gStatSelOutOfSync[6];
145	static STAMCOUNTER gStatSelOutOfSyncStateBack[6];
146	#endif
147
148	/*
149	* Global stuff.
150	*/
151
152	/** MMIO read callbacks. */
153	CPUReadMemoryFunc *g_apfnMMIORead[3] =
154	{
155	remR3MMIOReadU8,
156	remR3MMIOReadU16,
157	remR3MMIOReadU32
158	};
159
160	/** MMIO write callbacks. */
161	CPUWriteMemoryFunc *g_apfnMMIOWrite[3] =
162	{
163	remR3MMIOWriteU8,
164	remR3MMIOWriteU16,
165	remR3MMIOWriteU32
166	};
167
168	/** Handler read callbacks. */
169	CPUReadMemoryFunc *g_apfnHandlerRead[3] =
170	{
171	remR3HandlerReadU8,
172	remR3HandlerReadU16,
173	remR3HandlerReadU32
174	};
175
176	/** Handler write callbacks. */
177	CPUWriteMemoryFunc *g_apfnHandlerWrite[3] =
178	{
179	remR3HandlerWriteU8,
180	remR3HandlerWriteU16,
181	remR3HandlerWriteU32
182	};
183
184	#ifndef PGM_DYNAMIC_RAM_ALLOC
185	/* Guest physical RAM base. Not to be used in external code. */
186	static uint8_t *phys_ram_base;
187	#endif
188
189	/*
190	* Instance stuff.
191	*/
192	/** Pointer to the cpu state. */
193	CPUState *cpu_single_env;
194
195
196	#ifdef VBOX_WITH_DEBUGGER
197	/*
198	* Debugger commands.
199	*/
200	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
201
202	/** '.remstep' arguments. */
203	static const DBGCVARDESC g_aArgRemStep[] =
204	{
205	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
206	{ 0, ~0, DBGCVAR_CAT_NUMBER, 0, "on/off", "Boolean value/mnemonic indicating the new state." },
207	};
208
209	/** Command descriptors. */
210	static const DBGCCMD g_aCmds[] =
211	{
212	{
213	.pszCmd ="remstep",
214	.cArgsMin = 0,
215	.cArgsMax = 1,
216	.paArgDescs = &g_aArgRemStep[0],
217	.cArgDescs = ELEMENTS(g_aArgRemStep),
218	.pResultDesc = NULL,
219	.fFlags = 0,
220	.pfnHandler = remR3CmdDisasEnableStepping,
221	.pszSyntax = "[on/off]",
222	.pszDescription = "Enable or disable the single stepping with logged disassembly. "
223	"If no arguments show the current state."
224	}
225	};
226	#endif
227
228
229	/*******************************************************************************
230	* Internal Functions *
231	*******************************************************************************/
232	static void remAbort(int rc, const char *pszTip);
233
234
235	/* Put them here to avoid unused variable warning. */
236	AssertCompile(RT_SIZEOFMEMB(VM, rem.padding) >= RT_SIZEOFMEMB(VM, rem.s));
237	//AssertCompileMemberSize(REM, Env, REM_ENV_SIZE);
238	//AssertCompile(RT_SIZEOFMEMB(REM, Env) <= REM_ENV_SIZE);
239
240	/**
241	* Initializes the REM.
242	*
243	* @returns VBox status code.
244	* @param pVM The VM to operate on.
245	*/
246	REMR3DECL(int) REMR3Init(PVM pVM)
247	{
248	uint32_t u32Dummy;
249	AssertReleaseMsg(sizeof(pVM->rem.padding) >= sizeof(pVM->rem.s), ("%#x >= %#x; sizeof(Env)=%#x\n", sizeof(pVM->rem.padding), sizeof(pVM->rem.s), sizeof(pVM->rem.s.Env)));
250	//AssertReleaseMsg(sizeof(pVM->rem.s.Env) <= REM_ENV_SIZE, ("%#x == %#x\n", sizeof(pVM->rem.s.Env), REM_ENV_SIZE));
251	AssertReleaseMsg(!(RT_OFFSETOF(VM, rem) & 31), ("off=%#x\n", RT_OFFSETOF(VM, rem)));
252	#if 0 /* not merged yet */
253	Assert(!testmath());
254	#endif
255
256	/*
257	* Init some internal data members.
258	*/
259	pVM->rem.s.offVM = RT_OFFSETOF(VM, rem.s);
260	pVM->rem.s.Env.pVM = pVM;
261	#ifdef CPU_RAW_MODE_INIT
262	pVM->rem.s.state \|= CPU_RAW_MODE_INIT;
263	#endif
264
265	/* ctx. */
266	int rc = CPUMQueryGuestCtxPtr(pVM, &pVM->rem.s.pCtx);
267	if (VBOX_FAILURE(rc))
268	{
269	AssertMsgFailed(("Failed to obtain guest ctx pointer. rc=%Vrc\n", rc));
270	return rc;
271	}
272	AssertMsg(MMR3PhysGetRamSize(pVM) == 0, ("Init order have changed! REM depends on notification about ALL physical memory registrations\n"));
273
274	/*
275	* Init the recompiler.
276	*/
277	if (!cpu_x86_init(&pVM->rem.s.Env))
278	{
279	AssertMsgFailed(("cpu_x86_init failed - impossible!\n"));
280	return VERR_GENERAL_FAILURE;
281	}
282	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
283
284	/* allocate code buffer for single instruction emulation. */
285	pVM->rem.s.Env.cbCodeBuffer = 4096;
286	pVM->rem.s.Env.pvCodeBuffer = RTMemExecAlloc(pVM->rem.s.Env.cbCodeBuffer);
287	AssertMsgReturn(pVM->rem.s.Env.pvCodeBuffer, ("Failed to allocate code buffer!\n"), VERR_NO_MEMORY);
288
289	/* finally, set the cpu_single_env global. */
290	cpu_single_env = &pVM->rem.s.Env;
291
292	/* Nothing is pending by default */
293	pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
294
295	#ifdef DEBUG_bird
296	//cpu_breakpoint_insert(&pVM->rem.s.Env, some-address);
297	#endif
298
299	/*
300	* Register ram types.
301	*/
302	pVM->rem.s.iMMIOMemType = cpu_register_io_memory(0, g_apfnMMIORead, g_apfnMMIOWrite, pVM);
303	AssertReleaseMsg(pVM->rem.s.iMMIOMemType > 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType));
304	pVM->rem.s.iHandlerMemType = cpu_register_io_memory(0, g_apfnHandlerRead, g_apfnHandlerWrite, pVM);
305	AssertReleaseMsg(pVM->rem.s.iHandlerMemType > 0, ("pVM->rem.s.iHandlerMemType=%d\n", pVM->rem.s.iHandlerMemType));
306	Log2(("REM: iMMIOMemType=%d iHandlerMemType=%d\n", pVM->rem.s.iMMIOMemType, pVM->rem.s.iHandlerMemType));
307
308	/*
309	* Register the saved state data unit.
310	*/
311	rc = SSMR3RegisterInternal(pVM, "rem", 1, REM_SAVED_STATE_VERSION, sizeof(uint32_t) * 10,
312	NULL, remR3Save, NULL,
313	NULL, remR3Load, NULL);
314	if (VBOX_FAILURE(rc))
315	return rc;
316
317	#ifdef VBOX_WITH_DEBUGGER
318	/*
319	* Debugger commands.
320	*/
321	static bool fRegisteredCmds = false;
322	if (!fRegisteredCmds)
323	{
324	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
325	if (VBOX_SUCCESS(rc))
326	fRegisteredCmds = true;
327	}
328	#endif
329
330	#ifdef VBOX_WITH_STATISTICS
331	/*
332	* Statistics.
333	*/
334	STAM_REG(pVM, &gStatExecuteSingleInstr, STAMTYPE_PROFILE, "/PROF/REM/SingleInstr",STAMUNIT_TICKS_PER_CALL, "Profiling single instruction emulation.");
335	STAM_REG(pVM, &gStatCompilationQEmu, STAMTYPE_PROFILE, "/PROF/REM/Compile", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu compilation.");
336	STAM_REG(pVM, &gStatRunCodeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Runcode", STAMUNIT_TICKS_PER_CALL, "Profiling QEmu code execution.");
337	STAM_REG(pVM, &gStatTotalTimeQEmu, STAMTYPE_PROFILE, "/PROF/REM/Emulate", STAMUNIT_TICKS_PER_CALL, "Profiling code emulation.");
338	STAM_REG(pVM, &gStatTimers, STAMTYPE_PROFILE, "/PROF/REM/Timers", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
339	STAM_REG(pVM, &gStatTBLookup, STAMTYPE_PROFILE, "/PROF/REM/TBLookup", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
340	STAM_REG(pVM, &gStatIRQ, STAMTYPE_PROFILE, "/PROF/REM/IRQ", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
341	STAM_REG(pVM, &gStatRawCheck, STAMTYPE_PROFILE, "/PROF/REM/RawCheck", STAMUNIT_TICKS_PER_CALL, "Profiling timer scheduling.");
342	STAM_REG(pVM, &gStatMemRead, STAMTYPE_PROFILE, "/PROF/REM/MemRead", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
343	STAM_REG(pVM, &gStatMemWrite, STAMTYPE_PROFILE, "/PROF/REM/MemWrite", STAMUNIT_TICKS_PER_CALL, "Profiling memory access.");
344
345	STAM_REG(pVM, &gStatRefuseTFInhibit, STAMTYPE_COUNTER, "/REM/Refuse/TFInibit", STAMUNIT_OCCURENCES, "Raw mode refused because of TF or irq inhibit");
346	STAM_REG(pVM, &gStatRefuseVM86, STAMTYPE_COUNTER, "/REM/Refuse/VM86", STAMUNIT_OCCURENCES, "Raw mode refused because of VM86");
347	STAM_REG(pVM, &gStatRefusePaging, STAMTYPE_COUNTER, "/REM/Refuse/Paging", STAMUNIT_OCCURENCES, "Raw mode refused because of disabled paging/pm");
348	STAM_REG(pVM, &gStatRefusePAE, STAMTYPE_COUNTER, "/REM/Refuse/PAE", STAMUNIT_OCCURENCES, "Raw mode refused because of PAE");
349	STAM_REG(pVM, &gStatRefuseIOPLNot0, STAMTYPE_COUNTER, "/REM/Refuse/IOPLNot0", STAMUNIT_OCCURENCES, "Raw mode refused because of IOPL != 0");
350	STAM_REG(pVM, &gStatRefuseIF0, STAMTYPE_COUNTER, "/REM/Refuse/IF0", STAMUNIT_OCCURENCES, "Raw mode refused because of IF=0");
351	STAM_REG(pVM, &gStatRefuseCode16, STAMTYPE_COUNTER, "/REM/Refuse/Code16", STAMUNIT_OCCURENCES, "Raw mode refused because of 16 bit code");
352	STAM_REG(pVM, &gStatRefuseWP0, STAMTYPE_COUNTER, "/REM/Refuse/WP0", STAMUNIT_OCCURENCES, "Raw mode refused because of WP=0");
353	STAM_REG(pVM, &gStatRefuseRing1or2, STAMTYPE_COUNTER, "/REM/Refuse/Ring1or2", STAMUNIT_OCCURENCES, "Raw mode refused because of ring 1/2 execution");
354	STAM_REG(pVM, &gStatRefuseCanExecute, STAMTYPE_COUNTER, "/REM/Refuse/CanExecuteRaw", STAMUNIT_OCCURENCES, "Raw mode refused because of cCanExecuteRaw");
355
356	STAM_REG(pVM, &gStatREMGDTChange, STAMTYPE_COUNTER, "/REM/Change/GDTBase", STAMUNIT_OCCURENCES, "GDT base changes");
357	STAM_REG(pVM, &gStatREMLDTRChange, STAMTYPE_COUNTER, "/REM/Change/LDTR", STAMUNIT_OCCURENCES, "LDTR changes");
358	STAM_REG(pVM, &gStatREMIDTChange, STAMTYPE_COUNTER, "/REM/Change/IDTBase", STAMUNIT_OCCURENCES, "IDT base changes");
359	STAM_REG(pVM, &gStatREMTRChange, STAMTYPE_COUNTER, "/REM/Change/TR", STAMUNIT_OCCURENCES, "TR selector changes");
360
361	STAM_REG(pVM, &gStatSelOutOfSync[0], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
362	STAM_REG(pVM, &gStatSelOutOfSync[1], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
363	STAM_REG(pVM, &gStatSelOutOfSync[2], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
364	STAM_REG(pVM, &gStatSelOutOfSync[3], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
365	STAM_REG(pVM, &gStatSelOutOfSync[4], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
366	STAM_REG(pVM, &gStatSelOutOfSync[5], STAMTYPE_COUNTER, "/REM/State/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
367
368	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[0], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/ES", STAMUNIT_OCCURENCES, "ES out of sync");
369	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[1], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/CS", STAMUNIT_OCCURENCES, "CS out of sync");
370	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[2], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/SS", STAMUNIT_OCCURENCES, "SS out of sync");
371	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[3], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/DS", STAMUNIT_OCCURENCES, "DS out of sync");
372	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[4], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/FS", STAMUNIT_OCCURENCES, "FS out of sync");
373	STAM_REG(pVM, &gStatSelOutOfSyncStateBack[5], STAMTYPE_COUNTER, "/REM/StateBack/SelOutOfSync/GS", STAMUNIT_OCCURENCES, "GS out of sync");
374
375	#endif
376	return rc;
377	}
378
379
380	/**
381	* Terminates the REM.
382	*
383	* Termination means cleaning up and freeing all resources,
384	* the VM it self is at this point powered off or suspended.
385	*
386	* @returns VBox status code.
387	* @param pVM The VM to operate on.
388	*/
389	REMR3DECL(int) REMR3Term(PVM pVM)
390	{
391	return VINF_SUCCESS;
392	}
393
394
395	/**
396	* The VM is being reset.
397	*
398	* For the REM component this means to call the cpu_reset() and
399	* reinitialize some state variables.
400	*
401	* @param pVM VM handle.
402	*/
403	REMR3DECL(void) REMR3Reset(PVM pVM)
404	{
405	pVM->rem.s.fIgnoreCR3Load = true;
406	pVM->rem.s.fIgnoreInvlPg = true;
407	pVM->rem.s.fIgnoreCpuMode = true;
408
409	/*
410	* Reset the REM cpu.
411	*/
412	cpu_reset(&pVM->rem.s.Env);
413	pVM->rem.s.cInvalidatedPages = 0;
414
415	pVM->rem.s.fIgnoreCR3Load = false;
416	pVM->rem.s.fIgnoreInvlPg = false;
417	pVM->rem.s.fIgnoreCpuMode = false;
418	}
419
420
421	/**
422	* Execute state save operation.
423	*
424	* @returns VBox status code.
425	* @param pVM VM Handle.
426	* @param pSSM SSM operation handle.
427	*/
428	static DECLCALLBACK(int) remR3Save(PVM pVM, PSSMHANDLE pSSM)
429	{
430	LogFlow(("remR3Save:\n"));
431
432	/*
433	* Save the required CPU Env bits.
434	* (Not much because we're never in REM when doing the save.)
435	*/
436	PREM pRem = &pVM->rem.s;
437	Assert(!pRem->fInREM);
438	SSMR3PutU32(pSSM, pRem->Env.hflags);
439	SSMR3PutMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
440	SSMR3PutU32(pSSM, ~0); /* separator */
441
442	/*
443	* Save the REM stuff.
444	*/
445	SSMR3PutUInt(pSSM, pRem->cInvalidatedPages);
446	unsigned i;
447	for (i = 0; i < pRem->cInvalidatedPages; i++)
448	SSMR3PutGCPtr(pSSM, pRem->aGCPtrInvalidatedPages[i]);
449
450	SSMR3PutUInt(pSSM, pVM->rem.s.u32PendingInterrupt);
451
452	return SSMR3PutU32(pSSM, ~0); /* terminator */
453	}
454
455
456	/**
457	* Execute state load operation.
458	*
459	* @returns VBox status code.
460	* @param pVM VM Handle.
461	* @param pSSM SSM operation handle.
462	* @param u32Version Data layout version.
463	*/
464	static DECLCALLBACK(int) remR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
465	{
466	uint32_t u32Dummy;
467	LogFlow(("remR3Load:\n"));
468
469	/*
470	* Validate version.
471	*/
472	if (u32Version != REM_SAVED_STATE_VERSION)
473	{
474	Log(("remR3Load: Invalid version u32Version=%d!\n", u32Version));
475	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
476	}
477
478	/*
479	* Do a reset to be on the safe side...
480	*/
481	REMR3Reset(pVM);
482
483	/*
484	* Ignore all ignorable notifications.
485	* Not doing this will cause big trouble.
486	*/
487	pVM->rem.s.fIgnoreCR3Load = true;
488	pVM->rem.s.fIgnoreInvlPg = true;
489	pVM->rem.s.fIgnoreCpuMode = true;
490
491	/*
492	* Load the required CPU Env bits.
493	* (Not much because we're never in REM when doing the save.)
494	*/
495	PREM pRem = &pVM->rem.s;
496	Assert(!pRem->fInREM);
497	SSMR3GetU32(pSSM, &pRem->Env.hflags);
498	SSMR3GetMem(pSSM, &pRem->Env, RT_OFFSETOF(CPUState, jmp_env));
499	uint32_t u32Sep;
500	int rc = SSMR3GetU32(pSSM, &u32Sep); /* separator */
501	if (VBOX_FAILURE(rc))
502	return rc;
503	if (u32Sep != ~0)
504	{
505	AssertMsgFailed(("u32Sep=%#x\n", u32Sep));
506	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
507	}
508
509	/*
510	* Load the REM stuff.
511	*/
512	rc = SSMR3GetUInt(pSSM, &pRem->cInvalidatedPages);
513	if (VBOX_FAILURE(rc))
514	return rc;
515	if (pRem->cInvalidatedPages > ELEMENTS(pRem->aGCPtrInvalidatedPages))
516	{
517	AssertMsgFailed(("cInvalidatedPages=%#x\n", pRem->cInvalidatedPages));
518	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
519	}
520	unsigned i;
521	for (i = 0; i < pRem->cInvalidatedPages; i++)
522	SSMR3GetGCPtr(pSSM, &pRem->aGCPtrInvalidatedPages[i]);
523
524	rc = SSMR3GetUInt(pSSM, &pVM->rem.s.u32PendingInterrupt);
525	if (VBOX_FAILURE(rc))
526	return rc;
527
528	/* check the terminator. */
529	rc = SSMR3GetU32(pSSM, &u32Sep);
530	if (VBOX_FAILURE(rc))
531	return rc;
532	if (u32Sep != ~0)
533	{
534	AssertMsgFailed(("u32Sep=%#x (term)\n", u32Sep));
535	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
536	}
537
538	/*
539	* Get the CPUID features.
540	*/
541	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &pVM->rem.s.Env.cpuid_ext_features, &pVM->rem.s.Env.cpuid_features);
542
543	/*
544	* Sync the Load Flush the TLB
545	*/
546	tlb_flush(&pRem->Env, 1);
547
548	#if 0 /** @todo r=bird: this doesn't make sense. WHY? */
549	/*
550	* Clear all lazy flags (only FPU sync for now).
551	*/
552	CPUMGetAndClearFPUUsedREM(pVM);
553	#endif
554
555	/*
556	* Stop ignoring ignornable notifications.
557	*/
558	pVM->rem.s.fIgnoreCpuMode = false;
559	pVM->rem.s.fIgnoreInvlPg = false;
560	pVM->rem.s.fIgnoreCR3Load = false;
561
562	return VINF_SUCCESS;
563	}
564
565
566
567	#undef LOG_GROUP
568	#define LOG_GROUP LOG_GROUP_REM_RUN
569
570	/**
571	* Single steps an instruction in recompiled mode.
572	*
573	* Before calling this function the REM state needs to be in sync with
574	* the VM. Call REMR3State() to perform the sync. It's only necessary
575	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
576	* and after calling REMR3StateBack().
577	*
578	* @returns VBox status code.
579	*
580	* @param pVM VM Handle.
581	*/
582	REMR3DECL(int) REMR3Step(PVM pVM)
583	{
584	/*
585	* Lock the REM - we don't wanna have anyone interrupting us
586	* while stepping - and enabled single stepping. We also ignore
587	* pending interrupts and suchlike.
588	*/
589	int interrupt_request = pVM->rem.s.Env.interrupt_request;
590	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
591	pVM->rem.s.Env.interrupt_request = 0;
592	cpu_single_step(&pVM->rem.s.Env, 1);
593
594	/*
595	* If we're standing at a breakpoint, that have to be disabled before we start stepping.
596	*/
597	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
598	bool fBp = !cpu_breakpoint_remove(&pVM->rem.s.Env, GCPtrPC);
599
600	/*
601	* Execute and handle the return code.
602	* We execute without enabling the cpu tick, so on success we'll
603	* just flip it on and off to make sure it moves
604	*/
605	int rc = cpu_exec(&pVM->rem.s.Env);
606	if (rc == EXCP_DEBUG)
607	{
608	TMCpuTickResume(pVM);
609	TMCpuTickPause(pVM);
610	TMVirtualResume(pVM);
611	TMVirtualPause(pVM);
612	rc = VINF_EM_DBG_STEPPED;
613	}
614	else
615	{
616	AssertMsgFailed(("Damn, this shouldn't happen! cpu_exec returned %d while singlestepping\n", rc));
617	switch (rc)
618	{
619	case EXCP_INTERRUPT: rc = VINF_SUCCESS; break;
620	case EXCP_HLT: rc = VINF_EM_HALT; break;
621	case EXCP_RC:
622	rc = pVM->rem.s.rc;
623	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
624	break;
625	default:
626	AssertReleaseMsgFailed(("This really shouldn't happen, rc=%d!\n", rc));
627	rc = VERR_INTERNAL_ERROR;
628	break;
629	}
630	}
631
632	/*
633	* Restore the stuff we changed to prevent interruption.
634	* Unlock the REM.
635	*/
636	if (fBp)
637	{
638	int rc2 = cpu_breakpoint_insert(&pVM->rem.s.Env, GCPtrPC);
639	Assert(rc2 == 0); NOREF(rc2);
640	}
641	cpu_single_step(&pVM->rem.s.Env, 0);
642	pVM->rem.s.Env.interrupt_request = interrupt_request;
643
644	return rc;
645	}
646
647
648	/**
649	* Set a breakpoint using the REM facilities.
650	*
651	* @returns VBox status code.
652	* @param pVM The VM handle.
653	* @param Address The breakpoint address.
654	* @thread The emulation thread.
655	*/
656	REMR3DECL(int) REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address)
657	{
658	VM_ASSERT_EMT(pVM);
659	if (!cpu_breakpoint_insert(&pVM->rem.s.Env, Address))
660	{
661	LogFlow(("REMR3BreakpointSet: Address=%VGv\n", Address));
662	return VINF_SUCCESS;
663	}
664	LogFlow(("REMR3BreakpointSet: Address=%VGv - failed!\n", Address));
665	return VERR_REM_NO_MORE_BP_SLOTS;
666	}
667
668
669	/**
670	* Clears a breakpoint set by REMR3BreakpointSet().
671	*
672	* @returns VBox status code.
673	* @param pVM The VM handle.
674	* @param Address The breakpoint address.
675	* @thread The emulation thread.
676	*/
677	REMR3DECL(int) REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address)
678	{
679	VM_ASSERT_EMT(pVM);
680	if (!cpu_breakpoint_remove(&pVM->rem.s.Env, Address))
681	{
682	LogFlow(("REMR3BreakpointClear: Address=%VGv\n", Address));
683	return VINF_SUCCESS;
684	}
685	LogFlow(("REMR3BreakpointClear: Address=%VGv - not found!\n", Address));
686	return VERR_REM_BP_NOT_FOUND;
687	}
688
689
690	/**
691	* Emulate an instruction.
692	*
693	* This function executes one instruction without letting anyone
694	* interrupt it. This is intended for being called while being in
695	* raw mode and thus will take care of all the state syncing between
696	* REM and the rest.
697	*
698	* @returns VBox status code.
699	* @param pVM VM handle.
700	*/
701	REMR3DECL(int) REMR3EmulateInstruction(PVM pVM)
702	{
703	Log2(("REMR3EmulateInstruction: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
704
705	/*
706	* Sync the state and enable single instruction / single stepping.
707	*/
708	int rc = REMR3State(pVM);
709	if (VBOX_SUCCESS(rc))
710	{
711	int interrupt_request = pVM->rem.s.Env.interrupt_request;
712	Assert(!(interrupt_request & ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER \| CPU_INTERRUPT_EXTERNAL_HARD \| CPU_INTERRUPT_EXTERNAL_EXIT \| CPU_INTERRUPT_EXTERNAL_TIMER)));
713	Assert(!pVM->rem.s.Env.singlestep_enabled);
714	#if 1
715
716	/*
717	* Now we set the execute single instruction flag and enter the cpu_exec loop.
718	*/
719	pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR;
720	rc = cpu_exec(&pVM->rem.s.Env);
721	switch (rc)
722	{
723	/*
724	* Executed without anything out of the way happening.
725	*/
726	case EXCP_SINGLE_INSTR:
727	rc = VINF_EM_RESCHEDULE;
728	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_SINGLE_INSTR\n"));
729	break;
730
731	/*
732	* If we take a trap or start servicing a pending interrupt, we might end up here.
733	* (Timer thread or some other thread wishing EMT's attention.)
734	*/
735	case EXCP_INTERRUPT:
736	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_INTERRUPT\n"));
737	rc = VINF_EM_RESCHEDULE;
738	break;
739
740	/*
741	* Single step, we assume!
742	* If there was a breakpoint there we're fucked now.
743	*/
744	case EXCP_DEBUG:
745	{
746	/* breakpoint or single step? */
747	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
748	int iBP;
749	rc = VINF_EM_DBG_STEPPED;
750	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
751	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
752	{
753	rc = VINF_EM_DBG_BREAKPOINT;
754	break;
755	}
756	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
757	break;
758	}
759
760	/*
761	* hlt instruction.
762	*/
763	case EXCP_HLT:
764	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
765	rc = VINF_EM_HALT;
766	break;
767
768	/*
769	* Switch to RAW-mode.
770	*/
771	case EXCP_EXECUTE_RAW:
772	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
773	rc = VINF_EM_RESCHEDULE_RAW;
774	break;
775
776	/*
777	* Switch to hardware accelerated RAW-mode.
778	*/
779	case EXCP_EXECUTE_HWACC:
780	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
781	rc = VINF_EM_RESCHEDULE_HWACC;
782	break;
783
784	/*
785	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
786	*/
787	case EXCP_RC:
788	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC\n"));
789	rc = pVM->rem.s.rc;
790	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
791	break;
792
793	/*
794	* Figure out the rest when they arrive....
795	*/
796	default:
797	AssertMsgFailed(("rc=%d\n", rc));
798	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
799	rc = VINF_EM_RESCHEDULE;
800	break;
801	}
802
803	/*
804	* Switch back the state.
805	*/
806	#else
807	pVM->rem.s.Env.interrupt_request = 0;
808	cpu_single_step(&pVM->rem.s.Env, 1);
809
810	/*
811	* Execute and handle the return code.
812	* We execute without enabling the cpu tick, so on success we'll
813	* just flip it on and off to make sure it moves.
814	*
815	* (We do not use emulate_single_instr() because that doesn't enter the
816	* right way in will cause serious trouble if a longjmp was attempted.)
817	*/
818	#ifdef DEBUG_bird
819	remR3DisasInstr(&pVM->rem.s.Env, 1, "REMR3EmulateInstruction");
820	#endif
821	int cTimesMax = 16384;
822	uint32_t eip = pVM->rem.s.Env.eip;
823	do
824	{
825	rc = cpu_exec(&pVM->rem.s.Env);
826	} while ( eip == pVM->rem.s.Env.eip
827	&& (rc == EXCP_DEBUG \|\| rc == EXCP_EXECUTE_RAW)
828	&& --cTimesMax > 0);
829	switch (rc)
830	{
831	/*
832	* Single step, we assume!
833	* If there was a breakpoint there we're fucked now.
834	*/
835	case EXCP_DEBUG:
836	{
837	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG\n"));
838	rc = VINF_EM_RESCHEDULE;
839	break;
840	}
841
842	/*
843	* We cannot be interrupted!
844	*/
845	case EXCP_INTERRUPT:
846	AssertMsgFailed(("Shouldn't happen! Everything was locked!\n"));
847	rc = VERR_INTERNAL_ERROR;
848	break;
849
850	/*
851	* hlt instruction.
852	*/
853	case EXCP_HLT:
854	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_HLT\n"));
855	rc = VINF_EM_HALT;
856	break;
857
858	/*
859	* Switch to RAW-mode.
860	*/
861	case EXCP_EXECUTE_RAW:
862	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_RAW\n"));
863	rc = VINF_EM_RESCHEDULE_RAW;
864	break;
865
866	/*
867	* Switch to hardware accelerated RAW-mode.
868	*/
869	case EXCP_EXECUTE_HWACC:
870	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
871	rc = VINF_EM_RESCHEDULE_HWACC;
872	break;
873
874	/*
875	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
876	*/
877	case EXCP_RC:
878	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
879	rc = pVM->rem.s.rc;
880	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
881	break;
882
883	/*
884	* Figure out the rest when they arrive....
885	*/
886	default:
887	AssertMsgFailed(("rc=%d\n", rc));
888	Log2(("REMR3EmulateInstruction: cpu_exec -> %d\n", rc));
889	rc = VINF_SUCCESS;
890	break;
891	}
892
893	/*
894	* Switch back the state.
895	*/
896	cpu_single_step(&pVM->rem.s.Env, 0);
897	#endif
898	pVM->rem.s.Env.interrupt_request = interrupt_request;
899	int rc2 = REMR3StateBack(pVM);
900	AssertRC(rc2);
901	}
902
903	Log2(("REMR3EmulateInstruction: returns %Vrc (cs:eip=%04x:%08x)\n",
904	rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
905	return rc;
906	}
907
908
909	/**
910	* Runs code in recompiled mode.
911	*
912	* Before calling this function the REM state needs to be in sync with
913	* the VM. Call REMR3State() to perform the sync. It's only necessary
914	* (and permitted) to sync at the first call to REMR3Step()/REMR3Run()
915	* and after calling REMR3StateBack().
916	*
917	* @returns VBox status code.
918	*
919	* @param pVM VM Handle.
920	*/
921	REMR3DECL(int) REMR3Run(PVM pVM)
922	{
923	Log2(("REMR3Run: (cs:eip=%04x:%08x)\n", pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
924	Assert(pVM->rem.s.fInREM);
925	////Keyboard / tb stuff:
926	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0xf000
927	// && pVM->rem.s.Env.eip >= 0xe860
928	// && pVM->rem.s.Env.eip <= 0xe880)
929	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
930	////A20:
931	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x9020
932	// && pVM->rem.s.Env.eip >= 0x970
933	// && pVM->rem.s.Env.eip <= 0x9a0)
934	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
935	////Speaker (port 61h)
936	//if ( pVM->rem.s.Env.segs[R_CS].selector == 0x0010
937	// && ( (pVM->rem.s.Env.eip >= 0x90278c10 && pVM->rem.s.Env.eip <= 0x90278c30)
938	// \|\| (pVM->rem.s.Env.eip >= 0x9010e250 && pVM->rem.s.Env.eip <= 0x9010e260)
939	// )
940	// )
941	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
942	//DBGFR3InfoLog(pVM, "timers", NULL);
943
944
945	int rc = cpu_exec(&pVM->rem.s.Env);
946	switch (rc)
947	{
948	/*
949	* This happens when the execution was interrupted
950	* by an external event, like pending timers.
951	*/
952	case EXCP_INTERRUPT:
953	Log2(("REMR3Run: cpu_exec -> EXCP_INTERRUPT\n"));
954	rc = VINF_SUCCESS;
955	break;
956
957	/*
958	* hlt instruction.
959	*/
960	case EXCP_HLT:
961	Log2(("REMR3Run: cpu_exec -> EXCP_HLT\n"));
962	rc = VINF_EM_HALT;
963	break;
964
965	/*
966	* Breakpoint/single step.
967	*/
968	case EXCP_DEBUG:
969	{
970	#if 0//def DEBUG_bird
971	static int iBP = 0;
972	printf("howdy, breakpoint! iBP=%d\n", iBP);
973	switch (iBP)
974	{
975	case 0:
976	cpu_breakpoint_remove(&pVM->rem.s.Env, pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base);
977	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
978	//pVM->rem.s.Env.interrupt_request = 0;
979	//pVM->rem.s.Env.exception_index = -1;
980	//g_fInterruptDisabled = 1;
981	rc = VINF_SUCCESS;
982	asm("int3");
983	break;
984	default:
985	asm("int3");
986	break;
987	}
988	iBP++;
989	#else
990	/* breakpoint or single step? */
991	RTGCPTR GCPtrPC = pVM->rem.s.Env.eip + pVM->rem.s.Env.segs[R_CS].base;
992	int iBP;
993	rc = VINF_EM_DBG_STEPPED;
994	for (iBP = 0; iBP < pVM->rem.s.Env.nb_breakpoints; iBP++)
995	if (pVM->rem.s.Env.breakpoints[iBP] == GCPtrPC)
996	{
997	rc = VINF_EM_DBG_BREAKPOINT;
998	break;
999	}
1000	Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));
1001	#endif
1002	break;
1003	}
1004
1005	/*
1006	* Switch to RAW-mode.
1007	*/
1008	case EXCP_EXECUTE_RAW:
1009	Log2(("REMR3Run: cpu_exec -> EXCP_EXECUTE_RAW\n"));
1010	rc = VINF_EM_RESCHEDULE_RAW;
1011	break;
1012
1013	/*
1014	* Switch to hardware accelerated RAW-mode.
1015	*/
1016	case EXCP_EXECUTE_HWACC:
1017	Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_EXECUTE_HWACC\n"));
1018	rc = VINF_EM_RESCHEDULE_HWACC;
1019	break;
1020
1021	/*
1022	* An EM RC was raised (VMR3Reset/Suspend/PowerOff).
1023	*/
1024	case EXCP_RC:
1025	Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Vrc\n", pVM->rem.s.rc));
1026	rc = pVM->rem.s.rc;
1027	pVM->rem.s.rc = VERR_INTERNAL_ERROR;
1028	break;
1029
1030	/*
1031	* Figure out the rest when they arrive....
1032	*/
1033	default:
1034	AssertMsgFailed(("rc=%d\n", rc));
1035	Log2(("REMR3Run: cpu_exec -> %d\n", rc));
1036	rc = VINF_SUCCESS;
1037	break;
1038	}
1039
1040	Log2(("REMR3Run: returns %Vrc (cs:eip=%04x:%08x)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));
1041	return rc;
1042	}
1043
1044
1045	/**
1046	* Check if the cpu state is suitable for Raw execution.
1047	*
1048	* @returns boolean
1049	* @param env The CPU env struct.
1050	* @param eip The EIP to check this for (might differ from env->eip).
1051	* @param fFlags hflags OR'ed with IOPL, TF and VM from eflags.
1052	* @param pExceptionIndex Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
1053	*
1054	* @remark This function must be kept in perfect sync with the scheduler in EM.cpp!
1055	*/
1056	bool remR3CanExecuteRaw(CPUState env, RTGCPTR eip, unsigned fFlags, uint32_t pExceptionIndex)
1057	{
1058	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1059	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1060	/* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
1061
1062	/* Update counter. */
1063	env->pVM->rem.s.cCanExecuteRaw++;
1064
1065	if (HWACCMIsEnabled(env->pVM))
1066	{
1067	env->state \|= CPU_RAW_HWACC;
1068
1069	/*
1070	* Create partial context for HWACCMR3CanExecuteGuest
1071	*/
1072	CPUMCTX Ctx;
1073	Ctx.cr0 = env->cr[0];
1074	Ctx.cr3 = env->cr[3];
1075	Ctx.cr4 = env->cr[4];
1076
1077	Ctx.tr = env->tr.selector;
1078	Ctx.trHid.u32Base = (uint32_t)env->tr.base;
1079	Ctx.trHid.u32Limit = env->tr.limit;
1080	Ctx.trHid.Attr.u = (env->tr.flags >> 8) & 0xF0FF;
1081
1082	Ctx.idtr.cbIdt = env->idt.limit;
1083	Ctx.idtr.pIdt = (uint32_t)env->idt.base;
1084
1085	Ctx.eflags.u32 = env->eflags;
1086
1087	Ctx.cs = env->segs[R_CS].selector;
1088	Ctx.csHid.u32Base = (uint32_t)env->segs[R_CS].base;
1089	Ctx.csHid.u32Limit = env->segs[R_CS].limit;
1090	Ctx.csHid.Attr.u = (env->segs[R_CS].flags >> 8) & 0xF0FF;
1091
1092	Ctx.ss = env->segs[R_SS].selector;
1093	Ctx.ssHid.u32Base = (uint32_t)env->segs[R_SS].base;
1094	Ctx.ssHid.u32Limit = env->segs[R_SS].limit;
1095	Ctx.ssHid.Attr.u = (env->segs[R_SS].flags >> 8) & 0xF0FF;
1096
1097	/* Hardware accelerated raw-mode:
1098	*
1099	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1100	*/
1101	if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
1102	{
1103	*pExceptionIndex = EXCP_EXECUTE_HWACC;
1104	return true;
1105	}
1106	return false;
1107	}
1108
1109	/*
1110	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1111	* or 32 bits protected mode ring 0 code
1112	*
1113	* The tests are ordered by the likelyhood of being true during normal execution.
1114	*/
1115	if (fFlags & (HF_TF_MASK \| HF_INHIBIT_IRQ_MASK))
1116	{
1117	STAM_COUNTER_INC(&gStatRefuseTFInhibit);
1118	Log2(("raw mode refused: fFlags=%#x\n", fFlags));
1119	return false;
1120	}
1121
1122	#ifndef VBOX_RAW_V86
1123	if (fFlags & VM_MASK) {
1124	STAM_COUNTER_INC(&gStatRefuseVM86);
1125	Log2(("raw mode refused: VM_MASK\n"));
1126	return false;
1127	}
1128	#endif
1129
1130	if (env->state & CPU_EMULATE_SINGLE_INSTR)
1131	{
1132	#ifndef DEBUG_bird
1133	Log2(("raw mode refused: CPU_EMULATE_SINGLE_INSTR\n"));
1134	#endif
1135	return false;
1136	}
1137
1138	if (env->singlestep_enabled)
1139	{
1140	//Log2(("raw mode refused: Single step\n"));
1141	return false;
1142	}
1143
1144	if (env->nb_breakpoints > 0)
1145	{
1146	//Log2(("raw mode refused: Breakpoints\n"));
1147	return false;
1148	}
1149
1150	uint32_t u32CR0 = env->cr[0];
1151	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
1152	{
1153	STAM_COUNTER_INC(&gStatRefusePaging);
1154	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1155	return false;
1156	}
1157
1158	if (env->cr[4] & CR4_PAE_MASK)
1159	{
1160	STAM_COUNTER_INC(&gStatRefusePAE);
1161	//Log2(("raw mode refused: PAE\n"));
1162	return false;
1163	}
1164
1165	if (((fFlags >> HF_CPL_SHIFT) & 3) == 3)
1166	{
1167	if (!EMIsRawRing3Enabled(env->pVM))
1168	return false;
1169
1170	if (!(env->eflags & IF_MASK))
1171	{
1172	#ifdef VBOX_RAW_V86
1173	if(!(fFlags & VM_MASK))
1174	return false;
1175	#else
1176	STAM_COUNTER_INC(&gStatRefuseIF0);
1177	Log2(("raw mode refused: IF (RawR3)\n"));
1178	return false;
1179	#endif
1180	}
1181
1182	if (!(u32CR0 & CR0_WP_MASK) && EMIsRawRing0Enabled(env->pVM))
1183	{
1184	STAM_COUNTER_INC(&gStatRefuseWP0);
1185	Log2(("raw mode refused: CR0.WP + RawR0\n"));
1186	return false;
1187	}
1188	}
1189	else
1190	{
1191	if (!EMIsRawRing0Enabled(env->pVM))
1192	return false;
1193
1194	// Let's start with pure 32 bits ring 0 code first
1195	if ((fFlags & (HF_SS32_MASK \| HF_CS32_MASK)) != (HF_SS32_MASK \| HF_CS32_MASK))
1196	{
1197	STAM_COUNTER_INC(&gStatRefuseCode16);
1198	Log2(("raw r0 mode refused: HF_[S\|C]S32_MASK fFlags=%#x\n", fFlags));
1199	return false;
1200	}
1201
1202	// Only R0
1203	if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
1204	{
1205	STAM_COUNTER_INC(&gStatRefuseRing1or2);
1206	Log2(("raw r0 mode refused: CPL %d\n", ((fFlags >> HF_CPL_SHIFT) & 3) ));
1207	return false;
1208	}
1209
1210	if (!(u32CR0 & CR0_WP_MASK))
1211	{
1212	STAM_COUNTER_INC(&gStatRefuseWP0);
1213	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1214	return false;
1215	}
1216
1217	if (PATMIsPatchGCAddr(env->pVM, eip))
1218	{
1219	Log2(("raw r0 mode forced: patch code\n"));
1220	*pExceptionIndex = EXCP_EXECUTE_RAW;
1221	return true;
1222	}
1223
1224	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1225	if (!(env->eflags & IF_MASK))
1226	{
1227	STAM_COUNTER_INC(&gStatRefuseIF0);
1228	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, *env->pVMeflags));
1229	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1230	return false;
1231	}
1232	#endif
1233
1234	env->state \|= CPU_RAW_RING0;
1235	}
1236
1237	/*
1238	* Don't reschedule the first time we're called, because there might be
1239	* special reasons why we're here that is not covered by the above checks.
1240	*/
1241	if (env->pVM->rem.s.cCanExecuteRaw == 1)
1242	{
1243	Log2(("raw mode refused: first scheduling\n"));
1244	STAM_COUNTER_INC(&gStatRefuseCanExecute);
1245	return false;
1246	}
1247
1248	Assert(PGMPhysIsA20Enabled(env->pVM));
1249	*pExceptionIndex = EXCP_EXECUTE_RAW;
1250	return true;
1251	}
1252
1253
1254	/**
1255	* Fetches a code byte.
1256	*
1257	* @returns Success indicator (bool) for ease of use.
1258	* @param env The CPU environment structure.
1259	* @param GCPtrInstr Where to fetch code.
1260	* @param pu8Byte Where to store the byte on success
1261	*/
1262	bool remR3GetOpcode(CPUState env, RTGCPTR GCPtrInstr, uint8_t pu8Byte)
1263	{
1264	int rc = PATMR3QueryOpcode(env->pVM, GCPtrInstr, pu8Byte);
1265	if (VBOX_SUCCESS(rc))
1266	return true;
1267	return false;
1268	}
1269
1270
1271	/**
1272	* Flush (or invalidate if you like) page table/dir entry.
1273	*
1274	* (invlpg instruction; tlb_flush_page)
1275	*
1276	* @param env Pointer to cpu environment.
1277	* @param GCPtr The virtual address which page table/dir entry should be invalidated.
1278	*/
1279	void remR3FlushPage(CPUState *env, RTGCPTR GCPtr)
1280	{
1281	PVM pVM = env->pVM;
1282
1283	/*
1284	* When we're replaying invlpg instructions or restoring a saved
1285	* state we disable this path.
1286	*/
1287	if (pVM->rem.s.fIgnoreInvlPg)
1288	return;
1289	Log(("remR3FlushPage: GCPtr=%VGv\n", GCPtr));
1290
1291	//RAWEx_ProfileStop(env, STATS_QEMU_TOTAL);
1292
1293	/*
1294	* Update the control registers before calling PGMFlushPage.
1295	*/
1296	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1297	pCtx->cr0 = env->cr[0];
1298	pCtx->cr3 = env->cr[3];
1299	pCtx->cr4 = env->cr[4];
1300
1301	/*
1302	* Let PGM do the rest.
1303	*/
1304	int rc = PGMInvalidatePage(pVM, GCPtr);
1305	if (VBOX_FAILURE(rc))
1306	{
1307	AssertMsgFailed(("remR3FlushPage %x %x %x %d failed!!\n", GCPtr));
1308	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1309	}
1310	//RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
1311	}
1312
1313	/**
1314	* Set page table/dir entry. (called from tlb_set_page)
1315	*
1316	* @param env Pointer to cpu environment.
1317	*/
1318	void remR3SetPage(CPUState env, CPUTLBEntry pRead, CPUTLBEntry *pWrite, int prot, int is_user)
1319	{
1320	uint32_t virt_addr, addend;
1321
1322	Log2(("tlb_set_page_raw read (%x-%x) write (%x-%x) prot %x is_user %d\n", pRead->address, pRead->addend, pWrite->address, pWrite->addend, prot, is_user));
1323
1324	if (prot & PAGE_WRITE)
1325	{
1326	addend = pWrite->addend;
1327	virt_addr = pWrite->address;
1328	}
1329	else
1330	if (prot & PAGE_READ)
1331	{
1332	addend = pRead->addend;
1333	virt_addr = pRead->address;
1334	}
1335	else
1336	{
1337	// Should never happen!
1338	AssertMsgFailed(("tlb_set_page_raw unexpected protection flags %x\n", prot));
1339	return;
1340	}
1341
1342	// Clear IO_* flags (TODO: are they actually useful for us??)
1343	virt_addr &= ~0xFFF;
1344
1345	/*
1346	* Update the control registers before calling PGMFlushPage.
1347	*/
1348	PCPUMCTX pCtx = (PCPUMCTX)env->pVM->rem.s.pCtx;
1349	pCtx->cr0 = env->cr[0];
1350	pCtx->cr3 = env->cr[3];
1351	pCtx->cr4 = env->cr[4];
1352
1353	/*
1354	* Let PGM do the rest.
1355	*/
1356	int rc = PGMInvalidatePage(env->pVM, (RTGCPTR)virt_addr);
1357	if (VBOX_FAILURE(rc))
1358	{
1359	AssertMsgFailed(("RAWEx_SetPageEntry %x %x %d failed!!\n", virt_addr, prot, is_user));
1360	VM_FF_SET(env->pVM, VM_FF_PGM_SYNC_CR3);
1361	}
1362	}
1363
1364	/**
1365	* Called from tlb_protect_code in order to write monitor a code page.
1366	*
1367	* @param env Pointer to the CPU environment.
1368	* @param GCPtr Code page to monitor
1369	*/
1370	void remR3ProtectCode(CPUState *env, RTGCPTR GCPtr)
1371	{
1372	if ( (env->cr[0] & X86_CR0_PG) /* paging must be enabled */
1373	&& !(env->state & CPU_EMULATE_SINGLE_INSTR) /* ignore during single instruction execution */
1374	&& (((env->hflags >> HF_CPL_SHIFT) & 3) == 0) /* supervisor mode only */
1375	&& !(env->eflags & VM_MASK) /* no V86 mode */
1376	&& !HWACCMIsEnabled(env->pVM))
1377	CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
1378	}
1379
1380	/**
1381	* Called when the CPU is initialized, any of the CRx registers are changed or
1382	* when the A20 line is modified.
1383	*
1384	* @param env Pointer to the CPU environment.
1385	* @param fGlobal Set if the flush is global.
1386	*/
1387	void remR3FlushTLB(CPUState *env, bool fGlobal)
1388	{
1389	PVM pVM = env->pVM;
1390
1391	/*
1392	* When we're replaying invlpg instructions or restoring a saved
1393	* state we disable this path.
1394	*/
1395	if (pVM->rem.s.fIgnoreCR3Load)
1396	return;
1397
1398	/*
1399	* The caller doesn't check cr4, so we have to do that for ourselves.
1400	*/
1401	if (!fGlobal && !(env->cr[4] & X86_CR4_PGE))
1402	fGlobal = true;
1403	Log(("remR3FlushTLB: CR0=%VGp CR3=%VGp CR4=%VGp %s\n", env->cr[0], env->cr[3], env->cr[4], fGlobal ? " global" : ""));
1404
1405	/*
1406	* Update the control registers before calling PGMR3FlushTLB.
1407	*/
1408	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1409	pCtx->cr0 = env->cr[0];
1410	pCtx->cr3 = env->cr[3];
1411	pCtx->cr4 = env->cr[4];
1412
1413	/*
1414	* Let PGM do the rest.
1415	*/
1416	PGMFlushTLB(pVM, env->cr[3], fGlobal);
1417	}
1418
1419
1420	/**
1421	* Called when any of the cr0, cr4 or efer registers is updated.
1422	*
1423	* @param env Pointer to the CPU environment.
1424	*/
1425	void remR3ChangeCpuMode(CPUState *env)
1426	{
1427	int rc;
1428	PVM pVM = env->pVM;
1429
1430	/*
1431	* When we're replaying loads or restoring a saved
1432	* state this path is disabled.
1433	*/
1434	if (pVM->rem.s.fIgnoreCpuMode)
1435	return;
1436
1437	/*
1438	* Update the control registers before calling PGMR3ChangeMode()
1439	* as it may need to map whatever cr3 is pointing to.
1440	*/
1441	PCPUMCTX pCtx = (PCPUMCTX)pVM->rem.s.pCtx;
1442	pCtx->cr0 = env->cr[0];
1443	pCtx->cr3 = env->cr[3];
1444	pCtx->cr4 = env->cr[4];
1445
1446	#ifdef TARGET_X86_64
1447	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer);
1448	if (rc != VINF_SUCCESS)
1449	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], env->efer, rc);
1450	#else
1451	rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0);
1452	if (rc != VINF_SUCCESS)
1453	cpu_abort(env, "PGMChangeMode(, %08x, %08x, %016llx) -> %Vrc\n", env->cr[0], env->cr[4], 0LL, rc);
1454	#endif
1455	}
1456
1457
1458	/**
1459	* Called from compiled code to run dma.
1460	*
1461	* @param env Pointer to the CPU environment.
1462	*/
1463	void remR3DmaRun(CPUState *env)
1464	{
1465	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1466	PDMR3DmaRun(env->pVM);
1467	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1468	}
1469
1470	/**
1471	* Called from compiled code to schedule pending timers in VMM
1472	*
1473	* @param env Pointer to the CPU environment.
1474	*/
1475	void remR3TimersRun(CPUState *env)
1476	{
1477	remR3ProfileStop(STATS_QEMU_RUN_EMULATED_CODE);
1478	remR3ProfileStart(STATS_QEMU_RUN_TIMERS);
1479	TMR3TimerQueuesDo(env->pVM);
1480	remR3ProfileStop(STATS_QEMU_RUN_TIMERS);
1481	remR3ProfileStart(STATS_QEMU_RUN_EMULATED_CODE);
1482	}
1483
1484	/**
1485	* Record trap occurance
1486	*
1487	* @returns VBox status code
1488	* @param env Pointer to the CPU environment.
1489	* @param uTrap Trap nr
1490	* @param uErrorCode Error code
1491	* @param pvNextEIP Next EIP
1492	*/
1493	int remR3NotifyTrap(CPUState *env, uint32_t uTrap, uint32_t uErrorCode, uint32_t pvNextEIP)
1494	{
1495	PVM pVM = (PVM)env->pVM;
1496	#ifdef VBOX_WITH_STATISTICS
1497	static STAMCOUNTER aStatTrap[255];
1498	static bool aRegisters[ELEMENTS(aStatTrap)];
1499	#endif
1500
1501	#ifdef VBOX_WITH_STATISTICS
1502	if (uTrap < 255)
1503	{
1504	if (!aRegisters[uTrap])
1505	{
1506	aRegisters[uTrap] = true;
1507	char szStatName[64];
1508	RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
1509	STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
1510	}
1511	STAM_COUNTER_INC(&aStatTrap[uTrap]);
1512	}
1513	#endif
1514	Log(("remR3NotifyTrap: uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1515	if(uTrap < 0x20)
1516	{
1517	remR3DisasInstr(env, 1, "remR3NotifyTrap: ");
1518
1519	if(pVM->rem.s.uPendingException == uTrap && ++pVM->rem.s.cPendingExceptions > 128)
1520	{
1521	LogRel(("VERR_REM_TOO_MANY_TRAPS -> uTrap=%x error=%x next_eip=%VGv eip=%VGv cr2=%08x\n", uTrap, uErrorCode, pvNextEIP, env->eip, env->cr[2]));
1522	remR3RaiseRC(env->pVM, VERR_REM_TOO_MANY_TRAPS);
1523	return VERR_REM_TOO_MANY_TRAPS;
1524	}
1525	if(pVM->rem.s.uPendingException != uTrap \|\| pVM->rem.s.uPendingExcptEIP != env->eip \|\| pVM->rem.s.uPendingExcptCR2 != env->cr[2])
1526	pVM->rem.s.cPendingExceptions = 1;
1527	pVM->rem.s.uPendingException = uTrap;
1528	pVM->rem.s.uPendingExcptEIP = env->eip;
1529	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1530	}
1531	else
1532	{
1533	pVM->rem.s.cPendingExceptions = 0;
1534	pVM->rem.s.uPendingException = uTrap;
1535	pVM->rem.s.uPendingExcptEIP = env->eip;
1536	pVM->rem.s.uPendingExcptCR2 = env->cr[2];
1537	}
1538	return VINF_SUCCESS;
1539	}
1540
1541	/*
1542	* Clear current active trap
1543	*
1544	* @param pVM VM Handle.
1545	*/
1546	void remR3TrapClear(PVM pVM)
1547	{
1548	pVM->rem.s.cPendingExceptions = 0;
1549	pVM->rem.s.uPendingException = 0;
1550	pVM->rem.s.uPendingExcptEIP = 0;
1551	pVM->rem.s.uPendingExcptCR2 = 0;
1552	}
1553
1554
1555	/**
1556	* Syncs the internal REM state with the VM.
1557	*
1558	* This must be called before REMR3Run() is invoked whenever when the REM
1559	* state is not up to date. Calling it several times in a row is not
1560	* permitted.
1561	*
1562	* @returns VBox status code.
1563	*
1564	* @param pVM VM Handle.
1565	*
1566	* @remark The caller has to check for important FFs before calling REMR3Run. REMR3State will
1567	* no do this since the majority of the callers don't want any unnecessary of events
1568	* pending that would immediatly interrupt execution.
1569	*/
1570	REMR3DECL(int) REMR3State(PVM pVM)
1571	{
1572	Assert(!pVM->rem.s.fInREM);
1573	Log2(("REMR3State:\n"));
1574	STAM_PROFILE_START(&pVM->rem.s.StatsState, a);
1575	register const CPUMCTX *pCtx = pVM->rem.s.pCtx;
1576	register unsigned fFlags;
1577
1578	/*
1579	* Copy the registers which requires no special handling.
1580	*/
1581	Assert(R_EAX == 0);
1582	pVM->rem.s.Env.regs[R_EAX] = pCtx->eax;
1583	Assert(R_ECX == 1);
1584	pVM->rem.s.Env.regs[R_ECX] = pCtx->ecx;
1585	Assert(R_EDX == 2);
1586	pVM->rem.s.Env.regs[R_EDX] = pCtx->edx;
1587	Assert(R_EBX == 3);
1588	pVM->rem.s.Env.regs[R_EBX] = pCtx->ebx;
1589	Assert(R_ESP == 4);
1590	pVM->rem.s.Env.regs[R_ESP] = pCtx->esp;
1591	Assert(R_EBP == 5);
1592	pVM->rem.s.Env.regs[R_EBP] = pCtx->ebp;
1593	Assert(R_ESI == 6);
1594	pVM->rem.s.Env.regs[R_ESI] = pCtx->esi;
1595	Assert(R_EDI == 7);
1596	pVM->rem.s.Env.regs[R_EDI] = pCtx->edi;
1597	pVM->rem.s.Env.eip = pCtx->eip;
1598
1599	pVM->rem.s.Env.eflags = pCtx->eflags.u32;
1600
1601	pVM->rem.s.Env.cr[2] = pCtx->cr2;
1602
1603	/** @todo we could probably benefit from using a CPUM_CHANGED_DRx flag too! */
1604	pVM->rem.s.Env.dr[0] = pCtx->dr0;
1605	pVM->rem.s.Env.dr[1] = pCtx->dr1;
1606	pVM->rem.s.Env.dr[2] = pCtx->dr2;
1607	pVM->rem.s.Env.dr[3] = pCtx->dr3;
1608	pVM->rem.s.Env.dr[4] = pCtx->dr4;
1609	pVM->rem.s.Env.dr[5] = pCtx->dr5;
1610	pVM->rem.s.Env.dr[6] = pCtx->dr6;
1611	pVM->rem.s.Env.dr[7] = pCtx->dr7;
1612
1613	/*
1614	* Replay invlpg?
1615	*/
1616	if (pVM->rem.s.cInvalidatedPages)
1617	{
1618	pVM->rem.s.fIgnoreInvlPg = true;
1619	RTUINT i;
1620	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
1621	{
1622	Log2(("REMR3State: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
1623	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
1624	}
1625	pVM->rem.s.fIgnoreInvlPg = false;
1626	pVM->rem.s.cInvalidatedPages = 0;
1627	}
1628
1629	/*
1630	* Registers which are seldomly changed and require special handling / order when changed.
1631	*/
1632	fFlags = CPUMGetAndClearChangedFlagsREM(pVM);
1633	if (fFlags & ( CPUM_CHANGED_CR4 \| CPUM_CHANGED_CR3 \| CPUM_CHANGED_CR0
1634	\| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_TR
1635	\| CPUM_CHANGED_FPU_REM \| CPUM_CHANGED_SYSENTER_MSR))
1636	{
1637	if (fFlags & CPUM_CHANGED_FPU_REM)
1638	save_raw_fp_state(&pVM->rem.s.Env, (uint8_t )&pCtx->fpu); / 'save' is an excellent name. */
1639
1640	if (fFlags & CPUM_CHANGED_GLOBAL_TLB_FLUSH)
1641	{
1642	pVM->rem.s.fIgnoreCR3Load = true;
1643	tlb_flush(&pVM->rem.s.Env, true);
1644	pVM->rem.s.fIgnoreCR3Load = false;
1645	}
1646
1647	if (fFlags & CPUM_CHANGED_CR4)
1648	{
1649	pVM->rem.s.fIgnoreCR3Load = true;
1650	pVM->rem.s.fIgnoreCpuMode = true;
1651	cpu_x86_update_cr4(&pVM->rem.s.Env, pCtx->cr4);
1652	pVM->rem.s.fIgnoreCpuMode = false;
1653	pVM->rem.s.fIgnoreCR3Load = false;
1654	}
1655
1656	if (fFlags & CPUM_CHANGED_CR0)
1657	{
1658	pVM->rem.s.fIgnoreCR3Load = true;
1659	pVM->rem.s.fIgnoreCpuMode = true;
1660	cpu_x86_update_cr0(&pVM->rem.s.Env, pCtx->cr0);
1661	pVM->rem.s.fIgnoreCpuMode = false;
1662	pVM->rem.s.fIgnoreCR3Load = false;
1663	}
1664
1665	if (fFlags & CPUM_CHANGED_CR3)
1666	{
1667	pVM->rem.s.fIgnoreCR3Load = true;
1668	cpu_x86_update_cr3(&pVM->rem.s.Env, pCtx->cr3);
1669	pVM->rem.s.fIgnoreCR3Load = false;
1670	}
1671
1672	if (fFlags & CPUM_CHANGED_GDTR)
1673	{
1674	pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt;
1675	pVM->rem.s.Env.gdt.limit = pCtx->gdtr.cbGdt;
1676	}
1677
1678	if (fFlags & CPUM_CHANGED_IDTR)
1679	{
1680	pVM->rem.s.Env.idt.base = pCtx->idtr.pIdt;
1681	pVM->rem.s.Env.idt.limit = pCtx->idtr.cbIdt;
1682	}
1683
1684	if (fFlags & CPUM_CHANGED_SYSENTER_MSR)
1685	{
1686	pVM->rem.s.Env.sysenter_cs = pCtx->SysEnter.cs;
1687	pVM->rem.s.Env.sysenter_eip = pCtx->SysEnter.eip;
1688	pVM->rem.s.Env.sysenter_esp = pCtx->SysEnter.esp;
1689	}
1690
1691	if (fFlags & CPUM_CHANGED_LDTR)
1692	{
1693	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1694	{
1695	pVM->rem.s.Env.ldt.selector = pCtx->ldtr;
1696	pVM->rem.s.Env.ldt.base = pCtx->ldtrHid.u32Base;
1697	pVM->rem.s.Env.ldt.limit = pCtx->ldtrHid.u32Limit;
1698	pVM->rem.s.Env.ldt.flags = (pCtx->ldtrHid.Attr.u << 8) & 0xFFFFFF;;
1699	}
1700	else
1701	sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr);
1702	}
1703
1704	if (fFlags & CPUM_CHANGED_TR)
1705	{
1706	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1707	{
1708	pVM->rem.s.Env.tr.selector = pCtx->tr;
1709	pVM->rem.s.Env.tr.base = pCtx->trHid.u32Base;
1710	pVM->rem.s.Env.tr.limit = pCtx->trHid.u32Limit;
1711	pVM->rem.s.Env.tr.flags = (pCtx->trHid.Attr.u << 8) & 0xFFFFFF;;
1712	}
1713	else
1714	sync_tr(&pVM->rem.s.Env, pCtx->tr);
1715
1716	/** @note do_interrupt will fault if the busy flag is still set.... */
1717	pVM->rem.s.Env.tr.flags &= ~DESC_TSS_BUSY_MASK;
1718	}
1719	}
1720
1721	/*
1722	* Update selector registers.
1723	* This must be done after we've synced gdt, ldt and crX registers
1724	* since we're reading the GDT/LDT om sync_seg. This will happen with
1725	* saved state which takes a quick dip into rawmode for instance.
1726	*/
1727	/*
1728	* Stack; Note first check this one as the CPL might have changed. The
1729	* wrong CPL can cause QEmu to raise an exception in sync_seg!!
1730	*/
1731
1732	if (fFlags & CPUM_CHANGED_HIDDEN_SEL_REGS)
1733	{
1734	/* The hidden selector registers are valid in the CPU context. */
1735	/** @note QEmu saves the 2nd dword of the descriptor; we should convert the attribute word back! */
1736
1737	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_CS, pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, (pCtx->csHid.Attr.u << 8) & 0xFFFFFF);
1738	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_SS, pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, (pCtx->ssHid.Attr.u << 8) & 0xFFFFFF);
1739	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
1740	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
1741	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
1742	cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
1743
1744	/* Set current CPL. */
1745	if (pCtx->eflags.Bits.u1VM == 1)
1746	cpu_x86_set_cpl(&pVM->rem.s.Env, 3);
1747	else
1748	cpu_x86_set_cpl(&pVM->rem.s.Env, pCtx->ss & 3);
1749	}
1750	else
1751	{
1752	/* In 'normal' raw mode we don't have access to the hidden selector registers. */
1753	if (pVM->rem.s.Env.segs[R_SS].selector != (uint16_t)pCtx->ss)
1754	{
1755	Log2(("REMR3State: SS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_SS].selector, pCtx->ss));
1756
1757	cpu_x86_set_cpl(&pVM->rem.s.Env, (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & 3));
1758	sync_seg(&pVM->rem.s.Env, R_SS, pCtx->ss);
1759	#ifdef VBOX_WITH_STATISTICS
1760	if (pVM->rem.s.Env.segs[R_SS].newselector)
1761	{
1762	STAM_COUNTER_INC(&gStatSelOutOfSync[R_SS]);
1763	}
1764	#endif
1765	}
1766	else
1767	pVM->rem.s.Env.segs[R_SS].newselector = 0;
1768
1769	if (pVM->rem.s.Env.segs[R_ES].selector != pCtx->es)
1770	{
1771	Log2(("REMR3State: ES changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_ES].selector, pCtx->es));
1772	sync_seg(&pVM->rem.s.Env, R_ES, pCtx->es);
1773	#ifdef VBOX_WITH_STATISTICS
1774	if (pVM->rem.s.Env.segs[R_ES].newselector)
1775	{
1776	STAM_COUNTER_INC(&gStatSelOutOfSync[R_ES]);
1777	}
1778	#endif
1779	}
1780	else
1781	pVM->rem.s.Env.segs[R_ES].newselector = 0;
1782
1783	if (pVM->rem.s.Env.segs[R_CS].selector != pCtx->cs)
1784	{
1785	Log2(("REMR3State: CS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_CS].selector, pCtx->cs));
1786	sync_seg(&pVM->rem.s.Env, R_CS, pCtx->cs);
1787	#ifdef VBOX_WITH_STATISTICS
1788	if (pVM->rem.s.Env.segs[R_CS].newselector)
1789	{
1790	STAM_COUNTER_INC(&gStatSelOutOfSync[R_CS]);
1791	}
1792	#endif
1793	}
1794	else
1795	pVM->rem.s.Env.segs[R_CS].newselector = 0;
1796
1797	if (pVM->rem.s.Env.segs[R_DS].selector != pCtx->ds)
1798	{
1799	Log2(("REMR3State: DS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_DS].selector, pCtx->ds));
1800	sync_seg(&pVM->rem.s.Env, R_DS, pCtx->ds);
1801	#ifdef VBOX_WITH_STATISTICS
1802	if (pVM->rem.s.Env.segs[R_DS].newselector)
1803	{
1804	STAM_COUNTER_INC(&gStatSelOutOfSync[R_DS]);
1805	}
1806	#endif
1807	}
1808	else
1809	pVM->rem.s.Env.segs[R_DS].newselector = 0;
1810
1811	/** @todo need to find a way to communicate potential GDT/LDT changes and thread switches. The selector might
1812	* be the same but not the base/limit. */
1813	if (pVM->rem.s.Env.segs[R_FS].selector != pCtx->fs)
1814	{
1815	Log2(("REMR3State: FS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_FS].selector, pCtx->fs));
1816	sync_seg(&pVM->rem.s.Env, R_FS, pCtx->fs);
1817	#ifdef VBOX_WITH_STATISTICS
1818	if (pVM->rem.s.Env.segs[R_FS].newselector)
1819	{
1820	STAM_COUNTER_INC(&gStatSelOutOfSync[R_FS]);
1821	}
1822	#endif
1823	}
1824	else
1825	pVM->rem.s.Env.segs[R_FS].newselector = 0;
1826
1827	if (pVM->rem.s.Env.segs[R_GS].selector != pCtx->gs)
1828	{
1829	Log2(("REMR3State: GS changed from %04x to %04x!\n", pVM->rem.s.Env.segs[R_GS].selector, pCtx->gs));
1830	sync_seg(&pVM->rem.s.Env, R_GS, pCtx->gs);
1831	#ifdef VBOX_WITH_STATISTICS
1832	if (pVM->rem.s.Env.segs[R_GS].newselector)
1833	{
1834	STAM_COUNTER_INC(&gStatSelOutOfSync[R_GS]);
1835	}
1836	#endif
1837	}
1838	else
1839	pVM->rem.s.Env.segs[R_GS].newselector = 0;
1840	}
1841
1842	/*
1843	* Check for traps.
1844	*/
1845	pVM->rem.s.Env.exception_index = -1; /** @todo this won't work :/ */
1846	bool fIsSoftwareInterrupt;
1847	uint8_t u8TrapNo;
1848	int rc = TRPMQueryTrap(pVM, &u8TrapNo, &fIsSoftwareInterrupt);
1849	if (VBOX_SUCCESS(rc))
1850	{
1851	#ifdef DEBUG
1852	if (u8TrapNo == 0x80)
1853	{
1854	remR3DumpLnxSyscall(pVM);
1855	remR3DumpOBsdSyscall(pVM);
1856	}
1857	#endif
1858
1859	pVM->rem.s.Env.exception_index = u8TrapNo;
1860	if (!fIsSoftwareInterrupt)
1861	{
1862	pVM->rem.s.Env.exception_is_int = 0;
1863	pVM->rem.s.Env.exception_next_eip = pVM->rem.s.Env.eip;
1864	}
1865	else
1866	{
1867	/*
1868	* The there are two 1 byte opcodes and one 2 byte opcode for software interrupts.
1869	* We ASSUME that there are no prefixes and sets the default to 2 byte, and checks
1870	* for int03 and into.
1871	*/
1872	pVM->rem.s.Env.exception_is_int = 1;
1873	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 2;
1874	/* int 3 may be generated by one-byte 0xcc */
1875	if (u8TrapNo == 3)
1876	{
1877	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xcc)
1878	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1879	}
1880	/* int 4 may be generated by one-byte 0xce */
1881	else if (u8TrapNo == 4)
1882	{
1883	if (read_byte(&pVM->rem.s.Env, pVM->rem.s.Env.segs[R_CS].base + pCtx->eip) == 0xce)
1884	pVM->rem.s.Env.exception_next_eip = pCtx->eip + 1;
1885	}
1886	}
1887
1888	/* get error code and cr2 if needed. */
1889	switch (u8TrapNo)
1890	{
1891	case 0x0e:
1892	pVM->rem.s.Env.cr[2] = TRPMGetFaultAddress(pVM);
1893	/* fallthru */
1894	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
1895	pVM->rem.s.Env.error_code = TRPMGetErrorCode(pVM);
1896	break;
1897
1898	case 0x11: case 0x08:
1899	default:
1900	pVM->rem.s.Env.error_code = 0;
1901	break;
1902	}
1903
1904	/*
1905	* We can now reset the active trap since the recompiler is gonna have a go at it.
1906	*/
1907	rc = TRPMResetTrap(pVM);
1908	AssertRC(rc);
1909	Log2(("REMR3State: trap=%02x errcd=%VGv cr2=%VGv nexteip=%VGv%s\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.error_code,
1910	pVM->rem.s.Env.cr[2], pVM->rem.s.Env.exception_next_eip, pVM->rem.s.Env.exception_is_int ? " software" : ""));
1911	//if (pVM->rem.s.Env.eip == 0x40005a2f)
1912	// pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP \| CPU_RAW_MODE_DISABLED \| CPU_RAWR0_MODE_DISABLED;
1913	}
1914
1915	/*
1916	* Clear old interrupt request flags; Check for pending hardware interrupts.
1917	* (See @remark for why we don't check for other FFs.)
1918	*/
1919	pVM->rem.s.Env.interrupt_request &= ~(CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXIT \| CPU_INTERRUPT_EXITTB \| CPU_INTERRUPT_TIMER);
1920	if ( pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ
1921	\|\| VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
1922	pVM->rem.s.Env.interrupt_request \|= CPU_INTERRUPT_HARD;
1923
1924	/*
1925	* We're now in REM mode.
1926	*/
1927	pVM->rem.s.fInREM = true;
1928	pVM->rem.s.cCanExecuteRaw = 0;
1929	STAM_PROFILE_STOP(&pVM->rem.s.StatsState, a);
1930	Log2(("REMR3State: returns VINF_SUCCESS\n"));
1931	return VINF_SUCCESS;
1932	}
1933
1934
1935	/**
1936	* Syncs back changes in the REM state to the the VM state.
1937	*
1938	* This must be called after invoking REMR3Run().
1939	* Calling it several times in a row is not permitted.
1940	*
1941	* @returns VBox status code.
1942	*
1943	* @param pVM VM Handle.
1944	*/
1945	REMR3DECL(int) REMR3StateBack(PVM pVM)
1946	{
1947	Log2(("REMR3StateBack:\n"));
1948	Assert(pVM->rem.s.fInREM);
1949	STAM_PROFILE_START(&pVM->rem.s.StatsStateBack, a);
1950	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
1951
1952	/*
1953	* Copy back the registers.
1954	* This is done in the order they are declared in the CPUMCTX structure.
1955	*/
1956
1957	/** @todo FOP */
1958	/** @todo FPUIP */
1959	/** @todo CS */
1960	/** @todo FPUDP */
1961	/** @todo DS */
1962	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
1963	pCtx->fpu.MXCSR = 0;
1964	pCtx->fpu.MXCSR_MASK = 0;
1965
1966	/** @todo check if FPU/XMM was actually used in the recompiler */
1967	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
1968	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
1969
1970	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
1971	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
1972	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
1973	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
1974	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
1975	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
1976	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
1977
1978	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
1979	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
1980
1981	#ifdef VBOX_WITH_STATISTICS
1982	if (pVM->rem.s.Env.segs[R_SS].newselector)
1983	{
1984	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_SS]);
1985	}
1986	if (pVM->rem.s.Env.segs[R_GS].newselector)
1987	{
1988	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_GS]);
1989	}
1990	if (pVM->rem.s.Env.segs[R_FS].newselector)
1991	{
1992	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_FS]);
1993	}
1994	if (pVM->rem.s.Env.segs[R_ES].newselector)
1995	{
1996	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_ES]);
1997	}
1998	if (pVM->rem.s.Env.segs[R_DS].newselector)
1999	{
2000	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_DS]);
2001	}
2002	if (pVM->rem.s.Env.segs[R_CS].newselector)
2003	{
2004	STAM_COUNTER_INC(&gStatSelOutOfSyncStateBack[R_CS]);
2005	}
2006	#endif
2007	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2008	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2009	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2010	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2011	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2012
2013	pCtx->eip = pVM->rem.s.Env.eip;
2014	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2015
2016	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2017	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2018	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2019	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2020
2021	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2022	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2023	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2024	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2025	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2026	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2027	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2028	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2029
2030	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2031	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2032	{
2033	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2034	STAM_COUNTER_INC(&gStatREMGDTChange);
2035	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2036	}
2037
2038	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2039	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2040	{
2041	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2042	STAM_COUNTER_INC(&gStatREMIDTChange);
2043	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2044	}
2045
2046	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2047	{
2048	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2049	STAM_COUNTER_INC(&gStatREMLDTRChange);
2050	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2051	}
2052	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2053	{
2054	pCtx->tr = pVM->rem.s.Env.tr.selector;
2055	STAM_COUNTER_INC(&gStatREMTRChange);
2056	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2057	}
2058
2059	/** @todo These values could still be out of sync! */
2060	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2061	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2062	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2063	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xF0FF;
2064
2065	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2066	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2067	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xF0FF;
2068
2069	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2070	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2071	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xF0FF;
2072
2073	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2074	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2075	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xF0FF;
2076
2077	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2078	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2079	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xF0FF;
2080
2081	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2082	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2083	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xF0FF;
2084
2085	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2086	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2087	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xF0FF;
2088
2089	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2090	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2091	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xF0FF;
2092
2093	/* Sysenter MSR */
2094	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2095	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2096	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2097
2098	remR3TrapClear(pVM);
2099
2100	/*
2101	* Check for traps.
2102	*/
2103	if ( pVM->rem.s.Env.exception_index >= 0
2104	&& pVM->rem.s.Env.exception_index < 256)
2105	{
2106	Log(("REMR3StateBack: Pending trap %x %d\n", pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int));
2107	int rc = TRPMAssertTrap(pVM, pVM->rem.s.Env.exception_index, pVM->rem.s.Env.exception_is_int);
2108	AssertRC(rc);
2109	switch (pVM->rem.s.Env.exception_index)
2110	{
2111	case 0x0e:
2112	TRPMSetFaultAddress(pVM, pCtx->cr2);
2113	/* fallthru */
2114	case 0x0a: case 0x0b: case 0x0c: case 0x0d:
2115	case 0x11: case 0x08: /* 0 */
2116	TRPMSetErrorCode(pVM, pVM->rem.s.Env.error_code);
2117	break;
2118	}
2119
2120	}
2121
2122	/*
2123	* We're not longer in REM mode.
2124	*/
2125	pVM->rem.s.fInREM = false;
2126	STAM_PROFILE_STOP(&pVM->rem.s.StatsStateBack, a);
2127	Log2(("REMR3StateBack: returns VINF_SUCCESS\n"));
2128	return VINF_SUCCESS;
2129	}
2130
2131
2132	/**
2133	* This is called by the disassembler when it wants to update the cpu state
2134	* before for instance doing a register dump.
2135	*/
2136	static void remR3StateUpdate(PVM pVM)
2137	{
2138	Assert(pVM->rem.s.fInREM);
2139	register PCPUMCTX pCtx = pVM->rem.s.pCtx;
2140
2141	/*
2142	* Copy back the registers.
2143	* This is done in the order they are declared in the CPUMCTX structure.
2144	*/
2145
2146	/** @todo FOP */
2147	/** @todo FPUIP */
2148	/** @todo CS */
2149	/** @todo FPUDP */
2150	/** @todo DS */
2151	/** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
2152	pCtx->fpu.MXCSR = 0;
2153	pCtx->fpu.MXCSR_MASK = 0;
2154
2155	/** @todo check if FPU/XMM was actually used in the recompiler */
2156	restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
2157	//// dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
2158
2159	pCtx->edi = pVM->rem.s.Env.regs[R_EDI];
2160	pCtx->esi = pVM->rem.s.Env.regs[R_ESI];
2161	pCtx->ebp = pVM->rem.s.Env.regs[R_EBP];
2162	pCtx->eax = pVM->rem.s.Env.regs[R_EAX];
2163	pCtx->ebx = pVM->rem.s.Env.regs[R_EBX];
2164	pCtx->edx = pVM->rem.s.Env.regs[R_EDX];
2165	pCtx->ecx = pVM->rem.s.Env.regs[R_ECX];
2166
2167	pCtx->esp = pVM->rem.s.Env.regs[R_ESP];
2168	pCtx->ss = pVM->rem.s.Env.segs[R_SS].selector;
2169
2170	pCtx->gs = pVM->rem.s.Env.segs[R_GS].selector;
2171	pCtx->fs = pVM->rem.s.Env.segs[R_FS].selector;
2172	pCtx->es = pVM->rem.s.Env.segs[R_ES].selector;
2173	pCtx->ds = pVM->rem.s.Env.segs[R_DS].selector;
2174	pCtx->cs = pVM->rem.s.Env.segs[R_CS].selector;
2175
2176	pCtx->eip = pVM->rem.s.Env.eip;
2177	pCtx->eflags.u32 = pVM->rem.s.Env.eflags;
2178
2179	pCtx->cr0 = pVM->rem.s.Env.cr[0];
2180	pCtx->cr2 = pVM->rem.s.Env.cr[2];
2181	pCtx->cr3 = pVM->rem.s.Env.cr[3];
2182	pCtx->cr4 = pVM->rem.s.Env.cr[4];
2183
2184	pCtx->dr0 = pVM->rem.s.Env.dr[0];
2185	pCtx->dr1 = pVM->rem.s.Env.dr[1];
2186	pCtx->dr2 = pVM->rem.s.Env.dr[2];
2187	pCtx->dr3 = pVM->rem.s.Env.dr[3];
2188	pCtx->dr4 = pVM->rem.s.Env.dr[4];
2189	pCtx->dr5 = pVM->rem.s.Env.dr[5];
2190	pCtx->dr6 = pVM->rem.s.Env.dr[6];
2191	pCtx->dr7 = pVM->rem.s.Env.dr[7];
2192
2193	pCtx->gdtr.cbGdt = pVM->rem.s.Env.gdt.limit;
2194	if (pCtx->gdtr.pGdt != (uint32_t)pVM->rem.s.Env.gdt.base)
2195	{
2196	pCtx->gdtr.pGdt = (uint32_t)pVM->rem.s.Env.gdt.base;
2197	STAM_COUNTER_INC(&gStatREMGDTChange);
2198	VM_FF_SET(pVM, VM_FF_SELM_SYNC_GDT);
2199	}
2200
2201	pCtx->idtr.cbIdt = pVM->rem.s.Env.idt.limit;
2202	if (pCtx->idtr.pIdt != (uint32_t)pVM->rem.s.Env.idt.base)
2203	{
2204	pCtx->idtr.pIdt = (uint32_t)pVM->rem.s.Env.idt.base;
2205	STAM_COUNTER_INC(&gStatREMIDTChange);
2206	VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
2207	}
2208
2209	if (pCtx->ldtr != pVM->rem.s.Env.ldt.selector)
2210	{
2211	pCtx->ldtr = pVM->rem.s.Env.ldt.selector;
2212	STAM_COUNTER_INC(&gStatREMLDTRChange);
2213	VM_FF_SET(pVM, VM_FF_SELM_SYNC_LDT);
2214	}
2215	if (pCtx->tr != pVM->rem.s.Env.tr.selector)
2216	{
2217	pCtx->tr = pVM->rem.s.Env.tr.selector;
2218	STAM_COUNTER_INC(&gStatREMTRChange);
2219	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2220	}
2221
2222	/** @todo These values could still be out of sync! */
2223	pCtx->csHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_CS].base;
2224	pCtx->csHid.u32Limit = pVM->rem.s.Env.segs[R_CS].limit;
2225	/** @note QEmu saves the 2nd dword of the descriptor; we should store the attribute word only! */
2226	pCtx->csHid.Attr.u = (pVM->rem.s.Env.segs[R_CS].flags >> 8) & 0xFFFF;
2227
2228	pCtx->dsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_DS].base;
2229	pCtx->dsHid.u32Limit = pVM->rem.s.Env.segs[R_DS].limit;
2230	pCtx->dsHid.Attr.u = (pVM->rem.s.Env.segs[R_DS].flags >> 8) & 0xFFFF;
2231
2232	pCtx->esHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_ES].base;
2233	pCtx->esHid.u32Limit = pVM->rem.s.Env.segs[R_ES].limit;
2234	pCtx->esHid.Attr.u = (pVM->rem.s.Env.segs[R_ES].flags >> 8) & 0xFFFF;
2235
2236	pCtx->fsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_FS].base;
2237	pCtx->fsHid.u32Limit = pVM->rem.s.Env.segs[R_FS].limit;
2238	pCtx->fsHid.Attr.u = (pVM->rem.s.Env.segs[R_FS].flags >> 8) & 0xFFFF;
2239
2240	pCtx->gsHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_GS].base;
2241	pCtx->gsHid.u32Limit = pVM->rem.s.Env.segs[R_GS].limit;
2242	pCtx->gsHid.Attr.u = (pVM->rem.s.Env.segs[R_GS].flags >> 8) & 0xFFFF;
2243
2244	pCtx->ssHid.u32Base = (uint32_t)pVM->rem.s.Env.segs[R_SS].base;
2245	pCtx->ssHid.u32Limit = pVM->rem.s.Env.segs[R_SS].limit;
2246	pCtx->ssHid.Attr.u = (pVM->rem.s.Env.segs[R_SS].flags >> 8) & 0xFFFF;
2247
2248	pCtx->ldtrHid.u32Base = (uint32_t)pVM->rem.s.Env.ldt.base;
2249	pCtx->ldtrHid.u32Limit = pVM->rem.s.Env.ldt.limit;
2250	pCtx->ldtrHid.Attr.u = (pVM->rem.s.Env.ldt.flags >> 8) & 0xFFFF;
2251
2252	pCtx->trHid.u32Base = (uint32_t)pVM->rem.s.Env.tr.base;
2253	pCtx->trHid.u32Limit = pVM->rem.s.Env.tr.limit;
2254	pCtx->trHid.Attr.u = (pVM->rem.s.Env.tr.flags >> 8) & 0xFFFF;
2255
2256	/* Sysenter MSR */
2257	pCtx->SysEnter.cs = pVM->rem.s.Env.sysenter_cs;
2258	pCtx->SysEnter.eip = pVM->rem.s.Env.sysenter_eip;
2259	pCtx->SysEnter.esp = pVM->rem.s.Env.sysenter_esp;
2260	}
2261
2262
2263	/**
2264	* Update the VMM state information if we're currently in REM.
2265	*
2266	* This method is used by the DBGF and PDMDevice when there is any uncertainty of whether
2267	* we're currently executing in REM and the VMM state is invalid. This method will of
2268	* course check that we're executing in REM before syncing any data over to the VMM.
2269	*
2270	* @param pVM The VM handle.
2271	*/
2272	REMR3DECL(void) REMR3StateUpdate(PVM pVM)
2273	{
2274	if (pVM->rem.s.fInREM)
2275	remR3StateUpdate(pVM);
2276	}
2277
2278
2279	#undef LOG_GROUP
2280	#define LOG_GROUP LOG_GROUP_REM
2281
2282
2283	/**
2284	* Notify the recompiler about Address Gate 20 state change.
2285	*
2286	* This notification is required since A20 gate changes are
2287	* initialized from a device driver and the VM might just as
2288	* well be in REM mode as in RAW mode.
2289	*
2290	* @param pVM VM handle.
2291	* @param fEnable True if the gate should be enabled.
2292	* False if the gate should be disabled.
2293	*/
2294	REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable)
2295	{
2296	LogFlow(("REMR3A20Set: fEnable=%d\n", fEnable));
2297	VM_ASSERT_EMT(pVM);
2298	cpu_x86_set_a20(&pVM->rem.s.Env, fEnable);
2299	}
2300
2301
2302	/**
2303	* Replays the invalidated recorded pages.
2304	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2305	*
2306	* @param pVM VM handle.
2307	*/
2308	REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM)
2309	{
2310	VM_ASSERT_EMT(pVM);
2311
2312	/*
2313	* Sync the required registers.
2314	*/
2315	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2316	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2317	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2318	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2319
2320	/*
2321	* Replay the flushes.
2322	*/
2323	pVM->rem.s.fIgnoreInvlPg = true;
2324	RTUINT i;
2325	for (i = 0; i < pVM->rem.s.cInvalidatedPages; i++)
2326	{
2327	Log2(("REMR3ReplayInvalidatedPages: invlpg %VGv\n", pVM->rem.s.aGCPtrInvalidatedPages[i]));
2328	tlb_flush_page(&pVM->rem.s.Env, pVM->rem.s.aGCPtrInvalidatedPages[i]);
2329	}
2330	pVM->rem.s.fIgnoreInvlPg = false;
2331	pVM->rem.s.cInvalidatedPages = 0;
2332	}
2333
2334
2335	/**
2336	* Replays the invalidated recorded pages.
2337	* Called in response to VERR_REM_FLUSHED_PAGES_OVERFLOW from the RAW execution loop.
2338	*
2339	* @param pVM VM handle.
2340	*/
2341	REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM)
2342	{
2343	LogFlow(("REMR3ReplayInvalidatedPages:\n"));
2344	VM_ASSERT_EMT(pVM);
2345
2346	/*
2347	* Replay the flushes.
2348	*/
2349	RTUINT i;
2350	const RTUINT c = pVM->rem.s.cHandlerNotifications;
2351	pVM->rem.s.cHandlerNotifications = 0;
2352	for (i = 0; i < c; i++)
2353	{
2354	PREMHANDLERNOTIFICATION pRec = &pVM->rem.s.aHandlerNotifications[i];
2355	switch (pRec->enmKind)
2356	{
2357	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_REGISTER:
2358	REMR3NotifyHandlerPhysicalRegister(pVM,
2359	pRec->u.PhysicalRegister.enmType,
2360	pRec->u.PhysicalRegister.GCPhys,
2361	pRec->u.PhysicalRegister.cb,
2362	pRec->u.PhysicalRegister.fHasHCHandler);
2363	break;
2364
2365	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_DEREGISTER:
2366	REMR3NotifyHandlerPhysicalDeregister(pVM,
2367	pRec->u.PhysicalDeregister.enmType,
2368	pRec->u.PhysicalDeregister.GCPhys,
2369	pRec->u.PhysicalDeregister.cb,
2370	pRec->u.PhysicalDeregister.fHasHCHandler,
2371	pRec->u.PhysicalDeregister.pvHCPtr);
2372	break;
2373
2374	case REMHANDLERNOTIFICATIONKIND_PHYSICAL_MODIFY:
2375	REMR3NotifyHandlerPhysicalModify(pVM,
2376	pRec->u.PhysicalModify.enmType,
2377	pRec->u.PhysicalModify.GCPhysOld,
2378	pRec->u.PhysicalModify.GCPhysNew,
2379	pRec->u.PhysicalModify.cb,
2380	pRec->u.PhysicalModify.fHasHCHandler,
2381	pRec->u.PhysicalModify.pvHCPtr);
2382	break;
2383
2384	default:
2385	AssertReleaseMsgFailed(("enmKind=%d\n", pRec->enmKind));
2386	break;
2387	}
2388	}
2389	}
2390
2391
2392	/**
2393	* Notify REM about changed code page.
2394	*
2395	* @returns VBox status code.
2396	* @param pVM VM handle.
2397	* @param pvCodePage Code page address
2398	*/
2399	REMR3DECL(int) REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage)
2400	{
2401	int rc;
2402	RTGCPHYS PhysGC;
2403	uint64_t flags;
2404
2405	VM_ASSERT_EMT(pVM);
2406
2407	/*
2408	* Get the physical page address.
2409	*/
2410	rc = PGMGstGetPage(pVM, pvCodePage, &flags, &PhysGC);
2411	if (rc == VINF_SUCCESS)
2412	{
2413	/*
2414	* Sync the required registers and flush the whole page.
2415	* (Easier to do the whole page than notifying it about each physical
2416	* byte that was changed.
2417	*/
2418	pVM->rem.s.Env.cr[0] = pVM->rem.s.pCtx->cr0;
2419	pVM->rem.s.Env.cr[2] = pVM->rem.s.pCtx->cr2;
2420	pVM->rem.s.Env.cr[3] = pVM->rem.s.pCtx->cr3;
2421	pVM->rem.s.Env.cr[4] = pVM->rem.s.pCtx->cr4;
2422
2423	tb_invalidate_phys_page_range(PhysGC, PhysGC + PAGE_SIZE - 1, 0);
2424	}
2425	return VINF_SUCCESS;
2426	}
2427
2428	/**
2429	* Notification about a successful MMR3PhysRegister() call.
2430	*
2431	* @param pVM VM handle.
2432	* @param GCPhys The physical address the RAM.
2433	* @param cb Size of the memory.
2434	* @param pvRam The HC address of the RAM.
2435	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2436	*/
2437	REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
2438	{
2439	Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2440	VM_ASSERT_EMT(pVM);
2441
2442	/*
2443	* Validate input - we trust the caller.
2444	*/
2445	Assert(!GCPhys \|\| pvRam);
2446	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2447	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2448	Assert(cb);
2449	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2450
2451	/*
2452	* Base ram?
2453	*/
2454	if (!GCPhys)
2455	{
2456	#ifndef PGM_DYNAMIC_RAM_ALLOC
2457	AssertRelease(!phys_ram_base);
2458	phys_ram_base = pvRam;
2459	#endif
2460	phys_ram_size = cb;
2461	phys_ram_dirty = MMR3HeapAllocZ(pVM, MM_TAG_REM, cb >> PAGE_SHIFT);
2462	AssertReleaseMsg(phys_ram_dirty, ("failed to allocate %d bytes of dirty bytes\n", cb >> PAGE_SHIFT));
2463	}
2464	#ifndef PGM_DYNAMIC_RAM_ALLOC
2465	AssertRelease(phys_ram_base);
2466	#endif
2467
2468	/*
2469	* Register the ram.
2470	*/
2471	#ifdef PGM_DYNAMIC_RAM_ALLOC
2472	if (!GCPhys)
2473	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_RAM_MISSING);
2474	else
2475	{
2476	uint32_t i;
2477
2478	cpu_register_physical_memory(GCPhys, cb, GCPhys \| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2479
2480	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2481	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2482	{
2483	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2484	{
2485	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2486	pVM->rem.s.aPhysReg[i].cb = cb;
2487	break;
2488	}
2489	}
2490	if (i == pVM->rem.s.cPhysRegistrations)
2491	{
2492	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2493	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvRam;
2494	pVM->rem.s.aPhysReg[i].cb = cb;
2495	pVM->rem.s.cPhysRegistrations++;
2496	}
2497	}
2498	#else
2499	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvRam - (uintptr_t)phys_ram_base)
2500	\| (fFlags & MM_RAM_FLAGS_RESERVED ? IO_MEM_UNASSIGNED : 0));
2501	#endif
2502	}
2503
2504
2505	/**
2506	* Notification about a successful PGMR3PhysRegisterChunk() call.
2507	*
2508	* @param pVM VM handle.
2509	* @param GCPhys The physical address the RAM.
2510	* @param cb Size of the memory.
2511	* @param pvRam The HC address of the RAM.
2512	* @param fFlags Flags of the MM_RAM_FLAGS_* defines.
2513	*/
2514	REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
2515	{
2516	uint32_t idx;
2517
2518	Log(("REMR3NotifyPhysRamChunkRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
2519	VM_ASSERT_EMT(pVM);
2520
2521	/*
2522	* Validate input - we trust the caller.
2523	*/
2524	Assert(pvRam);
2525	Assert(RT_ALIGN(pvRam, PAGE_SIZE) == pvRam);
2526	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2527	Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2528	Assert(fFlags == 0 /* normal RAM */);
2529
2530	if (!pVM->rem.s.paHCVirtToGCPhys)
2531	{
2532	uint32_t size = (_4G >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(REMCHUNKINFO);
2533
2534	Assert(phys_ram_size);
2535
2536	pVM->rem.s.paHCVirtToGCPhys = (PREMCHUNKINFO)MMR3HeapAllocZ(pVM, MM_TAG_REM, size);
2537	pVM->rem.s.paGCPhysToHCVirt = (RTHCPTR)MMR3HeapAllocZ(pVM, MM_TAG_REM, (phys_ram_size >> PGM_DYNAMIC_CHUNK_SHIFT)*sizeof(RTHCPTR));
2538	}
2539	pVM->rem.s.paGCPhysToHCVirt[GCPhys >> PGM_DYNAMIC_CHUNK_SHIFT] = pvRam;
2540
2541	idx = (pvRam >> PGM_DYNAMIC_CHUNK_SHIFT);
2542	if (!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1)
2543	{
2544	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1 = pvRam;
2545	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 = GCPhys;
2546	}
2547	else
2548	{
2549	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2);
2550	pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2 = pvRam;
2551	pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 = GCPhys;
2552	}
2553	/* Does the region spawn two chunks? */
2554	if (pvRam & PGM_DYNAMIC_CHUNK_OFFSET_MASK)
2555	{
2556	if (!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1)
2557	{
2558	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk1 = pvRam;
2559	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys1 = GCPhys;
2560	}
2561	else
2562	{
2563	Assert(!pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2);
2564	pVM->rem.s.paHCVirtToGCPhys[idx+1].pChunk2 = pvRam;
2565	pVM->rem.s.paHCVirtToGCPhys[idx+1].GCPhys2 = GCPhys;
2566	}
2567	}
2568	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2569	}
2570
2571	/**
2572	* Convert GC physical address to HC virt
2573	*
2574	* @returns The HC virt address corresponding to addr.
2575	* @param env The cpu environment.
2576	* @param addr The physical address.
2577	*/
2578	void remR3GCPhys2HCVirt(void env, target_ulong addr)
2579	{
2580	#ifdef PGM_DYNAMIC_RAM_ALLOC
2581	PVM pVM = ((CPUState *)env)->pVM;
2582	uint32_t i;
2583
2584	/* lookup in pVM->rem.s.aPhysReg array first (for ROM range(s) inside the guest's RAM) */
2585	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2586	{
2587	uint32_t off = addr - pVM->rem.s.aPhysReg[i].GCPhys;
2588	if (off < pVM->rem.s.aPhysReg[i].cb)
2589	{
2590	Log(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].HCVirt + off));
2591	return (void *)(pVM->rem.s.aPhysReg[i].HCVirt + off);
2592	}
2593	}
2594	AssertMsg(addr < phys_ram_size, ("remR3GCPhys2HCVirt: unknown physical address %x\n", addr));
2595	Log(("remR3GCPhys2HCVirt: %x -> %x\n", addr, pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK)));
2596	return (void *)(pVM->rem.s.paGCPhysToHCVirt[addr >> PGM_DYNAMIC_CHUNK_SHIFT] + (addr & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2597	#else
2598	return phys_ram_base + addr;
2599	#endif
2600	}
2601
2602	/**
2603	* Convert GC physical address to HC virt
2604	*
2605	* @returns The HC virt address corresponding to addr.
2606	* @param env The cpu environment.
2607	* @param addr The physical address.
2608	*/
2609	target_ulong remR3HCVirt2GCPhys(void env, void addr)
2610	{
2611	#ifdef PGM_DYNAMIC_RAM_ALLOC
2612	PVM pVM = ((CPUState *)env)->pVM;
2613	RTHCUINTPTR HCVirt = (RTHCUINTPTR)addr;
2614	uint32_t idx = (HCVirt >> PGM_DYNAMIC_CHUNK_SHIFT);
2615	RTHCUINTPTR off;
2616	RTUINT i;
2617
2618	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1;
2619
2620	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk1
2621	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2622	{
2623	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off));
2624	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys1 + off;
2625	}
2626
2627	off = HCVirt - pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2;
2628	if ( pVM->rem.s.paHCVirtToGCPhys[idx].pChunk2
2629	&& off < PGM_DYNAMIC_CHUNK_SIZE)
2630	{
2631	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off));
2632	return pVM->rem.s.paHCVirtToGCPhys[idx].GCPhys2 + off;
2633	}
2634
2635	/* Must be externally registered RAM/ROM range */
2636	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2637	{
2638	uint32_t off = HCVirt - pVM->rem.s.aPhysReg[i].HCVirt;
2639	if (off < pVM->rem.s.aPhysReg[i].cb)
2640	{
2641	Log(("remR3HCVirt2GCPhys %x -> %x\n", addr, pVM->rem.s.aPhysReg[i].GCPhys + off));
2642	return pVM->rem.s.aPhysReg[i].GCPhys + off;
2643	}
2644	}
2645	AssertReleaseMsgFailed(("No translation for physical address %VHv???\n", addr));
2646	return 0;
2647	#else
2648	return (target_ulong)addr - (target_ulong)phys_ram_base;
2649	#endif
2650	}
2651
2652	/**
2653	* Grows dynamically allocated guest RAM.
2654	* Will raise a fatal error if the operation fails.
2655	*
2656	* @param physaddr The physical address.
2657	*/
2658	void remR3GrowDynRange(unsigned long physaddr)
2659	{
2660	int rc;
2661	PVM pVM = cpu_single_env->pVM;
2662
2663	Log(("remR3GrowDynRange %VGp\n", physaddr));
2664	rc = PGM3PhysGrowRange(pVM, (RTGCPHYS)physaddr);
2665	if (VBOX_SUCCESS(rc))
2666	return;
2667
2668	LogRel(("\nUnable to allocate guest RAM chunk at %VGp\n", physaddr));
2669	cpu_abort(cpu_single_env, "Unable to allocate guest RAM chunk at %VGp\n", physaddr);
2670	AssertFatalFailed();
2671	}
2672
2673	/**
2674	* Notification about a successful MMR3PhysRomRegister() call.
2675	*
2676	* @param pVM VM handle.
2677	* @param GCPhys The physical address of the ROM.
2678	* @param cb The size of the ROM.
2679	* @param pvCopy Pointer to the ROM copy.
2680	*/
2681	REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy)
2682	{
2683	#ifdef PGM_DYNAMIC_RAM_ALLOC
2684	uint32_t i;
2685	#endif
2686	Log(("REMR3NotifyPhysRomRegister: GCPhys=%VGp cb=%d pvCopy=%p\n", GCPhys, cb, pvCopy));
2687	VM_ASSERT_EMT(pVM);
2688
2689	/*
2690	* Validate input - we trust the caller.
2691	*/
2692	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2693	Assert(cb);
2694	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2695	Assert(pvCopy);
2696	Assert(RT_ALIGN_P(pvCopy, PAGE_SIZE) == pvCopy);
2697
2698	/*
2699	* Register the rom.
2700	*/
2701	#ifdef PGM_DYNAMIC_RAM_ALLOC
2702	cpu_register_physical_memory(GCPhys, cb, GCPhys \| IO_MEM_ROM);
2703	AssertRelease(pVM->rem.s.cPhysRegistrations < REM_MAX_PHYS_REGISTRATIONS);
2704	for (i=0;i<pVM->rem.s.cPhysRegistrations;i++)
2705	{
2706	if (pVM->rem.s.aPhysReg[i].GCPhys == GCPhys)
2707	{
2708	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2709	pVM->rem.s.aPhysReg[i].cb = cb;
2710	break;
2711	}
2712	}
2713	if (i == pVM->rem.s.cPhysRegistrations)
2714	{
2715	pVM->rem.s.aPhysReg[i].GCPhys = GCPhys;
2716	pVM->rem.s.aPhysReg[i].HCVirt = (RTHCUINTPTR)pvCopy;
2717	pVM->rem.s.aPhysReg[i].cb = cb;
2718	pVM->rem.s.cPhysRegistrations++;
2719	}
2720	#else
2721	AssertRelease(phys_ram_base);
2722	cpu_register_physical_memory(GCPhys, cb, ((uintptr_t)pvCopy - (uintptr_t)phys_ram_base) \| IO_MEM_ROM);
2723	#endif
2724	Log2(("%.64Vhxd\n", (char *)pvCopy + cb - 64));
2725	}
2726
2727
2728	/**
2729	* Notification about a successful MMR3PhysRegister() call.
2730	*
2731	* @param pVM VM Handle.
2732	* @param GCPhys Start physical address.
2733	* @param cb The size of the range.
2734	*/
2735	REMR3DECL(void) REMR3NotifyPhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cb)
2736	{
2737	LogFlow(("REMR3NotifyPhysReserve: GCPhys=%VGp cb=%d\n", GCPhys, cb));
2738	VM_ASSERT_EMT(pVM);
2739
2740	/*
2741	* Validate input - we trust the caller.
2742	*/
2743	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2744	Assert(cb);
2745	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb);
2746
2747	/*
2748	* Unassigning the memory.
2749	*/
2750	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2751	}
2752
2753
2754	/**
2755	* Notification about a successful PGMR3HandlerPhysicalRegister() call.
2756	*
2757	* @param pVM VM Handle.
2758	* @param enmType Handler type.
2759	* @param GCPhys Handler range address.
2760	* @param cb Size of the handler range.
2761	* @param fHasHCHandler Set if the handler has a HC callback function.
2762	*
2763	* @remark MMR3PhysRomRegister assumes that this function will not apply the
2764	* Handler memory type to memory which has no HC handler.
2765	*/
2766	REMR3DECL(void) REMR3NotifyHandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler)
2767	{
2768	LogFlow(("REMR3NotifyHandlerPhysicalRegister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d\n",
2769	enmType, GCPhys, cb, fHasHCHandler));
2770	VM_ASSERT_EMT(pVM);
2771	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2772	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2773
2774	if (pVM->rem.s.cHandlerNotifications)
2775	REMR3ReplayHandlerNotifications(pVM);
2776
2777	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2778	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iMMIOMemType);
2779	else if (fHasHCHandler)
2780	cpu_register_physical_memory(GCPhys, cb, pVM->rem.s.iHandlerMemType);
2781	}
2782
2783
2784	/**
2785	* Notification about a successful PGMR3HandlerPhysicalDeregister() operation.
2786	*
2787	* @param pVM VM Handle.
2788	* @param enmType Handler type.
2789	* @param GCPhys Handler range address.
2790	* @param cb Size of the handler range.
2791	* @param fHasHCHandler Set if the handler has a HC callback function.
2792	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2793	*/
2794	REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2795	{
2796	LogFlow(("REMR3NotifyHandlerPhysicalDeregister: enmType=%d GCPhys=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p RAM=%08x\n",
2797	enmType, GCPhys, cb, fHasHCHandler, pvHCPtr, MMR3PhysGetRamSize(pVM)));
2798	VM_ASSERT_EMT(pVM);
2799
2800	if (pVM->rem.s.cHandlerNotifications)
2801	REMR3ReplayHandlerNotifications(pVM);
2802
2803	if (enmType == PGMPHYSHANDLERTYPE_MMIO)
2804	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2805	else if (fHasHCHandler)
2806	{
2807	if (!pvHCPtr)
2808	{
2809	Assert(GCPhys > MMR3PhysGetRamSize(pVM));
2810	cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
2811	}
2812	else
2813	{
2814	/* This is not prefect, but it'll do for PD monitoring... */
2815	Assert(cb == PAGE_SIZE);
2816	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2817	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2818	#ifdef PGM_DYNAMIC_RAM_ALLOC
2819	cpu_register_physical_memory(GCPhys, cb, GCPhys);
2820	#else
2821	cpu_register_physical_memory(GCPhys, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2822	#endif
2823	}
2824	}
2825	}
2826
2827
2828	/**
2829	* Notification about a successful PGMR3HandlerPhysicalModify() call.
2830	*
2831	* @param pVM VM Handle.
2832	* @param enmType Handler type.
2833	* @param GCPhysOld Old handler range address.
2834	* @param GCPhysNew New handler range address.
2835	* @param cb Size of the handler range.
2836	* @param fHasHCHandler Set if the handler has a HC callback function.
2837	* @param pvHCPtr The HC virtual address corresponding to GCPhys if available.
2838	*/
2839	REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, void *pvHCPtr)
2840	{
2841	LogFlow(("REMR3NotifyHandlerPhysicalModify: enmType=%d GCPhysOld=%VGp GCPhysNew=%VGp cb=%d fHasHCHandler=%d pvHCPtr=%p\n",
2842	enmType, GCPhysOld, GCPhysNew, cb, fHasHCHandler, pvHCPtr));
2843	VM_ASSERT_EMT(pVM);
2844	AssertReleaseMsg(enmType != PGMPHYSHANDLERTYPE_MMIO, ("enmType=%d\n", enmType));
2845
2846	if (pVM->rem.s.cHandlerNotifications)
2847	REMR3ReplayHandlerNotifications(pVM);
2848
2849	if (fHasHCHandler)
2850	{
2851	/*
2852	* Reset the old page.
2853	*/
2854	if (!pvHCPtr)
2855	cpu_register_physical_memory(GCPhysOld, cb, IO_MEM_UNASSIGNED);
2856	else
2857	{
2858	/* This is not prefect, but it'll do for PD monitoring... */
2859	Assert(cb == PAGE_SIZE);
2860	Assert(RT_ALIGN_T(GCPhysOld, PAGE_SIZE, RTGCPHYS) == GCPhysOld);
2861	Assert(remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr) < MMR3PhysGetRamSize(pVM));
2862	#ifdef PGM_DYNAMIC_RAM_ALLOC
2863	cpu_register_physical_memory(GCPhysOld, cb, GCPhysOld);
2864	#else
2865	cpu_register_physical_memory(GCPhysOld, cb, remR3HCVirt2GCPhys(cpu_single_env, pvHCPtr));
2866	#endif
2867	}
2868
2869	/*
2870	* Update the new page.
2871	*/
2872	Assert(RT_ALIGN_T(GCPhysNew, PAGE_SIZE, RTGCPHYS) == GCPhysNew);
2873	Assert(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb);
2874	cpu_register_physical_memory(GCPhysNew, cb, pVM->rem.s.iHandlerMemType);
2875	}
2876	}
2877
2878
2879	/**
2880	* Checks if we're handling access to this page or not.
2881	*
2882	* @returns true if we're trapping access.
2883	* @returns false if we aren't.
2884	* @param pVM The VM handle.
2885	* @param GCPhys The physical address.
2886	*
2887	* @remark This function will only work correctly in VBOX_STRICT builds!
2888	*/
2889	REMDECL(bool) REMR3IsPageAccessHandled(PVM pVM, RTGCPHYS GCPhys)
2890	{
2891	#ifdef VBOX_STRICT
2892	if (pVM->rem.s.cHandlerNotifications)
2893	REMR3ReplayHandlerNotifications(pVM);
2894
2895	unsigned long off = get_phys_page_offset(GCPhys);
2896	return (off & PAGE_OFFSET_MASK) == pVM->rem.s.iHandlerMemType
2897	\|\| (off & PAGE_OFFSET_MASK) == pVM->rem.s.iMMIOMemType
2898	\|\| (off & PAGE_OFFSET_MASK) == IO_MEM_ROM;
2899	#else
2900	return false;
2901	#endif
2902	}
2903
2904
2905	/**
2906	* Deals with a rare case in get_phys_addr_code where the code
2907	* is being monitored.
2908	*
2909	* It could also be an MMIO page, in which case we will raise a fatal error.
2910	*
2911	* @returns The physical address corresponding to addr.
2912	* @param env The cpu environment.
2913	* @param addr The virtual address.
2914	* @param pTLBEntry The TLB entry.
2915	*/
2916	target_ulong remR3PhysGetPhysicalAddressCode(CPUState env, target_ulong addr, CPUTLBEntry pTLBEntry)
2917	{
2918	PVM pVM = env->pVM;
2919	if ((pTLBEntry->address & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
2920	{
2921	target_ulong ret = pTLBEntry->addend + addr;
2922	AssertMsg2("remR3PhysGetPhysicalAddressCode: addr=%VGv address=%VGv addend=%VGp ret=%VGp\n",
2923	(RTGCPTR)addr, (RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, ret);
2924	return ret;
2925	}
2926	LogRel(("\nTrying to execute code with memory type address=%VGv addend=%VGp at %VGv! (iHandlerMemType=%#x iMMIOMemType=%#x)\n"
2927	"*** handlers\n",
2928	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType));
2929	DBGFR3Info(pVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
2930	LogRel(("*** mmio\n"));
2931	DBGFR3Info(pVM, "mmio", NULL, DBGFR3InfoLogRelHlp());
2932	LogRel(("*** phys\n"));
2933	DBGFR3Info(pVM, "phys", NULL, DBGFR3InfoLogRelHlp());
2934	cpu_abort(env, "Trying to execute code with memory type address=%VGv addend=%VGp at %VGv. (iHandlerMemType=%#x iMMIOMemType=%#x)\n",
2935	(RTGCPTR)pTLBEntry->address, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType);
2936	AssertFatalFailed();
2937	}
2938
2939	/**
2940	* Read guest RAM and ROM.
2941	*
2942	* @param pbSrcPhys The source address. Relative to guest RAM.
2943	* @param pvDst The destination address.
2944	* @param cb Number of bytes
2945	*/
2946	void remR3PhysReadBytes(uint8_t pbSrcPhys, void pvDst, unsigned cb)
2947	{
2948	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2949
2950	/*
2951	* Calc the physical address ('off') and check that it's within the RAM.
2952	* ROM is accessed this way, even if it's not part of the RAM.
2953	*/
2954	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2955	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2956	if (off < (uintptr_t)phys_ram_size)
2957	PGMPhysRead(cpu_single_env->pVM, (RTGCPHYS)off, pvDst, cb);
2958	else
2959	{
2960	/* ROM range outside physical RAM, HC address passed directly */
2961	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2962	memcpy(pvDst, pbSrcPhys, cb);
2963	}
2964	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2965	}
2966
2967	/** @todo r=bird: s/Byte/U8/ s/Word/U16/ s/Dword/U32/, see MMIO and other functions.
2968	* It could be an idea to inline these wrapper functions... */
2969
2970	/**
2971	* Read guest RAM and ROM.
2972	*
2973	* @param pbSrcPhys The source address. Relative to guest RAM.
2974	*/
2975	uint8_t remR3PhysReadUByte(uint8_t *pbSrcPhys)
2976	{
2977	uint8_t val;
2978
2979	STAM_PROFILE_ADV_START(&gStatMemRead, a);
2980
2981	/*
2982	* Calc the physical address ('off') and check that it's within the RAM.
2983	* ROM is accessed this way, even if it's not part of the RAM.
2984	*/
2985	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
2986	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
2987	if (off < (uintptr_t)phys_ram_size)
2988	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
2989	else
2990	{
2991	/* ROM range outside physical RAM, HC address passed directly */
2992	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
2993	val = *pbSrcPhys;
2994	}
2995	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
2996	return val;
2997	}
2998
2999	/**
3000	* Read guest RAM and ROM.
3001	*
3002	* @param pbSrcPhys The source address. Relative to guest RAM.
3003	*/
3004	int8_t remR3PhysReadSByte(uint8_t *pbSrcPhys)
3005	{
3006	int8_t val;
3007
3008	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3009
3010	/*
3011	* Calc the physical address ('off') and check that it's within the RAM.
3012	* ROM is accessed this way, even if it's not part of the RAM.
3013	*/
3014	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3015	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3016	if (off < (uintptr_t)phys_ram_size)
3017	val = PGMR3PhysReadByte(cpu_single_env->pVM, (RTGCPHYS)off);
3018	else
3019	{
3020	/* ROM range outside physical RAM, HC address passed directly */
3021	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3022	val = (int8_t )pbSrcPhys;
3023	}
3024	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3025	return val;
3026	}
3027
3028	/**
3029	* Read guest RAM and ROM.
3030	*
3031	* @param pbSrcPhys The source address. Relative to guest RAM.
3032	*/
3033	uint16_t remR3PhysReadUWord(uint8_t *pbSrcPhys)
3034	{
3035	uint16_t val;
3036
3037	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3038
3039	/*
3040	* Calc the physical address ('off') and check that it's within the RAM.
3041	* ROM is accessed this way, even if it's not part of the RAM.
3042	*/
3043	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3044	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3045	if (off < (uintptr_t)phys_ram_size)
3046	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3047	else
3048	{
3049	/* ROM range outside physical RAM, HC address passed directly */
3050	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3051	val = (uint16_t )pbSrcPhys;
3052	}
3053	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3054	return val;
3055	}
3056
3057	/**
3058	* Read guest RAM and ROM.
3059	*
3060	* @param pbSrcPhys The source address. Relative to guest RAM.
3061	*/
3062	int16_t remR3PhysReadSWord(uint8_t *pbSrcPhys)
3063	{
3064	int16_t val;
3065
3066	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3067
3068	/*
3069	* Calc the physical address ('off') and check that it's within the RAM.
3070	* ROM is accessed this way, even if it's not part of the RAM.
3071	*/
3072	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3073	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3074	if (off < (uintptr_t)phys_ram_size)
3075	val = PGMR3PhysReadWord(cpu_single_env->pVM, (RTGCPHYS)off);
3076	else
3077	{
3078	/* ROM range outside physical RAM, HC address passed directly */
3079	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3080	val = (int16_t )pbSrcPhys;
3081	}
3082	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3083	return val;
3084	}
3085
3086	/**
3087	* Read guest RAM and ROM.
3088	*
3089	* @param pbSrcPhys The source address. Relative to guest RAM.
3090	*/
3091	uint32_t remR3PhysReadULong(uint8_t *pbSrcPhys)
3092	{
3093	uint32_t val;
3094
3095	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3096
3097	/*
3098	* Calc the physical address ('off') and check that it's within the RAM.
3099	* ROM is accessed this way, even if it's not part of the RAM.
3100	*/
3101	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3102	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3103	if (off < (uintptr_t)phys_ram_size)
3104	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3105	else
3106	{
3107	/* ROM range outside physical RAM, HC address passed directly */
3108	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3109	val = (uint32_t )pbSrcPhys;
3110	}
3111	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3112	return val;
3113	}
3114
3115	/**
3116	* Read guest RAM and ROM.
3117	*
3118	* @param pbSrcPhys The source address. Relative to guest RAM.
3119	*/
3120	int32_t remR3PhysReadSLong(uint8_t *pbSrcPhys)
3121	{
3122	int32_t val;
3123
3124	STAM_PROFILE_ADV_START(&gStatMemRead, a);
3125
3126	/*
3127	* Calc the physical address ('off') and check that it's within the RAM.
3128	* ROM is accessed this way, even if it's not part of the RAM.
3129	*/
3130	/** @todo This is rather ugly, but there's no other way when we don't wish to touch many other files. */
3131	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbSrcPhys);
3132	if (off < (uintptr_t)phys_ram_size)
3133	val = PGMR3PhysReadDword(cpu_single_env->pVM, (RTGCPHYS)off);
3134	else
3135	{
3136	/* ROM range outside physical RAM, HC address passed directly */
3137	Log4(("remR3PhysReadBytes ROM: %p\n", pbSrcPhys));
3138	val = (int32_t )pbSrcPhys;
3139	}
3140	STAM_PROFILE_ADV_STOP(&gStatMemRead, a);
3141	return val;
3142	}
3143
3144	/**
3145	* Write guest RAM.
3146	*
3147	* @param pbDstPhys The destination address. Relative to guest RAM.
3148	* @param pvSrc The source address.
3149	* @param cb Number of bytes to write
3150	*/
3151	void remR3PhysWriteBytes(uint8_t pbDstPhys, const void pvSrc, unsigned cb)
3152	{
3153	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3154	/*
3155	* Calc the physical address ('off') and check that it's within the RAM.
3156	*/
3157	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3158	if (off < (uintptr_t)phys_ram_size)
3159	PGMPhysWrite(cpu_single_env->pVM, (RTGCPHYS)off, pvSrc, cb);
3160	else
3161	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, cb));
3162	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3163	}
3164
3165
3166	/**
3167	* Write guest RAM.
3168	*
3169	* @param pbDstPhys The destination address. Relative to guest RAM.
3170	* @param val Value
3171	*/
3172	void remR3PhysWriteByte(uint8_t *pbDstPhys, uint8_t val)
3173	{
3174	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3175	/*
3176	* Calc the physical address ('off') and check that it's within the RAM.
3177	*/
3178	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3179	if (off < (uintptr_t)phys_ram_size)
3180	PGMR3PhysWriteByte(cpu_single_env->pVM, (RTGCPHYS)off, val);
3181	else
3182	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 1));
3183	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3184	}
3185
3186	/**
3187	* Write guest RAM.
3188	*
3189	* @param pbDstPhys The destination address. Relative to guest RAM.
3190	* @param val Value
3191	*/
3192	void remR3PhysWriteWord(uint8_t *pbDstPhys, uint16_t val)
3193	{
3194	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3195	/*
3196	* Calc the physical address ('off') and check that it's within the RAM.
3197	*/
3198	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3199	if (off < (uintptr_t)phys_ram_size)
3200	PGMR3PhysWriteWord(cpu_single_env->pVM, (RTGCPHYS)off, val);
3201	else
3202	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 2));
3203	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3204	}
3205
3206	/**
3207	* Write guest RAM.
3208	*
3209	* @param pbDstPhys The destination address. Relative to guest RAM.
3210	* @param val Value
3211	*/
3212	void remR3PhysWriteDword(uint8_t *pbDstPhys, uint32_t val)
3213	{
3214	STAM_PROFILE_ADV_START(&gStatMemWrite, a);
3215	/*
3216	* Calc the physical address ('off') and check that it's within the RAM.
3217	*/
3218	uintptr_t off = remR3HCVirt2GCPhys(cpu_single_env, pbDstPhys);
3219	if (off < (uintptr_t)phys_ram_size)
3220	PGMR3PhysWriteDword(cpu_single_env->pVM, (RTGCPHYS)off, val);
3221	else
3222	AssertMsgFailed(("pbDstPhys=%p off=%p cb=%d\n", pbDstPhys, off, 4));
3223	STAM_PROFILE_ADV_STOP(&gStatMemWrite, a);
3224	}
3225
3226
3227
3228	#undef LOG_GROUP
3229	#define LOG_GROUP LOG_GROUP_REM_MMIO
3230
3231	/** Read MMIO memory. */
3232	static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys)
3233	{
3234	uint32_t u32 = 0;
3235	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1);
3236	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3237	Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32));
3238	return u32;
3239	}
3240
3241	/** Read MMIO memory. */
3242	static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys)
3243	{
3244	uint32_t u32 = 0;
3245	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2);
3246	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3247	Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32));
3248	return u32;
3249	}
3250
3251	/** Read MMIO memory. */
3252	static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys)
3253	{
3254	uint32_t u32 = 0;
3255	int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4);
3256	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3257	Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32));
3258	return u32;
3259	}
3260
3261	/** Write to MMIO memory. */
3262	static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3263	{
3264	Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3265	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1);
3266	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3267	}
3268
3269	/** Write to MMIO memory. */
3270	static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3271	{
3272	Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3273	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2);
3274	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3275	}
3276
3277	/** Write to MMIO memory. */
3278	static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3279	{
3280	Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3281	int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4);
3282	AssertMsg(rc == VINF_SUCCESS, ("rc=%Vrc\n", rc)); NOREF(rc);
3283	}
3284
3285
3286	#undef LOG_GROUP
3287	#define LOG_GROUP LOG_GROUP_REM_HANDLER
3288
3289	/* !!!WARNING!!! This is extremely hackish right now, we assume it's only for LFB access! !!!WARNING!!! */
3290
3291	static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys)
3292	{
3293	Log2(("remR3HandlerReadU8: GCPhys=%VGp\n", GCPhys));
3294	uint8_t u8;
3295	PGMPhysRead((PVM)pvVM, GCPhys, &u8, sizeof(u8));
3296	return u8;
3297	}
3298
3299	static uint32_t remR3HandlerReadU16(void *pvVM, target_phys_addr_t GCPhys)
3300	{
3301	Log2(("remR3HandlerReadU16: GCPhys=%VGp\n", GCPhys));
3302	uint16_t u16;
3303	PGMPhysRead((PVM)pvVM, GCPhys, &u16, sizeof(u16));
3304	return u16;
3305	}
3306
3307	static uint32_t remR3HandlerReadU32(void *pvVM, target_phys_addr_t GCPhys)
3308	{
3309	Log2(("remR3HandlerReadU32: GCPhys=%VGp\n", GCPhys));
3310	uint32_t u32;
3311	PGMPhysRead((PVM)pvVM, GCPhys, &u32, sizeof(u32));
3312	return u32;
3313	}
3314
3315	static void remR3HandlerWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3316	{
3317	Log2(("remR3HandlerWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3318	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint8_t));
3319	}
3320
3321	static void remR3HandlerWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3322	{
3323	Log2(("remR3HandlerWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3324	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint16_t));
3325	}
3326
3327	static void remR3HandlerWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32)
3328	{
3329	Log2(("remR3HandlerWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32));
3330	PGMPhysWrite((PVM)pvVM, GCPhys, &u32, sizeof(uint32_t));
3331	}
3332
3333	/* -+- disassembly -+- */
3334
3335	#undef LOG_GROUP
3336	#define LOG_GROUP LOG_GROUP_REM_DISAS
3337
3338
3339	/**
3340	* Enables or disables singled stepped disassembly.
3341	*
3342	* @returns VBox status code.
3343	* @param pVM VM handle.
3344	* @param fEnable To enable set this flag, to disable clear it.
3345	*/
3346	static DECLCALLBACK(int) remR3DisasEnableStepping(PVM pVM, bool fEnable)
3347	{
3348	LogFlow(("remR3DisasEnableStepping: fEnable=%d\n", fEnable));
3349	VM_ASSERT_EMT(pVM);
3350
3351	if (fEnable)
3352	pVM->rem.s.Env.state \|= CPU_EMULATE_SINGLE_STEP;
3353	else
3354	pVM->rem.s.Env.state &= ~CPU_EMULATE_SINGLE_STEP;
3355	return VINF_SUCCESS;
3356	}
3357
3358
3359	/**
3360	* Enables or disables singled stepped disassembly.
3361	*
3362	* @returns VBox status code.
3363	* @param pVM VM handle.
3364	* @param fEnable To enable set this flag, to disable clear it.
3365	*/
3366	REMR3DECL(int) REMR3DisasEnableStepping(PVM pVM, bool fEnable)
3367	{
3368	PVMREQ pReq;
3369	int rc;
3370
3371	LogFlow(("REMR3DisasEnableStepping: fEnable=%d\n", fEnable));
3372	if (VM_IS_EMT(pVM))
3373	return remR3DisasEnableStepping(pVM, fEnable);
3374
3375	rc = VMR3ReqCall(pVM, &pReq, RT_INDEFINITE_WAIT, (PFNRT)remR3DisasEnableStepping, 2, pVM, fEnable);
3376	AssertRC(rc);
3377	if (VBOX_SUCCESS(rc))
3378	rc = pReq->iStatus;
3379	VMR3ReqFree(pReq);
3380	return rc;
3381	}
3382
3383
3384	#ifdef VBOX_WITH_DEBUGGER
3385	/**
3386	* External Debugger Command: .remstep [on\|off\|1\|0]
3387	*/
3388	static DECLCALLBACK(int) remR3CmdDisasEnableStepping(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3389	{
3390	bool fEnable;
3391	int rc;
3392
3393	/* print status */
3394	if (cArgs == 0)
3395	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "DisasStepping is %s\n",
3396	pVM->rem.s.Env.state & CPU_EMULATE_SINGLE_STEP ? "enabled" : "disabled");
3397
3398	/* convert the argument and change the mode. */
3399	rc = pCmdHlp->pfnVarToBool(pCmdHlp, &paArgs[0], &fEnable);
3400	if (VBOX_FAILURE(rc))
3401	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "boolean conversion failed!\n");
3402	rc = REMR3DisasEnableStepping(pVM, fEnable);
3403	if (VBOX_FAILURE(rc))
3404	return pCmdHlp->pfnVBoxError(pCmdHlp, rc, "REMR3DisasEnableStepping failed!\n");
3405	return rc;
3406	}
3407	#endif
3408
3409
3410	/**
3411	* Disassembles n instructions and prints them to the log.
3412	*
3413	* @returns Success indicator.
3414	* @param env Pointer to the recompiler CPU structure.
3415	* @param f32BitCode Indicates that whether or not the code should
3416	* be disassembled as 16 or 32 bit. If -1 the CS
3417	* selector will be inspected.
3418	* @param nrInstructions Nr of instructions to disassemble
3419	* @param pszPrefix
3420	* @remark not currently used for anything but ad-hoc debugging.
3421	*/
3422	bool remR3DisasBlock(CPUState env, int f32BitCode, int nrInstructions, char pszPrefix)
3423	{
3424	int i;
3425
3426	/*
3427	* Determin 16/32 bit mode.
3428	*/
3429	if (f32BitCode == -1)
3430	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3431
3432	/*
3433	* Convert cs:eip to host context address.
3434	* We don't care to much about cross page correctness presently.
3435	*/
3436	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3437	void *pvPC;
3438	if (f32BitCode && (env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3439	{
3440	/* convert eip to physical address. */
3441	int rc = PGMPhysGCPtr2HCPtrByGstCR3(env->pVM,
3442	GCPtrPC,
3443	env->cr[3],
3444	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE), /** @todo add longmode flag */
3445	&pvPC);
3446	if (VBOX_FAILURE(rc))
3447	{
3448	if (!PATMIsPatchGCAddr(env->pVM, GCPtrPC))
3449	return false;
3450	pvPC = (char *)PATMR3QueryPatchMemHC(env->pVM, NULL)
3451	+ (GCPtrPC - PATMR3QueryPatchMemGC(env->pVM, NULL));
3452	}
3453	}
3454	else
3455	{
3456	/* physical address */
3457	int rc = PGMPhysGCPhys2HCPtr(env->pVM, (RTGCPHYS)GCPtrPC, nrInstructions*16, &pvPC);
3458	if (VBOX_FAILURE(rc))
3459	return false;
3460	}
3461
3462	/*
3463	* Disassemble.
3464	*/
3465	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3466	DISCPUSTATE Cpu;
3467	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3468	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3469	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3470	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3471	//Cpu.dwUserData[2] = GCPtrPC;
3472
3473	for (i=0;i<nrInstructions;i++)
3474	{
3475	char szOutput[256];
3476	uint32_t cbOp;
3477	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3478	return false;
3479	if (pszPrefix)
3480	Log(("%s: %s", pszPrefix, szOutput));
3481	else
3482	Log(("%s", szOutput));
3483
3484	pvPC += cbOp;
3485	}
3486	return true;
3487	}
3488
3489
3490	/** @todo need to test the new code, using the old code in the mean while. */
3491	#define USE_OLD_DUMP_AND_DISASSEMBLY
3492
3493	/**
3494	* Disassembles one instruction and prints it to the log.
3495	*
3496	* @returns Success indicator.
3497	* @param env Pointer to the recompiler CPU structure.
3498	* @param f32BitCode Indicates that whether or not the code should
3499	* be disassembled as 16 or 32 bit. If -1 the CS
3500	* selector will be inspected.
3501	* @param pszPrefix
3502	*/
3503	bool remR3DisasInstr(CPUState env, int f32BitCode, char pszPrefix)
3504	{
3505	#ifdef USE_OLD_DUMP_AND_DISASSEMBLY
3506	PVM pVM = env->pVM;
3507
3508	/*
3509	* Determin 16/32 bit mode.
3510	*/
3511	if (f32BitCode == -1)
3512	f32BitCode = !!(env->segs[R_CS].flags & X86_DESC_DB); /** @todo is this right?!!?!?!?!? */
3513
3514	/*
3515	* Log registers
3516	*/
3517	if (LogIs2Enabled())
3518	{
3519	remR3StateUpdate(pVM);
3520	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3521	}
3522
3523	/*
3524	* Convert cs:eip to host context address.
3525	* We don't care to much about cross page correctness presently.
3526	*/
3527	RTGCPTR GCPtrPC = env->segs[R_CS].base + env->eip;
3528	void *pvPC;
3529	if ((env->cr[0] & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG))
3530	{
3531	/* convert eip to physical address. */
3532	int rc = PGMPhysGCPtr2HCPtrByGstCR3(pVM,
3533	GCPtrPC,
3534	env->cr[3],
3535	env->cr[4] & (X86_CR4_PSE \| X86_CR4_PAE),
3536	&pvPC);
3537	if (VBOX_FAILURE(rc))
3538	{
3539	if (!PATMIsPatchGCAddr(pVM, GCPtrPC))
3540	return false;
3541	pvPC = (char *)PATMR3QueryPatchMemHC(pVM, NULL)
3542	+ (GCPtrPC - PATMR3QueryPatchMemGC(pVM, NULL));
3543	}
3544	}
3545	else
3546	{
3547
3548	/* physical address */
3549	int rc = PGMPhysGCPhys2HCPtr(pVM, (RTGCPHYS)GCPtrPC, 16, &pvPC);
3550	if (VBOX_FAILURE(rc))
3551	return false;
3552	}
3553
3554	/*
3555	* Disassemble.
3556	*/
3557	RTINTPTR off = env->eip - (RTINTPTR)pvPC;
3558	DISCPUSTATE Cpu;
3559	Cpu.mode = f32BitCode ? CPUMODE_32BIT : CPUMODE_16BIT;
3560	Cpu.pfnReadBytes = NULL; /** @todo make cs:eip reader for the disassembler. */
3561	//Cpu.dwUserData[0] = (uintptr_t)pVM;
3562	//Cpu.dwUserData[1] = (uintptr_t)pvPC;
3563	//Cpu.dwUserData[2] = GCPtrPC;
3564	char szOutput[256];
3565	uint32_t cbOp;
3566	if (!DISInstr(&Cpu, (uintptr_t)pvPC, off, &cbOp, &szOutput[0]))
3567	return false;
3568
3569	if (!f32BitCode)
3570	{
3571	if (pszPrefix)
3572	Log(("%s: %04X:%s", pszPrefix, env->segs[R_CS].selector, szOutput));
3573	else
3574	Log(("%04X:%s", env->segs[R_CS].selector, szOutput));
3575	}
3576	else
3577	{
3578	if (pszPrefix)
3579	Log(("%s: %s", pszPrefix, szOutput));
3580	else
3581	Log(("%s", szOutput));
3582	}
3583	return true;
3584
3585	#else /* !USE_OLD_DUMP_AND_DISASSEMBLY */
3586	PVM pVM = env->pVM;
3587	const bool fLog = LogIsEnabled();
3588	const bool fLog2 = LogIs2Enabled();
3589	int rc = VINF_SUCCESS;
3590
3591	/*
3592	* Don't bother if there ain't any log output to do.
3593	*/
3594	if (!fLog && !fLog2)
3595	return true;
3596
3597	/*
3598	* Update the state so DBGF reads the correct register values.
3599	*/
3600	remR3StateUpdate(pVM);
3601
3602	/*
3603	* Log registers if requested.
3604	*/
3605	if (!fLog2)
3606	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
3607
3608	/*
3609	* Disassemble to log.
3610	*/
3611	if (fLog)
3612	rc = DBGFR3DisasInstrCurrentLogInternal(pVM, pszPrefix);
3613
3614	return VBOX_SUCCESS(rc);
3615	#endif
3616	}
3617
3618
3619	/**
3620	* Disassemble recompiled code.
3621	*
3622	* @param phFileIgnored Ignored, logfile usually.
3623	* @param pvCode Pointer to the code block.
3624	* @param cb Size of the code block.
3625	*/
3626	void disas(FILE phFileIgnored, void pvCode, unsigned long cb)
3627	{
3628	if (LogIs2Enabled())
3629	{
3630	unsigned off = 0;
3631	char szOutput[256];
3632	DISCPUSTATE Cpu = {0};
3633	Cpu.mode = CPUMODE_32BIT;
3634
3635	RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
3636	while (off < cb)
3637	{
3638	uint32_t cbInstr;
3639	if (DISInstr(&Cpu, (uintptr_t)pvCode + off, 0, &cbInstr, szOutput))
3640	RTLogPrintf("%s", szOutput);
3641	else
3642	{
3643	RTLogPrintf("disas error\n");
3644	cbInstr = 1;
3645	}
3646	off += cbInstr;
3647	}
3648	}
3649	NOREF(phFileIgnored);
3650	}
3651
3652
3653	/**
3654	* Disassemble guest code.
3655	*
3656	* @param phFileIgnored Ignored, logfile usually.
3657	* @param uCode The guest address of the code to disassemble. (flat?)
3658	* @param cb Number of bytes to disassemble.
3659	* @param fFlags Flags, probably something which tells if this is 16, 32 or 64 bit code.
3660	*/
3661	void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
3662	{
3663	if (LogIs2Enabled())
3664	{
3665	PVM pVM = cpu_single_env->pVM;
3666
3667	/*
3668	* Update the state so DBGF reads the correct register values (flags).
3669	*/
3670	remR3StateUpdate(pVM);
3671
3672	/*
3673	* Do the disassembling.
3674	*/
3675	RTLogPrintf("Guest Code: PC=%VGp #VGp (%VGp) bytes fFlags=%d\n", uCode, cb, cb, fFlags);
3676	RTSEL cs = cpu_single_env->segs[R_CS].selector;
3677	RTGCUINTPTR eip = uCode - cpu_single_env->segs[R_CS].base;
3678	for (;;)
3679	{
3680	char szBuf[256];
3681	size_t cbInstr;
3682	int rc = DBGFR3DisasInstrEx(pVM,
3683	cs,
3684	eip,
3685	0,
3686	szBuf, sizeof(szBuf),
3687	&cbInstr);
3688	if (VBOX_SUCCESS(rc))
3689	RTLogPrintf("%VGp %s\n", uCode, szBuf);
3690	else
3691	{
3692	RTLogPrintf("%VGp %04x:%VGp: %s\n", uCode, cs, eip, szBuf);
3693	cbInstr = 1;
3694	}
3695
3696	/* next */
3697	if (cb <= cbInstr)
3698	break;
3699	cb -= cbInstr;
3700	uCode += cbInstr;
3701	eip += cbInstr;
3702	}
3703	}
3704	NOREF(phFileIgnored);
3705	}
3706
3707
3708	/**
3709	* Looks up a guest symbol.
3710	*
3711	* @returns Pointer to symbol name. This is a static buffer.
3712	* @param orig_addr The address in question.
3713	*/
3714	const char *lookup_symbol(target_ulong orig_addr)
3715	{
3716	RTGCINTPTR off = 0;
3717	DBGFSYMBOL Sym;
3718	PVM pVM = cpu_single_env->pVM;
3719	int rc = DBGFR3SymbolByAddr(pVM, orig_addr, &off, &Sym);
3720	if (VBOX_SUCCESS(rc))
3721	{
3722	static char szSym[sizeof(Sym.szName) + 48];
3723	if (!off)
3724	RTStrPrintf(szSym, sizeof(szSym), "%s\n", Sym.szName);
3725	else if (off > 0)
3726	RTStrPrintf(szSym, sizeof(szSym), "%s+%x\n", Sym.szName, off);
3727	else
3728	RTStrPrintf(szSym, sizeof(szSym), "%s-%x\n", Sym.szName, -off);
3729	return szSym;
3730	}
3731	return "<N/A>";
3732	}
3733
3734
3735	#undef LOG_GROUP
3736	#define LOG_GROUP LOG_GROUP_REM
3737
3738
3739	/* -+- FF notifications -+- */
3740
3741
3742	/**
3743	* Notification about a pending interrupt.
3744	*
3745	* @param pVM VM Handle.
3746	* @param u8Interrupt Interrupt
3747	* @thread The emulation thread.
3748	*/
3749	REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt)
3750	{
3751	Assert(pVM->rem.s.u32PendingInterrupt == REM_NO_PENDING_IRQ);
3752	pVM->rem.s.u32PendingInterrupt = u8Interrupt;
3753	}
3754
3755	/**
3756	* Notification about a pending interrupt.
3757	*
3758	* @returns Pending interrupt or REM_NO_PENDING_IRQ
3759	* @param pVM VM Handle.
3760	* @thread The emulation thread.
3761	*/
3762	REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM)
3763	{
3764	return pVM->rem.s.u32PendingInterrupt;
3765	}
3766
3767	/**
3768	* Notification about the interrupt FF being set.
3769	*
3770	* @param pVM VM Handle.
3771	* @thread The emulation thread.
3772	*/
3773	REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM)
3774	{
3775	LogFlow(("REMR3NotifyInterruptSet: fInRem=%d interrupts %s\n", pVM->rem.s.fInREM,
3776	(pVM->rem.s.Env.eflags & IF_MASK) && !(pVM->rem.s.Env.hflags & HF_INHIBIT_IRQ_MASK) ? "enabled" : "disabled"));
3777	if (pVM->rem.s.fInREM)
3778	{
3779	if (VM_IS_EMT(pVM))
3780	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3781	else
3782	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_HARD);
3783	}
3784	}
3785
3786
3787	/**
3788	* Notification about the interrupt FF being set.
3789	*
3790	* @param pVM VM Handle.
3791	* @thread The emulation thread.
3792	*/
3793	REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM)
3794	{
3795	LogFlow(("REMR3NotifyInterruptClear:\n"));
3796	VM_ASSERT_EMT(pVM);
3797	if (pVM->rem.s.fInREM)
3798	cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
3799	}
3800
3801
3802	/**
3803	* Notification about pending timer(s).
3804	*
3805	* @param pVM VM Handle.
3806	* @thread Any.
3807	*/
3808	REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM)
3809	{
3810	#ifndef DEBUG_bird
3811	LogFlow(("REMR3NotifyTimerPending: fInRem=%d\n", pVM->rem.s.fInREM));
3812	#endif
3813	if (pVM->rem.s.fInREM)
3814	{
3815	if (VM_IS_EMT(pVM))
3816	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3817	else
3818	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_TIMER);
3819	}
3820	}
3821
3822
3823	/**
3824	* Notification about pending DMA transfers.
3825	*
3826	* @param pVM VM Handle.
3827	* @thread Any.
3828	*/
3829	REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM)
3830	{
3831	LogFlow(("REMR3NotifyDmaPending: fInRem=%d\n", pVM->rem.s.fInREM));
3832	if (pVM->rem.s.fInREM)
3833	{
3834	if (VM_IS_EMT(pVM))
3835	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3836	else
3837	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_DMA);
3838	}
3839	}
3840
3841
3842	/**
3843	* Notification about pending timer(s).
3844	*
3845	* @param pVM VM Handle.
3846	* @thread Any.
3847	*/
3848	REMR3DECL(void) REMR3NotifyQueuePending(PVM pVM)
3849	{
3850	LogFlow(("REMR3NotifyQueuePending: fInRem=%d\n", pVM->rem.s.fInREM));
3851	if (pVM->rem.s.fInREM)
3852	{
3853	if (VM_IS_EMT(pVM))
3854	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3855	else
3856	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3857	}
3858	}
3859
3860
3861	/**
3862	* Notification about pending FF set by an external thread.
3863	*
3864	* @param pVM VM handle.
3865	* @thread Any.
3866	*/
3867	REMR3DECL(void) REMR3NotifyFF(PVM pVM)
3868	{
3869	LogFlow(("REMR3NotifyFF: fInRem=%d\n", pVM->rem.s.fInREM));
3870	if (pVM->rem.s.fInREM)
3871	{
3872	if (VM_IS_EMT(pVM))
3873	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
3874	else
3875	ASMAtomicOrS32(&cpu_single_env->interrupt_request, CPU_INTERRUPT_EXTERNAL_EXIT);
3876	}
3877	}
3878
3879
3880	#ifdef VBOX_WITH_STATISTICS
3881	void remR3ProfileStart(int statcode)
3882	{
3883	STAMPROFILEADV *pStat;
3884	switch(statcode)
3885	{
3886	case STATS_EMULATE_SINGLE_INSTR:
3887	pStat = &gStatExecuteSingleInstr;
3888	break;
3889	case STATS_QEMU_COMPILATION:
3890	pStat = &gStatCompilationQEmu;
3891	break;
3892	case STATS_QEMU_RUN_EMULATED_CODE:
3893	pStat = &gStatRunCodeQEmu;
3894	break;
3895	case STATS_QEMU_TOTAL:
3896	pStat = &gStatTotalTimeQEmu;
3897	break;
3898	case STATS_QEMU_RUN_TIMERS:
3899	pStat = &gStatTimers;
3900	break;
3901	case STATS_TLB_LOOKUP:
3902	pStat= &gStatTBLookup;
3903	break;
3904	case STATS_IRQ_HANDLING:
3905	pStat= &gStatIRQ;
3906	break;
3907	case STATS_RAW_CHECK:
3908	pStat = &gStatRawCheck;
3909	break;
3910
3911	default:
3912	AssertMsgFailed(("unknown stat %d\n", statcode));
3913	return;
3914	}
3915	STAM_PROFILE_ADV_START(pStat, a);
3916	}
3917
3918
3919	void remR3ProfileStop(int statcode)
3920	{
3921	STAMPROFILEADV *pStat;
3922	switch(statcode)
3923	{
3924	case STATS_EMULATE_SINGLE_INSTR:
3925	pStat = &gStatExecuteSingleInstr;
3926	break;
3927	case STATS_QEMU_COMPILATION:
3928	pStat = &gStatCompilationQEmu;
3929	break;
3930	case STATS_QEMU_RUN_EMULATED_CODE:
3931	pStat = &gStatRunCodeQEmu;
3932	break;
3933	case STATS_QEMU_TOTAL:
3934	pStat = &gStatTotalTimeQEmu;
3935	break;
3936	case STATS_QEMU_RUN_TIMERS:
3937	pStat = &gStatTimers;
3938	break;
3939	case STATS_TLB_LOOKUP:
3940	pStat= &gStatTBLookup;
3941	break;
3942	case STATS_IRQ_HANDLING:
3943	pStat= &gStatIRQ;
3944	break;
3945	case STATS_RAW_CHECK:
3946	pStat = &gStatRawCheck;
3947	break;
3948	default:
3949	AssertMsgFailed(("unknown stat %d\n", statcode));
3950	return;
3951	}
3952	STAM_PROFILE_ADV_STOP(pStat, a);
3953	}
3954	#endif
3955
3956	/**
3957	* Raise an RC, force rem exit.
3958	*
3959	* @param pVM VM handle.
3960	* @param rc The rc.
3961	*/
3962	void remR3RaiseRC(PVM pVM, int rc)
3963	{
3964	Log(("remR3RaiseRC: rc=%Vrc\n", rc));
3965	Assert(pVM->rem.s.fInREM);
3966	VM_ASSERT_EMT(pVM);
3967	pVM->rem.s.rc = rc;
3968	cpu_interrupt(&pVM->rem.s.Env, CPU_INTERRUPT_RC);
3969	}
3970
3971
3972	/* -+- timers -+- */
3973
3974	uint64_t cpu_get_tsc(CPUX86State *env)
3975	{
3976	return TMCpuTickGet(env->pVM);
3977	}
3978
3979
3980	/* -+- interrupts -+- */
3981
3982	void cpu_set_ferr(CPUX86State *env)
3983	{
3984	int rc = PDMIsaSetIrq(env->pVM, 13, 1);
3985	LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc);
3986	}
3987
3988	int cpu_get_pic_interrupt(CPUState *env)
3989	{
3990	uint8_t u8Interrupt;
3991	int rc;
3992
3993	/* When we fail to forward interrupts directly in raw mode, we fall back to the recompiler.
3994	* In that case we can't call PDMGetInterrupt anymore, because it has already cleared the interrupt
3995	* with the (a)pic.
3996	*/
3997	/** @note We assume we will go directly to the recompiler to handle the pending interrupt! */
3998	/** @todo r=bird: In the long run we should just do the interrupt handling in EM/CPUM/TRPM/somewhere and
3999	* if we cannot execute the interrupt handler in raw-mode just reschedule to REM. Once that is done we
4000	* remove this kludge. */
4001	if (env->pVM->rem.s.u32PendingInterrupt != REM_NO_PENDING_IRQ)
4002	{
4003	rc = VINF_SUCCESS;
4004	Assert(env->pVM->rem.s.u32PendingInterrupt >= 0 && env->pVM->rem.s.u32PendingInterrupt <= 255);
4005	u8Interrupt = env->pVM->rem.s.u32PendingInterrupt;
4006	env->pVM->rem.s.u32PendingInterrupt = REM_NO_PENDING_IRQ;
4007	}
4008	else
4009	rc = PDMGetInterrupt(env->pVM, &u8Interrupt);
4010
4011	LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Vrc\n", u8Interrupt, rc));
4012	if (VBOX_SUCCESS(rc))
4013	{
4014	if (VM_FF_ISPENDING(env->pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
4015	env->interrupt_request \|= CPU_INTERRUPT_HARD;
4016	return u8Interrupt;
4017	}
4018	return -1;
4019	}
4020
4021
4022	/* -+- local apic -+- */
4023
4024	void cpu_set_apic_base(CPUX86State *env, uint64_t val)
4025	{
4026	int rc = PDMApicSetBase(env->pVM, val);
4027	LogFlow(("cpu_set_apic_base: val=%#llx rc=%Vrc\n", val, rc)); NOREF(rc);
4028	}
4029
4030	uint64_t cpu_get_apic_base(CPUX86State *env)
4031	{
4032	uint64_t u64;
4033	int rc = PDMApicGetBase(env->pVM, &u64);
4034	if (VBOX_SUCCESS(rc))
4035	{
4036	LogFlow(("cpu_get_apic_base: returns %#llx \n", u64));
4037	return u64;
4038	}
4039	LogFlow(("cpu_get_apic_base: returns 0 (rc=%Vrc)\n", rc));
4040	return 0;
4041	}
4042
4043	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
4044	{
4045	int rc = PDMApicSetTPR(env->pVM, val);
4046	LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Vrc\n", val, rc)); NOREF(rc);
4047	}
4048
4049	uint8_t cpu_get_apic_tpr(CPUX86State *env)
4050	{
4051	uint8_t u8;
4052	int rc = PDMApicGetTPR(env->pVM, &u8);
4053	if (VBOX_SUCCESS(rc))
4054	{
4055	LogFlow(("cpu_get_apic_tpr: returns %#x\n", u8));
4056	return u8;
4057	}
4058	LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Vrc)\n", rc));
4059	return 0;
4060	}
4061
4062
4063	/* -+- I/O Ports -+- */
4064
4065	#undef LOG_GROUP
4066	#define LOG_GROUP LOG_GROUP_REM_IOPORT
4067
4068	void cpu_outb(CPUState *env, int addr, int val)
4069	{
4070	if (addr != 0x80 && addr != 0x70 && addr != 0x61)
4071	Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val));
4072
4073	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);
4074	if (rc == VINF_SUCCESS)
4075	return;
4076	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4077	{
4078	Log(("cpu_outb: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4079	remR3RaiseRC(env->pVM, rc);
4080	return;
4081	}
4082	remAbort(rc, __FUNCTION__);
4083	}
4084
4085	void cpu_outw(CPUState *env, int addr, int val)
4086	{
4087	//Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val));
4088	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);
4089	if (rc == VINF_SUCCESS)
4090	return;
4091	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4092	{
4093	Log(("cpu_outw: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4094	remR3RaiseRC(env->pVM, rc);
4095	return;
4096	}
4097	remAbort(rc, __FUNCTION__);
4098	}
4099
4100	void cpu_outl(CPUState *env, int addr, int val)
4101	{
4102	Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val));
4103	int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);
4104	if (rc == VINF_SUCCESS)
4105	return;
4106	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4107	{
4108	Log(("cpu_outl: addr=%#06x val=%#x -> %Vrc\n", addr, val, rc));
4109	remR3RaiseRC(env->pVM, rc);
4110	return;
4111	}
4112	remAbort(rc, __FUNCTION__);
4113	}
4114
4115	int cpu_inb(CPUState *env, int addr)
4116	{
4117	uint32_t u32 = 0;
4118	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);
4119	if (rc == VINF_SUCCESS)
4120	{
4121	if (/addr != 0x61 && /addr != 0x71)
4122	Log2(("cpu_inb: addr=%#06x -> %#x\n", addr, u32));
4123	return (int)u32;
4124	}
4125	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4126	{
4127	Log(("cpu_inb: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4128	remR3RaiseRC(env->pVM, rc);
4129	return (int)u32;
4130	}
4131	remAbort(rc, __FUNCTION__);
4132	return 0xff;
4133	}
4134
4135	int cpu_inw(CPUState *env, int addr)
4136	{
4137	uint32_t u32 = 0;
4138	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);
4139	if (rc == VINF_SUCCESS)
4140	{
4141	Log2(("cpu_inw: addr=%#06x -> %#x\n", addr, u32));
4142	return (int)u32;
4143	}
4144	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4145	{
4146	Log(("cpu_inw: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4147	remR3RaiseRC(env->pVM, rc);
4148	return (int)u32;
4149	}
4150	remAbort(rc, __FUNCTION__);
4151	return 0xffff;
4152	}
4153
4154	int cpu_inl(CPUState *env, int addr)
4155	{
4156	uint32_t u32 = 0;
4157	int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);
4158	if (rc == VINF_SUCCESS)
4159	{
4160	//if (addr==0x01f0 && u32 == 0x6b6d)
4161	// loglevel = ~0;
4162	Log2(("cpu_inl: addr=%#06x -> %#x\n", addr, u32));
4163	return (int)u32;
4164	}
4165	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
4166	{
4167	Log(("cpu_inl: addr=%#06x -> %#x rc=%Vrc\n", addr, u32, rc));
4168	remR3RaiseRC(env->pVM, rc);
4169	return (int)u32;
4170	}
4171	remAbort(rc, __FUNCTION__);
4172	return 0xffffffff;
4173	}
4174
4175	#undef LOG_GROUP
4176	#define LOG_GROUP LOG_GROUP_REM
4177
4178
4179	/* -+- helpers and misc other interfaces -+- */
4180
4181	/**
4182	* Perform the CPUID instruction.
4183	*
4184	* ASMCpuId cannot be invoked from some source files where this is used because of global
4185	* register allocations.
4186	*
4187	* @param env Pointer to the recompiler CPU structure.
4188	* @param uOperator CPUID operation (eax).
4189	* @param pvEAX Where to store eax.
4190	* @param pvEBX Where to store ebx.
4191	* @param pvECX Where to store ecx.
4192	* @param pvEDX Where to store edx.
4193	*/
4194	void remR3CpuId(CPUState env, unsigned uOperator, void pvEAX, void pvEBX, void pvECX, void *pvEDX)
4195	{
4196	CPUMGetGuestCpuId(env->pVM, uOperator, (uint32_t )pvEAX, (uint32_t )pvEBX, (uint32_t )pvECX, (uint32_t )pvEDX);
4197	}
4198
4199
4200	#if 0 /* not used */
4201	/**
4202	* Interface for qemu hardware to report back fatal errors.
4203	*/
4204	void hw_error(const char *pszFormat, ...)
4205	{
4206	/*
4207	* Bitch about it.
4208	*/
4209	/** @todo Add support for nested arg lists in the LogPrintfV routine! I've code for
4210	* this in my Odin32 tree at home! */
4211	va_list args;
4212	va_start(args, pszFormat);
4213	RTLogPrintf("fatal error in virtual hardware:");
4214	RTLogPrintfV(pszFormat, args);
4215	va_end(args);
4216	AssertReleaseMsgFailed(("fatal error in virtual hardware: %s\n", pszFormat));
4217
4218	/*
4219	* If we're in REM context we'll sync back the state before 'jumping' to
4220	* the EMs failure handling.
4221	*/
4222	PVM pVM = cpu_single_env->pVM;
4223	if (pVM->rem.s.fInREM)
4224	REMR3StateBack(pVM);
4225	EMR3FatalError(pVM, VERR_REM_VIRTUAL_HARDWARE_ERROR);
4226	AssertMsgFailed(("EMR3FatalError returned!\n"));
4227	}
4228	#endif
4229
4230	/**
4231	* Interface for the qemu cpu to report unhandled situation
4232	* raising a fatal VM error.
4233	*/
4234	void cpu_abort(CPUState env, const char pszFormat, ...)
4235	{
4236	/*
4237	* Bitch about it.
4238	*/
4239	RTLogFlags(NULL, "nodisabled nobuffered");
4240	va_list args;
4241	va_start(args, pszFormat);
4242	RTLogPrintf("fatal error in recompiler cpu: %N\n", pszFormat, &args);
4243	va_end(args);
4244	va_start(args, pszFormat);
4245	AssertReleaseMsgFailed(("fatal error in recompiler cpu: %N\n", pszFormat, &args));
4246	va_end(args);
4247
4248	/*
4249	* If we're in REM context we'll sync back the state before 'jumping' to
4250	* the EMs failure handling.
4251	*/
4252	PVM pVM = cpu_single_env->pVM;
4253	if (pVM->rem.s.fInREM)
4254	REMR3StateBack(pVM);
4255	EMR3FatalError(pVM, VERR_REM_VIRTUAL_CPU_ERROR);
4256	AssertMsgFailed(("EMR3FatalError returned!\n"));
4257	}
4258
4259
4260	/**
4261	* Aborts the VM.
4262	*
4263	* @param rc VBox error code.
4264	* @param pszTip Hint about why/when this happend.
4265	*/
4266	static void remAbort(int rc, const char *pszTip)
4267	{
4268	/*
4269	* Bitch about it.
4270	*/
4271	RTLogPrintf("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip);
4272	AssertReleaseMsgFailed(("internal REM fatal error: rc=%Vrc %s\n", rc, pszTip));
4273
4274	/*
4275	* Jump back to where we entered the recompiler.
4276	*/
4277	PVM pVM = cpu_single_env->pVM;
4278	if (pVM->rem.s.fInREM)
4279	REMR3StateBack(pVM);
4280	EMR3FatalError(pVM, rc);
4281	AssertMsgFailed(("EMR3FatalError returned!\n"));
4282	}
4283
4284
4285	/**
4286	* Dumps a linux system call.
4287	* @param pVM VM handle.
4288	*/
4289	void remR3DumpLnxSyscall(PVM pVM)
4290	{
4291	static const char *apsz[] =
4292	{
4293	"sys_restart_syscall", /* 0 - old "setup()" system call, used for restarting */
4294	"sys_exit",
4295	"sys_fork",
4296	"sys_read",
4297	"sys_write",
4298	"sys_open", /* 5 */
4299	"sys_close",
4300	"sys_waitpid",
4301	"sys_creat",
4302	"sys_link",
4303	"sys_unlink", /* 10 */
4304	"sys_execve",
4305	"sys_chdir",
4306	"sys_time",
4307	"sys_mknod",
4308	"sys_chmod", /* 15 */
4309	"sys_lchown16",
4310	"sys_ni_syscall", /* old break syscall holder */
4311	"sys_stat",
4312	"sys_lseek",
4313	"sys_getpid", /* 20 */
4314	"sys_mount",
4315	"sys_oldumount",
4316	"sys_setuid16",
4317	"sys_getuid16",
4318	"sys_stime", /* 25 */
4319	"sys_ptrace",
4320	"sys_alarm",
4321	"sys_fstat",
4322	"sys_pause",
4323	"sys_utime", /* 30 */
4324	"sys_ni_syscall", /* old stty syscall holder */
4325	"sys_ni_syscall", /* old gtty syscall holder */
4326	"sys_access",
4327	"sys_nice",
4328	"sys_ni_syscall", /* 35 - old ftime syscall holder */
4329	"sys_sync",
4330	"sys_kill",
4331	"sys_rename",
4332	"sys_mkdir",
4333	"sys_rmdir", /* 40 */
4334	"sys_dup",
4335	"sys_pipe",
4336	"sys_times",
4337	"sys_ni_syscall", /* old prof syscall holder */
4338	"sys_brk", /* 45 */
4339	"sys_setgid16",
4340	"sys_getgid16",
4341	"sys_signal",
4342	"sys_geteuid16",
4343	"sys_getegid16", /* 50 */
4344	"sys_acct",
4345	"sys_umount", /* recycled never used phys() */
4346	"sys_ni_syscall", /* old lock syscall holder */
4347	"sys_ioctl",
4348	"sys_fcntl", /* 55 */
4349	"sys_ni_syscall", /* old mpx syscall holder */
4350	"sys_setpgid",
4351	"sys_ni_syscall", /* old ulimit syscall holder */
4352	"sys_olduname",
4353	"sys_umask", /* 60 */
4354	"sys_chroot",
4355	"sys_ustat",
4356	"sys_dup2",
4357	"sys_getppid",
4358	"sys_getpgrp", /* 65 */
4359	"sys_setsid",
4360	"sys_sigaction",
4361	"sys_sgetmask",
4362	"sys_ssetmask",
4363	"sys_setreuid16", /* 70 */
4364	"sys_setregid16",
4365	"sys_sigsuspend",
4366	"sys_sigpending",
4367	"sys_sethostname",
4368	"sys_setrlimit", /* 75 */
4369	"sys_old_getrlimit",
4370	"sys_getrusage",
4371	"sys_gettimeofday",
4372	"sys_settimeofday",
4373	"sys_getgroups16", /* 80 */
4374	"sys_setgroups16",
4375	"old_select",
4376	"sys_symlink",
4377	"sys_lstat",
4378	"sys_readlink", /* 85 */
4379	"sys_uselib",
4380	"sys_swapon",
4381	"sys_reboot",
4382	"old_readdir",
4383	"old_mmap", /* 90 */
4384	"sys_munmap",
4385	"sys_truncate",
4386	"sys_ftruncate",
4387	"sys_fchmod",
4388	"sys_fchown16", /* 95 */
4389	"sys_getpriority",
4390	"sys_setpriority",
4391	"sys_ni_syscall", /* old profil syscall holder */
4392	"sys_statfs",
4393	"sys_fstatfs", /* 100 */
4394	"sys_ioperm",
4395	"sys_socketcall",
4396	"sys_syslog",
4397	"sys_setitimer",
4398	"sys_getitimer", /* 105 */
4399	"sys_newstat",
4400	"sys_newlstat",
4401	"sys_newfstat",
4402	"sys_uname",
4403	"sys_iopl", /* 110 */
4404	"sys_vhangup",
4405	"sys_ni_syscall", /* old "idle" system call */
4406	"sys_vm86old",
4407	"sys_wait4",
4408	"sys_swapoff", /* 115 */
4409	"sys_sysinfo",
4410	"sys_ipc",
4411	"sys_fsync",
4412	"sys_sigreturn",
4413	"sys_clone", /* 120 */
4414	"sys_setdomainname",
4415	"sys_newuname",
4416	"sys_modify_ldt",
4417	"sys_adjtimex",
4418	"sys_mprotect", /* 125 */
4419	"sys_sigprocmask",
4420	"sys_ni_syscall", /* old "create_module" */
4421	"sys_init_module",
4422	"sys_delete_module",
4423	"sys_ni_syscall", /* 130: old "get_kernel_syms" */
4424	"sys_quotactl",
4425	"sys_getpgid",
4426	"sys_fchdir",
4427	"sys_bdflush",
4428	"sys_sysfs", /* 135 */
4429	"sys_personality",
4430	"sys_ni_syscall", /* reserved for afs_syscall */
4431	"sys_setfsuid16",
4432	"sys_setfsgid16",
4433	"sys_llseek", /* 140 */
4434	"sys_getdents",
4435	"sys_select",
4436	"sys_flock",
4437	"sys_msync",
4438	"sys_readv", /* 145 */
4439	"sys_writev",
4440	"sys_getsid",
4441	"sys_fdatasync",
4442	"sys_sysctl",
4443	"sys_mlock", /* 150 */
4444	"sys_munlock",
4445	"sys_mlockall",
4446	"sys_munlockall",
4447	"sys_sched_setparam",
4448	"sys_sched_getparam", /* 155 */
4449	"sys_sched_setscheduler",
4450	"sys_sched_getscheduler",
4451	"sys_sched_yield",
4452	"sys_sched_get_priority_max",
4453	"sys_sched_get_priority_min", /* 160 */
4454	"sys_sched_rr_get_interval",
4455	"sys_nanosleep",
4456	"sys_mremap",
4457	"sys_setresuid16",
4458	"sys_getresuid16", /* 165 */
4459	"sys_vm86",
4460	"sys_ni_syscall", /* Old sys_query_module */
4461	"sys_poll",
4462	"sys_nfsservctl",
4463	"sys_setresgid16", /* 170 */
4464	"sys_getresgid16",
4465	"sys_prctl",
4466	"sys_rt_sigreturn",
4467	"sys_rt_sigaction",
4468	"sys_rt_sigprocmask", /* 175 */
4469	"sys_rt_sigpending",
4470	"sys_rt_sigtimedwait",
4471	"sys_rt_sigqueueinfo",
4472	"sys_rt_sigsuspend",
4473	"sys_pread64", /* 180 */
4474	"sys_pwrite64",
4475	"sys_chown16",
4476	"sys_getcwd",
4477	"sys_capget",
4478	"sys_capset", /* 185 */
4479	"sys_sigaltstack",
4480	"sys_sendfile",
4481	"sys_ni_syscall", /* reserved for streams1 */
4482	"sys_ni_syscall", /* reserved for streams2 */
4483	"sys_vfork", /* 190 */
4484	"sys_getrlimit",
4485	"sys_mmap2",
4486	"sys_truncate64",
4487	"sys_ftruncate64",
4488	"sys_stat64", /* 195 */
4489	"sys_lstat64",
4490	"sys_fstat64",
4491	"sys_lchown",
4492	"sys_getuid",
4493	"sys_getgid", /* 200 */
4494	"sys_geteuid",
4495	"sys_getegid",
4496	"sys_setreuid",
4497	"sys_setregid",
4498	"sys_getgroups", /* 205 */
4499	"sys_setgroups",
4500	"sys_fchown",
4501	"sys_setresuid",
4502	"sys_getresuid",
4503	"sys_setresgid", /* 210 */
4504	"sys_getresgid",
4505	"sys_chown",
4506	"sys_setuid",
4507	"sys_setgid",
4508	"sys_setfsuid", /* 215 */
4509	"sys_setfsgid",
4510	"sys_pivot_root",
4511	"sys_mincore",
4512	"sys_madvise",
4513	"sys_getdents64", /* 220 */
4514	"sys_fcntl64",
4515	"sys_ni_syscall", /* reserved for TUX */
4516	"sys_ni_syscall",
4517	"sys_gettid",
4518	"sys_readahead", /* 225 */
4519	"sys_setxattr",
4520	"sys_lsetxattr",
4521	"sys_fsetxattr",
4522	"sys_getxattr",
4523	"sys_lgetxattr", /* 230 */
4524	"sys_fgetxattr",
4525	"sys_listxattr",
4526	"sys_llistxattr",
4527	"sys_flistxattr",
4528	"sys_removexattr", /* 235 */
4529	"sys_lremovexattr",
4530	"sys_fremovexattr",
4531	"sys_tkill",
4532	"sys_sendfile64",
4533	"sys_futex", /* 240 */
4534	"sys_sched_setaffinity",
4535	"sys_sched_getaffinity",
4536	"sys_set_thread_area",
4537	"sys_get_thread_area",
4538	"sys_io_setup", /* 245 */
4539	"sys_io_destroy",
4540	"sys_io_getevents",
4541	"sys_io_submit",
4542	"sys_io_cancel",
4543	"sys_fadvise64", /* 250 */
4544	"sys_ni_syscall",
4545	"sys_exit_group",
4546	"sys_lookup_dcookie",
4547	"sys_epoll_create",
4548	"sys_epoll_ctl", /* 255 */
4549	"sys_epoll_wait",
4550	"sys_remap_file_pages",
4551	"sys_set_tid_address",
4552	"sys_timer_create",
4553	"sys_timer_settime", /* 260 */
4554	"sys_timer_gettime",
4555	"sys_timer_getoverrun",
4556	"sys_timer_delete",
4557	"sys_clock_settime",
4558	"sys_clock_gettime", /* 265 */
4559	"sys_clock_getres",
4560	"sys_clock_nanosleep",
4561	"sys_statfs64",
4562	"sys_fstatfs64",
4563	"sys_tgkill", /* 270 */
4564	"sys_utimes",
4565	"sys_fadvise64_64",
4566	"sys_ni_syscall" /* sys_vserver */
4567	};
4568
4569	uint32_t uEAX = CPUMGetGuestEAX(pVM);
4570	switch (uEAX)
4571	{
4572	default:
4573	if (uEAX < ELEMENTS(apsz))
4574	Log(("REM: linux syscall %3d: %s (eip=%VGv ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x ebp=%08x)\n",
4575	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), CPUMGetGuestEBX(pVM), CPUMGetGuestECX(pVM),
4576	CPUMGetGuestEDX(pVM), CPUMGetGuestESI(pVM), CPUMGetGuestEDI(pVM), CPUMGetGuestEBP(pVM)));
4577	else
4578	Log(("eip=%08x: linux syscall %d (#%x) unknown\n", CPUMGetGuestEIP(pVM), uEAX, uEAX));
4579	break;
4580
4581	}
4582	}
4583
4584
4585	/**
4586	* Dumps an OpenBSD system call.
4587	* @param pVM VM handle.
4588	*/
4589	void remR3DumpOBsdSyscall(PVM pVM)
4590	{
4591	static const char *apsz[] =
4592	{
4593	"SYS_syscall", //0
4594	"SYS_exit", //1
4595	"SYS_fork", //2
4596	"SYS_read", //3
4597	"SYS_write", //4
4598	"SYS_open", //5
4599	"SYS_close", //6
4600	"SYS_wait4", //7
4601	"SYS_8",
4602	"SYS_link", //9
4603	"SYS_unlink", //10
4604	"SYS_11",
4605	"SYS_chdir", //12
4606	"SYS_fchdir", //13
4607	"SYS_mknod", //14
4608	"SYS_chmod", //15
4609	"SYS_chown", //16
4610	"SYS_break", //17
4611	"SYS_18",
4612	"SYS_19",
4613	"SYS_getpid", //20
4614	"SYS_mount", //21
4615	"SYS_unmount", //22
4616	"SYS_setuid", //23
4617	"SYS_getuid", //24
4618	"SYS_geteuid", //25
4619	"SYS_ptrace", //26
4620	"SYS_recvmsg", //27
4621	"SYS_sendmsg", //28
4622	"SYS_recvfrom", //29
4623	"SYS_accept", //30
4624	"SYS_getpeername", //31
4625	"SYS_getsockname", //32
4626	"SYS_access", //33
4627	"SYS_chflags", //34
4628	"SYS_fchflags", //35
4629	"SYS_sync", //36
4630	"SYS_kill", //37
4631	"SYS_38",
4632	"SYS_getppid", //39
4633	"SYS_40",
4634	"SYS_dup", //41
4635	"SYS_opipe", //42
4636	"SYS_getegid", //43
4637	"SYS_profil", //44
4638	"SYS_ktrace", //45
4639	"SYS_sigaction", //46
4640	"SYS_getgid", //47
4641	"SYS_sigprocmask", //48
4642	"SYS_getlogin", //49
4643	"SYS_setlogin", //50
4644	"SYS_acct", //51
4645	"SYS_sigpending", //52
4646	"SYS_osigaltstack", //53
4647	"SYS_ioctl", //54
4648	"SYS_reboot", //55
4649	"SYS_revoke", //56
4650	"SYS_symlink", //57
4651	"SYS_readlink", //58
4652	"SYS_execve", //59
4653	"SYS_umask", //60
4654	"SYS_chroot", //61
4655	"SYS_62",
4656	"SYS_63",
4657	"SYS_64",
4658	"SYS_65",
4659	"SYS_vfork", //66
4660	"SYS_67",
4661	"SYS_68",
4662	"SYS_sbrk", //69
4663	"SYS_sstk", //70
4664	"SYS_61",
4665	"SYS_vadvise", //72
4666	"SYS_munmap", //73
4667	"SYS_mprotect", //74
4668	"SYS_madvise", //75
4669	"SYS_76",
4670	"SYS_77",
4671	"SYS_mincore", //78
4672	"SYS_getgroups", //79
4673	"SYS_setgroups", //80
4674	"SYS_getpgrp", //81
4675	"SYS_setpgid", //82
4676	"SYS_setitimer", //83
4677	"SYS_84",
4678	"SYS_85",
4679	"SYS_getitimer", //86
4680	"SYS_87",
4681	"SYS_88",
4682	"SYS_89",
4683	"SYS_dup2", //90
4684	"SYS_91",
4685	"SYS_fcntl", //92
4686	"SYS_select", //93
4687	"SYS_94",
4688	"SYS_fsync", //95
4689	"SYS_setpriority", //96
4690	"SYS_socket", //97
4691	"SYS_connect", //98
4692	"SYS_99",
4693	"SYS_getpriority", //100
4694	"SYS_101",
4695	"SYS_102",
4696	"SYS_sigreturn", //103
4697	"SYS_bind", //104
4698	"SYS_setsockopt", //105
4699	"SYS_listen", //106
4700	"SYS_107",
4701	"SYS_108",
4702	"SYS_109",
4703	"SYS_110",
4704	"SYS_sigsuspend", //111
4705	"SYS_112",
4706	"SYS_113",
4707	"SYS_114",
4708	"SYS_115",
4709	"SYS_gettimeofday", //116
4710	"SYS_getrusage", //117
4711	"SYS_getsockopt", //118
4712	"SYS_119",
4713	"SYS_readv", //120
4714	"SYS_writev", //121
4715	"SYS_settimeofday", //122
4716	"SYS_fchown", //123
4717	"SYS_fchmod", //124
4718	"SYS_125",
4719	"SYS_setreuid", //126
4720	"SYS_setregid", //127
4721	"SYS_rename", //128
4722	"SYS_129",
4723	"SYS_130",
4724	"SYS_flock", //131
4725	"SYS_mkfifo", //132
4726	"SYS_sendto", //133
4727	"SYS_shutdown", //134
4728	"SYS_socketpair", //135
4729	"SYS_mkdir", //136
4730	"SYS_rmdir", //137
4731	"SYS_utimes", //138
4732	"SYS_139",
4733	"SYS_adjtime", //140
4734	"SYS_141",
4735	"SYS_142",
4736	"SYS_143",
4737	"SYS_144",
4738	"SYS_145",
4739	"SYS_146",
4740	"SYS_setsid", //147
4741	"SYS_quotactl", //148
4742	"SYS_149",
4743	"SYS_150",
4744	"SYS_151",
4745	"SYS_152",
4746	"SYS_153",
4747	"SYS_154",
4748	"SYS_nfssvc", //155
4749	"SYS_156",
4750	"SYS_157",
4751	"SYS_158",
4752	"SYS_159",
4753	"SYS_160",
4754	"SYS_getfh", //161
4755	"SYS_162",
4756	"SYS_163",
4757	"SYS_164",
4758	"SYS_sysarch", //165
4759	"SYS_166",
4760	"SYS_167",
4761	"SYS_168",
4762	"SYS_169",
4763	"SYS_170",
4764	"SYS_171",
4765	"SYS_172",
4766	"SYS_pread", //173
4767	"SYS_pwrite", //174
4768	"SYS_175",
4769	"SYS_176",
4770	"SYS_177",
4771	"SYS_178",
4772	"SYS_179",
4773	"SYS_180",
4774	"SYS_setgid", //181
4775	"SYS_setegid", //182
4776	"SYS_seteuid", //183
4777	"SYS_lfs_bmapv", //184
4778	"SYS_lfs_markv", //185
4779	"SYS_lfs_segclean", //186
4780	"SYS_lfs_segwait", //187
4781	"SYS_188",
4782	"SYS_189",
4783	"SYS_190",
4784	"SYS_pathconf", //191
4785	"SYS_fpathconf", //192
4786	"SYS_swapctl", //193
4787	"SYS_getrlimit", //194
4788	"SYS_setrlimit", //195
4789	"SYS_getdirentries", //196
4790	"SYS_mmap", //197
4791	"SYS___syscall", //198
4792	"SYS_lseek", //199
4793	"SYS_truncate", //200
4794	"SYS_ftruncate", //201
4795	"SYS___sysctl", //202
4796	"SYS_mlock", //203
4797	"SYS_munlock", //204
4798	"SYS_205",
4799	"SYS_futimes", //206
4800	"SYS_getpgid", //207
4801	"SYS_xfspioctl", //208
4802	"SYS_209",
4803	"SYS_210",
4804	"SYS_211",
4805	"SYS_212",
4806	"SYS_213",
4807	"SYS_214",
4808	"SYS_215",
4809	"SYS_216",
4810	"SYS_217",
4811	"SYS_218",
4812	"SYS_219",
4813	"SYS_220",
4814	"SYS_semget", //221
4815	"SYS_222",
4816	"SYS_223",
4817	"SYS_224",
4818	"SYS_msgget", //225
4819	"SYS_msgsnd", //226
4820	"SYS_msgrcv", //227
4821	"SYS_shmat", //228
4822	"SYS_229",
4823	"SYS_shmdt", //230
4824	"SYS_231",
4825	"SYS_clock_gettime", //232
4826	"SYS_clock_settime", //233
4827	"SYS_clock_getres", //234
4828	"SYS_235",
4829	"SYS_236",
4830	"SYS_237",
4831	"SYS_238",
4832	"SYS_239",
4833	"SYS_nanosleep", //240
4834	"SYS_241",
4835	"SYS_242",
4836	"SYS_243",
4837	"SYS_244",
4838	"SYS_245",
4839	"SYS_246",
4840	"SYS_247",
4841	"SYS_248",
4842	"SYS_249",
4843	"SYS_minherit", //250
4844	"SYS_rfork", //251
4845	"SYS_poll", //252
4846	"SYS_issetugid", //253
4847	"SYS_lchown", //254
4848	"SYS_getsid", //255
4849	"SYS_msync", //256
4850	"SYS_257",
4851	"SYS_258",
4852	"SYS_259",
4853	"SYS_getfsstat", //260
4854	"SYS_statfs", //261
4855	"SYS_fstatfs", //262
4856	"SYS_pipe", //263
4857	"SYS_fhopen", //264
4858	"SYS_265",
4859	"SYS_fhstatfs", //266
4860	"SYS_preadv", //267
4861	"SYS_pwritev", //268
4862	"SYS_kqueue", //269
4863	"SYS_kevent", //270
4864	"SYS_mlockall", //271
4865	"SYS_munlockall", //272
4866	"SYS_getpeereid", //273
4867	"SYS_274",
4868	"SYS_275",
4869	"SYS_276",
4870	"SYS_277",
4871	"SYS_278",
4872	"SYS_279",
4873	"SYS_280",
4874	"SYS_getresuid", //281
4875	"SYS_setresuid", //282
4876	"SYS_getresgid", //283
4877	"SYS_setresgid", //284
4878	"SYS_285",
4879	"SYS_mquery", //286
4880	"SYS_closefrom", //287
4881	"SYS_sigaltstack", //288
4882	"SYS_shmget", //289
4883	"SYS_semop", //290
4884	"SYS_stat", //291
4885	"SYS_fstat", //292
4886	"SYS_lstat", //293
4887	"SYS_fhstat", //294
4888	"SYS___semctl", //295
4889	"SYS_shmctl", //296
4890	"SYS_msgctl", //297
4891	"SYS_MAXSYSCALL", //298
4892	//299
4893	//300
4894	};
4895	uint32_t uEAX;
4896	#ifndef DEBUG_bird
4897	if (!LogIsEnabled())
4898	return;
4899	#endif
4900	uEAX = CPUMGetGuestEAX(pVM);
4901	switch (uEAX)
4902	{
4903	default:
4904	if (uEAX < ELEMENTS(apsz))
4905	{
4906	uint32_t au32Args[8] = {0};
4907	PGMPhysReadGCPtr(pVM, au32Args, CPUMGetGuestESP(pVM), sizeof(au32Args));
4908	RTLogPrintf("REM: OpenBSD syscall %3d: %s (eip=%08x %08x %08x %08x %08x %08x %08x %08x %08x)\n",
4909	uEAX, apsz[uEAX], CPUMGetGuestEIP(pVM), au32Args[0], au32Args[1], au32Args[2], au32Args[3],
4910	au32Args[4], au32Args[5], au32Args[6], au32Args[7]);
4911	}
4912	else
4913	RTLogPrintf("eip=%08x: OpenBSD syscall %d (#%x) unknown!!\n", CPUMGetGuestEIP(pVM), uEAX, uEAX);
4914	break;
4915	}
4916	}

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source: vbox/trunk/src/recompiler/VBoxRecompiler.c@ 1125

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