cidet.h@ 104195

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1	/* $Id: cidet.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2	/** @file
3	* CPU Instruction Decoding & Execution Tests - C/C++ Header.
4	*/
5
6	/*
7	* Copyright (C) 2014-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* The contents of this file may alternatively be used under the terms
26	* of the Common Development and Distribution License Version 1.0
27	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	* in the VirtualBox distribution, in which case the provisions of the
29	* CDDL are applicable instead of those of the GPL.
30	*
31	* You may elect to license modified versions of this file under the
32	* terms and conditions of either the GPL or the CDDL or both.
33	*
34	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	*/
36
37	#ifndef VBOX_INCLUDED_SRC_cpu_cidet_h
38	#define VBOX_INCLUDED_SRC_cpu_cidet_h
39	#ifndef RT_WITHOUT_PRAGMA_ONCE
40	# pragma once
41	#endif
42
43	#include <iprt/types.h>
44	#include <iprt/x86.h>
45
46
47	/** @name CIDET - Operand flags.
48	* @{ */
49	#define CIDET_OF_FIXED_MASK UINT32_C(0x0000001f) /*< Fixed register/whatever mask. /
50
51	#define CIDET_OF_Z_SHIFT 8 /*< Size shift. /
52	#define CIDET_OF_Z_MASK UINT32_C(0x00000f00) /*< Size mask. /
53	#define CIDET_OF_Z_NONE UINT32_C(0x00000000) /*< Unused zero value. /
54	#define CIDET_OF_Z_BYTE UINT32_C(0x00000100) /*< Byte size. /
55	#define CIDET_OF_Z_WORD UINT32_C(0x00000200) /*< Word (2 bytes) size. /
56	#define CIDET_OF_Z_DWORD UINT32_C(0x00000300) /*< Double word (4 bytes) size. /
57	#define CIDET_OF_Z_QWORD UINT32_C(0x00000400) /*< Quad word (8 bytes) size. /
58	#define CIDET_OF_Z_TBYTE UINT32_C(0x00000500) /*< Ten byte (10 bytes) size - aka TWORD. /
59	#define CIDET_OF_Z_OWORD UINT32_C(0x00000600) /*< Octa word (16 bytes) size - aka DQWORD. /
60	#define CIDET_OF_Z_YWORD UINT32_C(0x00000700) /*< Yxx sized, i.e. 32 bytes. /
61	#define CIDET_OF_Z_ZWORD UINT32_C(0x00000800) /*< Zxx sized, i.e. 64 bytes. /
62	#define CIDET_OF_Z_VAR_WDQ UINT32_C(0x00000900) /*< Variable size depending on size prefix (2, 4, or 8 bytes). /
63	#define CIDET_OF_Z_SPECIAL UINT32_C(0x00000f00) /*< Special size, see instruction flags or smth. /
64
65	#define CIDET_OF_K_MASK UINT32_C(0x0000f000) /*< Kind of operand. /
66	#define CIDET_OF_K_NONE UINT32_C(0x00000000) /*< Unused zero value. /
67	#define CIDET_OF_K_GPR UINT32_C(0x00001000) /*< General purpose register. Includes memory when used with CIDET_OF_M_RM. /
68	#define CIDET_OF_K_SREG UINT32_C(0x00002000) /*< Segment register. /
69	#define CIDET_OF_K_CR UINT32_C(0x00003000) /*< Control register. /
70	#define CIDET_OF_K_SSE UINT32_C(0x00004000) /*< SSE register. /
71	#define CIDET_OF_K_AVX UINT32_C(0x00005000) /*< AVX register. /
72	#define CIDET_OF_K_AVX512 UINT32_C(0x00006000) /*< AVX-512 register. /
73	#define CIDET_OF_K_AVXFUTURE UINT32_C(0x00007000) /*< Reserved for future AVX register set. /
74	#define CIDET_OF_K_VRX_TST_MASK UINT32_C(0x0000c000) /*< Used for testing for VRX register kind, see CIDET_OF_K_IS_VRX. /
75	#define CIDET_OF_K_VRX_TST_RES UINT32_C(0x00004000) /*< Used for testing for VRX register kind, see CIDET_OF_K_IS_VRX. /
76	#define CIDET_OF_K_FPU UINT32_C(0x00008000) /*< FPU register. /
77	#define CIDET_OF_K_MMX UINT32_C(0x00009000) /*< MMX register. /
78	#define CIDET_OF_K_TEST UINT32_C(0x0000a000) /*< Test register. /
79	#define CIDET_OF_K_IMM UINT32_C(0x0000d000) /*< Immediate. /
80	#define CIDET_OF_K_MEM UINT32_C(0x0000e000) /*< Memory. /
81	#define CIDET_OF_K_SPECIAL UINT32_C(0x0000f000) /*< Special. /
82	/** Check if @a a_fOp is a general purpose register. */
83	#define CIDET_OF_K_IS_GPR(a_fOp) ( ((a_fOp) & CIDET_OF_K_MASK) == CIDET_OF_K_GPR )
84	/** Check if @a a_fOp is a XMM (SSE), YMM (AVX), ZMM (AVX-512) or similar register. */
85	#define CIDET_OF_K_IS_VRX(a_fOp) ( ((a_fOp) & CIDET_OF_K_VRX_TST_MASK) == CIDET_OF_K_VRX_TST_RES )
86	/** Check if @a a_fOp1 and @a a_fOp2 specify the same kind of register,
87	* treating SSE, AVX, AVX-512 and AVX-future as the same kind and ignoring the
88	* special register kind. */
89	#define CIDET_OF_K_IS_SAME(a_fOp1, a_fOp2) \
90	( ((a_fOp1) & CIDET_OF_K_MASK) == ((a_fOp2) & CIDET_OF_K_MASK) \
91	? ((a_fOp1) & CIDET_OF_K_MASK) != CIDET_OF_K_SPECIAL \
92	: (CIDET_OF_K_IS_VRX(a_fOp1) && CIDET_OF_K_IS_VRX(a_fOp2)) )
93
94	#define CIDET_OF_M_RM_ONLY_R UINT32_C(0x00010000)
95	#define CIDET_OF_M_RM_ONLY_M UINT32_C(0x00020000)
96	#define CIDET_OF_M_RM (CIDET_OF_M_RM_ONLY_R \| CIDET_OF_M_RM_ONLY_M)
97	#define CIDET_OF_M_REG UINT32_C(0x00040000)
98
99	#define CIDET_OF_A_R UINT32_C(0x00080000) /*< Read access. /
100	#define CIDET_OF_A_W UINT32_C(0x00100000) /*< Write access. /
101	#define CIDET_OF_A_RW UINT32_C(0x00180000) /*< Read & write access. /
102
103	/** The operand defaults to 64-bit width in 64-bit mode, making 32-bit width
104	* inaccessible. */
105	#define CIDET_OF_DEFAULT_64BIT UINT32_C(0x40000000)
106	/** Operand always uses the ES segment for memory accesses. */
107	#define CIDET_OF_ALWAYS_SEG_ES UINT32_C(0x80000000)
108	/** @} */
109
110
111	/** @name CIDET - Instruction flags.
112	* @{ */
113	#define CIDET_IF_MODRM RT_BIT_64(0) /*< ModR/M encoded. /
114	#define CIDET_IF_PRIVILEGED RT_BIT_64(1) /*< Privileged. /
115	/** @} */
116
117
118	/**
119	* Callback function for setting up the input and expected output CPU contexts.
120	*
121	* @returns VBox status code.
122	* @retval VINF_EOF when static test data wraps (first entry is returned).
123	* @retval VERR_NO_DATA if @a fInvalid is set and there are no invalid operand
124	* values for this instruction.
125	* @retval VERR_NOT_SUPPORTED if something in the setup prevents us from
126	* comming up with working set of inputs and outputs.
127	*
128	* @param pThis The core CIDET state structure. The InCtx
129	* and ExpectedCtx members will be modified.
130	* @param fInvalid When set, get the next invalid operands that will
131	* cause exceptions/faults.
132	*/
133	typedef DECLCALLBACKTYPE(int, FNCIDETSETUPINOUT,(struct CIDETCORE *pThis, bool fInvalid));
134	/** Pointer to a FNCIDETSETUPINOUT function. */
135	typedef FNCIDETSETUPINOUT *PFNCIDETSETUPINOUT;
136
137
138	/**
139	* Instruction test descriptor.
140	*/
141	typedef struct CIDETINSTR
142	{
143	/** The mnemonic (kind of). */
144	const char *pszMnemonic;
145	/** Setup input and outputs. */
146	PFNCIDETSETUPINOUT pfnSetupInOut;
147	/** Number of opcode bytes. */
148	uint8_t cbOpcode;
149	/** Opcode byte(s). */
150	uint8_t abOpcode[3];
151	/** Mandatory prefix (zero if not applicable). */
152	uint8_t bMandatoryPrefix;
153	/** Number of operands. */
154	uint8_t cOperands;
155	/** Operand flags. */
156	uint32_t afOperands[4];
157	/** Flags. */
158	uint64_t fFlags;
159	} CIDETINSTR;
160	/** Pointer to an instruction test descriptor. */
161	typedef CIDETINSTR const *PCCIDETINSTR;
162
163
164	/**
165	* CPU Context with a few extra bits for expectations and results.
166	*/
167	typedef struct CIDETCPUCTX
168	{
169	uint64_t rip;
170	uint64_t rfl;
171	uint64_t aGRegs[16];
172	uint16_t aSRegs[6];
173
174	#ifndef CIDET_REDUCED_CTX
175	uint16_t tr;
176	uint16_t ldtr;
177	uint64_t cr0;
178	#else
179	uint16_t au16Padding[2];
180	#endif
181	uint64_t cr2;
182	#ifndef CIDET_REDUCED_CTX
183	uint64_t cr3;
184	uint64_t cr4;
185	uint64_t cr8;
186	uint64_t dr0;
187	uint64_t dr1;
188	uint64_t dr2;
189	uint64_t dr3;
190	uint64_t dr6;
191	uint64_t dr7;
192	#endif
193
194	uint64_t uErr; /*< Exception error code. UINT64_MAX if not applicable. (Not for input context.) /
195	uint32_t uXcpt; /*< Exception number. UINT32_MAX if no exception. (Not for input context.) /
196
197	uint32_t fIgnoredRFlags; /*< Only for expected result. /
198	bool fTrickyStack; /*< Set if the stack might be bad. May come at the cost of accurate flags (32-bit). /
199	} CIDETCPUCTX;
200	typedef CIDETCPUCTX *PCIDETCPUCTX;
201	typedef CIDETCPUCTX const *PCCIDETCPUCTX;
202
203	/** Number of bytes of CIDETCPUCTX that can be compared quickly using memcmp.
204	* Anything following these bytes are not relevant to the compare. */
205	#define CIDETCPUCTX_COMPARE_SIZE RT_UOFFSETOF(CIDETCPUCTX, fIgnoredRFlags)
206
207
208	/** @name CPU mode + bits + environment.
209	* @{ */
210	#define CIDETMODE_BIT_MASK UINT8_C(0x0e) /*< The instruction bit count. Results in byte size when masked. /
211	#define CIDETMODE_BIT_16 UINT8_C(0x02) /*< 16-bit instructions. /
212	#define CIDETMODE_BIT_32 UINT8_C(0x04) /*< 32-bit instructions. /
213	#define CIDETMODE_BIT_64 UINT8_C(0x08) /*< 64-bit instructions. /
214	#define CIDETMODE_MODE_MASK UINT8_C(0x70) /*< CPU mode mask. /
215	#define CIDETMODE_MODE_RM UINT8_C(0x00) /*< Real mode. /
216	#define CIDETMODE_MODE_PE UINT8_C(0x10) /*< Protected mode without paging. /
217	#define CIDETMODE_MODE_PP UINT8_C(0x20) /*< Paged protected mode. /
218	#define CIDETMODE_MODE_PAE UINT8_C(0x30) /*< PAE protected mode (paged). /
219	#define CIDETMODE_MODE_LM UINT8_C(0x40) /*< Long mode (paged). /
220	#define CIDETMODE_ENV_MASK UINT8_C(0x81) /*< Execution environment. /
221	#define CIDETMODE_ENV_NORMAL UINT8_C(0x01) /*< Normal environment. /
222	#define CIDETMODE_ENV_V86 UINT8_C(0x80) /*< V8086 environment. /
223	#define CIDETMODE_RM (CIDETMODE_MODE_RM \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_NORMAL)
224	#define CIDETMODE_PE_16 (CIDETMODE_MODE_PE \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_NORMAL)
225	#define CIDETMODE_PE_32 (CIDETMODE_MODE_PE \| CIDETMODE_BIT_32 \| CIDETMODE_ENV_NORMAL)
226	#define CIDETMODE_PE_V86 (CIDETMODE_MODE_PE \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_V86)
227	#define CIDETMODE_PP_16 (CIDETMODE_MODE_PP \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_NORMAL)
228	#define CIDETMODE_PP_32 (CIDETMODE_MODE_PP \| CIDETMODE_BIT_32 \| CIDETMODE_ENV_NORMAL)
229	#define CIDETMODE_PP_V86 (CIDETMODE_MODE_PP \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_V86)
230	#define CIDETMODE_PAE_16 (CIDETMODE_MODE_PAE \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_NORMAL)
231	#define CIDETMODE_PAE_32 (CIDETMODE_MODE_PAE \| CIDETMODE_BIT_32 \| CIDETMODE_ENV_NORMAL)
232	#define CIDETMODE_PAE_V86 (CIDETMODE_MODE_PAE \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_V86)
233	#define CIDETMODE_LM_16 (CIDETMODE_MODE_LM \| CIDETMODE_BIT_16 \| CIDETMODE_ENV_NORMAL)
234	#define CIDETMODE_LM_32 (CIDETMODE_MODE_LM \| CIDETMODE_BIT_32 \| CIDETMODE_ENV_NORMAL)
235	#define CIDETMODE_LM_64 (CIDETMODE_MODE_LM \| CIDETMODE_BIT_64 \| CIDETMODE_ENV_NORMAL)
236	/** Test if @a a_bMode is a 16-bit mode. */
237	#define CIDETMODE_IS_16BIT(a_bMode) ( ((a_bMode) & CIDETMODE_BIT_MASK) == CIDETMODE_BIT_16 )
238	/** Test if @a a_bMode is a 32-bit mode. */
239	#define CIDETMODE_IS_32BIT(a_bMode) ( ((a_bMode) & CIDETMODE_BIT_MASK) == CIDETMODE_BIT_32 )
240	/** Test if @a a_bMode is a 64-bit mode. */
241	#define CIDETMODE_IS_64BIT(a_bMode) ( ((a_bMode) & CIDETMODE_BIT_MASK) == CIDETMODE_BIT_64 )
242	/** Get the instruction bit count. */
243	#define CIDETMODE_GET_BIT_COUNT(a_bMode) ( CIDETMODE_GET_BYTE_COUNT(a_bMode) * 8 )
244	/** Get the instruction byte count. */
245	#define CIDETMODE_GET_BYTE_COUNT(a_bMode) ( (a_bMode) & CIDETMODE_BIT_MASK )
246	/** Test if @a a_bMode long mode. */
247	#define CIDETMODE_IS_LM(a_bMode) ( ((a_bMode) & CIDETMODE_MODE_MASK) == CIDETMODE_MODE_LM )
248	/** Test if @a a_bMode some kind of protected mode. */
249	#define CIDETMODE_IS_PROT(a_bMode) ( ((a_bMode) & CIDETMODE_MODE_MASK) >= CIDETMODE_MODE_PE )
250
251	/** @} */
252
253
254	/** @name Test Configuration Flags.
255	* @{ */
256	#define CIDET_TESTCFG_SEG_PRF_CS UINT64_C(0x0000000000000001)
257	#define CIDET_TESTCFG_SEG_PRF_SS UINT64_C(0x0000000000000002)
258	#define CIDET_TESTCFG_SEG_PRF_DS UINT64_C(0x0000000000000004)
259	#define CIDET_TESTCFG_SEG_PRF_ES UINT64_C(0x0000000000000008)
260	#define CIDET_TESTCFG_SEG_PRF_FS UINT64_C(0x0000000000000010)
261	#define CIDET_TESTCFG_SEG_PRF_GS UINT64_C(0x0000000000000020)
262	#define CIDET_TESTCFG_SEG_PRF_MASK UINT64_C(0x000000000000003f)
263	/** @} */
264
265	/** */
266	typedef enum CIDETREG
267	{
268	kCidetReg_Gpr_Invalid = 0,
269
270	kCidetReg_Gpr_al,
271	kCidetReg_Gpr_cl,
272	kCidetReg_Gpr_dl,
273	kCidetReg_Gpr_bl,
274	kCidetReg_Gpr_spl,
275	kCidetReg_Gpr_bpl,
276	kCidetReg_Gpr_sil,
277	kCidetReg_Gpr_dil,
278	kCidetReg_Gpr_r8b,
279	kCidetReg_Gpr_r9b,
280	kCidetReg_Gpr_r10b,
281	kCidetReg_Gpr_r11b,
282	kCidetReg_Gpr_r12b,
283	kCidetReg_Gpr_r13b,
284	kCidetReg_Gpr_r14b,
285	kCidetReg_Gpr_r15b,
286	kCidetReg_Gpr_ah,
287	kCidetReg_Gpr_ch,
288	kCidetReg_Gpr_dh,
289	kCidetReg_Gpr_bh,
290	#define kCidetReg_Gpr_Byte_First kCidetReg_Gpr_al
291	#define kCidetReg_Gpr_Byte_First_Upper kCidetReg_Gpr_ah
292	#define kCidetReg_Gpr_Byte_Last kCidetReg_Gpr_bh
293
294	kCidetReg_Gpr_ax,
295	kCidetReg_Gpr_cx,
296	kCidetReg_Gpr_dx,
297	kCidetReg_Gpr_bx,
298	kCidetReg_Gpr_sp,
299	kCidetReg_Gpr_bp,
300	kCidetReg_Gpr_si,
301	kCidetReg_Gpr_di,
302	kCidetReg_Gpr_r8w,
303	kCidetReg_Gpr_r9w,
304	kCidetReg_Gpr_r10w,
305	kCidetReg_Gpr_r11w,
306	kCidetReg_Gpr_r12w,
307	kCidetReg_Gpr_r13w,
308	kCidetReg_Gpr_r14w,
309	kCidetReg_Gpr_r15w,
310	#define kCidetReg_Gpr_Word_First kCidetReg_Gpr_ax
311	#define kCidetReg_Gpr_Word_Last kCidetReg_Gpr_r15w
312
313	kCidetReg_Gpr_eax,
314	kCidetReg_Gpr_ecx,
315	kCidetReg_Gpr_edx,
316	kCidetReg_Gpr_ebx,
317	kCidetReg_Gpr_esp,
318	kCidetReg_Gpr_ebp,
319	kCidetReg_Gpr_esi,
320	kCidetReg_Gpr_edi,
321	kCidetReg_Gpr_r8d,
322	kCidetReg_Gpr_r9d,
323	kCidetReg_Gpr_r10d,
324	kCidetReg_Gpr_r11d,
325	kCidetReg_Gpr_r12d,
326	kCidetReg_Gpr_r13d,
327	kCidetReg_Gpr_r14d,
328	kCidetReg_Gpr_r15d,
329	#define kCidetReg_Gpr_DWord_First kCidetReg_Gpr_eax
330	#define kCidetReg_Gpr_DWord_Last kCidetReg_Gpr_r15d
331
332	kCidetReg_Gpr_rax,
333	kCidetReg_Gpr_rcx,
334	kCidetReg_Gpr_rdx,
335	kCidetReg_Gpr_rbx,
336	kCidetReg_Gpr_rsp,
337	kCidetReg_Gpr_rbp,
338	kCidetReg_Gpr_rsi,
339	kCidetReg_Gpr_rdi,
340	kCidetReg_Gpr_r8,
341	kCidetReg_Gpr_r9,
342	kCidetReg_Gpr_r10,
343	kCidetReg_Gpr_r11,
344	kCidetReg_Gpr_r12,
345	kCidetReg_Gpr_r13,
346	kCidetReg_Gpr_r14,
347	kCidetReg_Gpr_r15,
348	#define kCidetReg_Gpr_QWord_First kCidetReg_Gpr_rax
349	#define kCidetReg_Gpr_QWord_Last kCidetReg_Gpr_r15
350
351	kCidetReg_Seg_es,
352	kCidetReg_Seg_cs,
353	kCidetReg_Seg_ss,
354	kCidetReg_Seg_ds,
355	kCidetReg_Seg_fs,
356	kCidetReg_Seg_gs,
357	kCidetReg_Seg_Inv6,
358	kCidetReg_Seg_Inv7,
359	#define kCidetReg_Seg_First kCidetReg_Seg_es
360	#define kCidetReg_Seg_Last kCidetReg_Seg_gs
361	#define kCidetReg_Seg_Last_Inv kCidetReg_Seg_Inv7
362
363	kCidetReg_Misc_ip,
364	kCidetReg_Misc_eip,
365	kCidetReg_Misc_rip,
366	kCidetReg_Misc_flags,
367	kCidetReg_Misc_eflags,
368	kCidetReg_Misc_rflags,
369	kCidetReg_Misc_tr,
370	kCidetReg_Misc_ldtr,
371	kCidetReg_Misc_gdtr,
372	kCidetReg_Misc_idtr,
373
374	kCidetReg_Ctrl_cr0,
375	kCidetReg_Ctrl_cr1,
376	kCidetReg_Ctrl_cr2,
377	kCidetReg_Ctrl_cr3,
378	kCidetReg_Ctrl_cr4,
379	kCidetReg_Ctrl_cr5,
380	kCidetReg_Ctrl_cr6,
381	kCidetReg_Ctrl_cr7,
382	kCidetReg_Ctrl_cr8,
383	kCidetReg_Ctrl_cr9,
384	kCidetReg_Ctrl_cr10,
385	kCidetReg_Ctrl_cr11,
386	kCidetReg_Ctrl_cr12,
387	kCidetReg_Ctrl_cr13,
388	kCidetReg_Ctrl_cr14,
389	kCidetReg_Ctrl_cr15,
390	#define kCidetReg_Ctrl_First kCidetReg_Ctrl_cr0
391	#define kCidetReg_Ctrl_Last kCidetReg_Ctrl_cr15
392	#define CIDETREG_CTRL_IS_VALID(a_iReg) ( (a_iReg) == kCidetReg_Ctrl_cr0 \
393	&& (a_iReg) == kCidetReg_Ctrl_cr2 \
394	&& (a_iReg) == kCidetReg_Ctrl_cr3 \
395	&& (a_iReg) == kCidetReg_Ctrl_cr4 \
396	&& (a_iReg) == kCidetReg_Ctrl_cr8 )
397
398	kCidetReg_Dbg_dr0,
399	kCidetReg_Dbg_dr1,
400	kCidetReg_Dbg_dr2,
401	kCidetReg_Dbg_dr3,
402	kCidetReg_Dbg_dr4,
403	kCidetReg_Dbg_dr5,
404	kCidetReg_Dbg_dr6,
405	kCidetReg_Dbg_dr7,
406	kCidetReg_Dbg_dr8,
407	kCidetReg_Dbg_dr9,
408	kCidetReg_Dbg_dr10,
409	kCidetReg_Dbg_dr11,
410	kCidetReg_Dbg_dr12,
411	kCidetReg_Dbg_dr13,
412	kCidetReg_Dbg_dr14,
413	kCidetReg_Dbg_dr15,
414	#define kCidetReg_Dbg_First kCidetReg_Dbg_dr0
415	#define kCidetReg_Dbg_Last kCidetReg_Dbg_dr15
416	#define CIDETREG_DBG_IS_VALID(a_iReg) ((a_iReg) < kCidetReg_Dbg_dr8 && (a_iReg) >= kCidetReg_Dbg_First)
417
418	kCidetReg_Test_tr0,
419	kCidetReg_Test_tr1,
420	kCidetReg_Test_tr2,
421	kCidetReg_Test_tr3,
422	kCidetReg_Test_tr4,
423	kCidetReg_Test_tr5,
424	kCidetReg_Test_tr6,
425	kCidetReg_Test_tr7,
426	kCidetReg_Test_tr8,
427	kCidetReg_Test_tr9,
428	kCidetReg_Test_tr10,
429	kCidetReg_Test_tr11,
430	kCidetReg_Test_tr12,
431	kCidetReg_Test_tr13,
432	kCidetReg_Test_tr14,
433	kCidetReg_Test_tr15,
434	#define kCidetReg_Test_First kCidetReg_Test_tr0
435	#define kCidetReg_Test_Last kCidetReg_Test_tr15
436
437	kCidetReg_Fpu_st0,
438	kCidetReg_Fpu_st1,
439	kCidetReg_Fpu_st2,
440	kCidetReg_Fpu_st3,
441	kCidetReg_Fpu_st4,
442	kCidetReg_Fpu_st5,
443	kCidetReg_Fpu_st6,
444	kCidetReg_Fpu_st7,
445	#define kCidetReg_Fpu_First kCidetReg_Mmx_st0
446	#define kCidetReg_Fpu_Last kCidetReg_Mmx_st7
447
448	kCidetReg_FpuMisc_cs,
449	kCidetReg_FpuMisc_ip,
450	kCidetReg_FpuMisc_ds,
451	kCidetReg_FpuMisc_dp,
452	kCidetReg_FpuMisc_fop,
453	kCidetReg_FpuMisc_ftw,
454	kCidetReg_FpuMisc_fsw,
455	kCidetReg_FpuMisc_fcw,
456	kCidetReg_FpuMisc_mxcsr_mask,
457	kCidetReg_FpuMisc_mxcsr,
458
459	kCidetReg_Mmx_mm0,
460	kCidetReg_Mmx_mm1,
461	kCidetReg_Mmx_mm2,
462	kCidetReg_Mmx_mm3,
463	kCidetReg_Mmx_mm4,
464	kCidetReg_Mmx_mm5,
465	kCidetReg_Mmx_mm6,
466	kCidetReg_Mmx_mm7,
467	#define kCidetReg_Mmx_First kCidetReg_Mmx_mm0
468	#define kCidetReg_Mmx_Last kCidetReg_Mmx_mm7
469
470	kCidetReg_Sse_xmm0,
471	kCidetReg_Sse_xmm1,
472	kCidetReg_Sse_xmm2,
473	kCidetReg_Sse_xmm3,
474	kCidetReg_Sse_xmm4,
475	kCidetReg_Sse_xmm5,
476	kCidetReg_Sse_xmm6,
477	kCidetReg_Sse_xmm7,
478	kCidetReg_Sse_xmm8,
479	kCidetReg_Sse_xmm9,
480	kCidetReg_Sse_xmm10,
481	kCidetReg_Sse_xmm11,
482	kCidetReg_Sse_xmm12,
483	kCidetReg_Sse_xmm13,
484	kCidetReg_Sse_xmm14,
485	kCidetReg_Sse_xmm15,
486	kCidetReg_Sse_xmm16,
487	kCidetReg_Sse_xmm17,
488	kCidetReg_Sse_xmm18,
489	kCidetReg_Sse_xmm19,
490	kCidetReg_Sse_xmm20,
491	kCidetReg_Sse_xmm21,
492	kCidetReg_Sse_xmm22,
493	kCidetReg_Sse_xmm23,
494	kCidetReg_Sse_xmm24,
495	kCidetReg_Sse_xmm25,
496	kCidetReg_Sse_xmm26,
497	kCidetReg_Sse_xmm27,
498	kCidetReg_Sse_xmm28,
499	kCidetReg_Sse_xmm29,
500	kCidetReg_Sse_xmm30,
501	kCidetReg_Sse_xmm31,
502	#define kCidetReg_Sse_First kCidetReg_Mmx_Xmm0
503	#define kCidetReg_Sse_Last kCidetReg_Mmx_Xmm15
504	#define kCidetReg_Sse_Last_Avx512 kCidetReg_Mmx_Xmm31
505
506	kCidetReg_Avx_Ymm0,
507	kCidetReg_Avx_Ymm1,
508	kCidetReg_Avx_Ymm2,
509	kCidetReg_Avx_Ymm3,
510	kCidetReg_Avx_Ymm4,
511	kCidetReg_Avx_Ymm5,
512	kCidetReg_Avx_Ymm6,
513	kCidetReg_Avx_Ymm7,
514	kCidetReg_Avx_Ymm8,
515	kCidetReg_Avx_Ymm9,
516	kCidetReg_Avx_Ymm10,
517	kCidetReg_Avx_Ymm11,
518	kCidetReg_Avx_Ymm12,
519	kCidetReg_Avx_Ymm13,
520	kCidetReg_Avx_Ymm14,
521	kCidetReg_Avx_Ymm15,
522	kCidetReg_Avx_Ymm16,
523	kCidetReg_Avx_Ymm17,
524	kCidetReg_Avx_Ymm18,
525	kCidetReg_Avx_Ymm19,
526	kCidetReg_Avx_Ymm20,
527	kCidetReg_Avx_Ymm21,
528	kCidetReg_Avx_Ymm22,
529	kCidetReg_Avx_Ymm23,
530	kCidetReg_Avx_Ymm24,
531	kCidetReg_Avx_Ymm25,
532	kCidetReg_Avx_Ymm26,
533	kCidetReg_Avx_Ymm27,
534	kCidetReg_Avx_Ymm28,
535	kCidetReg_Avx_Ymm29,
536	kCidetReg_Avx_Ymm30,
537	kCidetReg_Avx_Ymm31,
538	#define kCidetReg_Avx_First kCidetReg_Avx_Ymm0
539	#define kCidetReg_Avx_Last kCidetReg_Avx_Ymm15
540	#define kCidetReg_Avx_Last_Avx512 kCidetReg_Avx_Ymm31
541
542	kCidetReg_Avx512_Zmm0,
543	kCidetReg_Avx512_Zmm1,
544	kCidetReg_Avx512_Zmm2,
545	kCidetReg_Avx512_Zmm3,
546	kCidetReg_Avx512_Zmm4,
547	kCidetReg_Avx512_Zmm5,
548	kCidetReg_Avx512_Zmm6,
549	kCidetReg_Avx512_Zmm7,
550	kCidetReg_Avx512_Zmm8,
551	kCidetReg_Avx512_Zmm9,
552	kCidetReg_Avx512_Zmm10,
553	kCidetReg_Avx512_Zmm11,
554	kCidetReg_Avx512_Zmm12,
555	kCidetReg_Avx512_Zmm13,
556	kCidetReg_Avx512_Zmm14,
557	kCidetReg_Avx512_Zmm15,
558	kCidetReg_Avx512_Zmm16,
559	kCidetReg_Avx512_Zmm17,
560	kCidetReg_Avx512_Zmm18,
561	kCidetReg_Avx512_Zmm19,
562	kCidetReg_Avx512_Zmm20,
563	kCidetReg_Avx512_Zmm21,
564	kCidetReg_Avx512_Zmm22,
565	kCidetReg_Avx512_Zmm23,
566	kCidetReg_Avx512_Zmm24,
567	kCidetReg_Avx512_Zmm25,
568	kCidetReg_Avx512_Zmm26,
569	kCidetReg_Avx512_Zmm27,
570	kCidetReg_Avx512_Zmm28,
571	kCidetReg_Avx512_Zmm29,
572	kCidetReg_Avx512_Zmm30,
573	kCidetReg_Avx512_Zmm31,
574	#define kCidetReg_Avx512_First kCidetReg_Avx512_Zmm0
575	#define kCidetReg_Avx512_Last kCidetReg_Avx512_Zmm31
576
577	kCidetReg_End
578	} CIDETREG;
579
580
581	/** @name CIDETBUF_XXX - buffer flags.
582	* @{ */
583	#define CIDETBUF_PROT_MASK UINT32_C(0x0000000f) /*< Page protection mask. /
584	#define CIDETBUF_PROT_RWX UINT32_C(0x00000001) /*< Read + write + execute. /
585	#define CIDETBUF_PROT_RWNX UINT32_C(0x00000002) /*< Read + write + no execute. /
586	#define CIDETBUF_PROT_RX UINT32_C(0x00000003) /*< Read + execute. /
587	#define CIDETBUF_PROT_RNX UINT32_C(0x00000004) /*< Read + no execute. /
588	#define CIDETBUF_PROT_RWX_1NP UINT32_C(0x00000005) /*< Read + write + execute; 1 page not present. /
589	#define CIDETBUF_PROT_RWX_1RWNX UINT32_C(0x00000006) /*< Read + write + execute; 1 page read + write + no execute. /
590	#define CIDETBUF_PROT_RWX_1RNX UINT32_C(0x00000007) /*< Read + write + execute; 1 page read + no execute. /
591	#define CIDETBUF_PROT_RWX_1RWXS UINT32_C(0x00000008) /*< Read + write + execute; 1 page read + execute + supervisor. /
592
593	#define CIDETBUF_LOC_MASK UINT32_C(0x000000f0) /*< Location mask. /
594	/** Buffer located at top and start of the 32-bit address space. */
595	#define CIDETBUF_LOC_32BIT_WRAP UINT32_C(0x00000010)
596	/** Buffer located at the low canonical boundrary (AMD64). */
597	#define CIDETBUF_LOC_CANON_LO UINT32_C(0x00000020)
598	/** Buffer located at the high canonical boundrary (AMD64). */
599	#define CIDETBUF_LOC_CANON_HI UINT32_C(0x00000030)
600
601	/** Segment protection mask. */
602	#define CIDETBUF_SEG_MASK UINT32_C(0x00000f00)
603	#define CIDETBUF_SEG_EO UINT32_C(0x00000100) /*< Execute only /
604	#define CIDETBUF_SEG_ER UINT32_C(0x00000200) /*< Execute + read /
605	#define CIDETBUF_SEG_EO_CONF UINT32_C(0x00000300) /*< Execute only + conforming. /
606	#define CIDETBUF_SEG_ER_CONF UINT32_C(0x00000400) /*< Execute + read + conforming. /
607	#define CIDETBUF_SEG_RO UINT32_C(0x00000500) /*< Read only. /
608	#define CIDETBUF_SEG_RW UINT32_C(0x00000600) /*< Read + write. /
609	#define CIDETBUF_SEG_RO_DOWN UINT32_C(0x00000700) /*< Read only + expand down. /
610	#define CIDETBUF_SEG_RW_DOWN UINT32_C(0x00000800) /*< Read + write + expand down. /
611
612	#define CIDETBUF_DPL_MASK UINT32_C(0x00003000) /*< DPL mask. /
613	#define CIDETBUF_DPL_0 UINT32_C(0x00000000) /*< DPL=0. /
614	#define CIDETBUF_DPL_1 UINT32_C(0x00001000) /*< DPL=1. /
615	#define CIDETBUF_DPL_2 UINT32_C(0x00002000) /*< DPL=2. /
616	#define CIDETBUF_DPL_3 UINT32_C(0x00003000) /*< DPL=3. /
617	#define CIDETBUF_DPL_SAME UINT32_C(0x00004000) /*< Same DPL as the execution environment. /
618
619	#define CIDETBUF_SEG_LIMIT_BASE_CAP UINT32_C(0x00008000) /*< Capability to change segment limit and base. /
620
621	#define CIDETBUF_KIND_DATA UINT32_C(0x00000000) /*< Data buffer. /
622	#define CIDETBUF_KIND_CODE UINT32_C(0x80000000) /*< Code buffer. /
623	/** Checks if @a a_fFlags describes a code buffer. */
624	#define CIDETBUF_IS_CODE(a_fFlags) (((a_fFlags) & CIDETBUF_KIND_CODE) != 0)
625	/** Checks if @a a_fFlags describes a data buffer. */
626	#define CIDETBUF_IS_DATA(a_fFlags) (((a_fFlags) & CIDETBUF_KIND_CODE) == 0)
627	/** @} */
628
629	/** Code buffer size. (At least two pages.) */
630	#define CIDET_CODE_BUF_SIZE (PAGE_SIZE * 2)
631	/** Data buffer size. (At least two pages.) */
632	#define CIDET_DATA_BUF_SIZE (PAGE_SIZE * 3)
633
634
635	/**
636	* Detailed expected exception.
637	*
638	* This is used to internally in the core to calculate the expected exception
639	* considering all the things that may cause exceptions.
640	*/
641	typedef enum CIDETEXPECTXCPT
642	{
643	kCidetExpectXcpt_Invalid = 0,
644	/** No exception expected. */
645	kCidetExpectXcpt_None,
646
647	/** Page not present. */
648	kCidetExpectXcpt_PageNotPresent,
649	/** Write access to a non-writable page. */
650	kCidetExpectXcpt_PageNotWritable,
651	/** Executable access to a non-executable page. */
652	kCidetExpectXcpt_PageNotExecutable,
653	/** Access to supervisor page from user mode code. */
654	kCidetExpectXcpt_PagePrivileged,
655	#define kCidetExpectXcpt_First_PageFault kCidetExpectXcpt_PageNotPresent
656	#define kCidetExpectXcpt_Last_PageFault kCidetExpectXcpt_PagePrivileged
657
658	/** Read or write access to an execute only segment. */
659	kCidetExpectXcpt_SegExecuteOnly,
660	/** Write to a read only or execute+read segment. */
661	kCidetExpectXcpt_SegNotWritable,
662	/** Exceeded the limit of a non-stack access. */
663	kCidetExpectXcpt_SegExceededLimit,
664	/** Non-canonical address via any segment other than the stack. */
665	kCidetExpectXcpt_AddrNotCanonical,
666	/** Misaligned 16 or 32 byte SSE or AVX operand. */
667	kCidetExpectXcpt_MisalignedSseAvx,
668	/** Privileged instruction. */
669	kCidetExpectXcpt_PrivilegedInstruction,
670	#define kCidetExpectXcpt_First_GeneralProtectionFault kCidetExpectXcpt_SegExecuteOnly
671	#define kCidetExpectXcpt_Last_GeneralProtectionFault kCidetExpectXcpt_PrivilegedInstruction
672
673	/** Exceeded the limit of a stack access. */
674	kCidetExpectXcpt_StackExceededLimit,
675	/** Non-canonical stack address. */
676	kCidetExpectXcpt_StackAddrNotCanonical,
677	#define kCidetExpectXcpt_First_StackFault kCidetExpectXcpt_StackExceededLimit
678	#define kCidetExpectXcpt_Last_StackFault kCidetExpectXcpt_StackAddrNotCanonical
679
680	/** Misaligned memory operand (and alignment checking is in effect) if AC is
681	* enabled (executing in ring-3). */
682	kCidetExpectXcpt_MisalignedIfAcEnabled,
683	/** Misaligned 16 byte memory operand resulting in \#AC if ring-3 and
684	* enable, otherwise \#GP(0). */
685	kCidetExpectXcpt_Misaligned16ByteAcEnabledOrGp,
686	#define kCidetExpectXcpt_First_AlignmentCheckFault kCidetExpectXcpt_MisalignedIfAcEnabled
687	#define kCidetExpectXcpt_Last_AlignmentCheckFault kCidetExpectXcpt_Misaligned16ByteAcEnabledOrGp
688
689	kCidetExpectXcpt_End
690	} CIDETEXPECTXCPT;
691
692
693	/**
694	* Buffer configuration.
695	*/
696	typedef struct CIDETBUFCFG
697	{
698	/** The name of this buffer configuration. */
699	const char *pszName;
700	/** The buffer flags (CIDETBUF_XXX) */
701	uint32_t fFlags;
702	} CIDETBUFCFG;
703	/** Pointer to a constant buffer configuration. */
704	typedef CIDETBUFCFG const *PCCIDETBUFCFG;
705
706
707	/**
708	* CIDET buffer for code or data.
709	*
710	* ASSUMES page aligned buffers.
711	*/
712	typedef struct CIDETBUF
713	{
714	/** @name Owned & modified by the front end.
715	* @{ */
716	/** Effective buffer address. */
717	uint64_t uEffBufAddr;
718	/** The segment base address. */
719	uint64_t uSegBase;
720	/** The active segment limit (see also cbSegLimit). UINT64_MAX if flat. */
721	uint64_t cbActiveSegLimit;
722	/** This specifies the selector to use if a non-flat segment limit or special
723	* segment flags was requested via pfnSetupBuf. UINT32_MAX if any segment is
724	* selector works. */
725	uint32_t uSeg;
726	/** The off value at the last pfnReinitBuf call. */
727	uint16_t offActive;
728	/** The cb value at the last pfnReinitBuf call. */
729	uint16_t cbActive;
730	/** Prologue (or front fence) size. */
731	uint16_t cbPrologue;
732	/** Epilogue (or tail fence) size. */
733	uint16_t cbEpilogue;
734	/** @} */
735
736	/** @name Set by the core before pfnReinitBuf call.
737	* @{ */
738	/** Pointer to the buffer config. */
739	PCCIDETBUFCFG pCfg;
740	/** The configuration index. */
741	uint32_t idxCfg;
742	/** The offset into the buffer of the data / code. */
743	uint16_t off;
744	/** The number of bytes of data / code. */
745	uint16_t cb;
746	/** The segment limit relative to the start of the buffer (last byte included
747	* in count). UINT16_MAX if maximum segment size should be used. */
748	uint16_t cbSegLimit;
749	/** Desired segment base offset.
750	* This is for checking where the alignment checks are performed. */
751	uint8_t offSegBase;
752
753	/** Set if this buffer is actively being used. */
754	bool fActive : 1;
755	/** The operand index (if data), 7 if not active. */
756	uint8_t idxOp : 3;
757	/** Code: Set if the expected exception is supposed to occur on the
758	* following insturction, not the instruction unter test. */
759	bool fXcptAfterInstruction : 1;
760	/** Set if the instruction will read from the buffer. */
761	bool fRead : 1;
762	/** Set if the instruction will write to the buffer. */
763	bool fWrite : 1;
764	/** The expected exception. */
765	CIDETEXPECTXCPT enmExpectXcpt;
766	/** @} */
767	} CIDETBUF;
768	/** Pointer to a CIDET buffer for code or data. */
769	typedef CIDETBUF *PCIDETBUF;
770
771
772	/**
773	* CPU Instruction Decoding & Execution Testing (CIDET) state.
774	*/
775	typedef struct CIDETCORE
776	{
777	/** Magic number (CIDETCORE_MAGIC). */
778	uint32_t u32Magic;
779
780	/** The target CPU mode / environment. */
781	uint8_t bMode;
782	/** The target ring. */
783	uint8_t iRing;
784	/** Unused padding bytes. */
785	uint8_t abPadding1[2];
786
787	/** Test configuration. */
788	uint64_t fTestCfg;
789
790	/** Code buffer configurations to test.
791	* The first buffer must be a normal buffer that does not cause any problems. */
792	PCCIDETBUFCFG paCodeBufConfigs;
793	/** The number of code buffer configurations to test (pafCodeBufConfigs). */
794	uint32_t cCodeBufConfigs;
795	/** The number of data buffer configurations to test (pafDataBufConfigs). */
796	uint32_t cDataBufConfigs;
797	/** Data buffer configurations to test.
798	* The first buffer must be a normal buffer that does not cause any problems. */
799	PCCIDETBUFCFG paDataBufConfigs;
800
801	/** The instruction currently under testing. */
802	PCCIDETINSTR pCurInstr;
803
804	/** Primary data buffer. */
805	CIDETBUF DataBuf;
806	/** Secondary data buffer. */
807	CIDETBUF DataBuf2;
808
809	/** Handle to the random number source. */
810	RTRAND hRand;
811
812	/**
813	* Re-initializes one of the data buffers.
814	*
815	* @returns true on succes, false if the request cannot be satisfied.
816	* @param pThis The core state.
817	* @param pBuf Pointer to the buffer structure.
818	*/
819	DECLCALLBACKMEMBER(bool, pfnReInitDataBuf,(struct CIDETCORE *pThis, PCIDETBUF pBuf));
820
821	/**
822	* Copies bytes into the data buffer and sets it up for execution.
823	*
824	* @returns true on succes, false if the request cannot be satisfied.
825	* @param pThis The core state.
826	* @param pBuf Pointer to the buffer structure.
827	* @param pvSrc The source bytes (size and destination offset
828	* given in pfnReinitBuf call).
829	*/
830	DECLCALLBACKMEMBER(bool, pfnSetupDataBuf,(struct CIDETCORE pThis, PCIDETBUF pBuf, void const pvSrc));
831
832	/**
833	* Compares buffer content after test execution.
834	*
835	* This also checks any fill bytes in the buffer that the front end may
836	* have put up. The front end will double buffer the content of supposedly
837	* inaccessible pages as well as non-existing pages to simplify things for
838	* the core code.
839	*
840	* @returns true if equal, false if not.
841	* @param pThis The core state.
842	* @param pBuf Pointer to the buffer structure.
843	* @param pvExpected Pointer to the expected source bytes (size and
844	* buffer offset given in pfnReinitBuf call).
845	*/
846	DECLCALLBACKMEMBER(bool, pfnIsBufEqual,(struct CIDETCORE pThis, struct CIDETBUF pBuf, void const *pvExpected));
847
848	/**
849	* Re-initializes the code buffer.
850	*
851	* @returns true on succes, false if the request cannot be satisfied.
852	* @param pThis The core state.
853	* @param pBuf Pointer to the CodeBuf member. The off and cb
854	* members represent what the core wants to
855	* execute.
856	*/
857	DECLCALLBACKMEMBER(bool, pfnReInitCodeBuf,(struct CIDETCORE *pThis, PCIDETBUF pBuf));
858
859	/**
860	* Emit code into the code buffer, making everything ready for pfnExecute.
861	*
862	* @returns VBox status code.
863	* @param pThis Pointer to the core structure.
864	* @param pBuf Pointer to the CodeBuf member.
865	* @param pvInstr Pointer to the encoded instruction bytes.
866	*/
867	DECLCALLBACKMEMBER(bool, pfnSetupCodeBuf,(struct CIDETCORE pThis, PCIDETBUF pBuf, void const pvInstr));
868
869	/**
870	* Executes the code indicated by InCtx, returning the result in ActualCtx.
871	*
872	* @returns true if execute, false if skipped.
873	* @param pThis Pointer to the core structure.
874	*/
875	DECLCALLBACKMEMBER(bool, pfnExecute,(struct CIDETCORE *pThis));
876
877	/**
878	* Report a test failure.
879	*
880	* @param pThis Pointer to the core structure.
881	* @param pszFormat Format string containing failure details.
882	* @param va Arguments referenced in @a pszFormat.
883	*/
884	DECLCALLBACKMEMBER(void, pfnFailure,(struct CIDETCORE pThis, const char pszFormat, va_list va));
885
886	/** Array of indexes for use by FNCIDETSETUPINOUT.
887	* Reset when changing instruction or switching between valid and invalid
888	* inputs. */
889	uint32_t aiInOut[4];
890
891	/** @name Copyied and extracted instruction information.
892	* @{ */
893	/** The flags (CIDET_OF_XXX) for the MODRM.REG operand, 0 if not applicable. */
894	uint32_t fMrmRegOp;
895	/** The flags (CIDET_OF_XXX) for the MODRM.RM operand, 0 if not applicable. */
896	uint32_t fMrmRmOp;
897	/** Instruction flags (CIDETINSTR::fFlags). */
898	uint64_t fInstrFlags;
899	/** Number of operands (CIDETINSTR::cOperands). */
900	uint8_t cOperands;
901	/** Number of memory operands (set by CidetCoreSetupFirstMemoryOperandConfig). */
902	uint8_t cMemoryOperands : 3;
903	/** Set if we're working on a MOD R/M byte. */
904	bool fUsesModRm : 1;
905	/** The index of the MODRM.REG operand, 7 if not applicable. */
906	uint8_t idxMrmRegOp : 3;
907	/** The index of the MODRM.RM operand, 7 if not applicable. */
908	uint8_t idxMrmRmOp : 3;
909	/** Set if the SIB byte uses VEX registers for indexing. */
910	bool fUsesVexIndexRegs : 1;
911	/** @} */
912
913	/** @name Basic encoding knobs, wheels and indicators.
914	* @{ */
915	/** Set if we're working on a SIB byte. */
916	bool fSib : 1;
917	/** Required segment prefix (X86_SREG_XXX), X86_SREG_COUNT if not. */
918	uint8_t uSegPrf : 3;
919	/** The address size prefix. */
920	bool fAddrSizePrf : 1;
921	/** The operand size prefix. */
922	bool fOpSizePrf : 1;
923	/** The REX.W prefix value. */
924	bool fRexW : 1;
925	/** The REX.R prefix value. */
926	bool fRexR : 1;
927	/** The REX.X prefix value. */
928	bool fRexX : 1;
929	/** The REX.B prefix value. */
930	bool fRexB : 1;
931	/** Set if a REX prefix is required with or without flags (for byte regs). */
932	bool fRex : 1;
933	/** Use VEX encoding. */
934	bool fVex : 1;
935	/** Use EVEX encoding. */
936	bool fEvex : 1;
937	/** Indicator: Effective addressing mode in bytes (2, 4, 8). */
938	uint8_t cbAddrMode : 4;
939	/** Indicator: Set if there is an operand accessing memory. */
940	bool fHasMemoryOperand : 1;
941	/** Indicator: Set if a register is used in two or more operands, and one of
942	* them being for addressing. */
943	bool fHasRegCollisionMem : 1;
944	/** Indicator: Helper indicator for tracking SIB.BASE collision. */
945	bool fHasRegCollisionMemBase : 1;
946	/** Indicator: Helper indicator for tracking SIB.INDEX collision. */
947	bool fHasRegCollisionMemIndex : 1;
948	/** Indicator: Set if a register is used directly in more than one operand. */
949	bool fHasRegCollisionDirect : 1;
950
951	/** Indicator: Set if MODRM.REG is the stack register. */
952	bool fHasStackRegInMrmReg : 1;
953	/** Indicator: Set if MODRM.RM or SIB.BASE is the stack register. */
954	bool fHasStackRegInMrmRmBase: 1;
955
956	/** Indicator: High byte-register specified by MODRM.REG. */
957	bool fHasHighByteRegInMrmReg : 1;
958	/** Indicator: High byte-register specified by MODRM.RM. */
959	bool fHasHighByteRegInMrmRm : 1;
960	/** Indicator: Set if REX prefixes are incompatible with the byte-register
961	* specified by MODRM.REG. */
962	bool fNoRexPrefixMrmReg : 1;
963	/** Indicator: Set if REX prefixes are incompatible with the byte-register
964	* specified by MODRM.RM. */
965	bool fNoRexPrefixMrmRm : 1;
966	/** Indicator: fNoRexPrefixMrmReg \|\| fNoRexPrefixMrmMr. */
967	bool fNoRexPrefix : 1;
968	/** The MOD R/M byte we're working on (if fUsesModRm is set). */
969	uint8_t bModRm;
970	/** The SIB/VSIB byte we're working on (if fSib is set). */
971	uint8_t bSib;
972	/** @} */
973
974	/** The effective instruction address. (See InCtx.rip and InCtx.cs for the
975	* rest of the instruction addressing stuff.) */
976	uint64_t uInstrEffAddr;
977
978	/** Operand information, mainly for the FNCIDETSETUPINOUT and similar. */
979	struct
980	{
981	/** The operand flags copied from (CIDETINSTR::afOperands). */
982	uint32_t fFlags;
983	/** The encoded register number, if register, UINT8_MAX if not. */
984	uint8_t iReg;
985	/** The actual operand size (encoded). */
986	uint8_t cb;
987	/** Set if immediate value. */
988	bool fIsImmediate : 1;
989	/** Set if memory access. */
990	bool fIsMem : 1;
991	/** Set if addressing is relative to RIP. */
992	bool fIsRipRelative : 1;
993	/** Set if it's a high byte register. */
994	bool fIsHighByteRegister : 1;
995	/** Size of the disposition, 0 if none. */
996	uint8_t cbMemDisp;
997	/** Base register, UINT8_MAX if not applicable. */
998	uint8_t iMemBaseReg;
999	/** Index register, UINT8_MAX if not applicable. */
1000	uint8_t iMemIndexReg;
1001	/** Index register, 1 if not applicable. */
1002	uint8_t uMemScale;
1003	/** Effective segment register, UINT8_MAX if not memory access. */
1004	uint8_t iEffSeg;
1005	/** Segment offset if memory access. Undefined if not memory access. */
1006	uint64_t offSeg;
1007	/** The effective address if memory access. */
1008	uint64_t uEffAddr;
1009	/** Immediate or displacement value. */
1010	uint64_t uImmDispValue;
1011	/** Base register value, undefined if irrelevant. */
1012	uint64_t uMemBaseRegValue;
1013	/** Index register value, undefined if irrelevant. */
1014	uint64_t uMemIndexRegValue;
1015	/** Points to where the input data for this operand should be placed,
1016	* when possible. In the fIsMem = true case, it either points directly
1017	* to the input buffer or to a temporary one. While in the other case,
1018	* it'll point into InCtx when possible. */
1019	RTPTRUNION In;
1020	/** Points to where the expected output data for this operand should be
1021	* stored, when possible. In the fIsMem = false case, it'll point into
1022	* ExpectedCtx when possible. */
1023	RTPTRUNION Expected;
1024	/** Pointer to the data buffer for this operand. */
1025	PCIDETBUF pDataBuf;
1026	} aOperands[4];
1027
1028	/** Buffer where we assemble the instruction. */
1029	uint8_t abInstr[45];
1030	/** The size of the instruction in abInstr. */
1031	uint8_t cbInstr;
1032	/** Offset of the instruction into the buffer. */
1033	uint16_t offInstr;
1034	/** Current code buffer. */
1035	CIDETBUF CodeBuf;
1036
1037	/** The input context. Initalized by driver and FNCIDETSETUPINOUT. */
1038	CIDETCPUCTX InCtx;
1039	/** The expected output context. */
1040	CIDETCPUCTX ExpectedCtx;
1041	/** The actual output context. */
1042	CIDETCPUCTX ActualCtx;
1043	/** Template input context, initialized when setting the mode. */
1044	CIDETCPUCTX InTemplateCtx;
1045
1046	/** Input and expected output temporary memory buffers. */
1047	uint8_t abBuf[0x2000];
1048
1049
1050	/** Number of skipped tests because of pfnSetupInOut failures. */
1051	uint32_t cSkippedSetupInOut;
1052	/** Number of skipped tests because of pfnReInitDataBuf failures. */
1053	uint32_t cSkippedReInitDataBuf;
1054	/** Number of skipped tests because of pfnSetupDataBuf failures. */
1055	uint32_t cSkippedSetupDataBuf;
1056	/** Number of skipped tests because RIP relative addressing constraints. */
1057	uint32_t cSkippedDataBufWrtRip;
1058	/** Number of skipped tests because of assemble failures. */
1059	uint32_t cSkippedAssemble;
1060	/** Number of skipped tests because of pfnReInitCodeBuf failures. */
1061	uint32_t cSkippedReInitCodeBuf;
1062	/** Number of skipped tests because of pfnSetupCodeBuf failures. */
1063	uint32_t cSkippedSetupCodeBuf;
1064	/** Number of skipped tests because the base and index registers are the same
1065	* one and there was a remainder when trying to point to the data buffer. */
1066	uint32_t cSkippedSameBaseIndexRemainder;
1067	/** Number of skipped tests because index-only addressing left a remainder. */
1068	uint32_t cSkippedOnlyIndexRemainder;
1069	/** Number of skipped tests because of direct addressing overflowed. */
1070	uint32_t cSkippedDirectAddressingOverflow;
1071
1072
1073	} CIDETCORE;
1074	/** Pointer to the CIDET core state. */
1075	typedef CIDETCORE *PCIDETCORE;
1076
1077	/** Magic number for CIDETCORE (Lee Konitz). */
1078	#define CIDETCORE_MAGIC UINT32_C(0x19271013)
1079
1080
1081	int CidetCoreInit(PCIDETCORE pThis, RTRAND hRand);
1082	void CidetCoreDelete(PCIDETCORE pThis);
1083	int CidetCoreSetTargetMode(PCIDETCORE pThis, uint8_t bMode);
1084	uint32_t CidetCoreGetOperandSize(PCIDETCORE pThis, uint8_t iOp);
1085	bool CidetCoreTestInstruction(PCIDETCORE pThis, PCCIDETINSTR pInstr);
1086
1087
1088	extern const CIDETINSTR g_aCidetInstructions1[];
1089	extern const uint32_t g_cCidetInstructions1;
1090
1091	#endif /* !VBOX_INCLUDED_SRC_cpu_cidet_h */
1092

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source: vbox/trunk/src/VBox/ValidationKit/utils/cpu/cidet.h@ 104195

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