VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-pit.c@ 102157

Last change on this file since 102157 was 100782, checked in by vboxsync, 17 months ago

bs3kit,bs3-timers-1: Extended the bs3-timers-1 testcase to check for interrupt delivery and inhibiting. bugref:10369

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File size: 5.9 KB
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1/* $Id: bs3-cmn-pit.c 100782 2023-08-03 01:15:55Z vboxsync $ */
2/** @file
3 * BS3Kit - PIT Setup and Disable code.
4 */
5
6/*
7 * Copyright (C) 2007-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
41#include "bs3kit-template-header.h"
42#include <iprt/asm-amd64-x86.h>
43
44
45/*********************************************************************************************************************************
46* Defined Constants And Macros *
47*********************************************************************************************************************************/
48#define BS3_PIT_PORT_CMD 0x43
49#define BS3_PIT_PORT_CH0_DATA 0x40
50#define BS3_PIT_HZ UINT32_C(1193182)
51
52
53/*********************************************************************************************************************************
54* External Symbols *
55*********************************************************************************************************************************/
56extern FNBS3TRAPHANDLER16 bs3PitIrqHandler_c16;
57extern FNBS3TRAPHANDLER32 bs3PitIrqHandler_c32;
58extern FNBS3TRAPHANDLER64 bs3PitIrqHandler_c64;
59
60
61#undef Bs3PitSetupAndEnablePeriodTimer
62BS3_CMN_DEF(void, Bs3PitSetupAndEnablePeriodTimer,(uint16_t cHzDesired))
63{
64 RTCCUINTREG fSaved;
65 uint16_t cCount;
66 uint16_t cMsInterval;
67 uint32_t cNsInterval;
68
69 /*
70 * Disable the PIT and make sure we've configured the IRQ handlers.
71 */
72 Bs3PitDisable();
73 Bs3PicSetup(false /*fForcedReInit*/);
74 Bs3TrapSetHandlerEx(0x70, bs3PitIrqHandler_c16, bs3PitIrqHandler_c32, bs3PitIrqHandler_c64);
75
76 /*
77 * Reset the counters and IRQ PC.
78 */
79 g_cBs3PitNs = 0;
80 g_cBs3PitMs = 0;
81 g_cBs3PitTicks = 0;
82 g_Bs3PitIrqRip.u = 0;
83
84 /*
85 * Calculate an interval.
86 */
87 if (cHzDesired <= 18)
88 {
89 cCount = 0; /* 1193182 / 65536 = 18.206512451171875 Hz */
90 cHzDesired = 18;
91 cNsInterval = UINT32_C(54925401); /* 65536 / 1193182 = 0.054925401154224586022920225078823 seconds */
92 cMsInterval = 55;
93 }
94 else
95 {
96 cCount = BS3_PIT_HZ / cHzDesired;
97 cHzDesired = BS3_PIT_HZ / cCount;
98 /* 1s/1193182 = 0.000 000 838 095 110 38550698887512550474278 */
99#if ARCH_BITS == 64
100 cNsInterval = cCount * UINT64_C(838095110) / 1000000;
101#elif ARCH_BITS == 32
102 cNsInterval = cCount * UINT32_C(8381) / 10;
103#else
104 cNsInterval = cCount * 838;
105#endif
106 if (cCount <= 1194)
107 cMsInterval = 1; /* Must not be zero! */
108 else
109 cMsInterval = cCount / 1194;
110 }
111
112
113 /*
114 * Do the reprogramming.
115 */
116 fSaved = ASMIntDisableFlags();
117 ASMOutU8(BS3_PIT_PORT_CMD,
118 (0 << 6) /* select: channel 0 */
119 | (3 << 4) /* access mode: lobyte/hibyte */
120 | (2 << 1) /* operation: Mode 2 */
121 | 0 /* binary mode */
122 );
123 ASMOutU8(BS3_PIT_PORT_CH0_DATA, (uint8_t)cCount);
124 ASMOutU8(BS3_PIT_PORT_CH0_DATA, (uint8_t)(cCount >> 8));
125
126 g_cBs3PitIntervalNs = cNsInterval;
127 g_cBs3PitIntervalHz = cHzDesired;
128 g_cBs3PitIntervalMs = cMsInterval;
129
130 Bs3PicUpdateMask(UINT16_C(0xfffe), 0);
131
132 ASMSetFlags(fSaved);
133}
134
135
136#undef Bs3PitDisable
137BS3_CMN_DEF(void, Bs3PitDisable,(void))
138{
139 if (g_cBs3PitIntervalHz != 0)
140 {
141 RTCCUINTREG fSaved = ASMIntDisableFlags();
142
143 /*
144 * Not entirely sure what's the best way to do this, but let's try reprogram
145 * it to a no-reload mode like 0 and set the count to 1.
146 */
147 g_cBs3PitIntervalMs = 0;
148 ASMOutU8(BS3_PIT_PORT_CMD,
149 (0 << 6) /* select: channel 0 */
150 | (1 << 4) /* access mode: lobyte */
151 | (0 << 1) /* operation: Mode 0 */
152 | 0 /* binary mode */
153 );
154 ASMOutU8(BS3_PIT_PORT_CH0_DATA, (uint8_t)1);
155
156 /*
157 * Then mask the PIT IRQ on the PIC.
158 */
159 Bs3PicUpdateMask(UINT16_C(0xffff), 1);
160
161 ASMSetFlags(fSaved);
162 }
163
164 /*
165 * Reset the interval values (leave the ticks and elapsed ns/ms values as-is).
166 */
167 g_cBs3PitIntervalNs = 0;
168 g_cBs3PitIntervalMs = 0;
169 g_cBs3PitIntervalHz = 0;
170}
171
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