1 | /* $Id: bs3-cmn-PagingQueryAddressInfo.c 93115 2022-01-01 11:31:46Z vboxsync $ */
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2 | /** @file
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3 | * BS3Kit - Bs3PagingQueryAddressInfo
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2007-2022 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * The contents of this file may alternatively be used under the terms
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18 | * of the Common Development and Distribution License Version 1.0
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19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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20 | * VirtualBox OSE distribution, in which case the provisions of the
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21 | * CDDL are applicable instead of those of the GPL.
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22 | *
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23 | * You may elect to license modified versions of this file under the
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24 | * terms and conditions of either the GPL or the CDDL or both.
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25 | */
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26 |
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27 |
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28 | /*********************************************************************************************************************************
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29 | * Header Files *
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30 | *********************************************************************************************************************************/
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31 | #include <bs3kit.h>
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32 | #include <iprt/asm-amd64-x86.h>
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33 | #include <VBox/err.h>
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34 |
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35 |
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36 | #undef Bs3PagingQueryAddressInfo
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37 | BS3_CMN_DEF(int, Bs3PagingQueryAddressInfo,(uint64_t uFlat, PBS3PAGINGINFO4ADDR pPgInfo))
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38 | {
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39 | RTCCUINTXREG const cr3 = ASMGetCR3();
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40 | RTCCUINTXREG const cr4 = g_uBs3CpuDetected & BS3CPU_F_CPUID ? ASMGetCR4() : 0;
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41 | bool const fLegacyPTs = !(cr4 & X86_CR4_PAE);
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42 | int rc = VERR_OUT_OF_RANGE;
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43 |
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44 |
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45 | pPgInfo->fFlags = 0;
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46 | pPgInfo->u.apbEntries[0] = NULL;
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47 | pPgInfo->u.apbEntries[1] = NULL;
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48 | pPgInfo->u.apbEntries[2] = NULL;
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49 | pPgInfo->u.apbEntries[3] = NULL;
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50 |
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51 | if (!fLegacyPTs)
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52 | {
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53 | #if TMPL_BITS == 16
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54 | uint32_t const uMaxAddr = BS3_MODE_IS_RM_OR_V86(g_bBs3CurrentMode) ? _1M - 1 : BS3_SEL_TILED_AREA_SIZE - 1;
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55 | #else
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56 | uintptr_t const uMaxAddr = ~(uintptr_t)0;
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57 | #endif
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58 | uint64_t const fEfer = g_uBs3CpuDetected & BS3CPU_F_LONG_MODE ? ASMRdMsr(MSR_K6_EFER) : 0;
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59 |
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60 | pPgInfo->cEntries = fEfer & MSR_K6_EFER_LMA ? 4 : 3;
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61 | pPgInfo->cbEntry = sizeof(X86PTEPAE);
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62 | if ((cr3 & X86_CR3_AMD64_PAGE_MASK) <= uMaxAddr)
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63 | {
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64 | if ( (fEfer & MSR_K6_EFER_LMA)
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65 | && X86_IS_CANONICAL(uFlat))
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66 | {
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67 | /* 48-bit long mode paging. */
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68 | pPgInfo->u.Pae.pPml4e = (X86PML4E BS3_FAR *)Bs3XptrFlatToCurrent(cr3 & X86_CR3_AMD64_PAGE_MASK);
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69 | pPgInfo->u.Pae.pPml4e += (uFlat >> X86_PML4_SHIFT) & X86_PML4_MASK;
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70 | if (!pPgInfo->u.Pae.pPml4e->n.u1Present)
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71 | rc = VERR_PAGE_NOT_PRESENT;
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72 | else if ((pPgInfo->u.Pae.pPml4e->u & X86_PML4E_PG_MASK) <= uMaxAddr)
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73 | {
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74 | pPgInfo->u.Pae.pPdpe = (X86PDPE BS3_FAR *)Bs3XptrFlatToCurrent(pPgInfo->u.Pae.pPml4e->u & X86_PML4E_PG_MASK);
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75 | pPgInfo->u.Pae.pPdpe += (uFlat >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
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76 | if (!pPgInfo->u.Pae.pPdpe->n.u1Present)
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77 | rc = VERR_PAGE_NOT_PRESENT;
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78 | else if (pPgInfo->u.Pae.pPdpe->b.u1Size)
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79 | rc = VINF_SUCCESS;
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80 | else
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81 | rc = VINF_TRY_AGAIN;
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82 | }
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83 | }
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84 | else if ( !(fEfer & MSR_K6_EFER_LMA)
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85 | && uFlat <= _4G)
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86 | {
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87 | /* 32-bit PAE paging. */
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88 | pPgInfo->u.Pae.pPdpe = (X86PDPE BS3_FAR *)Bs3XptrFlatToCurrent(cr3 & X86_CR3_PAE_PAGE_MASK);
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89 | pPgInfo->u.Pae.pPdpe += ((uint32_t)uFlat >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
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90 | if (!pPgInfo->u.Pae.pPdpe->n.u1Present)
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91 | rc = VERR_PAGE_NOT_PRESENT;
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92 | else
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93 | rc = VINF_TRY_AGAIN;
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94 | }
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95 |
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96 | /* Common code for the PD and PT levels. */
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97 | if ( rc == VINF_TRY_AGAIN
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98 | && (pPgInfo->u.Pae.pPdpe->u & X86_PDPE_PG_MASK) <= uMaxAddr)
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99 | {
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100 | rc = VERR_OUT_OF_RANGE;
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101 | pPgInfo->u.Pae.pPde = (X86PDEPAE BS3_FAR *)Bs3XptrFlatToCurrent(pPgInfo->u.Pae.pPdpe->u & X86_PDPE_PG_MASK);
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102 | pPgInfo->u.Pae.pPde += (uFlat >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
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103 | if (!pPgInfo->u.Pae.pPde->n.u1Present)
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104 | rc = VERR_PAGE_NOT_PRESENT;
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105 | else if (pPgInfo->u.Pae.pPde->b.u1Size)
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106 | rc = VINF_SUCCESS;
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107 | else if ((pPgInfo->u.Pae.pPde->u & X86_PDE_PAE_PG_MASK) <= uMaxAddr)
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108 | {
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109 | pPgInfo->u.Pae.pPte = (X86PTEPAE BS3_FAR *)Bs3XptrFlatToCurrent(pPgInfo->u.Pae.pPde->u & X86_PDE_PAE_PG_MASK);
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110 | rc = VINF_SUCCESS;
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111 | }
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112 | }
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113 | else if (rc == VINF_TRY_AGAIN)
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114 | rc = VERR_OUT_OF_RANGE;
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115 | }
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116 | }
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117 | else
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118 | {
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119 | #if TMPL_BITS == 16
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120 | uint32_t const uMaxAddr = BS3_MODE_IS_RM_OR_V86(g_bBs3CurrentMode) ? _1M - 1 : BS3_SEL_TILED_AREA_SIZE - 1;
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121 | #else
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122 | uint32_t const uMaxAddr = UINT32_MAX;
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123 | #endif
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124 |
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125 | pPgInfo->cEntries = 2;
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126 | pPgInfo->cbEntry = sizeof(X86PTE);
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127 | if ( uFlat < _4G
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128 | && cr3 <= uMaxAddr)
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129 | {
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130 | pPgInfo->u.Legacy.pPde = (X86PDE BS3_FAR *)Bs3XptrFlatToCurrent(cr3 & X86_CR3_PAGE_MASK);
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131 | pPgInfo->u.Legacy.pPde += ((uint32_t)uFlat >> X86_PD_SHIFT) & X86_PD_MASK;
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132 | if (!pPgInfo->u.Legacy.pPde->b.u1Present)
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133 | rc = VERR_PAGE_NOT_PRESENT;
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134 | else if (pPgInfo->u.Legacy.pPde->b.u1Size)
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135 | rc = VINF_SUCCESS;
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136 | else if (pPgInfo->u.Legacy.pPde->u <= uMaxAddr)
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137 | {
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138 | pPgInfo->u.Legacy.pPte = (X86PTE BS3_FAR *)Bs3XptrFlatToCurrent(pPgInfo->u.Legacy.pPde->u & X86_PDE_PG_MASK);
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139 | pPgInfo->u.Legacy.pPte += ((uint32_t)uFlat >> X86_PT_SHIFT) & X86_PT_MASK;
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140 | if (pPgInfo->u.Legacy.pPte->n.u1Present)
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141 | rc = VINF_SUCCESS;
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142 | else
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143 | rc = VERR_PAGE_NOT_PRESENT;
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144 | }
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145 | }
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146 | }
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147 | return rc;
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148 | }
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149 |
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