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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-timers-1-x0.c@ 104620

Last change on this file since 104620 was 100782, checked in by vboxsync, 16 months ago

bs3kit,bs3-timers-1: Extended the bs3-timers-1 testcase to check for interrupt delivery and inhibiting. bugref:10369
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1/* $Id: bs3-timers-1-x0.c 100782 2023-08-03 01:15:55Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-timers-1, C test driver code (16-bit).
4 */
5
6/*
7 * Copyright (C) 2007-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35 */
36
37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
41#define BS3_USE_X0_TEXT_SEG
42#include <bs3kit.h>
43#include <iprt/asm.h>
44#include <iprt/asm-amd64-x86.h>
45
46
47/*********************************************************************************************************************************
48* Structures and Typedefs *
49*********************************************************************************************************************************/
50typedef enum BS3TIMERSIRQLOOP
51{
52 BS3TIMERSIRQLOOP_INVALID = 0,
53 BS3TIMERSIRQLOOP_SIMPLE,
54 BS3TIMERSIRQLOOP_STI_HLT_CLI,
55 BS3TIMERSIRQLOOP_STI_STI_CLI,
56 BS3TIMERSIRQLOOP_POPF_CLI,
57 BS3TIMERSIRQLOOP_END
58} BS3TIMERSIRQLOOP;
59
60
61typedef enum BS3TIMERSNOIRQLOOP
62{
63 BS3TIMERSNOIRQLOOP_INVALID = 0,
64 BS3TIMERSNOIRQLOOP_SIMPLE,
65 BS3TIMERSNOIRQLOOP_STI_CLI,
66 BS3TIMERSNOIRQLOOP_END
67} BS3TIMERSNOIRQLOOP;
68
69
70/*********************************************************************************************************************************
71* External Assembly Functions *
72*********************************************************************************************************************************/
73extern FNBS3NEAR bs3Timers1StiHltCli;
74extern FNBS3NEAR bs3Timers1StiHltCli_IrqPc;
75extern FNBS3NEAR bs3Timers1StiStiCli;
76extern FNBS3NEAR bs3Timers1StiStiCli_IrqPc;
77extern FNBS3NEAR bs3Timers1PopfCli;
78extern FNBS3NEAR bs3Timers1PopfCli_IrqPc;
79
80extern FNBS3NEAR bs3Timers1StiCli;
81
82
83
84static uint8_t bs3Timers1_Pit(uint8_t bMode, uint16_t uHz, uint32_t cNsMaxDiviation, BS3TIMERSIRQLOOP enmIrqLoop)
85{
86 uint32_t const cTargetTicks = uHz * 3;
87 uint16_t uActualHz;
88 uint64_t cNsElapsed;
89 int64_t cNsDelta;
90 uint64_t cNsDeltaAbs;
91
92 ASMIntEnable();
93 ASMNopPause();
94 ASMIntDisable();
95
96
97 ASMIntDisable(); /* paranoia */
98 Bs3PitSetupAndEnablePeriodTimer(uHz);
99 cNsElapsed = Bs3TestNow();
100 uActualHz = g_cBs3PitIntervalHz;
101
102 switch (enmIrqLoop)
103 {
104 default:
105 case BS3TIMERSIRQLOOP_SIMPLE:
106 ASMIntEnable();
107 while (g_cBs3PitTicks < cTargetTicks)
108 ASMHalt();
109 break;
110
111 /* This variant enabls interrupt like this: sti; hlt; cli */
112 case BS3TIMERSIRQLOOP_STI_HLT_CLI:
113 while (g_cBs3PitTicks < cTargetTicks)
114 {
115 uint32_t const uIrqPc = g_Bs3PitIrqRip.u32;
116 if (uIrqPc == (uint16_t)&bs3Timers1StiHltCli_IrqPc || uIrqPc == 0)
117 bs3Timers1StiHltCli();
118 else
119 {
120 Bs3TestFailedF("IrqPC = %#RX32, expected %#RX16!\n", uIrqPc, (uint16_t)&bs3Timers1StiHltCli_IrqPc);
121 break;
122 }
123 }
124 break;
125
126 /* This variant enabls interrupt like this: sti; sti; cli */
127 case BS3TIMERSIRQLOOP_STI_STI_CLI:
128 while (g_cBs3PitTicks < cTargetTicks)
129 {
130 uint32_t const uIrqPc = g_Bs3PitIrqRip.u32;
131 if (uIrqPc == (uint16_t)&bs3Timers1StiStiCli_IrqPc || uIrqPc == 0)
132 bs3Timers1StiStiCli();
133 else
134 {
135 Bs3TestFailedF("IrqPC = %#RX32, expected %#RX16!\n", uIrqPc, (uint16_t)&bs3Timers1StiStiCli_IrqPc);
136 break;
137 }
138 }
139 break;
140
141 /* This variant enabls interrupt like this: enabling-if-popf; cli */
142 case BS3TIMERSIRQLOOP_POPF_CLI:
143 while (g_cBs3PitTicks < cTargetTicks)
144 {
145 uint32_t const uIrqPc = g_Bs3PitIrqRip.u32;
146 if (uIrqPc == (uint16_t)&bs3Timers1PopfCli_IrqPc || uIrqPc == 0)
147 bs3Timers1PopfCli();
148 else
149 {
150 Bs3TestFailedF("IrqPC = %#RX32, expected %#RX16!\n", uIrqPc, (uint16_t)&bs3Timers1PopfCli_IrqPc);
151 break;
152 }
153 }
154 break;
155 }
156
157 Bs3PitDisable();
158 ASMIntDisable();
159 cNsElapsed = Bs3TestNow() - cNsElapsed;
160
161 /* Calculate the absolute delta and fail the test if the diviation is too high... */
162 cNsDelta = cNsElapsed - RT_NS_1SEC * 3;
163 cNsDeltaAbs = RT_ABS(cNsDelta);
164 /*Bs3TestPrintf("cNsElapsed=%RU64 g_cBs3PitTicks=%RU32 uHz=%u -> %RU64ns\n",
165 cNsElapsed, g_cBs3PitTicks, uActualHz, cNsDeltaAbs);*/
166 if (cNsDeltaAbs > cNsMaxDiviation)
167 Bs3TestFailedF("delta %c%RU64 ns (%RI32 ms), max %RU32 ns", cNsDelta < 0 ? '-' : '+', cNsDeltaAbs,
168 (int32_t)((uint64_t)cNsDelta / RT_NS_1MS), cNsMaxDiviation);
169 else if (g_Bs3PitIrqRip.u32 == 0)
170 Bs3TestFailedF("g_Bs3PitIrqRip.u32 is zero!\n");
171
172 return 0;
173}
174
175
176BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz)(uint8_t bMode)
177{
178 return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_SIMPLE);
179}
180
181
182BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_1000Hz)(uint8_t bMode)
183{
184 return bs3Timers1_Pit(bMode, 1000, RT_NS_10MS, BS3TIMERSIRQLOOP_SIMPLE);
185}
186
187
188BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_2000Hz)(uint8_t bMode)
189{
190 return bs3Timers1_Pit(bMode, 2000, RT_NS_10MS*2, BS3TIMERSIRQLOOP_SIMPLE);
191}
192
193
194BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_4000Hz)(uint8_t bMode)
195{
196 return bs3Timers1_Pit(bMode, 4000, RT_NS_10MS*4, BS3TIMERSIRQLOOP_SIMPLE);
197}
198
199
200BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_wait1)(uint8_t bMode)
201{
202 return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_STI_HLT_CLI);
203}
204
205
206BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_wait2)(uint8_t bMode)
207{
208 return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_STI_STI_CLI);
209}
210
211
212BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_wait3)(uint8_t bMode)
213{
214 return bs3Timers1_Pit(bMode, 100, RT_NS_10MS, BS3TIMERSIRQLOOP_POPF_CLI);
215}
216
217
218/**
219 * Negative test loop, i.e. no interrupts delivered.
220 *
221 * This is for testing interrupt disabling and inhibition
222 */
223static uint8_t bs3Timers1_PitNegative(uint8_t bMode, uint16_t uHz, BS3TIMERSNOIRQLOOP enmLoop)
224{
225 uint64_t uNsStart;
226
227 ASMIntDisable(); /* paranoia */
228 Bs3PitSetupAndEnablePeriodTimer(uHz);
229 uNsStart = Bs3TestNow();
230
231 switch (enmLoop)
232 {
233 default:
234 case BS3TIMERSNOIRQLOOP_SIMPLE:
235 while (Bs3TestNow() - uNsStart < RT_NS_1SEC * 2)
236 ASMNopPause();
237 break;
238
239 case BS3TIMERSNOIRQLOOP_STI_CLI:
240 while (Bs3TestNow() - uNsStart < RT_NS_1SEC * 2)
241 bs3Timers1StiCli();
242 break;
243 }
244
245 Bs3PitDisable();
246
247 if (g_cBs3PitTicks > 0)
248 Bs3TestFailedF("g_cBs3PitTicks=%RU32, expected zero!\n", g_cBs3PitTicks);
249
250 ASMIntEnable();
251 ASMNopPause();
252 ASMIntDisable();
253
254 return 0;
255}
256
257
258BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_negative1)(uint8_t bMode)
259{
260 return bs3Timers1_PitNegative(bMode, 100, BS3TIMERSNOIRQLOOP_SIMPLE);
261}
262
263
264BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3Timers1_Pit_100Hz_negative2)(uint8_t bMode)
265{
266 return bs3Timers1_PitNegative(bMode, 100, BS3TIMERSNOIRQLOOP_STI_CLI);
267}
268
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