VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac@ 107044

Last change on this file since 107044 was 106061, checked in by vboxsync, 2 months ago

Copyright year updates by scm.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 11.1 KB
Line 
1; $Id: bs3-cpu-weird-1-template.mac 106061 2024-09-16 14:03:52Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-weird-1 assembly template.
4;
5
6;
7; Copyright (C) 2007-2024 Oracle and/or its affiliates.
8;
9; This file is part of VirtualBox base platform packages, as
10; available from https://www.virtualbox.org.
11;
12; This program is free software; you can redistribute it and/or
13; modify it under the terms of the GNU General Public License
14; as published by the Free Software Foundation, in version 3 of the
15; License.
16;
17; This program is distributed in the hope that it will be useful, but
18; WITHOUT ANY WARRANTY; without even the implied warranty of
19; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20; General Public License for more details.
21;
22; You should have received a copy of the GNU General Public License
23; along with this program; if not, see <https://www.gnu.org/licenses>.
24;
25; The contents of this file may alternatively be used under the terms
26; of the Common Development and Distribution License Version 1.0
27; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28; in the VirtualBox distribution, in which case the provisions of the
29; CDDL are applicable instead of those of the GPL.
30;
31; You may elect to license modified versions of this file under the
32; terms and conditions of either the GPL or the CDDL or both.
33;
34; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35;
36
37
38;*********************************************************************************************************************************
39;* Header Files *
40;*********************************************************************************************************************************
41%include "bs3kit-template-header.mac" ; setup environment
42
43
44;*********************************************************************************************************************************
45;* External Symbols *
46;*********************************************************************************************************************************
47TMPL_BEGIN_TEXT
48
49
50;
51; Test code snippets containing code which differs between 16-bit, 32-bit
52; and 64-bit CPUs modes.
53;
54%ifdef BS3_INSTANTIATING_CMN
55
56
57%if TMPL_BITS != 64
58
59;
60; Inhibited int 80h.
61;
62BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedPopSsInt80, BS3_PBC_NEAR
63 ; Load SS from stack. This instruction causes fusing.
64 pop ss
65 ; The ring transition instruction.
66BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedPopSsInt80_int80), , 0
67 int 80h
68 ; We shouldn't get here!
69.ud2_again:
70 ud2
71 jmp .ud2_again
72BS3_PROC_END_CMN bs3CpuWeird1_InhibitedPopSsInt80
73
74;
75; Inhibited int 3.
76;
77BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedPopSsInt3, BS3_PBC_NEAR
78 ; Load SS from stack. This instruction causes fusing.
79 pop ss
80 ; The ring transition instruction.
81BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedPopSsInt3_int3), , 0
82 int 3
83 ; We shouldn't get here!
84.ud2_again:
85 ud2
86 jmp .ud2_again
87AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedPopSsInt3_int3) == 2)
88BS3_PROC_END_CMN bs3CpuWeird1_InhibitedPopSsInt3
89
90
91;
92; Inhibited int3.
93;
94BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedPopSsBp, BS3_PBC_NEAR
95 ; Load SS from stack. This instruction causes fusing.
96 pop ss
97 ; The ring transition instruction.
98BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedPopSsBp_int3), , 0
99 int3
100 ; We shouldn't get here!
101.ud2_again:
102 ud2
103 jmp .ud2_again
104AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedPopSsBp_int3) == 1)
105BS3_PROC_END_CMN bs3CpuWeird1_InhibitedPopSsBp
106
107%endif ; TMPL_BITS != 64
108
109
110;
111; Inhibited int 80h.
112;
113BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedMovSsInt80, BS3_PBC_NEAR
114 ; Load SS from stack. This instruction causes fusing.
115 mov ss, [xBP]
116 ; The ring transition instruction.
117BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsInt80_int80), , 0
118 int 80h
119 ; We shouldn't get here!
120.ud2_again:
121 ud2
122 jmp .ud2_again
123BS3_PROC_END_CMN bs3CpuWeird1_InhibitedMovSsInt80
124
125;
126; Inhibited int 3.
127;
128BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedMovSsInt3, BS3_PBC_NEAR
129 ; Load SS from stack. This instruction causes fusing.
130 mov ss, [xBP]
131 ; The ring transition instruction.
132BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsInt3_int3), , 0
133 int 3
134 ; We shouldn't get here!
135.ud2_again:
136 ud2
137 jmp .ud2_again
138AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsInt3_int3) == 2)
139BS3_PROC_END_CMN bs3CpuWeird1_InhibitedMovSsInt3
140
141
142;
143; Inhibited int3.
144;
145BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedMovSsBp, BS3_PBC_NEAR
146 ; Load SS from stack. This instruction causes fusing.
147 mov ss, [xBP]
148 ; The ring transition instruction.
149BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsBp_int3), , 0
150 int3
151 ; We shouldn't get here!
152.ud2_again:
153 ud2
154 jmp .ud2_again
155AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsBp_int3) == 1)
156BS3_PROC_END_CMN bs3CpuWeird1_InhibitedMovSsBp
157
158
159;
160; Inhibited syscall.
161;
162BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedMovSsSyscall, BS3_PBC_NEAR
163 ; Load SS from stack. This instruction causes fusing.
164%if 1
165 mov ss, [xBP]
166%else
167 pushf
168 or word [xBP - xCB], X86_EFL_TF
169 popf
170%endif
171 ; The ring transition instruction.
172BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsSyscall_syscall), , 0
173 syscall
174 ; We shouldn't get here!
175.ud2_again:
176 ud2
177 jmp .ud2_again
178AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedMovSsSyscall_syscall) == 2)
179BS3_PROC_END_CMN bs3CpuWeird1_InhibitedMovSsSyscall
180
181
182;
183; PC (IP/EIP) wrapper templates.
184; These will potentially trigger VM exits, except for the benign one.
185;
186; Note! Single instructions as the testcase will shift multibyte variations
187; across the wrap-around boundary and that would cause unpredictable
188; results for the 16-bit if there is more than one instruction.
189;
190
191BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign1, BS3_PBC_NEAR
192 nop
193BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign1
194
195BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign2, BS3_PBC_NEAR
196 xor xDX, xAX
197BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign2
198
199BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapCpuId, BS3_PBC_NEAR
200 cpuid
201BS3_PROC_END_CMN bs3CpuWeird1_PcWrapCpuId
202
203BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapIn80, BS3_PBC_NEAR
204 in al, 80h
205BS3_PROC_END_CMN bs3CpuWeird1_PcWrapIn80
206
207BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapOut80, BS3_PBC_NEAR
208 out 80h, al
209BS3_PROC_END_CMN bs3CpuWeird1_PcWrapOut80
210
211BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapSmsw, BS3_PBC_NEAR
212 smsw si
213BS3_PROC_END_CMN bs3CpuWeird1_PcWrapSmsw
214
215BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdCr0, BS3_PBC_NEAR
216 mov sAX, cr0
217BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdCr0
218
219BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdDr0, BS3_PBC_NEAR
220 mov sAX, dr0
221BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdDr0
222
223BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapWrDr0, BS3_PBC_NEAR
224 mov dr0, sAX
225BS3_PROC_END_CMN bs3CpuWeird1_PcWrapWrDr0
226
227
228;
229; PUSH / POP.
230;
231
232BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_xSP_Ud2, BS3_PBC_NEAR
233 push xSP
234.ud2_again:
235 ud2
236 jmp .ud2_again
237AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_xSP_Ud2) == 1)
238BS3_PROC_END_CMN bs3CpuWeird1_Push_xSP_Ud2
239
240BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_xSP_Ud2, BS3_PBC_NEAR
241 pop xSP
242.ud2_again:
243 ud2
244 jmp .ud2_again
245AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_xSP_Ud2) == 1)
246BS3_PROC_END_CMN bs3CpuWeird1_Pop_xSP_Ud2
247
248
249BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_xSP_Ud2, BS3_PBC_NEAR
250 db 066h
251 push xSP
252.ud2_again:
253 ud2
254 jmp .ud2_again
255AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_xSP_Ud2) == 2)
256BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_xSP_Ud2
257
258BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_xSP_Ud2, BS3_PBC_NEAR
259 db 066h
260 pop xSP
261.ud2_again:
262 ud2
263 jmp .ud2_again
264AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_xSP_Ud2) == 2)
265BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_xSP_Ud2
266
267
268BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_xBX_Ud2, BS3_PBC_NEAR
269 db 066h
270 push xBX
271.ud2_again:
272 ud2
273 jmp .ud2_again
274AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_xBX_Ud2) == 2)
275BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_xBX_Ud2
276
277BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_xBX_Ud2, BS3_PBC_NEAR
278 db 066h
279 pop xBX
280.ud2_again:
281 ud2
282 jmp .ud2_again
283AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_xBX_Ud2) == 2)
284BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_xBX_Ud2
285
286
287;
288; PUSH / POP SREG.
289;
290
291 %ifndef DEFINED_DO_PUSH_POP_MACROS
292 %define DEFINED_DO_PUSH_POP_MACROS
293 %macro DoPushSeg 2
294
295BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
296 push %1
297.ud2_again:
298 ud2
299 jmp .ud2_again
300AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_ %+ %1 %+ _Ud2) == %2)
301BS3_PROC_END_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2
302
303BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
304 db 066h
305 push %1
306.ud2_again:
307 ud2
308 jmp .ud2_again
309AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2) == (%2 + 1))
310BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2
311
312 %endmacro ; DoPushSeg
313
314 %macro DoPopSeg 2
315
316BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
317 pop %1
318.ud2_again:
319 ud2
320 jmp .ud2_again
321AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2) == %2)
322BS3_PROC_END_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2
323
324BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR
325 db 066h
326 pop %1
327.ud2_again:
328 ud2
329 jmp .ud2_again
330AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2) == (%2 + 1))
331BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2
332
333 %endmacro ; DoPopSeg
334 %endif ; !DEFINED_DO_PUSH_POP_MACROS
335
336DoPushSeg fs, 2
337DoPopSeg fs, 2
338DoPushSeg gs, 2
339DoPopSeg gs, 2
340 %if TMPL_BITS == 32 || TMPL_BITS == 16
341DoPushSeg es, 1
342DoPopSeg es, 1
343DoPushSeg ds, 1
344DoPopSeg ds, 1
345DoPushSeg ss, 1
346DoPopSeg ss, 1
347DoPushSeg cs, 1
348 %endif
349
350
351;
352; popf
353;
354BS3_PROC_BEGIN_CMN bs3CpuWeird1_Popf_Nop_Ud2, BS3_PBC_NEAR
355 popf
356 nop
357.ud2_again:
358 ud2
359 jmp .ud2_again
360AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Popf_Nop_Ud2) == 2)
361BS3_PROC_END_CMN bs3CpuWeird1_Popf_Nop_Ud2
362
363;
364; popf
365;
366BS3_PROC_BEGIN_CMN bs3CpuWeird1_Popf_opsize_Nop_Ud2, BS3_PBC_NEAR
367 db 066h
368 popf
369 nop
370.ud2_again:
371 ud2
372 jmp .ud2_again
373AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Popf_opsize_Nop_Ud2) == 3)
374BS3_PROC_END_CMN bs3CpuWeird1_Popf_opsize_Nop_Ud2
375
376
377%endif ; BS3_INSTANTIATING_CMN
378
379%include "bs3kit-template-footer.mac" ; reset environment
380
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette