bs3-cpu-instr-4-template.mac@ 106743

Last change on this file since 106743 was 106733, checked in by vboxsync, 5 weeks ago

ValidationKit/bootsectors: Implement SISD FP testcases for cvtsi2ss; bugref:10658; jiraref:VBP-1206

Bs3ExtCtxSetReg:

fix bs3CpuInstrXGetRegisterName() for arbitrary FSxReg
use RTUINT256U in place of ad hoc casts
use a mostly-static context struct for Bs3ExtCtxSetReg() args
fix Bs3ExtCtxSetReg() on 64-bit GPRs in non-64-bit execution modes
add a debug flag to print Bs3ExtCtxSetReg() actions

ValKit bs3-cpu-instr-4 test worker:

add ability to mark an instruction test as always faulting

ValKit bs3-cpu-instr-4 test setup:

fix some macros needing more parentheses
fix integer macros & move them where they belong

ValKit:

implement cvtsi2ss tests
improve test-function emitter comments

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

File size: 51.9 KB

Line
1	; $Id: bs3-cpu-instr-4-template.mac 106733 2024-10-28 03:47:44Z vboxsync $
2	;; @file
3	; BS3Kit - bs3-cpu-instr-4 - SSE, AVX FPU instructions, assembly template.
4	;
5
6	;
7	; Copyright (C) 2024 Oracle and/or its affiliates.
8	;
9	; This file is part of VirtualBox base platform packages, as
10	; available from https://www.virtualbox.org.
11	;
12	; This program is free software; you can redistribute it and/or
13	; modify it under the terms of the GNU General Public License
14	; as published by the Free Software Foundation, in version 3 of the
15	; License.
16	;
17	; This program is distributed in the hope that it will be useful, but
18	; WITHOUT ANY WARRANTY; without even the implied warranty of
19	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	; General Public License for more details.
21	;
22	; You should have received a copy of the GNU General Public License
23	; along with this program; if not, see <https://www.gnu.org/licenses>.
24	;
25	; The contents of this file may alternatively be used under the terms
26	; of the Common Development and Distribution License Version 1.0
27	; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	; in the VirtualBox distribution, in which case the provisions of the
29	; CDDL are applicable instead of those of the GPL.
30	;
31	; You may elect to license modified versions of this file under the
32	; terms and conditions of either the GPL or the CDDL or both.
33	;
34	; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	;
36
37
38	;*********************************************************************************************************************************
39	;* Header Files *
40	;*********************************************************************************************************************************
41	%include "bs3kit-template-header.mac" ; setup environment
42
43
44	;*********************************************************************************************************************************
45	;* External Symbols *
46	;*********************************************************************************************************************************
47	TMPL_BEGIN_TEXT
48
49
50	;
51	; Test code snippets containing code which differs between 16-bit, 32-bit
52	; and 64-bit CPUs modes.
53	;
54	%ifdef BS3_INSTANTIATING_CMN
55
56
57	;;
58	; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function
59	; with an instruction length byte.
60	;
61	; ASSUMES the length is between the start of the function and the .again label.
62	;
63	%ifndef BS3CPUINSTR4_PROC_BEGIN_CMN_DEFINED
64	%define BS3CPUINSTR4_PROC_BEGIN_CMN_DEFINED
65	%macro BS3CPUINSTR4_PROC_BEGIN_CMN 1
66	align 8, db 0cch
67	db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
68	BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR
69	%endmacro
70	%endif ; !BS3CPUINSTR4_PROC_BEGIN_CMN_DEFINED
71
72	;;
73	; FSxBX and its variants allow a memory reference to be embedded into a test
74	; instruction. `xBX' adjusts automatically to the addressing model: BX, EBX,
75	; or RBX depending on the number of address bits. FSxBX_D and so on allow to
76	; force a particular memory reference size; this is necessary for some AVX
77	; instructions where the mentioned XMM/YMM/ZMM register size doesn't fully
78	; control the memory size to be used. Macros are repeatedly redefined in
79	; order to pick up the current address-model-specific `xBX' value. (Other
80	; sizes could be defined: B=byte=1, W=word=2, T=tword=10(x87), z=zword=32)
81	;
82	%ifndef BS3CPUINSTR4_DEFINE_FSxBX_DEFINED
83	%define BS3CPUINSTR4_DEFINE_FSxBX_DEFINED
84	%macro BS3CPUINSTR4_DEFINE_FSxBX 0
85	%define FSxBX [fs:xBX] ; natural size of the instruction
86	%define FSxBX_D dword [fs:xBX] ; dword = 32 bits = 4 bytes = 2 words
87	%define FSxBX_Q qword [fs:xBX] ; qword = 64 bits = 8 bytes = 4 words
88	%define FSxBX_O oword [fs:xBX] ; oword = 128 bits = 16 bytes = 8 words
89	%define FSxBX_Y yword [fs:xBX] ; yword = 256 bits = 32 bytes = 16 words
90	%endmacro
91	%macro BS3CPUINSTR4_UNDEF_FSxBX 0
92	%undef FSxBX
93	%undef FSxBX_D
94	%undef FSxBX_Q
95	%undef FSxBX_O
96	%undef FSxBX_Y
97	%endmacro
98	%endif ; !BS3CPUINSTR4_DEFINE_FSxBX_DEFINED
99
100	;;
101	; The EMIT_INSTR_PLUS_ICEBP macros is for creating a common function for and
102	; named after a single instruction & args, followed by a looping ICEBP.
103	;
104	%ifndef EMIT_INSTR_PLUS_ICEBP_DEFINED
105	%define EMIT_INSTR_PLUS_ICEBP_DEFINED
106
107	%macro EMIT_INSTR_PLUS_ICEBP 2
108	BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _icebp
109	BS3CPUINSTR4_DEFINE_FSxBX
110	%1 %2
111	BS3CPUINSTR4_UNDEF_FSxBX
112	.again:
113	icebp
114	jmp .again
115	BS3_PROC_END_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _icebp
116	%endmacro
117
118	%macro EMIT_INSTR_PLUS_ICEBP 3
119	BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp
120	BS3CPUINSTR4_DEFINE_FSxBX
121	%1 %2, %3
122	BS3CPUINSTR4_UNDEF_FSxBX
123	.again:
124	icebp
125	jmp .again
126	BS3_PROC_END_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp
127	%endmacro
128
129	%macro EMIT_INSTR_PLUS_ICEBP 4
130	BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp
131	BS3CPUINSTR4_DEFINE_FSxBX
132	%1 %2, %3, %4
133	BS3CPUINSTR4_UNDEF_FSxBX
134	.again:
135	icebp
136	jmp .again
137	BS3_PROC_END_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp
138	%endmacro
139
140	%macro EMIT_INSTR_PLUS_ICEBP 5
141	BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp
142	BS3CPUINSTR4_DEFINE_FSxBX
143	%1 %2, %3, %4, %5
144	BS3CPUINSTR4_UNDEF_FSxBX
145	.again:
146	icebp
147	jmp .again
148	BS3_PROC_END_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp
149	%endmacro
150
151	%macro EMIT_INSTR_PLUS_ICEBP_C64 2
152	%if TMPL_BITS == 64
153	EMIT_INSTR_PLUS_ICEBP %1, %2
154	%endif
155	%endmacro
156
157	%macro EMIT_INSTR_PLUS_ICEBP_C64 3
158	%if TMPL_BITS == 64
159	EMIT_INSTR_PLUS_ICEBP %1, %2, %3
160	%endif
161	%endmacro
162
163	%macro EMIT_INSTR_PLUS_ICEBP_C64 4
164	%if TMPL_BITS == 64
165	EMIT_INSTR_PLUS_ICEBP %1, %2, %3, %4
166	%endif
167	%endmacro
168
169	%macro EMIT_INSTR_PLUS_ICEBP_C64 5
170	%if TMPL_BITS == 64
171	EMIT_INSTR_PLUS_ICEBP %1, %2, %3, %4, %5
172	%endif
173	%endmacro
174
175	%endif ; !EMIT_INSTR_PLUS_ICEBP_DEFINED
176
177	;
178	;; [v]addps
179	;
180	EMIT_INSTR_PLUS_ICEBP addps, XMM1, XMM2
181	EMIT_INSTR_PLUS_ICEBP addps, XMM1, FSxBX
182	EMIT_INSTR_PLUS_ICEBP_C64 addps, XMM8, XMM9
183	EMIT_INSTR_PLUS_ICEBP_C64 addps, XMM8, FSxBX
184
185	EMIT_INSTR_PLUS_ICEBP vaddps, XMM1, XMM2, XMM3
186	EMIT_INSTR_PLUS_ICEBP vaddps, XMM1, XMM2, FSxBX
187	EMIT_INSTR_PLUS_ICEBP_C64 vaddps, XMM8, XMM9, XMM10
188	EMIT_INSTR_PLUS_ICEBP_C64 vaddps, XMM8, XMM9, FSxBX
189
190	EMIT_INSTR_PLUS_ICEBP vaddps, YMM1, YMM2, YMM3
191	EMIT_INSTR_PLUS_ICEBP vaddps, YMM1, YMM2, FSxBX
192	EMIT_INSTR_PLUS_ICEBP_C64 vaddps, YMM8, YMM9, YMM10
193	EMIT_INSTR_PLUS_ICEBP_C64 vaddps, YMM8, YMM9, FSxBX
194
195	EMIT_INSTR_PLUS_ICEBP addps, XMM1, XMM1
196	EMIT_INSTR_PLUS_ICEBP_C64 addps, XMM8, XMM8
197	EMIT_INSTR_PLUS_ICEBP vaddps, YMM1, YMM1, YMM1
198	EMIT_INSTR_PLUS_ICEBP vaddps, YMM1, YMM1, YMM2
199	EMIT_INSTR_PLUS_ICEBP_C64 vaddps, YMM8, YMM8, YMM8
200	EMIT_INSTR_PLUS_ICEBP vaddps, YMM1, YMM1, FSxBX
201
202	;
203	;; [v]addpd
204	;
205	EMIT_INSTR_PLUS_ICEBP addpd, XMM1, XMM2
206	EMIT_INSTR_PLUS_ICEBP addpd, XMM1, FSxBX
207	EMIT_INSTR_PLUS_ICEBP_C64 addpd, XMM8, XMM9
208	EMIT_INSTR_PLUS_ICEBP_C64 addpd, XMM8, FSxBX
209
210	EMIT_INSTR_PLUS_ICEBP vaddpd, XMM1, XMM2, XMM3
211	EMIT_INSTR_PLUS_ICEBP vaddpd, XMM1, XMM2, FSxBX
212	EMIT_INSTR_PLUS_ICEBP_C64 vaddpd, XMM8, XMM9, XMM10
213	EMIT_INSTR_PLUS_ICEBP_C64 vaddpd, XMM8, XMM9, FSxBX
214
215	EMIT_INSTR_PLUS_ICEBP vaddpd, YMM1, YMM2, YMM3
216	EMIT_INSTR_PLUS_ICEBP vaddpd, YMM1, YMM2, FSxBX
217	EMIT_INSTR_PLUS_ICEBP_C64 vaddpd, YMM8, YMM9, YMM10
218	EMIT_INSTR_PLUS_ICEBP_C64 vaddpd, YMM8, YMM9, FSxBX
219
220	EMIT_INSTR_PLUS_ICEBP addpd, XMM1, XMM1
221	EMIT_INSTR_PLUS_ICEBP_C64 addpd, XMM8, XMM8
222	EMIT_INSTR_PLUS_ICEBP vaddpd, YMM1, YMM1, YMM1
223	EMIT_INSTR_PLUS_ICEBP vaddpd, YMM1, YMM1, YMM2
224	EMIT_INSTR_PLUS_ICEBP_C64 vaddpd, YMM8, YMM8, YMM8
225	EMIT_INSTR_PLUS_ICEBP vaddpd, YMM1, YMM1, FSxBX
226
227	;
228	;; [v]addss
229	;
230	EMIT_INSTR_PLUS_ICEBP addss, XMM1, XMM2
231	EMIT_INSTR_PLUS_ICEBP addss, XMM1, FSxBX
232	EMIT_INSTR_PLUS_ICEBP_C64 addss, XMM8, XMM9
233	EMIT_INSTR_PLUS_ICEBP_C64 addss, XMM8, FSxBX
234
235	EMIT_INSTR_PLUS_ICEBP vaddss, XMM1, XMM2, XMM3
236	EMIT_INSTR_PLUS_ICEBP vaddss, XMM1, XMM2, FSxBX
237	EMIT_INSTR_PLUS_ICEBP_C64 vaddss, XMM8, XMM9, XMM10
238	EMIT_INSTR_PLUS_ICEBP_C64 vaddss, XMM8, XMM9, FSxBX
239
240	EMIT_INSTR_PLUS_ICEBP addss, XMM1, XMM1
241	EMIT_INSTR_PLUS_ICEBP_C64 addss, XMM8, XMM8
242	EMIT_INSTR_PLUS_ICEBP vaddss, XMM1, XMM1, XMM1
243	EMIT_INSTR_PLUS_ICEBP vaddss, XMM1, XMM1, XMM2
244	EMIT_INSTR_PLUS_ICEBP_C64 vaddss, XMM8, XMM8, XMM8
245	EMIT_INSTR_PLUS_ICEBP vaddss, XMM1, XMM1, FSxBX
246
247	;
248	;; [v]addsd
249	;
250	EMIT_INSTR_PLUS_ICEBP addsd, XMM1, XMM2
251	EMIT_INSTR_PLUS_ICEBP addsd, XMM1, FSxBX
252	EMIT_INSTR_PLUS_ICEBP_C64 addsd, XMM8, XMM9
253	EMIT_INSTR_PLUS_ICEBP_C64 addsd, XMM8, FSxBX
254
255	EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM2, XMM3
256	EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM2, FSxBX
257	EMIT_INSTR_PLUS_ICEBP_C64 vaddsd, XMM8, XMM9, XMM10
258	EMIT_INSTR_PLUS_ICEBP_C64 vaddsd, XMM8, XMM9, FSxBX
259
260	EMIT_INSTR_PLUS_ICEBP addsd, XMM1, XMM1
261	EMIT_INSTR_PLUS_ICEBP_C64 addsd, XMM8, XMM8
262	EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM1, XMM1
263	EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM1, XMM2
264	EMIT_INSTR_PLUS_ICEBP_C64 vaddsd, XMM8, XMM8, XMM8
265	EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM1, FSxBX
266
267	;
268	;; [v]haddps
269	;
270	EMIT_INSTR_PLUS_ICEBP haddps, XMM1, XMM2
271	EMIT_INSTR_PLUS_ICEBP haddps, XMM1, FSxBX
272	EMIT_INSTR_PLUS_ICEBP_C64 haddps, XMM8, XMM9
273	EMIT_INSTR_PLUS_ICEBP_C64 haddps, XMM8, FSxBX
274
275	EMIT_INSTR_PLUS_ICEBP vhaddps, XMM1, XMM2, XMM3
276	EMIT_INSTR_PLUS_ICEBP vhaddps, XMM1, XMM2, FSxBX
277	EMIT_INSTR_PLUS_ICEBP_C64 vhaddps, XMM8, XMM9, XMM10
278	EMIT_INSTR_PLUS_ICEBP_C64 vhaddps, XMM8, XMM9, FSxBX
279
280	EMIT_INSTR_PLUS_ICEBP vhaddps, YMM1, YMM2, YMM3
281	EMIT_INSTR_PLUS_ICEBP vhaddps, YMM1, YMM2, FSxBX
282	EMIT_INSTR_PLUS_ICEBP_C64 vhaddps, YMM8, YMM9, YMM10
283	EMIT_INSTR_PLUS_ICEBP_C64 vhaddps, YMM8, YMM9, FSxBX
284
285	EMIT_INSTR_PLUS_ICEBP haddps, XMM1, XMM1
286	EMIT_INSTR_PLUS_ICEBP_C64 haddps, XMM8, XMM8
287	EMIT_INSTR_PLUS_ICEBP vhaddps, YMM1, YMM1, YMM1
288	EMIT_INSTR_PLUS_ICEBP vhaddps, YMM1, YMM1, YMM2
289	EMIT_INSTR_PLUS_ICEBP_C64 vhaddps, YMM8, YMM8, YMM8
290	EMIT_INSTR_PLUS_ICEBP vhaddps, YMM1, YMM1, FSxBX
291
292	;
293	;; [v]haddpd
294	;
295	EMIT_INSTR_PLUS_ICEBP haddpd, XMM1, XMM2
296	EMIT_INSTR_PLUS_ICEBP haddpd, XMM1, FSxBX
297	EMIT_INSTR_PLUS_ICEBP_C64 haddpd, XMM8, XMM9
298	EMIT_INSTR_PLUS_ICEBP_C64 haddpd, XMM8, FSxBX
299
300	EMIT_INSTR_PLUS_ICEBP vhaddpd, XMM1, XMM2, XMM3
301	EMIT_INSTR_PLUS_ICEBP vhaddpd, XMM1, XMM2, FSxBX
302	EMIT_INSTR_PLUS_ICEBP_C64 vhaddpd, XMM8, XMM9, XMM10
303	EMIT_INSTR_PLUS_ICEBP_C64 vhaddpd, XMM8, XMM9, FSxBX
304
305	EMIT_INSTR_PLUS_ICEBP vhaddpd, YMM1, YMM2, YMM3
306	EMIT_INSTR_PLUS_ICEBP vhaddpd, YMM1, YMM2, FSxBX
307	EMIT_INSTR_PLUS_ICEBP_C64 vhaddpd, YMM8, YMM9, YMM10
308	EMIT_INSTR_PLUS_ICEBP_C64 vhaddpd, YMM8, YMM9, FSxBX
309
310	EMIT_INSTR_PLUS_ICEBP haddpd, XMM1, XMM1
311	EMIT_INSTR_PLUS_ICEBP_C64 haddpd, XMM8, XMM8
312	EMIT_INSTR_PLUS_ICEBP vhaddpd, YMM1, YMM1, YMM1
313	EMIT_INSTR_PLUS_ICEBP vhaddpd, YMM1, YMM1, YMM2
314	EMIT_INSTR_PLUS_ICEBP_C64 vhaddpd, YMM8, YMM8, YMM8
315	EMIT_INSTR_PLUS_ICEBP vhaddpd, YMM1, YMM1, FSxBX
316
317	;
318	;; [v]subps
319	;
320	EMIT_INSTR_PLUS_ICEBP subps, XMM1, XMM2
321	EMIT_INSTR_PLUS_ICEBP subps, XMM1, FSxBX
322	EMIT_INSTR_PLUS_ICEBP_C64 subps, XMM8, XMM9
323	EMIT_INSTR_PLUS_ICEBP_C64 subps, XMM8, FSxBX
324
325	EMIT_INSTR_PLUS_ICEBP vsubps, XMM1, XMM2, XMM3
326	EMIT_INSTR_PLUS_ICEBP vsubps, XMM1, XMM2, FSxBX
327	EMIT_INSTR_PLUS_ICEBP_C64 vsubps, XMM8, XMM9, XMM10
328	EMIT_INSTR_PLUS_ICEBP_C64 vsubps, XMM8, XMM9, FSxBX
329
330	EMIT_INSTR_PLUS_ICEBP vsubps, YMM1, YMM2, YMM3
331	EMIT_INSTR_PLUS_ICEBP vsubps, YMM1, YMM2, FSxBX
332	EMIT_INSTR_PLUS_ICEBP_C64 vsubps, YMM8, YMM9, YMM10
333	EMIT_INSTR_PLUS_ICEBP_C64 vsubps, YMM8, YMM9, FSxBX
334
335	;
336	;; [v]subpd
337	;
338	EMIT_INSTR_PLUS_ICEBP subpd, XMM1, XMM2
339	EMIT_INSTR_PLUS_ICEBP subpd, XMM1, FSxBX
340	EMIT_INSTR_PLUS_ICEBP_C64 subpd, XMM8, XMM9
341	EMIT_INSTR_PLUS_ICEBP_C64 subpd, XMM8, FSxBX
342
343	EMIT_INSTR_PLUS_ICEBP vsubpd, XMM1, XMM2, XMM3
344	EMIT_INSTR_PLUS_ICEBP vsubpd, XMM1, XMM2, FSxBX
345	EMIT_INSTR_PLUS_ICEBP_C64 vsubpd, XMM8, XMM9, XMM10
346	EMIT_INSTR_PLUS_ICEBP_C64 vsubpd, XMM8, XMM9, FSxBX
347
348	EMIT_INSTR_PLUS_ICEBP vsubpd, YMM1, YMM2, YMM3
349	EMIT_INSTR_PLUS_ICEBP vsubpd, YMM1, YMM2, FSxBX
350	EMIT_INSTR_PLUS_ICEBP_C64 vsubpd, YMM8, YMM9, YMM10
351	EMIT_INSTR_PLUS_ICEBP_C64 vsubpd, YMM8, YMM9, FSxBX
352
353	;
354	;; [v]subss
355	;
356	EMIT_INSTR_PLUS_ICEBP subss, XMM1, XMM2
357	EMIT_INSTR_PLUS_ICEBP subss, XMM1, FSxBX
358	EMIT_INSTR_PLUS_ICEBP_C64 subss, XMM8, XMM9
359	EMIT_INSTR_PLUS_ICEBP_C64 subss, XMM8, FSxBX
360
361	EMIT_INSTR_PLUS_ICEBP vsubss, XMM1, XMM2, XMM3
362	EMIT_INSTR_PLUS_ICEBP vsubss, XMM1, XMM2, FSxBX
363	EMIT_INSTR_PLUS_ICEBP_C64 vsubss, XMM8, XMM9, XMM10
364	EMIT_INSTR_PLUS_ICEBP_C64 vsubss, XMM8, XMM9, FSxBX
365
366	;
367	;; [v]subsd
368	;
369	EMIT_INSTR_PLUS_ICEBP subsd, XMM1, XMM2
370	EMIT_INSTR_PLUS_ICEBP subsd, XMM1, FSxBX
371	EMIT_INSTR_PLUS_ICEBP_C64 subsd, XMM8, XMM9
372	EMIT_INSTR_PLUS_ICEBP_C64 subsd, XMM8, FSxBX
373
374	EMIT_INSTR_PLUS_ICEBP vsubsd, XMM1, XMM2, XMM3
375	EMIT_INSTR_PLUS_ICEBP vsubsd, XMM1, XMM2, FSxBX
376	EMIT_INSTR_PLUS_ICEBP_C64 vsubsd, XMM8, XMM9, XMM10
377	EMIT_INSTR_PLUS_ICEBP_C64 vsubsd, XMM8, XMM9, FSxBX
378
379	;
380	;; [v]hsubps
381	;
382	EMIT_INSTR_PLUS_ICEBP hsubps, XMM1, XMM2
383	EMIT_INSTR_PLUS_ICEBP hsubps, XMM1, FSxBX
384	EMIT_INSTR_PLUS_ICEBP_C64 hsubps, XMM8, XMM9
385	EMIT_INSTR_PLUS_ICEBP_C64 hsubps, XMM8, FSxBX
386
387	EMIT_INSTR_PLUS_ICEBP vhsubps, XMM1, XMM2, XMM3
388	EMIT_INSTR_PLUS_ICEBP vhsubps, XMM1, XMM2, FSxBX
389	EMIT_INSTR_PLUS_ICEBP_C64 vhsubps, XMM8, XMM9, XMM10
390	EMIT_INSTR_PLUS_ICEBP_C64 vhsubps, XMM8, XMM9, FSxBX
391
392	EMIT_INSTR_PLUS_ICEBP vhsubps, YMM1, YMM2, YMM3
393	EMIT_INSTR_PLUS_ICEBP vhsubps, YMM1, YMM2, FSxBX
394	EMIT_INSTR_PLUS_ICEBP_C64 vhsubps, YMM8, YMM9, YMM10
395	EMIT_INSTR_PLUS_ICEBP_C64 vhsubps, YMM8, YMM9, FSxBX
396
397	;
398	;; [v]hsubpd
399	;
400	EMIT_INSTR_PLUS_ICEBP hsubpd, XMM1, XMM2
401	EMIT_INSTR_PLUS_ICEBP hsubpd, XMM1, FSxBX
402	EMIT_INSTR_PLUS_ICEBP_C64 hsubpd, XMM8, XMM9
403	EMIT_INSTR_PLUS_ICEBP_C64 hsubpd, XMM8, FSxBX
404
405	EMIT_INSTR_PLUS_ICEBP vhsubpd, XMM1, XMM2, XMM3
406	EMIT_INSTR_PLUS_ICEBP vhsubpd, XMM1, XMM2, FSxBX
407	EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, XMM8, XMM9, XMM10
408	EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, XMM8, XMM9, FSxBX
409
410	EMIT_INSTR_PLUS_ICEBP vhsubpd, YMM1, YMM2, YMM3
411	EMIT_INSTR_PLUS_ICEBP vhsubpd, YMM1, YMM2, FSxBX
412	EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, YMM8, YMM9, YMM10
413	EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, YMM8, YMM9, FSxBX
414
415	;
416	;; [v]mulps
417	;
418	EMIT_INSTR_PLUS_ICEBP mulps, XMM1, XMM2
419	EMIT_INSTR_PLUS_ICEBP mulps, XMM1, FSxBX
420	EMIT_INSTR_PLUS_ICEBP_C64 mulps, XMM8, XMM9
421	EMIT_INSTR_PLUS_ICEBP_C64 mulps, XMM8, FSxBX
422
423	EMIT_INSTR_PLUS_ICEBP vmulps, XMM1, XMM2, XMM3
424	EMIT_INSTR_PLUS_ICEBP vmulps, XMM1, XMM2, FSxBX
425	EMIT_INSTR_PLUS_ICEBP_C64 vmulps, XMM8, XMM9, XMM10
426	EMIT_INSTR_PLUS_ICEBP_C64 vmulps, XMM8, XMM9, FSxBX
427
428	EMIT_INSTR_PLUS_ICEBP vmulps, YMM1, YMM2, YMM3
429	EMIT_INSTR_PLUS_ICEBP vmulps, YMM1, YMM2, FSxBX
430	EMIT_INSTR_PLUS_ICEBP_C64 vmulps, YMM8, YMM9, YMM10
431	EMIT_INSTR_PLUS_ICEBP_C64 vmulps, YMM8, YMM9, FSxBX
432
433	;
434	;; [v]mulpd
435	;
436	EMIT_INSTR_PLUS_ICEBP mulpd, XMM1, XMM2
437	EMIT_INSTR_PLUS_ICEBP mulpd, XMM1, FSxBX
438	EMIT_INSTR_PLUS_ICEBP_C64 mulpd, XMM8, XMM9
439	EMIT_INSTR_PLUS_ICEBP_C64 mulpd, XMM8, FSxBX
440
441	EMIT_INSTR_PLUS_ICEBP vmulpd, XMM1, XMM2, XMM3
442	EMIT_INSTR_PLUS_ICEBP vmulpd, XMM1, XMM2, FSxBX
443	EMIT_INSTR_PLUS_ICEBP_C64 vmulpd, XMM8, XMM9, XMM10
444	EMIT_INSTR_PLUS_ICEBP_C64 vmulpd, XMM8, XMM9, FSxBX
445
446	EMIT_INSTR_PLUS_ICEBP vmulpd, YMM1, YMM2, YMM3
447	EMIT_INSTR_PLUS_ICEBP vmulpd, YMM1, YMM2, FSxBX
448	EMIT_INSTR_PLUS_ICEBP_C64 vmulpd, YMM8, YMM9, YMM10
449	EMIT_INSTR_PLUS_ICEBP_C64 vmulpd, YMM8, YMM9, FSxBX
450
451	;
452	;; [v]mulss
453	;
454	EMIT_INSTR_PLUS_ICEBP mulss, XMM1, XMM2
455	EMIT_INSTR_PLUS_ICEBP mulss, XMM1, FSxBX
456	EMIT_INSTR_PLUS_ICEBP_C64 mulss, XMM8, XMM9
457	EMIT_INSTR_PLUS_ICEBP_C64 mulss, XMM8, FSxBX
458
459	EMIT_INSTR_PLUS_ICEBP vmulss, XMM1, XMM2, XMM3
460	EMIT_INSTR_PLUS_ICEBP vmulss, XMM1, XMM2, FSxBX
461	EMIT_INSTR_PLUS_ICEBP_C64 vmulss, XMM8, XMM9, XMM10
462	EMIT_INSTR_PLUS_ICEBP_C64 vmulss, XMM8, XMM9, FSxBX
463
464	;
465	;; [v]mulsd
466	;
467	EMIT_INSTR_PLUS_ICEBP mulsd, XMM1, XMM2
468	EMIT_INSTR_PLUS_ICEBP mulsd, XMM1, FSxBX
469	EMIT_INSTR_PLUS_ICEBP_C64 mulsd, XMM8, XMM9
470	EMIT_INSTR_PLUS_ICEBP_C64 mulsd, XMM8, FSxBX
471
472	EMIT_INSTR_PLUS_ICEBP vmulsd, XMM1, XMM2, XMM3
473	EMIT_INSTR_PLUS_ICEBP vmulsd, XMM1, XMM2, FSxBX
474	EMIT_INSTR_PLUS_ICEBP_C64 vmulsd, XMM8, XMM9, XMM10
475	EMIT_INSTR_PLUS_ICEBP_C64 vmulsd, XMM8, XMM9, FSxBX
476
477	;
478	;; [v]divps
479	;
480	EMIT_INSTR_PLUS_ICEBP divps, XMM1, XMM2
481	EMIT_INSTR_PLUS_ICEBP divps, XMM1, FSxBX
482	EMIT_INSTR_PLUS_ICEBP_C64 divps, XMM8, XMM9
483	EMIT_INSTR_PLUS_ICEBP_C64 divps, XMM8, FSxBX
484
485	EMIT_INSTR_PLUS_ICEBP vdivps, XMM1, XMM2, XMM3
486	EMIT_INSTR_PLUS_ICEBP vdivps, XMM1, XMM2, FSxBX
487	EMIT_INSTR_PLUS_ICEBP_C64 vdivps, XMM8, XMM9, XMM10
488	EMIT_INSTR_PLUS_ICEBP_C64 vdivps, XMM8, XMM9, FSxBX
489
490	EMIT_INSTR_PLUS_ICEBP vdivps, YMM1, YMM2, YMM3
491	EMIT_INSTR_PLUS_ICEBP vdivps, YMM1, YMM2, FSxBX
492	EMIT_INSTR_PLUS_ICEBP_C64 vdivps, YMM8, YMM9, YMM10
493	EMIT_INSTR_PLUS_ICEBP_C64 vdivps, YMM8, YMM9, FSxBX
494
495	;
496	;; [v]divpd
497	;
498	EMIT_INSTR_PLUS_ICEBP divpd, XMM1, XMM2
499	EMIT_INSTR_PLUS_ICEBP divpd, XMM1, FSxBX
500	EMIT_INSTR_PLUS_ICEBP_C64 divpd, XMM8, XMM9
501	EMIT_INSTR_PLUS_ICEBP_C64 divpd, XMM8, FSxBX
502
503	EMIT_INSTR_PLUS_ICEBP vdivpd, XMM1, XMM2, XMM3
504	EMIT_INSTR_PLUS_ICEBP vdivpd, XMM1, XMM2, FSxBX
505	EMIT_INSTR_PLUS_ICEBP_C64 vdivpd, XMM8, XMM9, XMM10
506	EMIT_INSTR_PLUS_ICEBP_C64 vdivpd, XMM8, XMM9, FSxBX
507
508	EMIT_INSTR_PLUS_ICEBP vdivpd, YMM1, YMM2, YMM3
509	EMIT_INSTR_PLUS_ICEBP vdivpd, YMM1, YMM2, FSxBX
510	EMIT_INSTR_PLUS_ICEBP_C64 vdivpd, YMM8, YMM9, YMM10
511	EMIT_INSTR_PLUS_ICEBP_C64 vdivpd, YMM8, YMM9, FSxBX
512
513	;
514	;; [v]divss
515	;
516	EMIT_INSTR_PLUS_ICEBP divss, XMM1, XMM2
517	EMIT_INSTR_PLUS_ICEBP divss, XMM1, FSxBX
518	EMIT_INSTR_PLUS_ICEBP_C64 divss, XMM8, XMM9
519	EMIT_INSTR_PLUS_ICEBP_C64 divss, XMM8, FSxBX
520
521	EMIT_INSTR_PLUS_ICEBP vdivss, XMM1, XMM2, XMM3
522	EMIT_INSTR_PLUS_ICEBP vdivss, XMM1, XMM2, FSxBX
523	EMIT_INSTR_PLUS_ICEBP_C64 vdivss, XMM8, XMM9, XMM10
524	EMIT_INSTR_PLUS_ICEBP_C64 vdivss, XMM8, XMM9, FSxBX
525
526	;
527	;; [v]divsd
528	;
529	EMIT_INSTR_PLUS_ICEBP divsd, XMM1, XMM2
530	EMIT_INSTR_PLUS_ICEBP divsd, XMM1, FSxBX
531	EMIT_INSTR_PLUS_ICEBP_C64 divsd, XMM8, XMM9
532	EMIT_INSTR_PLUS_ICEBP_C64 divsd, XMM8, FSxBX
533
534	EMIT_INSTR_PLUS_ICEBP vdivsd, XMM1, XMM2, XMM3
535	EMIT_INSTR_PLUS_ICEBP vdivsd, XMM1, XMM2, FSxBX
536	EMIT_INSTR_PLUS_ICEBP_C64 vdivsd, XMM8, XMM9, XMM10
537	EMIT_INSTR_PLUS_ICEBP_C64 vdivsd, XMM8, XMM9, FSxBX
538
539	;
540	;; [v]addsubps
541	;
542	EMIT_INSTR_PLUS_ICEBP addsubps, XMM1, XMM2
543	EMIT_INSTR_PLUS_ICEBP addsubps, XMM1, FSxBX
544	EMIT_INSTR_PLUS_ICEBP_C64 addsubps, XMM8, XMM9
545	EMIT_INSTR_PLUS_ICEBP_C64 addsubps, XMM8, FSxBX
546
547	EMIT_INSTR_PLUS_ICEBP vaddsubps, XMM1, XMM2, XMM3
548	EMIT_INSTR_PLUS_ICEBP vaddsubps, XMM1, XMM2, FSxBX
549	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, XMM8, XMM9, XMM10
550	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, XMM8, XMM9, FSxBX
551
552	EMIT_INSTR_PLUS_ICEBP vaddsubps, YMM1, YMM2, YMM3
553	EMIT_INSTR_PLUS_ICEBP vaddsubps, YMM1, YMM2, FSxBX
554	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, YMM13, YMM14, YMM15
555	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, YMM13, YMM14, FSxBX
556
557	;
558	;; [v]addsubpd
559	;
560	EMIT_INSTR_PLUS_ICEBP addsubpd, XMM1, XMM2
561	EMIT_INSTR_PLUS_ICEBP addsubpd, XMM1, FSxBX
562	EMIT_INSTR_PLUS_ICEBP_C64 addsubpd, XMM8, XMM9
563	EMIT_INSTR_PLUS_ICEBP_C64 addsubpd, XMM8, FSxBX
564
565	EMIT_INSTR_PLUS_ICEBP vaddsubpd, XMM1, XMM2, XMM3
566	EMIT_INSTR_PLUS_ICEBP vaddsubpd, XMM1, XMM2, FSxBX
567	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubpd, XMM8, XMM9, XMM10
568	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubpd, XMM8, XMM9, FSxBX
569
570	EMIT_INSTR_PLUS_ICEBP vaddsubpd, YMM1, YMM2, YMM3
571	EMIT_INSTR_PLUS_ICEBP vaddsubpd, YMM1, YMM2, FSxBX
572	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubpd, YMM13, YMM14, YMM15
573	EMIT_INSTR_PLUS_ICEBP_C64 vaddsubpd, YMM13, YMM14, FSxBX
574
575	;
576	;; [v]maxps
577	;
578	EMIT_INSTR_PLUS_ICEBP maxps, XMM1, XMM2
579	EMIT_INSTR_PLUS_ICEBP maxps, XMM1, FSxBX
580	EMIT_INSTR_PLUS_ICEBP_C64 maxps, XMM8, XMM9
581	EMIT_INSTR_PLUS_ICEBP_C64 maxps, XMM8, FSxBX
582
583	EMIT_INSTR_PLUS_ICEBP vmaxps, XMM1, XMM2, XMM3
584	EMIT_INSTR_PLUS_ICEBP vmaxps, XMM1, XMM2, FSxBX
585	EMIT_INSTR_PLUS_ICEBP_C64 vmaxps, XMM8, XMM9, XMM10
586	EMIT_INSTR_PLUS_ICEBP_C64 vmaxps, XMM8, XMM9, FSxBX
587
588	EMIT_INSTR_PLUS_ICEBP vmaxps, YMM1, YMM2, YMM3
589	EMIT_INSTR_PLUS_ICEBP vmaxps, YMM1, YMM2, FSxBX
590	EMIT_INSTR_PLUS_ICEBP_C64 vmaxps, YMM8, YMM9, YMM10
591	EMIT_INSTR_PLUS_ICEBP_C64 vmaxps, YMM8, YMM9, FSxBX
592
593	;
594	;; [v]maxpd
595	;
596	EMIT_INSTR_PLUS_ICEBP maxpd, XMM1, XMM2
597	EMIT_INSTR_PLUS_ICEBP maxpd, XMM1, FSxBX
598	EMIT_INSTR_PLUS_ICEBP_C64 maxpd, XMM8, XMM9
599	EMIT_INSTR_PLUS_ICEBP_C64 maxpd, XMM8, FSxBX
600
601	EMIT_INSTR_PLUS_ICEBP vmaxpd, XMM1, XMM2, XMM3
602	EMIT_INSTR_PLUS_ICEBP vmaxpd, XMM1, XMM2, FSxBX
603	EMIT_INSTR_PLUS_ICEBP_C64 vmaxpd, XMM8, XMM9, XMM10
604	EMIT_INSTR_PLUS_ICEBP_C64 vmaxpd, XMM8, XMM9, FSxBX
605
606	EMIT_INSTR_PLUS_ICEBP vmaxpd, YMM1, YMM2, YMM3
607	EMIT_INSTR_PLUS_ICEBP vmaxpd, YMM1, YMM2, FSxBX
608	EMIT_INSTR_PLUS_ICEBP_C64 vmaxpd, YMM8, YMM9, YMM10
609	EMIT_INSTR_PLUS_ICEBP_C64 vmaxpd, YMM8, YMM9, FSxBX
610
611	;
612	;; [v]maxss
613	;
614	EMIT_INSTR_PLUS_ICEBP maxss, XMM3, XMM4
615	EMIT_INSTR_PLUS_ICEBP maxss, XMM3, FSxBX
616	EMIT_INSTR_PLUS_ICEBP_C64 maxss, XMM8, XMM9
617	EMIT_INSTR_PLUS_ICEBP_C64 maxss, XMM8, FSxBX
618
619	EMIT_INSTR_PLUS_ICEBP vmaxss, XMM1, XMM6, XMM7
620	EMIT_INSTR_PLUS_ICEBP vmaxss, XMM1, XMM6, FSxBX
621	EMIT_INSTR_PLUS_ICEBP_C64 vmaxss, XMM8, XMM9, XMM10
622	EMIT_INSTR_PLUS_ICEBP_C64 vmaxss, XMM8, XMM9, FSxBX
623
624	;
625	;; [v]maxsd
626	;
627	EMIT_INSTR_PLUS_ICEBP maxsd, XMM3, XMM4
628	EMIT_INSTR_PLUS_ICEBP maxsd, XMM3, FSxBX
629	EMIT_INSTR_PLUS_ICEBP_C64 maxsd, XMM8, XMM9
630	EMIT_INSTR_PLUS_ICEBP_C64 maxsd, XMM8, FSxBX
631
632	EMIT_INSTR_PLUS_ICEBP vmaxsd, XMM1, XMM6, XMM7
633	EMIT_INSTR_PLUS_ICEBP vmaxsd, XMM1, XMM6, FSxBX
634	EMIT_INSTR_PLUS_ICEBP_C64 vmaxsd, XMM8, XMM9, XMM10
635	EMIT_INSTR_PLUS_ICEBP_C64 vmaxsd, XMM8, XMM9, FSxBX
636
637	;
638	;; [v]minps
639	;
640	EMIT_INSTR_PLUS_ICEBP minps, XMM1, XMM2
641	EMIT_INSTR_PLUS_ICEBP minps, XMM1, FSxBX
642	EMIT_INSTR_PLUS_ICEBP_C64 minps, XMM8, XMM9
643	EMIT_INSTR_PLUS_ICEBP_C64 minps, XMM8, FSxBX
644
645	EMIT_INSTR_PLUS_ICEBP vminps, XMM1, XMM2, XMM3
646	EMIT_INSTR_PLUS_ICEBP vminps, XMM1, XMM2, FSxBX
647	EMIT_INSTR_PLUS_ICEBP_C64 vminps, XMM8, XMM9, XMM10
648	EMIT_INSTR_PLUS_ICEBP_C64 vminps, XMM8, XMM9, FSxBX
649
650	EMIT_INSTR_PLUS_ICEBP vminps, YMM1, YMM2, YMM3
651	EMIT_INSTR_PLUS_ICEBP vminps, YMM1, YMM2, FSxBX
652	EMIT_INSTR_PLUS_ICEBP_C64 vminps, YMM8, YMM9, YMM10
653	EMIT_INSTR_PLUS_ICEBP_C64 vminps, YMM8, YMM9, FSxBX
654
655	;
656	;; [v]minpd
657	;
658	EMIT_INSTR_PLUS_ICEBP minpd, XMM1, XMM2
659	EMIT_INSTR_PLUS_ICEBP minpd, XMM1, FSxBX
660	EMIT_INSTR_PLUS_ICEBP_C64 minpd, XMM8, XMM9
661	EMIT_INSTR_PLUS_ICEBP_C64 minpd, XMM8, FSxBX
662
663	EMIT_INSTR_PLUS_ICEBP vminpd, XMM1, XMM2, XMM3
664	EMIT_INSTR_PLUS_ICEBP vminpd, XMM1, XMM2, FSxBX
665	EMIT_INSTR_PLUS_ICEBP_C64 vminpd, XMM8, XMM9, XMM10
666	EMIT_INSTR_PLUS_ICEBP_C64 vminpd, XMM8, XMM9, FSxBX
667
668	EMIT_INSTR_PLUS_ICEBP vminpd, YMM1, YMM2, YMM3
669	EMIT_INSTR_PLUS_ICEBP vminpd, YMM1, YMM2, FSxBX
670	EMIT_INSTR_PLUS_ICEBP_C64 vminpd, YMM8, YMM9, YMM10
671	EMIT_INSTR_PLUS_ICEBP_C64 vminpd, YMM8, YMM9, FSxBX
672
673	;
674	;; [v]minss
675	;
676	EMIT_INSTR_PLUS_ICEBP minss, XMM3, XMM4
677	EMIT_INSTR_PLUS_ICEBP minss, XMM3, FSxBX
678	EMIT_INSTR_PLUS_ICEBP_C64 minss, XMM8, XMM9
679	EMIT_INSTR_PLUS_ICEBP_C64 minss, XMM8, FSxBX
680
681	EMIT_INSTR_PLUS_ICEBP vminss, XMM1, XMM6, XMM7
682	EMIT_INSTR_PLUS_ICEBP vminss, XMM1, XMM6, FSxBX
683	EMIT_INSTR_PLUS_ICEBP_C64 vminss, XMM8, XMM9, XMM10
684	EMIT_INSTR_PLUS_ICEBP_C64 vminss, XMM8, XMM9, FSxBX
685
686	;
687	;; [v]minsd
688	;
689	EMIT_INSTR_PLUS_ICEBP minsd, XMM3, XMM4
690	EMIT_INSTR_PLUS_ICEBP minsd, XMM3, FSxBX
691	EMIT_INSTR_PLUS_ICEBP_C64 minsd, XMM8, XMM9
692	EMIT_INSTR_PLUS_ICEBP_C64 minsd, XMM8, FSxBX
693
694	EMIT_INSTR_PLUS_ICEBP vminsd, XMM1, XMM6, XMM7
695	EMIT_INSTR_PLUS_ICEBP vminsd, XMM1, XMM6, FSxBX
696	EMIT_INSTR_PLUS_ICEBP_C64 vminsd, XMM8, XMM9, XMM10
697	EMIT_INSTR_PLUS_ICEBP_C64 vminsd, XMM8, XMM9, FSxBX
698
699	;
700	;; [v]rcpps
701	;
702	EMIT_INSTR_PLUS_ICEBP rcpps, XMM1, XMM2
703	EMIT_INSTR_PLUS_ICEBP rcpps, XMM1, FSxBX
704	EMIT_INSTR_PLUS_ICEBP_C64 rcpps, XMM8, XMM9
705	EMIT_INSTR_PLUS_ICEBP_C64 rcpps, XMM8, FSxBX
706
707	EMIT_INSTR_PLUS_ICEBP vrcpps, XMM1, XMM2
708	EMIT_INSTR_PLUS_ICEBP vrcpps, XMM1, FSxBX
709	EMIT_INSTR_PLUS_ICEBP_C64 vrcpps, XMM8, XMM9
710	EMIT_INSTR_PLUS_ICEBP_C64 vrcpps, XMM8, FSxBX
711
712	EMIT_INSTR_PLUS_ICEBP vrcpps, YMM1, YMM2
713	EMIT_INSTR_PLUS_ICEBP vrcpps, YMM1, FSxBX
714	EMIT_INSTR_PLUS_ICEBP_C64 vrcpps, YMM8, YMM9
715	EMIT_INSTR_PLUS_ICEBP_C64 vrcpps, YMM8, FSxBX
716
717	;
718	;; [v]rcpss
719	;
720	EMIT_INSTR_PLUS_ICEBP rcpss, XMM1, XMM2
721	EMIT_INSTR_PLUS_ICEBP rcpss, XMM1, FSxBX
722	EMIT_INSTR_PLUS_ICEBP_C64 rcpss, XMM8, XMM9
723	EMIT_INSTR_PLUS_ICEBP_C64 rcpss, XMM8, FSxBX
724
725	EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM2, XMM3
726	EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM2, FSxBX
727	EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM13, XMM14, XMM15
728	EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM13, XMM14, FSxBX
729
730	EMIT_INSTR_PLUS_ICEBP rcpss, XMM1, XMM1
731	EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM1, XMM1
732	EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM1, XMM2
733	EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM2, XMM2
734	EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM1, FSxBX
735	EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM15, XMM15, XMM15
736	EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM15, XMM15, XMM13
737	EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM13, XMM14, XMM14
738
739	;
740	;; [v]sqrtps
741	;
742	EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, XMM2
743	EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, FSxBX
744	EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, XMM9
745	EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, FSxBX
746
747	EMIT_INSTR_PLUS_ICEBP vsqrtps, XMM1, XMM2
748	EMIT_INSTR_PLUS_ICEBP vsqrtps, XMM1, FSxBX
749	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtps, XMM8, XMM9
750	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtps, XMM8, FSxBX
751
752	EMIT_INSTR_PLUS_ICEBP vsqrtps, YMM1, YMM2
753	EMIT_INSTR_PLUS_ICEBP vsqrtps, YMM1, FSxBX
754	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtps, YMM8, YMM9
755	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtps, YMM8, FSxBX
756
757	EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, XMM1
758	EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, XMM8
759	EMIT_INSTR_PLUS_ICEBP vsqrtps, XMM1, XMM1
760	EMIT_INSTR_PLUS_ICEBP vsqrtps, YMM1, YMM1
761	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtps, YMM8, YMM8
762
763	;
764	;; [v]sqrtpd
765	;
766	EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, XMM2
767	EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, FSxBX
768	EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, XMM9
769	EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, FSxBX
770
771	EMIT_INSTR_PLUS_ICEBP vsqrtpd, XMM1, XMM2
772	EMIT_INSTR_PLUS_ICEBP vsqrtpd, XMM1, FSxBX
773	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtpd, XMM8, XMM9
774	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtpd, XMM8, FSxBX
775
776	EMIT_INSTR_PLUS_ICEBP vsqrtpd, YMM1, YMM2
777	EMIT_INSTR_PLUS_ICEBP vsqrtpd, YMM1, FSxBX
778	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtpd, YMM8, YMM9
779	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtpd, YMM8, FSxBX
780
781	EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, XMM1
782	EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, XMM8
783	EMIT_INSTR_PLUS_ICEBP vsqrtpd, XMM1, XMM1
784	EMIT_INSTR_PLUS_ICEBP vsqrtpd, YMM1, YMM1
785	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtpd, YMM8, YMM8
786
787	;
788	;; [v]sqrtss
789	;
790	EMIT_INSTR_PLUS_ICEBP sqrtss, XMM1, XMM2
791	EMIT_INSTR_PLUS_ICEBP sqrtss, XMM1, FSxBX
792	EMIT_INSTR_PLUS_ICEBP_C64 sqrtss, XMM8, XMM9
793	EMIT_INSTR_PLUS_ICEBP_C64 sqrtss, XMM8, FSxBX
794
795	EMIT_INSTR_PLUS_ICEBP vsqrtss, XMM1, XMM2, XMM3
796	EMIT_INSTR_PLUS_ICEBP vsqrtss, XMM1, XMM2, FSxBX
797	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtss, XMM8, XMM9, XMM10
798	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtss, XMM8, XMM9, FSxBX
799
800	EMIT_INSTR_PLUS_ICEBP sqrtss, XMM1, XMM1
801	EMIT_INSTR_PLUS_ICEBP_C64 sqrtss, XMM8, XMM8
802	EMIT_INSTR_PLUS_ICEBP vsqrtss, XMM1, XMM1, XMM1
803	EMIT_INSTR_PLUS_ICEBP vsqrtss, XMM1, XMM1, XMM2
804	EMIT_INSTR_PLUS_ICEBP vsqrtss, XMM1, XMM2, XMM2
805	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtss, XMM8, XMM8, XMM8
806	EMIT_INSTR_PLUS_ICEBP vsqrtss, XMM1, XMM1, FSxBX
807
808	;
809	;; [v]sqrtsd
810	;
811	EMIT_INSTR_PLUS_ICEBP sqrtsd, XMM1, XMM2
812	EMIT_INSTR_PLUS_ICEBP sqrtsd, XMM1, FSxBX
813	EMIT_INSTR_PLUS_ICEBP_C64 sqrtsd, XMM8, XMM9
814	EMIT_INSTR_PLUS_ICEBP_C64 sqrtsd, XMM8, FSxBX
815
816	EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM2, XMM3
817	EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM2, FSxBX
818	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtsd, XMM8, XMM9, XMM10
819	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtsd, XMM8, XMM9, FSxBX
820
821	EMIT_INSTR_PLUS_ICEBP sqrtsd, XMM1, XMM1
822	EMIT_INSTR_PLUS_ICEBP_C64 sqrtsd, XMM8, XMM8
823	EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM1, XMM1
824	EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM1, XMM2
825	EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM2, XMM2
826	EMIT_INSTR_PLUS_ICEBP_C64 vsqrtsd, XMM8, XMM8, XMM8
827	EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM1, FSxBX
828
829	;
830	;; [v]rsqrtps
831	;
832	EMIT_INSTR_PLUS_ICEBP rsqrtps, XMM1, XMM2
833	EMIT_INSTR_PLUS_ICEBP rsqrtps, XMM1, FSxBX
834	EMIT_INSTR_PLUS_ICEBP_C64 rsqrtps, XMM8, XMM9
835	EMIT_INSTR_PLUS_ICEBP_C64 rsqrtps, XMM8, FSxBX
836
837	EMIT_INSTR_PLUS_ICEBP vrsqrtps, XMM1, XMM2
838	EMIT_INSTR_PLUS_ICEBP vrsqrtps, XMM1, FSxBX
839	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, XMM8, XMM9
840	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, XMM8, FSxBX
841
842	EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, YMM2
843	EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, FSxBX
844	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, YMM8, YMM9
845	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, YMM8, FSxBX
846
847	EMIT_INSTR_PLUS_ICEBP rsqrtps, XMM1, XMM1
848	EMIT_INSTR_PLUS_ICEBP_C64 rsqrtps, XMM8, XMM8
849	EMIT_INSTR_PLUS_ICEBP vrsqrtps, XMM1, XMM1
850	EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, YMM1
851	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, YMM8, YMM8
852
853	;
854	;; [v]rsqrtss
855	;
856	EMIT_INSTR_PLUS_ICEBP rsqrtss, XMM1, XMM2
857	EMIT_INSTR_PLUS_ICEBP rsqrtss, XMM1, FSxBX
858	EMIT_INSTR_PLUS_ICEBP_C64 rsqrtss, XMM8, XMM9
859	EMIT_INSTR_PLUS_ICEBP_C64 rsqrtss, XMM8, FSxBX
860
861	EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM2, XMM3
862	EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM2, FSxBX
863	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtss, XMM8, XMM9, XMM10
864	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtss, XMM8, XMM9, FSxBX
865
866	EMIT_INSTR_PLUS_ICEBP rsqrtss, XMM1, XMM1
867	EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM1, XMM1
868	EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM1, XMM2
869	EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM2, XMM2
870	EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM1, FSxBX
871	EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtss, XMM8, XMM8, XMM8
872
873	;
874	;; cvtpi2ps
875	;
876	; SSE-128, fp32 <- int32 (packed:2; from MMX register)
877	EMIT_INSTR_PLUS_ICEBP cvtpi2ps, XMM1, MM1
878	EMIT_INSTR_PLUS_ICEBP cvtpi2ps, XMM1, FSxBX
879	EMIT_INSTR_PLUS_ICEBP_C64 cvtpi2ps, XMM8, MM1
880	EMIT_INSTR_PLUS_ICEBP_C64 cvtpi2ps, XMM8, FSxBX
881
882	;
883	;; cvtps2pi
884	;
885	; SSE-128, int32 <- fp32 (packed:2; to MMX register)
886	EMIT_INSTR_PLUS_ICEBP cvtps2pi, MM1, XMM1
887	EMIT_INSTR_PLUS_ICEBP cvtps2pi, MM1, FSxBX
888	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2pi, MM1, XMM8
889
890	;
891	;; cvttps2pi
892	;
893	; SSE-128, int32 <- fp32 (packed:2; truncated; to MMX register)
894	EMIT_INSTR_PLUS_ICEBP cvttps2pi, MM1, XMM1
895	EMIT_INSTR_PLUS_ICEBP cvttps2pi, MM1, FSxBX
896	EMIT_INSTR_PLUS_ICEBP_C64 cvttps2pi, MM1, XMM8
897
898	;
899	;; cvtsi2ss
900	;
901	; SSE-128, fp32 <- int32 (single)
902	EMIT_INSTR_PLUS_ICEBP cvtsi2ss, XMM1, EAX
903	EMIT_INSTR_PLUS_ICEBP cvtsi2ss, XMM1, FSxBX_D
904	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2ss, XMM8, R8D
905	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2ss, XMM8, FSxBX_D
906	; SSE-128, fp32 <- int64 (single)
907	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2ss, XMM1, RAX
908	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2ss, XMM1, FSxBX_Q
909	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2ss, XMM8, R8
910	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2ss, XMM8, FSxBX_Q
911	; AVX-128, fp32 <- int32 (single)
912	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM2, EAX
913	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM2, FSxBX_D
914	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM9, R8D
915	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM9, FSxBX_D
916	; AVX-128, fp32 <- int64 (single)
917	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM2, RAX ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
918	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM2, FSxBX_Q ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
919	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM9, R8
920	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM9, FSxBX_Q
921	; AVX-128, fp32 <- int32, same-reg (single)
922	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM1, EAX
923	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM1, FSxBX_D
924	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM8, R8D
925	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM8, FSxBX_D
926	; AVX-128, fp32 <- int64, same-reg (single)
927	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM1, RAX ;; @todo this assembles in 16/32 mode, but should it...?
928	EMIT_INSTR_PLUS_ICEBP vcvtsi2ss, XMM1, XMM1, FSxBX_Q ;; @todo this assembles in 16/32 mode, but should it...?
929	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM8, R8
930	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2ss, XMM8, XMM8, FSxBX_Q
931	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
932	; @todo same-reg fp32 <- int32 (SDM says W1 ignored in 32-bit modes) (see above)
933
934	;
935	;; cvtss2si
936	;
937	; SSE-128, int32 <- fp32
938	EMIT_INSTR_PLUS_ICEBP cvtss2si, EAX, XMM1
939	EMIT_INSTR_PLUS_ICEBP cvtss2si, EAX, FSxBX
940	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2si, R8D, XMM8
941	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2si, R8D, FSxBX
942	; SSE-128, int64 <- fp32
943	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2si, RAX, XMM1
944	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2si, RAX, FSxBX
945	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2si, R8, XMM8
946	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2si, R8, FSxBX
947	; AVX-128, int32 <- fp32
948	EMIT_INSTR_PLUS_ICEBP vcvtss2si, EAX, XMM1
949	EMIT_INSTR_PLUS_ICEBP vcvtss2si, EAX, FSxBX
950	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2si, R8D, XMM8
951	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2si, R8D, FSxBX
952	; AVX-128, int64 <- fp32
953	EMIT_INSTR_PLUS_ICEBP vcvtss2si, RAX, XMM1
954	EMIT_INSTR_PLUS_ICEBP vcvtss2si, RAX, FSxBX
955	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2si, R8, XMM8
956	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2si, R8, FSxBX
957	; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
958	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
959
960	;
961	;; cvttss2si
962	;
963	; SSE-128, int32 <- fp32 (single; truncated)
964	EMIT_INSTR_PLUS_ICEBP cvttss2si, EAX, XMM1
965	EMIT_INSTR_PLUS_ICEBP cvttss2si, EAX, FSxBX
966	EMIT_INSTR_PLUS_ICEBP_C64 cvttss2si, R8D, XMM8
967	EMIT_INSTR_PLUS_ICEBP_C64 cvttss2si, R8D, FSxBX
968	; SSE-128, int64 <- fp32 (single; truncated)
969	EMIT_INSTR_PLUS_ICEBP_C64 cvttss2si, RAX, XMM1
970	EMIT_INSTR_PLUS_ICEBP_C64 cvttss2si, RAX, FSxBX
971	EMIT_INSTR_PLUS_ICEBP_C64 cvttss2si, R8, XMM8
972	EMIT_INSTR_PLUS_ICEBP_C64 cvttss2si, R8, FSxBX
973	; AVX-128, int32 <- fp32 (single; truncated)
974	EMIT_INSTR_PLUS_ICEBP vcvttss2si, EAX, XMM1
975	EMIT_INSTR_PLUS_ICEBP vcvttss2si, EAX, FSxBX
976	EMIT_INSTR_PLUS_ICEBP_C64 vcvttss2si, R8D, XMM8
977	EMIT_INSTR_PLUS_ICEBP_C64 vcvttss2si, R8D, FSxBX
978	; AVX-128, int64 <- fp32 (single; truncated)
979	EMIT_INSTR_PLUS_ICEBP vcvttss2si, RAX, XMM1
980	EMIT_INSTR_PLUS_ICEBP vcvttss2si, RAX, FSxBX
981	EMIT_INSTR_PLUS_ICEBP_C64 vcvttss2si, R8, XMM8
982	EMIT_INSTR_PLUS_ICEBP_C64 vcvttss2si, R8, FSxBX
983	; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
984	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
985
986	;
987	;; cvtpi2pd
988	;
989	; SSE-128, fp64 <- int32 (packed:2; from MMX register)
990	EMIT_INSTR_PLUS_ICEBP cvtpi2pd, XMM1, MM1
991	EMIT_INSTR_PLUS_ICEBP cvtpi2pd, XMM1, FSxBX
992	EMIT_INSTR_PLUS_ICEBP_C64 cvtpi2pd, XMM8, MM1
993	EMIT_INSTR_PLUS_ICEBP_C64 cvtpi2pd, XMM8, FSxBX
994	; note: transition from x87 FPU to MMX; takes FPU exceptions (MM forms only)
995
996	;
997	;; cvtpd2pi
998	;
999	; SSE-128, int32 <- fp64 (packed:2; to MMX register)
1000	EMIT_INSTR_PLUS_ICEBP cvtpd2pi, MM1, XMM1
1001	EMIT_INSTR_PLUS_ICEBP cvtpd2pi, MM1, FSxBX
1002	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2pi, MM1, XMM8
1003	; note: transition from x87 FPU to MMX; takes FPU exceptions
1004
1005	;
1006	;; cvttpd2pi
1007	;
1008	; SSE-128, int32 <- fp64 (packed:2; truncated; to MMX register)
1009	EMIT_INSTR_PLUS_ICEBP cvttpd2pi, MM1, XMM1
1010	EMIT_INSTR_PLUS_ICEBP cvttpd2pi, MM1, FSxBX
1011	EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2pi, MM1, XMM8
1012	; note: transition from x87 FPU to MMX; takes FPU exceptions
1013
1014	;
1015	;; cvtsi2sd
1016	;
1017	; SSE-128, fp64 <- int32 (single)
1018	EMIT_INSTR_PLUS_ICEBP cvtsi2sd, XMM1, EAX
1019	EMIT_INSTR_PLUS_ICEBP cvtsi2sd, XMM1, FSxBX_D
1020	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2sd, XMM8, R8D
1021	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2sd, XMM8, FSxBX_D
1022	; SSE-128, fp64 <- int64 (single)
1023	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2sd, XMM1, RAX
1024	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2sd, XMM1, FSxBX_Q
1025	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2sd, XMM8, R8
1026	EMIT_INSTR_PLUS_ICEBP_C64 cvtsi2sd, XMM8, FSxBX_Q
1027	; AVX-128, fp64 <- int32 (single)
1028	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM2, EAX
1029	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM2, FSxBX_D
1030	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM9, EAX
1031	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM9, FSxBX_D
1032	; AVX-128, fp64 <- int64 (single)
1033	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM2, RAX
1034	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM2, FSxBX_Q
1035	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM9, RAX
1036	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM9, FSxBX_Q
1037	; AVX-128, fp64 <- int32, same-reg (single)
1038	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM1, EAX
1039	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM1, FSxBX_D
1040	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM8, EAX
1041	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM8, FSxBX_D
1042	; AVX-128, fp64 <- int64, same-reg (single)
1043	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM1, RAX
1044	EMIT_INSTR_PLUS_ICEBP vcvtsi2sd, XMM1, XMM1, FSxBX_Q
1045	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM8, RAX
1046	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsi2sd, XMM8, XMM8, FSxBX_Q
1047	; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
1048	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
1049
1050	;
1051	;; cvtsd2si
1052	;
1053	; SSE-128, int32 <- fp64 (single)
1054	EMIT_INSTR_PLUS_ICEBP cvtsd2si, EAX, XMM1
1055	EMIT_INSTR_PLUS_ICEBP cvtsd2si, EAX, FSxBX
1056	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2si, R8D, XMM8
1057	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2si, R8D, FSxBX
1058	; SSE-128, int64 <- fp64 (single)
1059	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2si, RAX, XMM1
1060	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2si, RAX, FSxBX
1061	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2si, R8, XMM8
1062	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2si, R8, FSxBX
1063	; AVX-128, int32 <- fp64 (single)
1064	EMIT_INSTR_PLUS_ICEBP vcvtsd2si, EAX, XMM1
1065	EMIT_INSTR_PLUS_ICEBP vcvtsd2si, EAX, FSxBX
1066	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2si, R8D, XMM8
1067	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2si, R8D, FSxBX
1068	; AVX-128, int64 <- fp64 (single)
1069	EMIT_INSTR_PLUS_ICEBP vcvtsd2si, RAX, XMM1 ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
1070	EMIT_INSTR_PLUS_ICEBP vcvtsd2si, RAX, FSxBX ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
1071	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2si, R8, XMM8
1072	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2si, R8, FSxBX
1073	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
1074	; @todo same-reg fp32 <- int32 (SDM says W1 ignored in 32-bit modes) (see above)
1075
1076	;
1077	;; cvttsd2si
1078	;
1079	; SSE-128, int32 <- fp64 (single; truncated)
1080	EMIT_INSTR_PLUS_ICEBP cvttsd2si, EAX, XMM1
1081	EMIT_INSTR_PLUS_ICEBP cvttsd2si, EAX, FSxBX
1082	EMIT_INSTR_PLUS_ICEBP_C64 cvttsd2si, R8D, XMM8
1083	EMIT_INSTR_PLUS_ICEBP_C64 cvttsd2si, R8D, FSxBX
1084	; SSE-128, int64 <- fp64 (single; truncated)
1085	EMIT_INSTR_PLUS_ICEBP_C64 cvttsd2si, RAX, XMM1
1086	EMIT_INSTR_PLUS_ICEBP_C64 cvttsd2si, RAX, FSxBX
1087	EMIT_INSTR_PLUS_ICEBP_C64 cvttsd2si, R8, XMM8
1088	EMIT_INSTR_PLUS_ICEBP_C64 cvttsd2si, R8, FSxBX
1089	; AVX-128, int32 <- fp64 (single; truncated)
1090	EMIT_INSTR_PLUS_ICEBP vcvttsd2si, EAX, XMM1
1091	EMIT_INSTR_PLUS_ICEBP vcvttsd2si, EAX, FSxBX
1092	EMIT_INSTR_PLUS_ICEBP_C64 vcvttsd2si, R8D, XMM8
1093	EMIT_INSTR_PLUS_ICEBP_C64 vcvttsd2si, R8D, FSxBX
1094	; AVX-128, int64 <- fp64 (single; truncated)
1095	EMIT_INSTR_PLUS_ICEBP vcvttsd2si, RAX, XMM1
1096	EMIT_INSTR_PLUS_ICEBP vcvttsd2si, RAX, FSxBX
1097	EMIT_INSTR_PLUS_ICEBP_C64 vcvttsd2si, R8, XMM8
1098	EMIT_INSTR_PLUS_ICEBP_C64 vcvttsd2si, R8, FSxBX
1099	; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
1100	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
1101
1102	;
1103	;; cvtdq2ps
1104	;
1105	; SSE-128, fp32 <- int32 (packed:4)
1106	EMIT_INSTR_PLUS_ICEBP cvtdq2ps, XMM1, XMM2
1107	EMIT_INSTR_PLUS_ICEBP cvtdq2ps, XMM1, FSxBX
1108	EMIT_INSTR_PLUS_ICEBP_C64 cvtdq2ps, XMM8, XMM9
1109	EMIT_INSTR_PLUS_ICEBP_C64 cvtdq2ps, XMM8, FSxBX
1110	; AVX-128, fp32 <- int32 (packed:4)
1111	EMIT_INSTR_PLUS_ICEBP vcvtdq2ps, XMM1, XMM2
1112	EMIT_INSTR_PLUS_ICEBP vcvtdq2ps, XMM1, FSxBX
1113	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2ps, XMM8, XMM9
1114	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2ps, XMM8, FSxBX
1115	; AVX-256, fp32 <- int32 (packed:8)
1116	EMIT_INSTR_PLUS_ICEBP vcvtdq2ps, YMM1, YMM2
1117	EMIT_INSTR_PLUS_ICEBP vcvtdq2ps, YMM1, FSxBX
1118	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2ps, YMM8, YMM9
1119	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2ps, YMM8, FSxBX
1120	; SSE-128, fp32 <- int32, same-reg (packed:4)
1121	EMIT_INSTR_PLUS_ICEBP cvtdq2ps, XMM1, XMM1
1122	EMIT_INSTR_PLUS_ICEBP_C64 cvtdq2ps, XMM8, XMM8
1123	; AVX-128, fp32 <- int32, same-reg (packed:4)
1124	EMIT_INSTR_PLUS_ICEBP vcvtdq2ps, XMM1, XMM1
1125	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2ps, XMM8, XMM8
1126	; AVX-256, fp32 <- int32, same-reg (packed:8)
1127	EMIT_INSTR_PLUS_ICEBP vcvtdq2ps, YMM1, YMM1
1128	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2ps, YMM8, YMM8
1129
1130	;
1131	;; cvtps2dq
1132	;
1133	; SSE-128, int32 <- fp32 (packed:4)
1134	EMIT_INSTR_PLUS_ICEBP cvtps2dq, XMM1, XMM2
1135	EMIT_INSTR_PLUS_ICEBP cvtps2dq, XMM1, FSxBX
1136	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2dq, XMM8, XMM9
1137	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2dq, XMM8, FSxBX
1138	; AVX-128, int32 <- fp32 (packed:4)
1139	EMIT_INSTR_PLUS_ICEBP vcvtps2dq, XMM1, XMM2
1140	EMIT_INSTR_PLUS_ICEBP vcvtps2dq, XMM1, FSxBX
1141	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2dq, XMM8, XMM9
1142	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2dq, XMM8, FSxBX
1143	; AVX-256, int32 <- fp32 (packed:8)
1144	EMIT_INSTR_PLUS_ICEBP vcvtps2dq, YMM1, YMM2
1145	EMIT_INSTR_PLUS_ICEBP vcvtps2dq, YMM1, FSxBX
1146	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2dq, YMM8, YMM9
1147	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2dq, YMM8, FSxBX
1148	; SSE-128, int32 <- fp32, same-reg (packed:4)
1149	EMIT_INSTR_PLUS_ICEBP cvtps2dq, XMM1, XMM1
1150	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2dq, XMM8, XMM8
1151	; AVX-128, int32 <- fp32, same-reg (packed:4)
1152	EMIT_INSTR_PLUS_ICEBP vcvtps2dq, XMM1, XMM1
1153	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2dq, XMM8, XMM8
1154	; AVX-256, int32 <- fp32, same-reg (packed:8)
1155	EMIT_INSTR_PLUS_ICEBP vcvtps2dq, YMM1, YMM1
1156	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2dq, YMM8, YMM8
1157
1158	;
1159	;; cvttps2dq
1160	;
1161	; SSE-128, int32 <- fp32 (packed:4; truncated)
1162	EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, XMM2
1163	EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, FSxBX_O
1164	EMIT_INSTR_PLUS_ICEBP_C64 cvttps2dq, XMM8, XMM9
1165	EMIT_INSTR_PLUS_ICEBP_C64 cvttps2dq, XMM8, FSxBX_O
1166	; AVX-128, int32 <- fp32 (packed:4; truncated)
1167	EMIT_INSTR_PLUS_ICEBP vcvttps2dq, XMM1, XMM2
1168	EMIT_INSTR_PLUS_ICEBP vcvttps2dq, XMM1, FSxBX_O
1169	EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, XMM8, XMM9
1170	EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, XMM8, FSxBX_O
1171	; AVX-256, int32 <- fp32 (packed:8; truncated)
1172	EMIT_INSTR_PLUS_ICEBP vcvttps2dq, YMM1, YMM2
1173	EMIT_INSTR_PLUS_ICEBP vcvttps2dq, YMM1, FSxBX_Y
1174	EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, YMM8, YMM9
1175	EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, YMM8, FSxBX_Y
1176	; AVX-128, int32 <- fp32, same-reg (packed:4; truncated)
1177	EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, XMM1
1178	EMIT_INSTR_PLUS_ICEBP_C64 cvttps2dq, XMM8, XMM8
1179	; AVX-128, int32 <- fp32, same-reg (packed:4; truncated)
1180	EMIT_INSTR_PLUS_ICEBP vcvttps2dq, XMM1, XMM1
1181	EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, XMM8, XMM8
1182	; AVX-256, int32 <- fp32, same-reg (packed:8; truncated)
1183	EMIT_INSTR_PLUS_ICEBP vcvttps2dq, YMM1, YMM1
1184	EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, YMM8, YMM8
1185
1186	;
1187	;; cvtdq2pd
1188	;
1189	; SSE-128, fp64 <- int32 (packed:2)
1190	EMIT_INSTR_PLUS_ICEBP cvtdq2pd, XMM1, XMM2
1191	EMIT_INSTR_PLUS_ICEBP cvtdq2pd, XMM1, FSxBX
1192	EMIT_INSTR_PLUS_ICEBP_C64 cvtdq2pd, XMM8, XMM9
1193	EMIT_INSTR_PLUS_ICEBP_C64 cvtdq2pd, XMM8, FSxBX
1194	; AVX-128, fp64 <- int32 (packed:2)
1195	EMIT_INSTR_PLUS_ICEBP vcvtdq2pd, XMM1, XMM2
1196	EMIT_INSTR_PLUS_ICEBP vcvtdq2pd, XMM1, FSxBX
1197	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2pd, XMM8, XMM9
1198	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2pd, XMM8, FSxBX
1199	; AVX-256, fp64 <- int32 (packed:4)
1200	EMIT_INSTR_PLUS_ICEBP vcvtdq2pd, YMM1, XMM2
1201	EMIT_INSTR_PLUS_ICEBP vcvtdq2pd, YMM1, FSxBX
1202	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2pd, YMM8, XMM9
1203	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2pd, YMM8, FSxBX
1204	; SSE-128, fp64 <- int32, same-reg (packed:2)
1205	EMIT_INSTR_PLUS_ICEBP cvtdq2pd, XMM1, XMM1
1206	EMIT_INSTR_PLUS_ICEBP_C64 cvtdq2pd, XMM8, XMM8
1207	; AVX-128, fp64 <- int32, same-reg (packed:2)
1208	EMIT_INSTR_PLUS_ICEBP vcvtdq2pd, XMM1, XMM1
1209	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2pd, XMM8, XMM8
1210	; AVX-256, fp64 <- int32, same-reg (packed:4)
1211	EMIT_INSTR_PLUS_ICEBP vcvtdq2pd, YMM1, XMM1
1212	EMIT_INSTR_PLUS_ICEBP_C64 vcvtdq2pd, YMM8, XMM8
1213
1214	;
1215	;; cvtpd2dq
1216	;
1217	; SSE-128, int32 <- fp64 (packed:2)
1218	EMIT_INSTR_PLUS_ICEBP cvtpd2dq, XMM1, XMM2
1219	EMIT_INSTR_PLUS_ICEBP cvtpd2dq, XMM1, FSxBX
1220	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2dq, XMM8, XMM9
1221	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2dq, XMM8, FSxBX
1222	; AVX-128, int32 <- fp64 (packed:2)
1223	EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, XMM2
1224	EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, FSxBX
1225	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, XMM9
1226	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, FSxBX
1227	; AVX-256, int32 <- fp64 (packed:4)
1228	EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, YMM2
1229	EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, YMM1, FSxBX
1230	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, YMM9
1231	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, YMM8, FSxBX
1232	; SSE-128, int32 <- fp64, same-reg (packed:2)
1233	EMIT_INSTR_PLUS_ICEBP cvtpd2dq, XMM1, XMM1
1234	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2dq, XMM8, XMM8
1235	; AVX-128, int32 <- fp64, same-reg (packed:2)
1236	EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, XMM1
1237	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, XMM8
1238	; AVX-256, int32 <- fp64, same-reg (packed:4)
1239	EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, YMM1
1240	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, YMM8
1241
1242	;
1243	;; cvttpd2dq
1244	;
1245	; SSE-128, int32 <- fp64 (packed:2; truncated)
1246	EMIT_INSTR_PLUS_ICEBP cvttpd2dq, XMM1, XMM2
1247	EMIT_INSTR_PLUS_ICEBP cvttpd2dq, XMM1, FSxBX_O
1248	EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2dq, XMM8, XMM9
1249	EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2dq, XMM8, FSxBX_O
1250	; AVX-128, int32 <- fp64 (packed:2; truncated)
1251	EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, XMM2
1252	EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, FSxBX_O
1253	EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, XMM9
1254	EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, FSxBX_O
1255	; AVX-256, int32 <- fp64 (packed:4; truncated)
1256	EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, YMM2
1257	EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, FSxBX_Y
1258	EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, YMM9
1259	EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, FSxBX_Y
1260	; AVX-128, int32 <- fp64, same-reg (packed:2; truncated)
1261	EMIT_INSTR_PLUS_ICEBP cvttpd2dq, XMM1, XMM1
1262	EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2dq, XMM8, XMM8
1263	; AVX-128, int32 <- fp64, same-reg (packed:2; truncated)
1264	EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, XMM1
1265	EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, XMM8
1266	; AVX-256, int32 <- fp64, same-reg (packed:4; truncated)
1267	EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, YMM1
1268	EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, YMM8
1269
1270	;
1271	;; cvtpd2ps
1272	;
1273	; SSE-128, fp32 <- fp64 (packed:2)
1274	EMIT_INSTR_PLUS_ICEBP cvtpd2ps, XMM1, XMM2
1275	EMIT_INSTR_PLUS_ICEBP cvtpd2ps, XMM1, FSxBX
1276	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2ps, XMM8, XMM9
1277	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2ps, XMM8, FSxBX
1278	; AVX-128, fp32 <- fp64 (packed:2)
1279	EMIT_INSTR_PLUS_ICEBP vcvtpd2ps, XMM1, XMM2
1280	EMIT_INSTR_PLUS_ICEBP vcvtpd2ps, XMM1, FSxBX_O
1281	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2ps, XMM8, XMM9
1282	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2ps, XMM8, FSxBX_O
1283	; AVX-256, fp32 <- fp64 (packed:4)
1284	EMIT_INSTR_PLUS_ICEBP vcvtpd2ps, XMM1, YMM2
1285	EMIT_INSTR_PLUS_ICEBP vcvtpd2ps, XMM1, FSxBX_Y
1286	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2ps, XMM8, YMM9
1287	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2ps, XMM8, FSxBX_Y
1288	; SSE-128, fp32 <- fp64, same-reg (packed:2)
1289	EMIT_INSTR_PLUS_ICEBP cvtpd2ps, XMM1, XMM1
1290	EMIT_INSTR_PLUS_ICEBP_C64 cvtpd2ps, XMM8, XMM8
1291	; AVX-128, fp32 <- fp64, same-reg (packed:2)
1292	EMIT_INSTR_PLUS_ICEBP vcvtpd2ps, XMM1, XMM1
1293	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2ps, XMM8, XMM8
1294	; AVX-256, fp32 <- fp64, same-reg (packed:4)
1295	EMIT_INSTR_PLUS_ICEBP vcvtpd2ps, XMM1, YMM1
1296	EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2ps, XMM8, YMM8
1297
1298	;
1299	;; cvtps2pd
1300	;
1301	; SSE-128, fp64 <- fp32 (packed:2)
1302	EMIT_INSTR_PLUS_ICEBP cvtps2pd, XMM1, XMM2
1303	EMIT_INSTR_PLUS_ICEBP cvtps2pd, XMM1, FSxBX
1304	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2pd, XMM8, XMM9
1305	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2pd, XMM8, FSxBX
1306	; AVX-128, fp64 <- fp32 (packed:2)
1307	EMIT_INSTR_PLUS_ICEBP vcvtps2pd, XMM1, XMM2
1308	EMIT_INSTR_PLUS_ICEBP vcvtps2pd, XMM1, FSxBX
1309	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, XMM8, XMM9
1310	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, XMM8, FSxBX
1311	; AVX-256, fp64 <- fp32 (packed:4)
1312	EMIT_INSTR_PLUS_ICEBP vcvtps2pd, YMM1, XMM2
1313	EMIT_INSTR_PLUS_ICEBP vcvtps2pd, YMM1, FSxBX_O
1314	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, YMM8, XMM9
1315	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, YMM8, FSxBX_O
1316	; SSE-128, fp64 <- fp32, same-reg (packed:2)
1317	EMIT_INSTR_PLUS_ICEBP cvtps2pd, XMM1, XMM1
1318	EMIT_INSTR_PLUS_ICEBP_C64 cvtps2pd, XMM8, XMM8
1319	; AVX-128, fp64 <- fp32, same-reg (packed:2)
1320	EMIT_INSTR_PLUS_ICEBP vcvtps2pd, XMM1, XMM1
1321	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, XMM8, XMM8
1322	; AVX-256, fp64 <- fp32, same-reg (packed:4)
1323	EMIT_INSTR_PLUS_ICEBP vcvtps2pd, YMM1, XMM1
1324	EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, YMM8, XMM8
1325
1326	;
1327	;; cvtsd2ss
1328	;
1329	; SSE-128, fp32 <- fp64 (single)
1330	EMIT_INSTR_PLUS_ICEBP cvtsd2ss, XMM1, XMM2
1331	EMIT_INSTR_PLUS_ICEBP cvtsd2ss, XMM1, FSxBX
1332	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2ss, XMM8, XMM9
1333	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2ss, XMM8, FSxBX
1334	; AVX-128, fp32 <- fp64 (single)
1335	EMIT_INSTR_PLUS_ICEBP vcvtsd2ss, XMM1, XMM2, XMM3
1336	EMIT_INSTR_PLUS_ICEBP vcvtsd2ss, XMM1, XMM2, FSxBX
1337	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM8, XMM9, XMM10
1338	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM8, XMM9, FSxBX
1339	; SSE-128, fp32 <- fp64, same-reg (single)
1340	EMIT_INSTR_PLUS_ICEBP cvtsd2ss, XMM1, XMM1
1341	EMIT_INSTR_PLUS_ICEBP_C64 cvtsd2ss, XMM8, XMM8
1342	; AVX-128, fp32 <- fp64, same-reg (single)
1343	EMIT_INSTR_PLUS_ICEBP vcvtsd2ss, XMM1, XMM1, XMM1
1344	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM1, XMM1, XMM8
1345	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM1, XMM8, XMM8
1346	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM1, XMM8, XMM1
1347	EMIT_INSTR_PLUS_ICEBP vcvtsd2ss, XMM1, XMM1, FSxBX
1348	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM8, XMM8, XMM8
1349	EMIT_INSTR_PLUS_ICEBP_C64 vcvtsd2ss, XMM8, XMM8, FSxBX
1350	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
1351
1352	;
1353	;; cvtss2sd
1354	;
1355	; SSE-128, fp64 <- fp32 (single)
1356	EMIT_INSTR_PLUS_ICEBP cvtss2sd, XMM1, XMM2
1357	EMIT_INSTR_PLUS_ICEBP cvtss2sd, XMM1, FSxBX
1358	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2sd, XMM8, XMM9
1359	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2sd, XMM8, FSxBX
1360	; AVX-128, fp64 <- fp32 (single)
1361	EMIT_INSTR_PLUS_ICEBP vcvtss2sd, XMM1, XMM2, XMM3
1362	EMIT_INSTR_PLUS_ICEBP vcvtss2sd, XMM1, XMM2, FSxBX
1363	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM8, XMM9, XMM10
1364	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM8, XMM9, FSxBX
1365	; SSE-128, fp64 <- fp32, same-reg (single)
1366	EMIT_INSTR_PLUS_ICEBP cvtss2sd, XMM1, XMM1
1367	EMIT_INSTR_PLUS_ICEBP_C64 cvtss2sd, XMM8, XMM8
1368	; AVX-128, fp64 <- fp32, same-reg (single)
1369	EMIT_INSTR_PLUS_ICEBP vcvtss2sd, XMM1, XMM1, XMM1
1370	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM1, XMM1, XMM8
1371	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM1, XMM8, XMM8
1372	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM1, XMM8, XMM1
1373	EMIT_INSTR_PLUS_ICEBP vcvtss2sd, XMM1, XMM1, FSxBX
1374	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM8, XMM8, XMM8
1375	EMIT_INSTR_PLUS_ICEBP_C64 vcvtss2sd, XMM8, XMM8, FSxBX
1376	; @todo test with VEX.L=1 (as if asking for YMM)? SDM says 'unpredictable behavior'...
1377
1378	%endif ; BS3_INSTANTIATING_CMN
1379
1380	%include "bs3kit-template-footer.mac" ; reset environment

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