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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac@ 95818

Last change on this file since 95818 was 95465, checked in by vboxsync, 2 years ago

ValKit/bs3-cpu-instr-2: Simple crc32 instruction test. bugref:9898
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1; $Id: bs3-cpu-instr-2-template.mac 95465 2022-07-01 00:44:40Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-instr-2 assembly template.
4;
5
6;
7; Copyright (C) 2007-2022 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; The contents of this file may alternatively be used under the terms
18; of the Common Development and Distribution License Version 1.0
19; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20; VirtualBox OSE distribution, in which case the provisions of the
21; CDDL are applicable instead of those of the GPL.
22;
23; You may elect to license modified versions of this file under the
24; terms and conditions of either the GPL or the CDDL or both.
25;
26
27
28;*********************************************************************************************************************************
29;* Header Files *
30;*********************************************************************************************************************************
31%include "bs3kit-template-header.mac" ; setup environment
32
33
34;*********************************************************************************************************************************
35;* Defined Constants And Macros *
36;*********************************************************************************************************************************
37;;
38; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function
39; with an instruction length byte.
40;
41; ASSUMES the length is between the start of the function and the .again label.
42;
43%ifndef BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
44 %define BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
45 %macro BS3CPUINSTR2_PROC_BEGIN_CMN 1
46 align 8, db 0cch
47 db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
48BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR
49 %endmacro
50%endif
51
52
53;*********************************************************************************************************************************
54;* External Symbols *
55;*********************************************************************************************************************************
56TMPL_BEGIN_TEXT
57
58
59;
60; Test code snippets containing code which differs between 16-bit, 32-bit
61; and 64-bit CPUs modes.
62;
63%ifdef BS3_INSTANTIATING_CMN
64
65BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
66 mul xBX
67.again:
68 ud2
69 jmp .again
70BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2
71
72
73BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
74 imul xBX
75.again:
76 ud2
77 jmp .again
78BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2
79
80
81BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
82 imul xCX, xBX
83.again:
84 ud2
85 jmp .again
86BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2
87
88
89BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
90 div xBX
91.again:
92 ud2
93 jmp .again
94BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2
95
96
97BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
98 idiv xBX
99.again:
100 ud2
101 jmp .again
102BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2
103
104
105;
106; BSF / BSR / TZCNT / LZCNT
107;
108%ifndef EMIT_BITSCAN_DEFINED
109%define EMIT_BITSCAN_DEFINED
110%macro EMIT_BITSCAN 3
111BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR
112 %2
113 %1 ax, bx
114.again:
115 ud2
116 jmp .again
117BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2
118
119BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR
120 %2
121 %1 ax, [fs:xBX]
122.again:
123 ud2
124 jmp .again
125BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2
126
127BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR
128 %2
129 %1 eax, ebx
130.again:
131 ud2
132 jmp .again
133BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2
134
135BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR
136 %2
137 %1 eax, [fs:xBX]
138.again:
139 ud2
140 jmp .again
141BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2
142
143 %if TMPL_BITS == 64
144BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR
145 %2
146 %1 rax, rbx
147.again:
148 ud2
149 jmp .again
150BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2
151
152BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR
153 %2
154 %1 rax, [fs:xBX]
155.again:
156 ud2
157 jmp .again
158BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2
159 %endif
160%endmacro
161%endif
162
163EMIT_BITSCAN bsf, .ignored:, bsf
164EMIT_BITSCAN bsr, .ignored:, bsr
165EMIT_BITSCAN tzcnt, .ignored:, tzcnt
166EMIT_BITSCAN lzcnt, .ignored:, lzcnt
167EMIT_BITSCAN bsf, db 0f2h, f2_bsf
168EMIT_BITSCAN bsr, db 0f2h, f2_bsr
169EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt
170EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt
171
172
173;
174; RORX - VEX instruction with a couple of questions about non-standard encodings.
175;
176;;%define icebp ud2
177BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR
178 rorx ebx, edx, 2
179.again:
180 icebp
181 jmp .again
182BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp
183
184BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR
185%if TMPL_BITS == 64
186 rorx rbx, rdx, 2
187%else
188 db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe)
189%endif
190.again:
191 icebp
192 jmp .again
193BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp
194
195BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR
196 db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs
197.again:
198 icebp
199 jmp .again
200BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1
201
202BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR
203 db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD
204.again:
205 icebp
206 jmp .again
207BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1
208
209BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR
210 db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD
211.again:
212 icebp
213 jmp .again
214BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15
215
216 %if TMPL_BITS == 64
217BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR
218 db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe
219.again:
220 icebp
221 jmp .again
222BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1
223 %endif
224
225; A couple of memory variants
226BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp, BS3_PBC_NEAR
227 rorx ebx, [xDI], 36
228.again:
229 icebp
230 jmp .again
231BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp
232
233BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp, BS3_PBC_NEAR
234 %if TMPL_BITS == 64
235 rorx rbx, [xDI], 68
236 %elif TMPL_BITS == 32
237 db 0C4h,0E3h,07Bh,0F0h,01Fh,044h ; 16-bit ignores VEX.W=1 (10980xe)
238 %else
239 db 0C4h,0E3h,0FBh,0F0h,01Dh,044h ; 16-bit ignores VEX.W=1 (10980xe)
240 %endif
241.again:
242 icebp
243 jmp .again
244BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp
245
246;
247; ANDN (BMI1)
248;
249BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR
250%if TMPL_BITS == 64
251 andn rax, rcx, rbx
252%else
253 db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
254%endif
255.again:
256 icebp
257 jmp .again
258BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp
259
260BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR
261 andn eax, ecx, ebx
262.again:
263 icebp
264 jmp .again
265BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp
266
267
268BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
269%if TMPL_BITS == 64
270 andn rax, rcx, [fs:rbx]
271%elif TMPL_BITS == 32
272 db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx]
273%else
274 db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx]
275%endif
276.again:
277 icebp
278 jmp .again
279BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp
280
281BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
282 andn eax, ecx, [fs:xBX]
283.again:
284 icebp
285 jmp .again
286BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp
287
288
289;
290; BEXTR / SHLX / SARX / SHRX - BMI1 (opcode f7h)
291; BZHI - BMI2 (opcode f5h)
292;
293; @param %1 instruction
294; @param %2 opcode
295; @param %3 prefix
296;
297%ifndef SHLX_SARX_SHRX_DEFINED
298%define SHLX_SARX_SHRX_DEFINED
299%macro SHLX_SARX_SHRX 3
300
301BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR
302 %if TMPL_BITS == 64
303 %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3
304 %else
305 db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
306 %endif
307.again:
308 icebp
309 jmp .again
310BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp
311
312BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR
313 %1 eax, ebx, ecx
314.again:
315 icebp
316 jmp .again
317BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp
318
319BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR
320 %if TMPL_BITS == 64
321 %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703
322 %elif TMPL_BITS == 32
323 db 064h,0C4h,0E2h,0F0h|%3,%2,003h
324 %else
325 db 064h,0C4h,0E2h,0F0h|%3,%2,007h
326 %endif
327.again:
328 icebp
329 jmp .again
330BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp
331
332BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR
333 %1 eax, [fs:xBX], ecx
334.again:
335 icebp
336 jmp .again
337BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp
338
339%endmacro
340%endif
341
342SHLX_SARX_SHRX bextr, 0f7h, 0 ; none
343SHLX_SARX_SHRX shlx, 0f7h, 1 ; 66h
344SHLX_SARX_SHRX sarx, 0f7h, 2 ; f3h
345SHLX_SARX_SHRX shrx, 0f7h, 3 ; f2h
346SHLX_SARX_SHRX bzhi, 0f5h, 0 ; none
347
348;
349; PPEP / PEXT - BMI2 (opcode f5h)
350;
351; @param %1 instruction
352; @param %2 opcode
353; @param %3 prefix
354;
355%ifndef PDEP_PEXT_DEFINED
356%define PDEP_PEXT_DEFINED
357%macro PDEP_PEXT_ 3
358
359BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp, BS3_PBC_NEAR
360 %if TMPL_BITS == 64
361 %1 rax, rcx, rbx
362 %else
363 db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
364 %endif
365.again:
366 icebp
367 jmp .again
368BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp
369
370BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp, BS3_PBC_NEAR
371 %1 eax, ecx, ebx
372.again:
373 icebp
374 jmp .again
375BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp
376
377BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
378 %if TMPL_BITS == 64
379 %1 rax, rcx, [fs:rbx]
380 %elif TMPL_BITS == 32
381 db 064h,0C4h,0E2h,0F0h|%3,%2,003h
382 %else
383 db 064h,0C4h,0E2h,0F0h|%3,%2,007h
384 %endif
385.again:
386 icebp
387 jmp .again
388BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp
389
390BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
391 %1 eax, ecx, [fs:xBX]
392.again:
393 icebp
394 jmp .again
395BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp
396
397%endmacro
398%endif
399
400PDEP_PEXT_ pext, 0f5h, 2 ; f3h
401PDEP_PEXT_ pdep, 0f5h, 3 ; f2h
402
403;
404; BLSR / BLSMSK / BLSI
405; These are encoded in the exact same way, only the /r differs (%2).
406;
407%ifndef BLSR_BLSMSK_BLSI_DEFINED
408%define BLSR_BLSMSK_BLSI_DEFINED
409%macro BLSR_BLSMSK_BLSI 2
410
411BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR
412 %if TMPL_BITS == 64
413 %1 rax, rbx ; BLSR=C4E2F8F3CB
414 %else
415 db 0C4h,0E2h,0F8h,0F3h,0C3h | (%2 << 3) ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
416 %endif
417.again:
418 icebp
419 jmp .again
420BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp
421
422BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR
423 %1 eax, ebx
424.again:
425 icebp
426 jmp .again
427BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp
428
429BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR
430 %if TMPL_BITS == 64
431 %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B
432 %elif TMPL_BITS == 32
433 db 064h,0C4h,0E2h,0F8h,0F3h,003h | (%2 << 3)
434 %else
435 db 064h,0C4h,0E2h,0F8h,0F3h,007h | (%2 << 3)
436 %endif
437.again:
438 icebp
439 jmp .again
440BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp
441
442BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR
443 %1 eax, [fs:xBX]
444.again:
445 icebp
446 jmp .again
447BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp
448
449%endmacro
450%endif
451
452BLSR_BLSMSK_BLSI blsr, 1
453BLSR_BLSMSK_BLSI blsmsk, 2
454BLSR_BLSMSK_BLSI blsi, 3
455
456;
457; MULX
458;
459BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
460 %if TMPL_BITS == 64
461 mulx rax, rcx, rbx ; C4E2F3F6C3
462 %else
463 db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
464 %endif
465.again:
466 icebp
467 jmp .again
468BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp
469
470BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
471 %if TMPL_BITS == 64
472 mulx rcx, rcx, rbx ; C4E2F3F6CB
473 %else
474 db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
475 %endif
476.again:
477 icebp
478 jmp .again
479BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp
480
481BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR
482 %if TMPL_BITS == 64
483 mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603
484 %elif TMPL_BITS == 32
485 db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
486 %else
487 db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
488 %endif
489.again:
490 icebp
491 jmp .again
492BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp
493
494BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
495 mulx eax, ecx, ebx
496.again:
497 icebp
498 jmp .again
499BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp
500
501BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
502 mulx ecx, ecx, ebx
503.again:
504 icebp
505 jmp .again
506BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp
507
508BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR
509 mulx eax, ecx, [fs:xBX]
510.again:
511 icebp
512 jmp .again
513BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp
514
515
516;
517; POPCNT
518;
519BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_BX_icebp, BS3_PBC_NEAR
520 popcnt ax, bx
521.again:
522 icebp
523 jmp .again
524BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_BX_icebp
525
526BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp, BS3_PBC_NEAR
527 popcnt eax, ebx
528.again:
529 icebp
530 jmp .again
531BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp
532
533 %if TMPL_BITS == 64
534BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp, BS3_PBC_NEAR
535 popcnt rax, rbx
536.again:
537 icebp
538 jmp .again
539BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp
540 %endif
541
542
543BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp, BS3_PBC_NEAR
544 popcnt ax, [fs:xBX]
545.again:
546 icebp
547 jmp .again
548BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp
549
550BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp, BS3_PBC_NEAR
551 popcnt eax, [fs:xBX]
552.again:
553 icebp
554 jmp .again
555BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp
556
557 %if TMPL_BITS == 64
558BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp, BS3_PBC_NEAR
559 popcnt rax, [fs:xBX]
560.again:
561 icebp
562 jmp .again
563BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp
564 %endif
565
566
567;
568; CRC32
569;
570BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
571 crc32 eax, bl
572.again:
573 icebp
574 jmp .again
575BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
576
577BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
578 crc32 eax, bx
579.again:
580 icebp
581 jmp .again
582BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
583
584BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
585 crc32 eax, ebx
586.again:
587 icebp
588 jmp .again
589BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
590
591 %if TMPL_BITS == 64
592BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
593 crc32 rax, rbx
594.again:
595 icebp
596 jmp .again
597BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
598 %endif
599
600
601BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
602 crc32 eax, byte [fs:xBX]
603.again:
604 icebp
605 jmp .again
606BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
607
608BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
609 crc32 eax, word [fs:xBX]
610.again:
611 icebp
612 jmp .again
613BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
614
615BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
616 crc32 eax, dword [fs:xBX]
617.again:
618 icebp
619 jmp .again
620BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
621
622 %if TMPL_BITS == 64
623BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
624 crc32 rax, qword [fs:xBX]
625.again:
626 icebp
627 jmp .again
628BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
629 %endif
630
631
632;
633; CMPXCHG16B
634;
635 %if TMPL_BITS == 64
636BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
637 cmpxchg16b [rdi]
638.again:
639 ud2
640 jmp .again
641AssertCompile(.again - BS3_LAST_LABEL == 4)
642BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2
643
644
645BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
646 lock cmpxchg16b [rdi]
647.again:
648 ud2
649 jmp .again
650AssertCompile(.again - BS3_LAST_LABEL == 5)
651BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
652
653
654BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
655 o16 cmpxchg16b [rdi]
656.again:
657 ud2
658 jmp .again
659AssertCompile(.again - BS3_LAST_LABEL == 5)
660BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
661
662
663BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
664 db 0f0h, 066h
665 cmpxchg16b [rdi]
666.again:
667 ud2
668 jmp .again
669AssertCompile(.again - BS3_LAST_LABEL == 6)
670BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
671
672
673BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
674 repz cmpxchg16b [rdi]
675.again:
676 ud2
677 jmp .again
678AssertCompile(.again - BS3_LAST_LABEL == 5)
679BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
680
681
682BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
683 db 0f0h, 0f3h
684 cmpxchg16b [rdi]
685.again:
686 ud2
687 jmp .again
688AssertCompile(.again - BS3_LAST_LABEL == 6)
689BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
690
691BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
692 repnz cmpxchg16b [rdi]
693.again:
694 ud2
695 jmp .again
696AssertCompile(.again - BS3_LAST_LABEL == 5)
697BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
698
699
700BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
701 db 0f0h, 0f2h
702 cmpxchg16b [rdi]
703.again:
704 ud2
705 jmp .again
706AssertCompile(.again - BS3_LAST_LABEL == 6)
707BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
708
709
710BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
711 wrfsbase rbx
712.again:
713 ud2
714 jmp .again
715AssertCompile(.again - BS3_LAST_LABEL == 5)
716BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2
717
718
719BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
720 wrfsbase ebx
721.again:
722 ud2
723 jmp .again
724AssertCompile(.again - BS3_LAST_LABEL == 4)
725BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2
726
727
728BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
729 wrgsbase rbx
730.again:
731 ud2
732 jmp .again
733AssertCompile(.again - BS3_LAST_LABEL == 5)
734BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2
735
736
737BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
738 wrgsbase ebx
739.again:
740 ud2
741 jmp .again
742AssertCompile(.again - BS3_LAST_LABEL == 4)
743BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2
744
745
746BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
747 wrfsbase rbx
748 mov ebx, 0
749 rdfsbase rcx
750.again:
751 ud2
752 jmp .again
753AssertCompile(.again - BS3_LAST_LABEL == 15)
754BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2
755
756
757BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
758 wrfsbase ebx
759 mov ebx, 0
760 rdfsbase ecx
761.again:
762 ud2
763 jmp .again
764AssertCompile(.again - BS3_LAST_LABEL == 13)
765BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2
766
767
768BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
769 wrgsbase rbx
770 mov ebx, 0
771 rdgsbase rcx
772.again:
773 ud2
774 jmp .again
775AssertCompile(.again - BS3_LAST_LABEL == 15)
776BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2
777
778
779BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
780 wrgsbase ebx
781 mov ebx, 0
782 rdgsbase ecx
783.again:
784 ud2
785 jmp .again
786AssertCompile(.again - BS3_LAST_LABEL == 13)
787BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2
788
789
790BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
791 rdfsbase rbx
792.again:
793 ud2
794 jmp .again
795AssertCompile(.again - BS3_LAST_LABEL == 5)
796BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2
797
798
799BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
800 rdfsbase ebx
801.again:
802 ud2
803 jmp .again
804AssertCompile(.again - BS3_LAST_LABEL == 4)
805BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2
806
807
808BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
809 rdgsbase rbx
810.again:
811 ud2
812 jmp .again
813AssertCompile(.again - BS3_LAST_LABEL == 5)
814BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2
815
816
817BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
818 rdgsbase ebx
819.again:
820 ud2
821 jmp .again
822AssertCompile(.again - BS3_LAST_LABEL == 4)
823BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2
824
825
826;; @todo figure out this fudge. sigh.
827times (348) db 0cch ; fudge to avoid 'rderr' during boot.
828
829 %endif ; TMPL_BITS == 64
830
831
832%endif ; BS3_INSTANTIATING_CMN
833
834%include "bs3kit-template-footer.mac" ; reset environment
835
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