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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac@ 97441

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1; $Id: bs3-cpu-instr-2-template.mac 96407 2022-08-22 17:43:14Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-instr-2 assembly template.
4;
5
6;
7; Copyright (C) 2007-2022 Oracle and/or its affiliates.
8;
9; This file is part of VirtualBox base platform packages, as
10; available from https://www.virtualbox.org.
11;
12; This program is free software; you can redistribute it and/or
13; modify it under the terms of the GNU General Public License
14; as published by the Free Software Foundation, in version 3 of the
15; License.
16;
17; This program is distributed in the hope that it will be useful, but
18; WITHOUT ANY WARRANTY; without even the implied warranty of
19; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20; General Public License for more details.
21;
22; You should have received a copy of the GNU General Public License
23; along with this program; if not, see <https://www.gnu.org/licenses>.
24;
25; The contents of this file may alternatively be used under the terms
26; of the Common Development and Distribution License Version 1.0
27; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28; in the VirtualBox distribution, in which case the provisions of the
29; CDDL are applicable instead of those of the GPL.
30;
31; You may elect to license modified versions of this file under the
32; terms and conditions of either the GPL or the CDDL or both.
33;
34; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35;
36
37
38;*********************************************************************************************************************************
39;* Header Files *
40;*********************************************************************************************************************************
41%include "bs3kit-template-header.mac" ; setup environment
42
43
44;*********************************************************************************************************************************
45;* Defined Constants And Macros *
46;*********************************************************************************************************************************
47;;
48; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function
49; with an instruction length byte.
50;
51; ASSUMES the length is between the start of the function and the .again label.
52;
53%ifndef BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
54 %define BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
55 %macro BS3CPUINSTR2_PROC_BEGIN_CMN 1
56 align 8, db 0cch
57 db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
58BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR
59 %endmacro
60%endif
61
62
63;*********************************************************************************************************************************
64;* External Symbols *
65;*********************************************************************************************************************************
66TMPL_BEGIN_TEXT
67
68
69;
70; Test code snippets containing code which differs between 16-bit, 32-bit
71; and 64-bit CPUs modes.
72;
73%ifdef BS3_INSTANTIATING_CMN
74
75BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
76 mul xBX
77.again:
78 ud2
79 jmp .again
80BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2
81
82
83BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
84 imul xBX
85.again:
86 ud2
87 jmp .again
88BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2
89
90
91BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
92 imul xCX, xBX
93.again:
94 ud2
95 jmp .again
96BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2
97
98
99BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
100 div xBX
101.again:
102 ud2
103 jmp .again
104BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2
105
106
107BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
108 idiv xBX
109.again:
110 ud2
111 jmp .again
112BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2
113
114
115;
116; BSF / BSR / TZCNT / LZCNT
117;
118%ifndef EMIT_BITSCAN_DEFINED
119%define EMIT_BITSCAN_DEFINED
120%macro EMIT_BITSCAN 3
121BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR
122 %2
123 %1 ax, bx
124.again:
125 ud2
126 jmp .again
127BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2
128
129BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR
130 %2
131 %1 ax, [fs:xBX]
132.again:
133 ud2
134 jmp .again
135BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2
136
137BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR
138 %2
139 %1 eax, ebx
140.again:
141 ud2
142 jmp .again
143BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2
144
145BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR
146 %2
147 %1 eax, [fs:xBX]
148.again:
149 ud2
150 jmp .again
151BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2
152
153 %if TMPL_BITS == 64
154BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR
155 %2
156 %1 rax, rbx
157.again:
158 ud2
159 jmp .again
160BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2
161
162BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR
163 %2
164 %1 rax, [fs:xBX]
165.again:
166 ud2
167 jmp .again
168BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2
169 %endif
170%endmacro
171%endif
172
173EMIT_BITSCAN bsf, .ignored:, bsf
174EMIT_BITSCAN bsr, .ignored:, bsr
175EMIT_BITSCAN tzcnt, .ignored:, tzcnt
176EMIT_BITSCAN lzcnt, .ignored:, lzcnt
177EMIT_BITSCAN bsf, db 0f2h, f2_bsf
178EMIT_BITSCAN bsr, db 0f2h, f2_bsr
179EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt
180EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt
181
182
183;
184; RORX - VEX instruction with a couple of questions about non-standard encodings.
185;
186;;%define icebp ud2
187BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR
188 rorx ebx, edx, 2
189.again:
190 icebp
191 jmp .again
192BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp
193
194BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR
195%if TMPL_BITS == 64
196 rorx rbx, rdx, 2
197%else
198 db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe)
199%endif
200.again:
201 icebp
202 jmp .again
203BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp
204
205BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR
206 db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs
207.again:
208 icebp
209 jmp .again
210BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1
211
212BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR
213 db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD
214.again:
215 icebp
216 jmp .again
217BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1
218
219BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR
220 db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD
221.again:
222 icebp
223 jmp .again
224BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15
225
226 %if TMPL_BITS == 64
227BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR
228 db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe
229.again:
230 icebp
231 jmp .again
232BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1
233 %endif
234
235; A couple of memory variants
236BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp, BS3_PBC_NEAR
237 rorx ebx, [xDI], 36
238.again:
239 icebp
240 jmp .again
241BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp
242
243BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp, BS3_PBC_NEAR
244 %if TMPL_BITS == 64
245 rorx rbx, [xDI], 68
246 %elif TMPL_BITS == 32
247 db 0C4h,0E3h,07Bh,0F0h,01Fh,044h ; 16-bit ignores VEX.W=1 (10980xe)
248 %else
249 db 0C4h,0E3h,0FBh,0F0h,01Dh,044h ; 16-bit ignores VEX.W=1 (10980xe)
250 %endif
251.again:
252 icebp
253 jmp .again
254BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp
255
256;
257; ANDN (BMI1)
258;
259BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR
260%if TMPL_BITS == 64
261 andn rax, rcx, rbx
262%else
263 db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
264%endif
265.again:
266 icebp
267 jmp .again
268BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp
269
270BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR
271 andn eax, ecx, ebx
272.again:
273 icebp
274 jmp .again
275BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp
276
277
278BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
279%if TMPL_BITS == 64
280 andn rax, rcx, [fs:rbx]
281%elif TMPL_BITS == 32
282 db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx]
283%else
284 db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx]
285%endif
286.again:
287 icebp
288 jmp .again
289BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp
290
291BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
292 andn eax, ecx, [fs:xBX]
293.again:
294 icebp
295 jmp .again
296BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp
297
298
299;
300; BEXTR / SHLX / SARX / SHRX - BMI1 (opcode f7h)
301; BZHI - BMI2 (opcode f5h)
302;
303; @param %1 instruction
304; @param %2 opcode
305; @param %3 prefix
306;
307%ifndef SHLX_SARX_SHRX_DEFINED
308%define SHLX_SARX_SHRX_DEFINED
309%macro SHLX_SARX_SHRX 3
310
311BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR
312 %if TMPL_BITS == 64
313 %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3
314 %else
315 db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
316 %endif
317.again:
318 icebp
319 jmp .again
320BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp
321
322BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR
323 %1 eax, ebx, ecx
324.again:
325 icebp
326 jmp .again
327BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp
328
329BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR
330 %if TMPL_BITS == 64
331 %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703
332 %elif TMPL_BITS == 32
333 db 064h,0C4h,0E2h,0F0h|%3,%2,003h
334 %else
335 db 064h,0C4h,0E2h,0F0h|%3,%2,007h
336 %endif
337.again:
338 icebp
339 jmp .again
340BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp
341
342BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR
343 %1 eax, [fs:xBX], ecx
344.again:
345 icebp
346 jmp .again
347BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp
348
349%endmacro
350%endif
351
352SHLX_SARX_SHRX bextr, 0f7h, 0 ; none
353SHLX_SARX_SHRX shlx, 0f7h, 1 ; 66h
354SHLX_SARX_SHRX sarx, 0f7h, 2 ; f3h
355SHLX_SARX_SHRX shrx, 0f7h, 3 ; f2h
356SHLX_SARX_SHRX bzhi, 0f5h, 0 ; none
357
358;
359; PPEP / PEXT - BMI2 (opcode f5h)
360;
361; @param %1 instruction
362; @param %2 opcode
363; @param %3 prefix
364;
365%ifndef PDEP_PEXT_DEFINED
366%define PDEP_PEXT_DEFINED
367%macro PDEP_PEXT_ 3
368
369BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp, BS3_PBC_NEAR
370 %if TMPL_BITS == 64
371 %1 rax, rcx, rbx
372 %else
373 db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
374 %endif
375.again:
376 icebp
377 jmp .again
378BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp
379
380BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp, BS3_PBC_NEAR
381 %1 eax, ecx, ebx
382.again:
383 icebp
384 jmp .again
385BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp
386
387BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
388 %if TMPL_BITS == 64
389 %1 rax, rcx, [fs:rbx]
390 %elif TMPL_BITS == 32
391 db 064h,0C4h,0E2h,0F0h|%3,%2,003h
392 %else
393 db 064h,0C4h,0E2h,0F0h|%3,%2,007h
394 %endif
395.again:
396 icebp
397 jmp .again
398BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp
399
400BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
401 %1 eax, ecx, [fs:xBX]
402.again:
403 icebp
404 jmp .again
405BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp
406
407%endmacro
408%endif
409
410PDEP_PEXT_ pext, 0f5h, 2 ; f3h
411PDEP_PEXT_ pdep, 0f5h, 3 ; f2h
412
413;
414; BLSR / BLSMSK / BLSI
415; These are encoded in the exact same way, only the /r differs (%2).
416;
417%ifndef BLSR_BLSMSK_BLSI_DEFINED
418%define BLSR_BLSMSK_BLSI_DEFINED
419%macro BLSR_BLSMSK_BLSI 2
420
421BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR
422 %if TMPL_BITS == 64
423 %1 rax, rbx ; BLSR=C4E2F8F3CB
424 %else
425 db 0C4h,0E2h,0F8h,0F3h,0C3h | (%2 << 3) ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
426 %endif
427.again:
428 icebp
429 jmp .again
430BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp
431
432BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR
433 %1 eax, ebx
434.again:
435 icebp
436 jmp .again
437BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp
438
439BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR
440 %if TMPL_BITS == 64
441 %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B
442 %elif TMPL_BITS == 32
443 db 064h,0C4h,0E2h,0F8h,0F3h,003h | (%2 << 3)
444 %else
445 db 064h,0C4h,0E2h,0F8h,0F3h,007h | (%2 << 3)
446 %endif
447.again:
448 icebp
449 jmp .again
450BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp
451
452BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR
453 %1 eax, [fs:xBX]
454.again:
455 icebp
456 jmp .again
457BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp
458
459%endmacro
460%endif
461
462BLSR_BLSMSK_BLSI blsr, 1
463BLSR_BLSMSK_BLSI blsmsk, 2
464BLSR_BLSMSK_BLSI blsi, 3
465
466;
467; MULX
468;
469BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
470 %if TMPL_BITS == 64
471 mulx rax, rcx, rbx ; C4E2F3F6C3
472 %else
473 db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
474 %endif
475.again:
476 icebp
477 jmp .again
478BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp
479
480BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
481 %if TMPL_BITS == 64
482 mulx rcx, rcx, rbx ; C4E2F3F6CB
483 %else
484 db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
485 %endif
486.again:
487 icebp
488 jmp .again
489BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp
490
491BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR
492 %if TMPL_BITS == 64
493 mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603
494 %elif TMPL_BITS == 32
495 db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
496 %else
497 db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
498 %endif
499.again:
500 icebp
501 jmp .again
502BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp
503
504BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
505 mulx eax, ecx, ebx
506.again:
507 icebp
508 jmp .again
509BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp
510
511BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
512 mulx ecx, ecx, ebx
513.again:
514 icebp
515 jmp .again
516BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp
517
518BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR
519 mulx eax, ecx, [fs:xBX]
520.again:
521 icebp
522 jmp .again
523BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp
524
525
526;
527; POPCNT
528;
529BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_BX_icebp, BS3_PBC_NEAR
530 popcnt ax, bx
531.again:
532 icebp
533 jmp .again
534BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_BX_icebp
535
536BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp, BS3_PBC_NEAR
537 popcnt eax, ebx
538.again:
539 icebp
540 jmp .again
541BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp
542
543 %if TMPL_BITS == 64
544BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp, BS3_PBC_NEAR
545 popcnt rax, rbx
546.again:
547 icebp
548 jmp .again
549BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp
550 %endif
551
552
553BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp, BS3_PBC_NEAR
554 popcnt ax, [fs:xBX]
555.again:
556 icebp
557 jmp .again
558BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp
559
560BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp, BS3_PBC_NEAR
561 popcnt eax, [fs:xBX]
562.again:
563 icebp
564 jmp .again
565BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp
566
567 %if TMPL_BITS == 64
568BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp, BS3_PBC_NEAR
569 popcnt rax, [fs:xBX]
570.again:
571 icebp
572 jmp .again
573BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp
574 %endif
575
576
577;
578; CRC32
579;
580BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
581 crc32 eax, bl
582.again:
583 icebp
584 jmp .again
585BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
586
587BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
588 crc32 eax, bx
589.again:
590 icebp
591 jmp .again
592BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
593
594BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
595 crc32 eax, ebx
596.again:
597 icebp
598 jmp .again
599BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
600
601 %if TMPL_BITS == 64
602BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
603 crc32 rax, rbx
604.again:
605 icebp
606 jmp .again
607BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
608 %endif
609
610
611BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
612 crc32 eax, byte [fs:xBX]
613.again:
614 icebp
615 jmp .again
616BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
617
618BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
619 crc32 eax, word [fs:xBX]
620.again:
621 icebp
622 jmp .again
623BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
624
625BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
626 crc32 eax, dword [fs:xBX]
627.again:
628 icebp
629 jmp .again
630BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
631
632 %if TMPL_BITS == 64
633BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
634 crc32 rax, qword [fs:xBX]
635.again:
636 icebp
637 jmp .again
638BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
639 %endif
640
641
642;
643; CMPXCHG16B
644;
645 %if TMPL_BITS == 64
646BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
647 cmpxchg16b [rdi]
648.again:
649 ud2
650 jmp .again
651AssertCompile(.again - BS3_LAST_LABEL == 4)
652BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2
653
654
655BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
656 lock cmpxchg16b [rdi]
657.again:
658 ud2
659 jmp .again
660AssertCompile(.again - BS3_LAST_LABEL == 5)
661BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
662
663
664BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
665 o16 cmpxchg16b [rdi]
666.again:
667 ud2
668 jmp .again
669AssertCompile(.again - BS3_LAST_LABEL == 5)
670BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
671
672
673BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
674 db 0f0h, 066h
675 cmpxchg16b [rdi]
676.again:
677 ud2
678 jmp .again
679AssertCompile(.again - BS3_LAST_LABEL == 6)
680BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
681
682
683BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
684 repz cmpxchg16b [rdi]
685.again:
686 ud2
687 jmp .again
688AssertCompile(.again - BS3_LAST_LABEL == 5)
689BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
690
691
692BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
693 db 0f0h, 0f3h
694 cmpxchg16b [rdi]
695.again:
696 ud2
697 jmp .again
698AssertCompile(.again - BS3_LAST_LABEL == 6)
699BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
700
701BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
702 repnz cmpxchg16b [rdi]
703.again:
704 ud2
705 jmp .again
706AssertCompile(.again - BS3_LAST_LABEL == 5)
707BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
708
709
710BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
711 db 0f0h, 0f2h
712 cmpxchg16b [rdi]
713.again:
714 ud2
715 jmp .again
716AssertCompile(.again - BS3_LAST_LABEL == 6)
717BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
718
719
720BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
721 wrfsbase rbx
722.again:
723 ud2
724 jmp .again
725AssertCompile(.again - BS3_LAST_LABEL == 5)
726BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2
727
728
729BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
730 wrfsbase ebx
731.again:
732 ud2
733 jmp .again
734AssertCompile(.again - BS3_LAST_LABEL == 4)
735BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2
736
737
738BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
739 wrgsbase rbx
740.again:
741 ud2
742 jmp .again
743AssertCompile(.again - BS3_LAST_LABEL == 5)
744BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2
745
746
747BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
748 wrgsbase ebx
749.again:
750 ud2
751 jmp .again
752AssertCompile(.again - BS3_LAST_LABEL == 4)
753BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2
754
755
756BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
757 wrfsbase rbx
758 mov ebx, 0
759 rdfsbase rcx
760.again:
761 ud2
762 jmp .again
763AssertCompile(.again - BS3_LAST_LABEL == 15)
764BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2
765
766
767BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
768 wrfsbase ebx
769 mov ebx, 0
770 rdfsbase ecx
771.again:
772 ud2
773 jmp .again
774AssertCompile(.again - BS3_LAST_LABEL == 13)
775BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2
776
777
778BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
779 wrgsbase rbx
780 mov ebx, 0
781 rdgsbase rcx
782.again:
783 ud2
784 jmp .again
785AssertCompile(.again - BS3_LAST_LABEL == 15)
786BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2
787
788
789BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
790 wrgsbase ebx
791 mov ebx, 0
792 rdgsbase ecx
793.again:
794 ud2
795 jmp .again
796AssertCompile(.again - BS3_LAST_LABEL == 13)
797BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2
798
799
800BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
801 rdfsbase rbx
802.again:
803 ud2
804 jmp .again
805AssertCompile(.again - BS3_LAST_LABEL == 5)
806BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2
807
808
809BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
810 rdfsbase ebx
811.again:
812 ud2
813 jmp .again
814AssertCompile(.again - BS3_LAST_LABEL == 4)
815BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2
816
817
818BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
819 rdgsbase rbx
820.again:
821 ud2
822 jmp .again
823AssertCompile(.again - BS3_LAST_LABEL == 5)
824BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2
825
826
827BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
828 rdgsbase ebx
829.again:
830 ud2
831 jmp .again
832AssertCompile(.again - BS3_LAST_LABEL == 4)
833BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2
834
835
836;; @todo figure out this fudge. sigh.
837times (348) db 0cch ; fudge to avoid 'rderr' during boot.
838
839 %endif ; TMPL_BITS == 64
840
841
842%endif ; BS3_INSTANTIATING_CMN
843
844%include "bs3kit-template-footer.mac" ; reset environment
845
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