| 1 | ; $Id: bs3-cpu-instr-2-template.mac 106061 2024-09-16 14:03:52Z vboxsync $
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| 2 | ;; @file
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| 3 | ; BS3Kit - bs3-cpu-instr-2 assembly template.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2024 Oracle and/or its affiliates.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox base platform packages, as
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| 10 | ; available from https://www.virtualbox.org.
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| 11 | ;
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| 12 | ; This program is free software; you can redistribute it and/or
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| 13 | ; modify it under the terms of the GNU General Public License
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| 14 | ; as published by the Free Software Foundation, in version 3 of the
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| 15 | ; License.
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| 16 | ;
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| 17 | ; This program is distributed in the hope that it will be useful, but
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| 18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | ; General Public License for more details.
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| 21 | ;
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| 22 | ; You should have received a copy of the GNU General Public License
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| 23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | ;
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| 25 | ; The contents of this file may alternatively be used under the terms
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| 26 | ; of the Common Development and Distribution License Version 1.0
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| 27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | ; in the VirtualBox distribution, in which case the provisions of the
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| 29 | ; CDDL are applicable instead of those of the GPL.
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| 30 | ;
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| 31 | ; You may elect to license modified versions of this file under the
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| 32 | ; terms and conditions of either the GPL or the CDDL or both.
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| 33 | ;
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| 34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | ;
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| 36 |
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| 37 |
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| 38 | ;*********************************************************************************************************************************
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| 39 | ;* Header Files *
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| 40 | ;*********************************************************************************************************************************
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| 41 | %include "bs3kit-template-header.mac" ; setup environment
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| 42 |
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| 43 |
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| 44 | ;*********************************************************************************************************************************
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| 45 | ;* Defined Constants And Macros *
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| 46 | ;*********************************************************************************************************************************
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| 47 | ;;
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| 48 | ; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function
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| 49 | ; with an instruction length byte.
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| 50 | ;
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| 51 | ; ASSUMES the length is between the start of the function and the .again label.
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| 52 | ;
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| 53 | %ifndef BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
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| 54 | %define BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
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| 55 | %macro BS3CPUINSTR2_PROC_BEGIN_CMN 1
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| 56 | align 8, db 0cch
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| 57 | db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
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| 58 | BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR
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| 59 | %endmacro
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| 60 | %endif
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| 61 |
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| 62 |
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| 63 | ;;
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| 64 | ; For defining simple instruction test.
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| 65 | %ifndef BS3CPUINSTR2_EMIT_INSTR_UD2_DEFINED
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| 66 | %define BS3CPUINSTR2_EMIT_INSTR_UD2_DEFINED
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| 67 | %macro BS3CPUINSTR2_EMIT_INSTR_UD2 2+
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| 68 | BS3CPUINSTR2_PROC_BEGIN_CMN %1
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| 69 | %2
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| 70 | .again:
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| 71 | ud2
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| 72 | jmp .again
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| 73 | BS3_PROC_END_CMN %1
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| 74 | %endmacro
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| 75 | %endif
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| 76 |
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| 77 | ;;
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| 78 | ; @param 1 The instruction menmonic.
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| 79 | ; @param 2 Whether there are both an 8-bit form and a 16/32-bit immediate form of the instruction (1) or not 0.
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| 80 | ; @param 3 Mask describing the immediate forms. Bit 0 = imm8; Bit 2 = immV.
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| 81 | ; @param 4 Whether there are alternative forms of the instruction.
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| 82 | ; @param
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| 83 | %ifnmacro BS3CPUINSTR2_BINARY_OP 4
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| 84 | %macro BS3CPUINSTR2_BINARY_OP 4
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| 85 | %if %2 != 0
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| 86 | ; 8-bit
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| 87 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _dl, %1 al, dl
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| 88 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _bh, %1 ch, bh
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| 89 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _ah, %1 dl, ah
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| 90 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _ah, %1 [xBX], ah
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| 91 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _bl, %1 [xDI], bl
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| 92 | %if %3 & 3
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| 93 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _Ib, %1 al, 0x7f
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| 94 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cl %+ _Ib, %1 cl, 0x7f
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| 95 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dh %+ _Ib, %1 dh, 0x7f
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| 96 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _Ib, %1 byte [xDI], 0x7f
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| 97 | %endif
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| 98 | %if %4 != 0
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| 99 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _DSxBX, %1 dl, [xBX]
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| 100 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _DSxBX, %1 ch, [xBX]
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| 101 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dh %+ _cl, ALT_INSTRUCTION8_ %+ %1 dh, cl
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| 102 | %endif
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| 103 | %ifdef TMPL_64BIT
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| 104 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _sil %+ _dil, %1 sil, dil
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| 105 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9b %+ _r8b, %1 r9b, r8b
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| 106 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _r13b, %1 al, r13b
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| 107 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx14 %+ _r11b, %1 [r14], r11b
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| 108 | %if %3 & 3
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| 109 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8b %+ _Ib, %1 r8b, 0x7e
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| 110 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14b %+ _Ib, %1 r14b, 0x7e
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| 111 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx13 %+ _Ib, %1 byte [r13], 0x7e
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| 112 | %endif
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| 113 | %if %4 != 0
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| 114 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r11b %+ _DSx12, %1 r11b, [r12]
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| 115 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dl %+ _r14b, ALT_INSTRUCTION8_ %+ %1 dl, r14b
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| 116 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r8b %+ _bl, ALT_INSTRUCTION8_ %+ %1 r8b, bl
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| 117 | %endif
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| 118 | %endif
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| 119 | %endif
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| 120 | ; 16-bit
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| 121 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _di %+ _si, %1 di, si
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| 122 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cx %+ _bp, %1 cx, bp
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| 123 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _si, %1 [xDI], si
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| 124 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _ax, %1 [xBX], ax
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| 125 | %if %3 & 1
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| 126 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ax %+ _Ib, %1 ax, strict byte 0x7f
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| 127 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _si %+ _Ib, %1 si, strict byte 0x7f
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| 128 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxDI %+ _Ib, %1 word [xDI], strict byte 0x7f
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| 129 | %endif
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| 130 | %if %3 & 2
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| 131 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ax %+ _Iw, %1 ax, 0x7f01
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| 132 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bx %+ _Iw, %1 bx, 0x7f01
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| 133 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _Iw, %1 word [xBX], 0x7f01
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| 134 | %endif
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| 135 | %if %4 != 0
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| 136 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _si %+ _DSxDI, %1 si, [xDI]
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| 137 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ax %+ _DSxBX, %1 ax, [xBX]
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| 138 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _bp %+ _bx, ALT_INSTRUCTION16_ %+ %1 bp, bx
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| 139 | %endif
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| 140 | %ifdef TMPL_64BIT
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| 141 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _cx, %1 r8w, cx
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| 142 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r15w %+ _r10w, %1 r15w, r10w
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| 143 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx15 %+ _r12w, %1 [r15], r12w
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| 144 | %if %3 & 1
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| 145 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _Ib, %1 r8w, strict byte 0x77
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| 146 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r12w %+ _Ib, %1 r12w, strict byte 0x77
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| 147 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSx14 %+ _Ib, %1 word [r14], strict byte 0x77
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| 148 | %endif
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| 149 | %if %3 & 2
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| 150 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _Iw, %1 r8w, 0x7788
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| 151 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13w %+ _Iw, %1 r13w, 0x7788
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| 152 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx11 %+ _Iw, %1 word [r11], 0x7788
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| 153 | %endif
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| 154 | %if %4 != 0
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| 155 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9w %+ _DSx8, %1 r9w, [r8]
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| 156 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r13w %+ _ax, ALT_INSTRUCTION16_ %+ %1 r13w, ax
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| 157 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _si %+ _r9w, ALT_INSTRUCTION16_ %+ %1 si, r9w
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| 158 | %endif
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| 159 | %endif
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| 160 | ; 32-bit
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| 161 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _ebx, %1 eax, ebx
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| 162 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _ebp, %1 ecx, ebp
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| 163 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _edx %+ _edi, %1 edx, edi
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| 164 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxDI %+ _esi, %1 [xDI], esi
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| 165 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _eax, %1 [xBX], eax
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| 166 | %if %3 & 1
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| 167 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _Ib, %1 eax, strict byte 0x7f
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| 168 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _Ib, %1 ecx, strict byte 0x7f
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| 169 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxDI %+ _Ib, %1 dword [xDI], strict byte 0x7f
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| 170 | %endif
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| 171 | %if %3 & 2
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| 172 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _Id, %1 eax, 0x7f011234
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| 173 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ebp %+ _Id, %1 ebp, 0x7f011234
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| 174 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxSI %+ _Id, %1 dword [xSI], 0x7f011234
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| 175 | %endif
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| 176 | %if %4 != 0
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| 177 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _DSxBX, %1 eax, [xBX]
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| 178 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ebp %+ _DSxDI, %1 ebp, [xDI]
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| 179 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _edi %+ _esi, ALT_INSTRUCTION32_ %+ %1 edi, esi
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| 180 | %endif
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| 181 | %ifdef TMPL_64BIT
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| 182 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _r8d, %1 eax, r8d
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| 183 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9d %+ _ecx, %1 r9d, ecx
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| 184 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13d %+ _r14d, %1 r13d, r14d
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| 185 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx10 %+ _r11d, %1 [r10], r11d
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| 186 | %if %3 & 1
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| 187 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8d %+ _Ib, %1 r8d, strict byte 0x77
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| 188 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r11d %+ _Ib, %1 r11d, strict byte 0x77
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| 189 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSx15 %+ _Ib, %1 dword [r15], strict byte 0x77
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| 190 | %endif
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| 191 | %if %3 & 2
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| 192 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8d %+ _Id, %1 r8d, 0x778899aa
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| 193 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14d %+ _Id, %1 r14d, 0x778899aa
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| 194 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx12 %+ _Id, %1 dword [r12], 0x778899aa
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| 195 | %endif
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| 196 | %if %4 != 0
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| 197 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14d %+ _DSx12, %1 r14d, [r12]
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| 198 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15d %+ _esi, ALT_INSTRUCTION32_ %+ %1 r15d, esi
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| 199 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _eax %+ _r10d, ALT_INSTRUCTION32_ %+ %1 eax, r10d
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| 200 | %endif
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| 201 | %endif
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| 202 | ; 64-bit
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| 203 | %ifdef TMPL_64BIT
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| 204 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _rbx, %1 rax, rbx
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| 205 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _rax, %1 r8, rax
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| 206 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rdx %+ _r10, %1 rdx, r10
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| 207 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSxBX %+ _rax, %1 [rbx], rax
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| 208 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _DSx12 %+ _r8, %1 [r12], r8
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| 209 | %if %3 & 1
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| 210 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _Ib, %1 rax, strict byte 0x77
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| 211 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rbp %+ _Ib, %1 rbp, strict byte 0x77
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| 212 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _Ib, %1 r8, strict byte 0x77
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| 213 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r11 %+ _Ib, %1 r11, strict byte 0x77
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| 214 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxSI %+ _Ib, %1 qword [rsi], strict byte 0x77
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| 215 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx8 %+ _Ib, %1 qword [r8], strict byte 0x77
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| 216 | %endif
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| 217 | %if %3 & 2
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| 218 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _Id, %1 rax, 0x778899aa
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| 219 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _Id, %1 r8, 0x778899aa
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| 220 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rbx %+ _Id, %1 rbx, 0x778899aa
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| 221 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r14 %+ _Id, %1 r14, 0x778899aa
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| 222 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx12 %+ _Id, %1 qword [r12], 0x778899aa
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| 223 | %endif
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| 224 | %if %4 != 0
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| 225 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _DSxBX, %1 rax, [rbx]
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| 226 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _DSx12, %1 r8, [r12]
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| 227 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15 %+ _rsi, ALT_INSTRUCTION64_ %+ %1 r15, rsi
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| 228 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _rbx %+ _r14, ALT_INSTRUCTION64_ %+ %1 rbx, r14
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|---|
| 229 | %endif
|
|---|
| 230 | %endif
|
|---|
| 231 | %endmacro ; BS3CPUINSTR2_BINARY_OP
|
|---|
| 232 | %endif
|
|---|
| 233 |
|
|---|
| 234 |
|
|---|
| 235 | ;;
|
|---|
| 236 | ; @param 1 The instruction menmonic.
|
|---|
| 237 | %ifnmacro BS3CPUINSTR2_SHIFT_OP 1
|
|---|
| 238 | %macro BS3CPUINSTR2_SHIFT_OP 1
|
|---|
| 239 | ; 8-bit
|
|---|
| 240 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _1, %1 al, 1
|
|---|
| 241 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _Ib, %1 dl, 7
|
|---|
| 242 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _cl, %1 ch, cl
|
|---|
| 243 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxBX %+ _1, %1 byte [xBX], 1
|
|---|
| 244 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxDI %+ _Ib, %1 byte [xDI], 6
|
|---|
| 245 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxSI %+ _cl, %1 byte [xSI], cl
|
|---|
| 246 | %ifdef TMPL_64BIT
|
|---|
| 247 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _sil %+ _1, %1 sil, 1
|
|---|
| 248 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9b %+ _Ib, %1 r9b, 5
|
|---|
| 249 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13b %+ _cl, %1 r13b, cl
|
|---|
| 250 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSx14 %+ _1, %1 byte [r14], 1
|
|---|
| 251 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSxAX %+ _Ib, %1 byte [rax], 4
|
|---|
| 252 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bDSx9 %+ _cl, %1 byte [r9], cl
|
|---|
| 253 | %endif
|
|---|
| 254 | ; 16-bit
|
|---|
| 255 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _di %+ _1, %1 di, 1
|
|---|
| 256 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cx %+ _Ib, %1 cx, 15
|
|---|
| 257 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _bp %+ _cl, %1 bp, cl
|
|---|
| 258 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxSI %+ _1, %1 word [xSI], 1
|
|---|
| 259 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxDI %+ _Ib, %1 word [xDI], 14
|
|---|
| 260 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxBX %+ _cl, %1 word [xBX], cl
|
|---|
| 261 | %ifdef TMPL_64BIT
|
|---|
| 262 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _1, %1 r8w, 1
|
|---|
| 263 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9w %+ _Ib, %1 r9w, 5
|
|---|
| 264 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13w %+ _cl, %1 r13w, cl
|
|---|
| 265 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSx14 %+ _1, %1 word [r14], 1
|
|---|
| 266 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSxBP %+ _Ib, %1 word [rbp], 4
|
|---|
| 267 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _wDSx9 %+ _cl, %1 word [r9], cl
|
|---|
| 268 | %endif
|
|---|
| 269 | ; 32-bit
|
|---|
| 270 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _edi %+ _1, %1 edi, 1
|
|---|
| 271 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _Ib, %1 ecx, 25
|
|---|
| 272 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ebp %+ _cl, %1 ebp, cl
|
|---|
| 273 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxSI %+ _1, %1 dword [xSI], 1
|
|---|
| 274 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxBX %+ _Ib, %1 dword [xBX], 24
|
|---|
| 275 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxDI %+ _cl, %1 dword [xDI], cl
|
|---|
| 276 | %ifdef TMPL_64BIT
|
|---|
| 277 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8d %+ _1, %1 r8d, 1
|
|---|
| 278 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9d %+ _Ib, %1 r9d, 23
|
|---|
| 279 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13d %+ _cl, %1 r13d, cl
|
|---|
| 280 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSx14 %+ _1, %1 dword [r14], 1
|
|---|
| 281 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSxBP %+ _Ib, %1 dword [rbp], 22
|
|---|
| 282 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dwDSx9 %+ _cl, %1 dword [r9], cl
|
|---|
| 283 | %endif
|
|---|
| 284 | ; 64-bit
|
|---|
| 285 | %ifdef TMPL_64BIT
|
|---|
| 286 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rdi %+ _1, %1 rdi, 1
|
|---|
| 287 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rcx %+ _Ib, %1 rcx, 35
|
|---|
| 288 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rbp %+ _cl, %1 rbp, cl
|
|---|
| 289 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxSI %+ _1, %1 qword [xSI], 1
|
|---|
| 290 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxBX %+ _Ib, %1 qword [xBX], 24
|
|---|
| 291 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxDI %+ _cl, %1 qword [xDI], cl
|
|---|
| 292 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _1, %1 r8, 1
|
|---|
| 293 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9 %+ _Ib, %1 r9, 48
|
|---|
| 294 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13 %+ _cl, %1 r13, cl
|
|---|
| 295 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx14 %+ _1, %1 qword [r14], 1
|
|---|
| 296 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSxBP %+ _Ib, %1 qword [rbp], 56
|
|---|
| 297 | BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _qwDSx9 %+ _cl, %1 qword [r9], cl
|
|---|
| 298 | %endif
|
|---|
| 299 | %endmacro ; BS3CPUINSTR2_SHIFT_OP
|
|---|
| 300 | %endif
|
|---|
| 301 |
|
|---|
| 302 |
|
|---|
| 303 |
|
|---|
| 304 | ;*********************************************************************************************************************************
|
|---|
| 305 | ;* External Symbols *
|
|---|
| 306 | ;*********************************************************************************************************************************
|
|---|
| 307 | TMPL_BEGIN_TEXT
|
|---|
| 308 |
|
|---|
| 309 |
|
|---|
| 310 | ;
|
|---|
| 311 | ; Test code snippets containing code which differs between 16-bit, 32-bit
|
|---|
| 312 | ; and 64-bit CPUs modes.
|
|---|
| 313 | ;
|
|---|
| 314 | %ifdef BS3_INSTANTIATING_CMN
|
|---|
| 315 |
|
|---|
| 316 | %ifndef ALT_INSTRUCTION_MACROS_DEFINED
|
|---|
| 317 | %define ALT_INSTRUCTION_MACROS_DEFINED
|
|---|
| 318 | %macro ALT_INSTRUCTION8_REG_RM 3+
|
|---|
| 319 | X86_MKOP_REX8 %1, %2
|
|---|
| 320 | db %3
|
|---|
| 321 | X86_MKOP_MODRM8 X86_MOD_REG, %1, %2
|
|---|
| 322 | %endmacro
|
|---|
| 323 |
|
|---|
| 324 | %macro ALT_INSTRUCTION16_REG_RM 3+
|
|---|
| 325 | %if TMPL_BITS != 16
|
|---|
| 326 | db X86_OP_PRF_SIZE_OP
|
|---|
| 327 | %endif
|
|---|
| 328 | X86_MKOP_REX16 %1, %2
|
|---|
| 329 | db %3
|
|---|
| 330 | X86_MKOP_MODRM16 X86_MOD_REG, %1, %2
|
|---|
| 331 | %endmacro
|
|---|
| 332 |
|
|---|
| 333 | %macro ALT_INSTRUCTION32_REG_RM 3+
|
|---|
| 334 | %if TMPL_BITS == 16
|
|---|
| 335 | db X86_OP_PRF_SIZE_OP
|
|---|
| 336 | %endif
|
|---|
| 337 | X86_MKOP_REX32 %1, %2
|
|---|
| 338 | db %3
|
|---|
| 339 | X86_MKOP_MODRM32 X86_MOD_REG, %1, %2
|
|---|
| 340 | %endmacro
|
|---|
| 341 |
|
|---|
| 342 | %macro ALT_INSTRUCTION64_REG_RM 3+
|
|---|
| 343 | X86_MKOP_REX64 %1, %2
|
|---|
| 344 | db %3
|
|---|
| 345 | X86_MKOP_MODRM64 X86_MOD_REG, %1, %2
|
|---|
| 346 | %endmacro
|
|---|
| 347 |
|
|---|
| 348 | ; nasm v2.16.02rc1 encodes the 20h and 21h variants (AND rm,reg)
|
|---|
| 349 | %macro ALT_INSTRUCTION8_and 2
|
|---|
| 350 | ALT_INSTRUCTION8_REG_RM %1, %2, 22h
|
|---|
| 351 | %endmacro
|
|---|
| 352 | %macro ALT_INSTRUCTION16_and 2
|
|---|
| 353 | ALT_INSTRUCTION16_REG_RM %1, %2, 23h
|
|---|
| 354 | %endmacro
|
|---|
| 355 | %macro ALT_INSTRUCTION32_and 2
|
|---|
| 356 | ALT_INSTRUCTION32_REG_RM %1, %2, 23h
|
|---|
| 357 | %endmacro
|
|---|
| 358 | %macro ALT_INSTRUCTION64_and 2
|
|---|
| 359 | ALT_INSTRUCTION64_REG_RM %1, %2, 23h
|
|---|
| 360 | %endmacro
|
|---|
| 361 |
|
|---|
| 362 | ; nasm v2.16.02rc1 encodes the 08h and 09h variants (OR rm,reg)
|
|---|
| 363 | %macro ALT_INSTRUCTION8_or 2
|
|---|
| 364 | ALT_INSTRUCTION8_REG_RM %1, %2, 0ah
|
|---|
| 365 | %endmacro
|
|---|
| 366 | %macro ALT_INSTRUCTION16_or 2
|
|---|
| 367 | ALT_INSTRUCTION16_REG_RM %1, %2, 0bh
|
|---|
| 368 | %endmacro
|
|---|
| 369 | %macro ALT_INSTRUCTION32_or 2
|
|---|
| 370 | ALT_INSTRUCTION32_REG_RM %1, %2, 0bh
|
|---|
| 371 | %endmacro
|
|---|
| 372 | %macro ALT_INSTRUCTION64_or 2
|
|---|
| 373 | ALT_INSTRUCTION64_REG_RM %1, %2, 0bh
|
|---|
| 374 | %endmacro
|
|---|
| 375 |
|
|---|
| 376 | ; nasm v2.16.02rc1 encodes the 30h and 31h variants (XOR rm,reg)
|
|---|
| 377 | %macro ALT_INSTRUCTION8_xor 2
|
|---|
| 378 | ALT_INSTRUCTION8_REG_RM %1, %2, 32h
|
|---|
| 379 | %endmacro
|
|---|
| 380 | %macro ALT_INSTRUCTION16_xor 2
|
|---|
| 381 | ALT_INSTRUCTION16_REG_RM %1, %2, 33h
|
|---|
| 382 | %endmacro
|
|---|
| 383 | %macro ALT_INSTRUCTION32_xor 2
|
|---|
| 384 | ALT_INSTRUCTION32_REG_RM %1, %2, 33h
|
|---|
| 385 | %endmacro
|
|---|
| 386 | %macro ALT_INSTRUCTION64_xor 2
|
|---|
| 387 | ALT_INSTRUCTION64_REG_RM %1, %2, 33h
|
|---|
| 388 | %endmacro
|
|---|
| 389 |
|
|---|
| 390 | ; nasm v2.16.02rc1 encodes the 00h and 01h variants (ADD rm,reg)
|
|---|
| 391 | %macro ALT_INSTRUCTION8_add 2
|
|---|
| 392 | ALT_INSTRUCTION8_REG_RM %1, %2, 02h
|
|---|
| 393 | %endmacro
|
|---|
| 394 | %macro ALT_INSTRUCTION16_add 2
|
|---|
| 395 | ALT_INSTRUCTION16_REG_RM %1, %2, 03h
|
|---|
| 396 | %endmacro
|
|---|
| 397 | %macro ALT_INSTRUCTION32_add 2
|
|---|
| 398 | ALT_INSTRUCTION32_REG_RM %1, %2, 03h
|
|---|
| 399 | %endmacro
|
|---|
| 400 | %macro ALT_INSTRUCTION64_add 2
|
|---|
| 401 | ALT_INSTRUCTION64_REG_RM %1, %2, 03h
|
|---|
| 402 | %endmacro
|
|---|
| 403 |
|
|---|
| 404 | ; nasm v2.16.02rc1 encodes the 10h and 11h variants (ADC rm,reg)
|
|---|
| 405 | %macro ALT_INSTRUCTION8_adc 2
|
|---|
| 406 | ALT_INSTRUCTION8_REG_RM %1, %2, 12h
|
|---|
| 407 | %endmacro
|
|---|
| 408 | %macro ALT_INSTRUCTION16_adc 2
|
|---|
| 409 | ALT_INSTRUCTION16_REG_RM %1, %2, 13h
|
|---|
| 410 | %endmacro
|
|---|
| 411 | %macro ALT_INSTRUCTION32_adc 2
|
|---|
| 412 | ALT_INSTRUCTION32_REG_RM %1, %2, 13h
|
|---|
| 413 | %endmacro
|
|---|
| 414 | %macro ALT_INSTRUCTION64_adc 2
|
|---|
| 415 | ALT_INSTRUCTION64_REG_RM %1, %2, 13h
|
|---|
| 416 | %endmacro
|
|---|
| 417 |
|
|---|
| 418 | ; nasm v2.16.02rc1 encodes the 28h and 29h variants (SUB rm,reg)
|
|---|
| 419 | %macro ALT_INSTRUCTION8_sub 2
|
|---|
| 420 | ALT_INSTRUCTION8_REG_RM %1, %2, 2ah
|
|---|
| 421 | %endmacro
|
|---|
| 422 | %macro ALT_INSTRUCTION16_sub 2
|
|---|
| 423 | ALT_INSTRUCTION16_REG_RM %1, %2, 2bh
|
|---|
| 424 | %endmacro
|
|---|
| 425 | %macro ALT_INSTRUCTION32_sub 2
|
|---|
| 426 | ALT_INSTRUCTION32_REG_RM %1, %2, 2bh
|
|---|
| 427 | %endmacro
|
|---|
| 428 | %macro ALT_INSTRUCTION64_sub 2
|
|---|
| 429 | ALT_INSTRUCTION64_REG_RM %1, %2, 2bh
|
|---|
| 430 | %endmacro
|
|---|
| 431 |
|
|---|
| 432 | ; nasm v2.16.02rc1 encodes the 18h and 19h variants (SBB rm,reg)
|
|---|
| 433 | %macro ALT_INSTRUCTION8_sbb 2
|
|---|
| 434 | ALT_INSTRUCTION8_REG_RM %1, %2, 1ah
|
|---|
| 435 | %endmacro
|
|---|
| 436 | %macro ALT_INSTRUCTION16_sbb 2
|
|---|
| 437 | ALT_INSTRUCTION16_REG_RM %1, %2, 1bh
|
|---|
| 438 | %endmacro
|
|---|
| 439 | %macro ALT_INSTRUCTION32_sbb 2
|
|---|
| 440 | ALT_INSTRUCTION32_REG_RM %1, %2, 1bh
|
|---|
| 441 | %endmacro
|
|---|
| 442 | %macro ALT_INSTRUCTION64_sbb 2
|
|---|
| 443 | ALT_INSTRUCTION64_REG_RM %1, %2, 1bh
|
|---|
| 444 | %endmacro
|
|---|
| 445 |
|
|---|
| 446 | ; nasm v2.16.02rc1 encodes the 38h and 39h variants (CMP rm,reg)
|
|---|
| 447 | %macro ALT_INSTRUCTION8_cmp 2
|
|---|
| 448 | ALT_INSTRUCTION8_REG_RM %1, %2, 3ah
|
|---|
| 449 | %endmacro
|
|---|
| 450 | %macro ALT_INSTRUCTION16_cmp 2
|
|---|
| 451 | ALT_INSTRUCTION16_REG_RM %1, %2, 3bh
|
|---|
| 452 | %endmacro
|
|---|
| 453 | %macro ALT_INSTRUCTION32_cmp 2
|
|---|
| 454 | ALT_INSTRUCTION32_REG_RM %1, %2, 3bh
|
|---|
| 455 | %endmacro
|
|---|
| 456 | %macro ALT_INSTRUCTION64_cmp 2
|
|---|
| 457 | ALT_INSTRUCTION64_REG_RM %1, %2, 3bh
|
|---|
| 458 | %endmacro
|
|---|
| 459 |
|
|---|
| 460 | %endif ; !ALT_INSTRUCTION_MACROS_DEFINED
|
|---|
| 461 |
|
|---|
| 462 | BS3CPUINSTR2_BINARY_OP and, 1, 3, 1
|
|---|
| 463 | BS3CPUINSTR2_BINARY_OP or, 1, 3, 1
|
|---|
| 464 | BS3CPUINSTR2_BINARY_OP xor, 1, 3, 1
|
|---|
| 465 | BS3CPUINSTR2_BINARY_OP test, 1, 2, 0
|
|---|
| 466 |
|
|---|
| 467 | BS3CPUINSTR2_BINARY_OP add, 1, 3, 1
|
|---|
| 468 | BS3CPUINSTR2_BINARY_OP adc, 1, 3, 1
|
|---|
| 469 | BS3CPUINSTR2_BINARY_OP sub, 1, 3, 1
|
|---|
| 470 | BS3CPUINSTR2_BINARY_OP sbb, 1, 3, 1
|
|---|
| 471 | BS3CPUINSTR2_BINARY_OP cmp, 1, 3, 1
|
|---|
| 472 |
|
|---|
| 473 | BS3CPUINSTR2_BINARY_OP bt, 0, 1, 0
|
|---|
| 474 | BS3CPUINSTR2_BINARY_OP btc, 0, 1, 0
|
|---|
| 475 | BS3CPUINSTR2_BINARY_OP btr, 0, 1, 0
|
|---|
| 476 | BS3CPUINSTR2_BINARY_OP bts, 0, 1, 0
|
|---|
| 477 |
|
|---|
| 478 |
|
|---|
| 479 | BS3CPUINSTR2_SHIFT_OP shl
|
|---|
| 480 | BS3CPUINSTR2_SHIFT_OP shr
|
|---|
| 481 | BS3CPUINSTR2_SHIFT_OP sar
|
|---|
| 482 | BS3CPUINSTR2_SHIFT_OP rol
|
|---|
| 483 | BS3CPUINSTR2_SHIFT_OP ror
|
|---|
| 484 | BS3CPUINSTR2_SHIFT_OP rcl
|
|---|
| 485 | BS3CPUINSTR2_SHIFT_OP rcr
|
|---|
| 486 |
|
|---|
| 487 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
|
|---|
| 488 | mul xBX
|
|---|
| 489 | .again:
|
|---|
| 490 | ud2
|
|---|
| 491 | jmp .again
|
|---|
| 492 | BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2
|
|---|
| 493 |
|
|---|
| 494 |
|
|---|
| 495 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
|
|---|
| 496 | imul xBX
|
|---|
| 497 | .again:
|
|---|
| 498 | ud2
|
|---|
| 499 | jmp .again
|
|---|
| 500 | BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2
|
|---|
| 501 |
|
|---|
| 502 |
|
|---|
| 503 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
|
|---|
| 504 | imul xCX, xBX
|
|---|
| 505 | .again:
|
|---|
| 506 | ud2
|
|---|
| 507 | jmp .again
|
|---|
| 508 | BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2
|
|---|
| 509 |
|
|---|
| 510 |
|
|---|
| 511 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
|
|---|
| 512 | div xBX
|
|---|
| 513 | .again:
|
|---|
| 514 | ud2
|
|---|
| 515 | jmp .again
|
|---|
| 516 | BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2
|
|---|
| 517 |
|
|---|
| 518 |
|
|---|
| 519 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
|
|---|
| 520 | idiv xBX
|
|---|
| 521 | .again:
|
|---|
| 522 | ud2
|
|---|
| 523 | jmp .again
|
|---|
| 524 | BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2
|
|---|
| 525 |
|
|---|
| 526 |
|
|---|
| 527 | ;
|
|---|
| 528 | ; BSF / BSR / TZCNT / LZCNT
|
|---|
| 529 | ;
|
|---|
| 530 | %ifndef EMIT_BITSCAN_DEFINED
|
|---|
| 531 | %define EMIT_BITSCAN_DEFINED
|
|---|
| 532 | %macro EMIT_BITSCAN 3
|
|---|
| 533 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR
|
|---|
| 534 | %2
|
|---|
| 535 | %1 ax, bx
|
|---|
| 536 | .again:
|
|---|
| 537 | ud2
|
|---|
| 538 | jmp .again
|
|---|
| 539 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2
|
|---|
| 540 |
|
|---|
| 541 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR
|
|---|
| 542 | %2
|
|---|
| 543 | %1 ax, [fs:xBX]
|
|---|
| 544 | .again:
|
|---|
| 545 | ud2
|
|---|
| 546 | jmp .again
|
|---|
| 547 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2
|
|---|
| 548 |
|
|---|
| 549 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR
|
|---|
| 550 | %2
|
|---|
| 551 | %1 eax, ebx
|
|---|
| 552 | .again:
|
|---|
| 553 | ud2
|
|---|
| 554 | jmp .again
|
|---|
| 555 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2
|
|---|
| 556 |
|
|---|
| 557 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR
|
|---|
| 558 | %2
|
|---|
| 559 | %1 eax, [fs:xBX]
|
|---|
| 560 | .again:
|
|---|
| 561 | ud2
|
|---|
| 562 | jmp .again
|
|---|
| 563 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2
|
|---|
| 564 |
|
|---|
| 565 | %if TMPL_BITS == 64
|
|---|
| 566 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR
|
|---|
| 567 | %2
|
|---|
| 568 | %1 rax, rbx
|
|---|
| 569 | .again:
|
|---|
| 570 | ud2
|
|---|
| 571 | jmp .again
|
|---|
| 572 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2
|
|---|
| 573 |
|
|---|
| 574 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR
|
|---|
| 575 | %2
|
|---|
| 576 | %1 rax, [fs:xBX]
|
|---|
| 577 | .again:
|
|---|
| 578 | ud2
|
|---|
| 579 | jmp .again
|
|---|
| 580 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2
|
|---|
| 581 | %endif
|
|---|
| 582 | %endmacro
|
|---|
| 583 | %endif
|
|---|
| 584 |
|
|---|
| 585 | EMIT_BITSCAN bsf, .ignored:, bsf
|
|---|
| 586 | EMIT_BITSCAN bsr, .ignored:, bsr
|
|---|
| 587 | EMIT_BITSCAN tzcnt, .ignored:, tzcnt
|
|---|
| 588 | EMIT_BITSCAN lzcnt, .ignored:, lzcnt
|
|---|
| 589 | EMIT_BITSCAN bsf, db 0f2h, f2_bsf
|
|---|
| 590 | EMIT_BITSCAN bsr, db 0f2h, f2_bsr
|
|---|
| 591 | EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt
|
|---|
| 592 | EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt
|
|---|
| 593 |
|
|---|
| 594 |
|
|---|
| 595 | ;
|
|---|
| 596 | ; RORX - VEX instruction with a couple of questions about non-standard encodings.
|
|---|
| 597 | ;
|
|---|
| 598 | ;;%define icebp ud2
|
|---|
| 599 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR
|
|---|
| 600 | rorx ebx, edx, 2
|
|---|
| 601 | .again:
|
|---|
| 602 | icebp
|
|---|
| 603 | jmp .again
|
|---|
| 604 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp
|
|---|
| 605 |
|
|---|
| 606 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR
|
|---|
| 607 | %if TMPL_BITS == 64
|
|---|
| 608 | rorx rbx, rdx, 2
|
|---|
| 609 | %else
|
|---|
| 610 | db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe)
|
|---|
| 611 | %endif
|
|---|
| 612 | .again:
|
|---|
| 613 | icebp
|
|---|
| 614 | jmp .again
|
|---|
| 615 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp
|
|---|
| 616 |
|
|---|
| 617 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR
|
|---|
| 618 | db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs
|
|---|
| 619 | .again:
|
|---|
| 620 | icebp
|
|---|
| 621 | jmp .again
|
|---|
| 622 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1
|
|---|
| 623 |
|
|---|
| 624 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR
|
|---|
| 625 | db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD
|
|---|
| 626 | .again:
|
|---|
| 627 | icebp
|
|---|
| 628 | jmp .again
|
|---|
| 629 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1
|
|---|
| 630 |
|
|---|
| 631 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR
|
|---|
| 632 | db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD
|
|---|
| 633 | .again:
|
|---|
| 634 | icebp
|
|---|
| 635 | jmp .again
|
|---|
| 636 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15
|
|---|
| 637 |
|
|---|
| 638 | %if TMPL_BITS == 64
|
|---|
| 639 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR
|
|---|
| 640 | db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe
|
|---|
| 641 | .again:
|
|---|
| 642 | icebp
|
|---|
| 643 | jmp .again
|
|---|
| 644 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1
|
|---|
| 645 | %endif
|
|---|
| 646 |
|
|---|
| 647 | ; A couple of memory variants
|
|---|
| 648 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp, BS3_PBC_NEAR
|
|---|
| 649 | rorx ebx, [xDI], 36
|
|---|
| 650 | .again:
|
|---|
| 651 | icebp
|
|---|
| 652 | jmp .again
|
|---|
| 653 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp
|
|---|
| 654 |
|
|---|
| 655 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp, BS3_PBC_NEAR
|
|---|
| 656 | %if TMPL_BITS == 64
|
|---|
| 657 | rorx rbx, [xDI], 68
|
|---|
| 658 | %elif TMPL_BITS == 32
|
|---|
| 659 | db 0C4h,0E3h,07Bh,0F0h,01Fh,044h ; 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 660 | %else
|
|---|
| 661 | db 0C4h,0E3h,0FBh,0F0h,01Dh,044h ; 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 662 | %endif
|
|---|
| 663 | .again:
|
|---|
| 664 | icebp
|
|---|
| 665 | jmp .again
|
|---|
| 666 | BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp
|
|---|
| 667 |
|
|---|
| 668 | ;
|
|---|
| 669 | ; ANDN (BMI1)
|
|---|
| 670 | ;
|
|---|
| 671 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR
|
|---|
| 672 | %if TMPL_BITS == 64
|
|---|
| 673 | andn rax, rcx, rbx
|
|---|
| 674 | %else
|
|---|
| 675 | db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 676 | %endif
|
|---|
| 677 | .again:
|
|---|
| 678 | icebp
|
|---|
| 679 | jmp .again
|
|---|
| 680 | BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp
|
|---|
| 681 |
|
|---|
| 682 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR
|
|---|
| 683 | andn eax, ecx, ebx
|
|---|
| 684 | .again:
|
|---|
| 685 | icebp
|
|---|
| 686 | jmp .again
|
|---|
| 687 | BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp
|
|---|
| 688 |
|
|---|
| 689 |
|
|---|
| 690 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 691 | %if TMPL_BITS == 64
|
|---|
| 692 | andn rax, rcx, [fs:rbx]
|
|---|
| 693 | %elif TMPL_BITS == 32
|
|---|
| 694 | db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx]
|
|---|
| 695 | %else
|
|---|
| 696 | db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx]
|
|---|
| 697 | %endif
|
|---|
| 698 | .again:
|
|---|
| 699 | icebp
|
|---|
| 700 | jmp .again
|
|---|
| 701 | BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp
|
|---|
| 702 |
|
|---|
| 703 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 704 | andn eax, ecx, [fs:xBX]
|
|---|
| 705 | .again:
|
|---|
| 706 | icebp
|
|---|
| 707 | jmp .again
|
|---|
| 708 | BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp
|
|---|
| 709 |
|
|---|
| 710 |
|
|---|
| 711 | ;
|
|---|
| 712 | ; BEXTR / SHLX / SARX / SHRX - BMI1 (opcode f7h)
|
|---|
| 713 | ; BZHI - BMI2 (opcode f5h)
|
|---|
| 714 | ;
|
|---|
| 715 | ; @param %1 instruction
|
|---|
| 716 | ; @param %2 opcode
|
|---|
| 717 | ; @param %3 prefix
|
|---|
| 718 | ;
|
|---|
| 719 | %ifndef SHLX_SARX_SHRX_DEFINED
|
|---|
| 720 | %define SHLX_SARX_SHRX_DEFINED
|
|---|
| 721 | %macro SHLX_SARX_SHRX 3
|
|---|
| 722 |
|
|---|
| 723 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR
|
|---|
| 724 | %if TMPL_BITS == 64
|
|---|
| 725 | %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3
|
|---|
| 726 | %else
|
|---|
| 727 | db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 728 | %endif
|
|---|
| 729 | .again:
|
|---|
| 730 | icebp
|
|---|
| 731 | jmp .again
|
|---|
| 732 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp
|
|---|
| 733 |
|
|---|
| 734 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR
|
|---|
| 735 | %1 eax, ebx, ecx
|
|---|
| 736 | .again:
|
|---|
| 737 | icebp
|
|---|
| 738 | jmp .again
|
|---|
| 739 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp
|
|---|
| 740 |
|
|---|
| 741 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR
|
|---|
| 742 | %if TMPL_BITS == 64
|
|---|
| 743 | %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703
|
|---|
| 744 | %elif TMPL_BITS == 32
|
|---|
| 745 | db 064h,0C4h,0E2h,0F0h|%3,%2,003h
|
|---|
| 746 | %else
|
|---|
| 747 | db 064h,0C4h,0E2h,0F0h|%3,%2,007h
|
|---|
| 748 | %endif
|
|---|
| 749 | .again:
|
|---|
| 750 | icebp
|
|---|
| 751 | jmp .again
|
|---|
| 752 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp
|
|---|
| 753 |
|
|---|
| 754 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR
|
|---|
| 755 | %1 eax, [fs:xBX], ecx
|
|---|
| 756 | .again:
|
|---|
| 757 | icebp
|
|---|
| 758 | jmp .again
|
|---|
| 759 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp
|
|---|
| 760 |
|
|---|
| 761 | %endmacro
|
|---|
| 762 | %endif
|
|---|
| 763 |
|
|---|
| 764 | SHLX_SARX_SHRX bextr, 0f7h, 0 ; none
|
|---|
| 765 | SHLX_SARX_SHRX shlx, 0f7h, 1 ; 66h
|
|---|
| 766 | SHLX_SARX_SHRX sarx, 0f7h, 2 ; f3h
|
|---|
| 767 | SHLX_SARX_SHRX shrx, 0f7h, 3 ; f2h
|
|---|
| 768 | SHLX_SARX_SHRX bzhi, 0f5h, 0 ; none
|
|---|
| 769 |
|
|---|
| 770 | ;
|
|---|
| 771 | ; PPEP / PEXT - BMI2 (opcode f5h)
|
|---|
| 772 | ;
|
|---|
| 773 | ; @param %1 instruction
|
|---|
| 774 | ; @param %2 opcode
|
|---|
| 775 | ; @param %3 prefix
|
|---|
| 776 | ;
|
|---|
| 777 | %ifndef PDEP_PEXT_DEFINED
|
|---|
| 778 | %define PDEP_PEXT_DEFINED
|
|---|
| 779 | %macro PDEP_PEXT_ 3
|
|---|
| 780 |
|
|---|
| 781 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp, BS3_PBC_NEAR
|
|---|
| 782 | %if TMPL_BITS == 64
|
|---|
| 783 | %1 rax, rcx, rbx
|
|---|
| 784 | %else
|
|---|
| 785 | db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 786 | %endif
|
|---|
| 787 | .again:
|
|---|
| 788 | icebp
|
|---|
| 789 | jmp .again
|
|---|
| 790 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp
|
|---|
| 791 |
|
|---|
| 792 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp, BS3_PBC_NEAR
|
|---|
| 793 | %1 eax, ecx, ebx
|
|---|
| 794 | .again:
|
|---|
| 795 | icebp
|
|---|
| 796 | jmp .again
|
|---|
| 797 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp
|
|---|
| 798 |
|
|---|
| 799 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 800 | %if TMPL_BITS == 64
|
|---|
| 801 | %1 rax, rcx, [fs:rbx]
|
|---|
| 802 | %elif TMPL_BITS == 32
|
|---|
| 803 | db 064h,0C4h,0E2h,0F0h|%3,%2,003h
|
|---|
| 804 | %else
|
|---|
| 805 | db 064h,0C4h,0E2h,0F0h|%3,%2,007h
|
|---|
| 806 | %endif
|
|---|
| 807 | .again:
|
|---|
| 808 | icebp
|
|---|
| 809 | jmp .again
|
|---|
| 810 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp
|
|---|
| 811 |
|
|---|
| 812 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 813 | %1 eax, ecx, [fs:xBX]
|
|---|
| 814 | .again:
|
|---|
| 815 | icebp
|
|---|
| 816 | jmp .again
|
|---|
| 817 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp
|
|---|
| 818 |
|
|---|
| 819 | %endmacro
|
|---|
| 820 | %endif
|
|---|
| 821 |
|
|---|
| 822 | PDEP_PEXT_ pext, 0f5h, 2 ; f3h
|
|---|
| 823 | PDEP_PEXT_ pdep, 0f5h, 3 ; f2h
|
|---|
| 824 |
|
|---|
| 825 | ;
|
|---|
| 826 | ; BLSR / BLSMSK / BLSI
|
|---|
| 827 | ; These are encoded in the exact same way, only the /r differs (%2).
|
|---|
| 828 | ;
|
|---|
| 829 | %ifndef BLSR_BLSMSK_BLSI_DEFINED
|
|---|
| 830 | %define BLSR_BLSMSK_BLSI_DEFINED
|
|---|
| 831 | %macro BLSR_BLSMSK_BLSI 2
|
|---|
| 832 |
|
|---|
| 833 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR
|
|---|
| 834 | %if TMPL_BITS == 64
|
|---|
| 835 | %1 rax, rbx ; BLSR=C4E2F8F3CB
|
|---|
| 836 | %else
|
|---|
| 837 | db 0C4h,0E2h,0F8h,0F3h,0C3h | (%2 << 3) ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 838 | %endif
|
|---|
| 839 | .again:
|
|---|
| 840 | icebp
|
|---|
| 841 | jmp .again
|
|---|
| 842 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp
|
|---|
| 843 |
|
|---|
| 844 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR
|
|---|
| 845 | %1 eax, ebx
|
|---|
| 846 | .again:
|
|---|
| 847 | icebp
|
|---|
| 848 | jmp .again
|
|---|
| 849 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp
|
|---|
| 850 |
|
|---|
| 851 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 852 | %if TMPL_BITS == 64
|
|---|
| 853 | %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B
|
|---|
| 854 | %elif TMPL_BITS == 32
|
|---|
| 855 | db 064h,0C4h,0E2h,0F8h,0F3h,003h | (%2 << 3)
|
|---|
| 856 | %else
|
|---|
| 857 | db 064h,0C4h,0E2h,0F8h,0F3h,007h | (%2 << 3)
|
|---|
| 858 | %endif
|
|---|
| 859 | .again:
|
|---|
| 860 | icebp
|
|---|
| 861 | jmp .again
|
|---|
| 862 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp
|
|---|
| 863 |
|
|---|
| 864 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 865 | %1 eax, [fs:xBX]
|
|---|
| 866 | .again:
|
|---|
| 867 | icebp
|
|---|
| 868 | jmp .again
|
|---|
| 869 | BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp
|
|---|
| 870 |
|
|---|
| 871 | %endmacro
|
|---|
| 872 | %endif
|
|---|
| 873 |
|
|---|
| 874 | BLSR_BLSMSK_BLSI blsr, 1
|
|---|
| 875 | BLSR_BLSMSK_BLSI blsmsk, 2
|
|---|
| 876 | BLSR_BLSMSK_BLSI blsi, 3
|
|---|
| 877 |
|
|---|
| 878 | ;
|
|---|
| 879 | ; MULX
|
|---|
| 880 | ;
|
|---|
| 881 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
|
|---|
| 882 | %if TMPL_BITS == 64
|
|---|
| 883 | mulx rax, rcx, rbx ; C4E2F3F6C3
|
|---|
| 884 | %else
|
|---|
| 885 | db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 886 | %endif
|
|---|
| 887 | .again:
|
|---|
| 888 | icebp
|
|---|
| 889 | jmp .again
|
|---|
| 890 | BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp
|
|---|
| 891 |
|
|---|
| 892 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
|
|---|
| 893 | %if TMPL_BITS == 64
|
|---|
| 894 | mulx rcx, rcx, rbx ; C4E2F3F6CB
|
|---|
| 895 | %else
|
|---|
| 896 | db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 897 | %endif
|
|---|
| 898 | .again:
|
|---|
| 899 | icebp
|
|---|
| 900 | jmp .again
|
|---|
| 901 | BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp
|
|---|
| 902 |
|
|---|
| 903 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR
|
|---|
| 904 | %if TMPL_BITS == 64
|
|---|
| 905 | mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603
|
|---|
| 906 | %elif TMPL_BITS == 32
|
|---|
| 907 | db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 908 | %else
|
|---|
| 909 | db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
|
|---|
| 910 | %endif
|
|---|
| 911 | .again:
|
|---|
| 912 | icebp
|
|---|
| 913 | jmp .again
|
|---|
| 914 | BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp
|
|---|
| 915 |
|
|---|
| 916 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
|
|---|
| 917 | mulx eax, ecx, ebx
|
|---|
| 918 | .again:
|
|---|
| 919 | icebp
|
|---|
| 920 | jmp .again
|
|---|
| 921 | BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp
|
|---|
| 922 |
|
|---|
| 923 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
|
|---|
| 924 | mulx ecx, ecx, ebx
|
|---|
| 925 | .again:
|
|---|
| 926 | icebp
|
|---|
| 927 | jmp .again
|
|---|
| 928 | BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp
|
|---|
| 929 |
|
|---|
| 930 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR
|
|---|
| 931 | mulx eax, ecx, [fs:xBX]
|
|---|
| 932 | .again:
|
|---|
| 933 | icebp
|
|---|
| 934 | jmp .again
|
|---|
| 935 | BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp
|
|---|
| 936 |
|
|---|
| 937 |
|
|---|
| 938 | ;
|
|---|
| 939 | ; POPCNT
|
|---|
| 940 | ;
|
|---|
| 941 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_BX_icebp, BS3_PBC_NEAR
|
|---|
| 942 | popcnt ax, bx
|
|---|
| 943 | .again:
|
|---|
| 944 | icebp
|
|---|
| 945 | jmp .again
|
|---|
| 946 | BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_BX_icebp
|
|---|
| 947 |
|
|---|
| 948 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp, BS3_PBC_NEAR
|
|---|
| 949 | popcnt eax, ebx
|
|---|
| 950 | .again:
|
|---|
| 951 | icebp
|
|---|
| 952 | jmp .again
|
|---|
| 953 | BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp
|
|---|
| 954 |
|
|---|
| 955 | %if TMPL_BITS == 64
|
|---|
| 956 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp, BS3_PBC_NEAR
|
|---|
| 957 | popcnt rax, rbx
|
|---|
| 958 | .again:
|
|---|
| 959 | icebp
|
|---|
| 960 | jmp .again
|
|---|
| 961 | BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp
|
|---|
| 962 | %endif
|
|---|
| 963 |
|
|---|
| 964 |
|
|---|
| 965 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 966 | popcnt ax, [fs:xBX]
|
|---|
| 967 | .again:
|
|---|
| 968 | icebp
|
|---|
| 969 | jmp .again
|
|---|
| 970 | BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp
|
|---|
| 971 |
|
|---|
| 972 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 973 | popcnt eax, [fs:xBX]
|
|---|
| 974 | .again:
|
|---|
| 975 | icebp
|
|---|
| 976 | jmp .again
|
|---|
| 977 | BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp
|
|---|
| 978 |
|
|---|
| 979 | %if TMPL_BITS == 64
|
|---|
| 980 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp, BS3_PBC_NEAR
|
|---|
| 981 | popcnt rax, [fs:xBX]
|
|---|
| 982 | .again:
|
|---|
| 983 | icebp
|
|---|
| 984 | jmp .again
|
|---|
| 985 | BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp
|
|---|
| 986 | %endif
|
|---|
| 987 |
|
|---|
| 988 |
|
|---|
| 989 | ;
|
|---|
| 990 | ; CRC32
|
|---|
| 991 | ;
|
|---|
| 992 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
|
|---|
| 993 | crc32 eax, bl
|
|---|
| 994 | .again:
|
|---|
| 995 | icebp
|
|---|
| 996 | jmp .again
|
|---|
| 997 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
|
|---|
| 998 |
|
|---|
| 999 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
|
|---|
| 1000 | crc32 eax, bx
|
|---|
| 1001 | .again:
|
|---|
| 1002 | icebp
|
|---|
| 1003 | jmp .again
|
|---|
| 1004 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
|
|---|
| 1005 |
|
|---|
| 1006 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
|
|---|
| 1007 | crc32 eax, ebx
|
|---|
| 1008 | .again:
|
|---|
| 1009 | icebp
|
|---|
| 1010 | jmp .again
|
|---|
| 1011 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
|
|---|
| 1012 |
|
|---|
| 1013 | %if TMPL_BITS == 64
|
|---|
| 1014 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
|
|---|
| 1015 | crc32 rax, rbx
|
|---|
| 1016 | .again:
|
|---|
| 1017 | icebp
|
|---|
| 1018 | jmp .again
|
|---|
| 1019 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
|
|---|
| 1020 | %endif
|
|---|
| 1021 |
|
|---|
| 1022 |
|
|---|
| 1023 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
|
|---|
| 1024 | crc32 eax, byte [fs:xBX]
|
|---|
| 1025 | .again:
|
|---|
| 1026 | icebp
|
|---|
| 1027 | jmp .again
|
|---|
| 1028 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
|
|---|
| 1029 |
|
|---|
| 1030 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
|
|---|
| 1031 | crc32 eax, word [fs:xBX]
|
|---|
| 1032 | .again:
|
|---|
| 1033 | icebp
|
|---|
| 1034 | jmp .again
|
|---|
| 1035 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
|
|---|
| 1036 |
|
|---|
| 1037 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
|
|---|
| 1038 | crc32 eax, dword [fs:xBX]
|
|---|
| 1039 | .again:
|
|---|
| 1040 | icebp
|
|---|
| 1041 | jmp .again
|
|---|
| 1042 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
|
|---|
| 1043 |
|
|---|
| 1044 | %if TMPL_BITS == 64
|
|---|
| 1045 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
|
|---|
| 1046 | crc32 rax, qword [fs:xBX]
|
|---|
| 1047 | .again:
|
|---|
| 1048 | icebp
|
|---|
| 1049 | jmp .again
|
|---|
| 1050 | BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
|
|---|
| 1051 | %endif
|
|---|
| 1052 |
|
|---|
| 1053 |
|
|---|
| 1054 | ;
|
|---|
| 1055 | ; ADCX
|
|---|
| 1056 | ;
|
|---|
| 1057 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp
|
|---|
| 1058 | adcx eax, ebx
|
|---|
| 1059 | .again:
|
|---|
| 1060 | icebp
|
|---|
| 1061 | jmp .again
|
|---|
| 1062 | BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp
|
|---|
| 1063 |
|
|---|
| 1064 | %if TMPL_BITS == 64
|
|---|
| 1065 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp
|
|---|
| 1066 | adcx rax, rbx
|
|---|
| 1067 | .again:
|
|---|
| 1068 | icebp
|
|---|
| 1069 | jmp .again
|
|---|
| 1070 | BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp
|
|---|
| 1071 | %endif
|
|---|
| 1072 |
|
|---|
| 1073 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp
|
|---|
| 1074 | adcx eax, dword [fs:xBX]
|
|---|
| 1075 | .again:
|
|---|
| 1076 | icebp
|
|---|
| 1077 | jmp .again
|
|---|
| 1078 | BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp
|
|---|
| 1079 |
|
|---|
| 1080 | %if TMPL_BITS == 64
|
|---|
| 1081 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp
|
|---|
| 1082 | adcx rax, qword [fs:xBX]
|
|---|
| 1083 | .again:
|
|---|
| 1084 | icebp
|
|---|
| 1085 | jmp .again
|
|---|
| 1086 | BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp
|
|---|
| 1087 | %endif
|
|---|
| 1088 |
|
|---|
| 1089 |
|
|---|
| 1090 | ;
|
|---|
| 1091 | ; ADOX
|
|---|
| 1092 | ;
|
|---|
| 1093 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_EBX_icebp
|
|---|
| 1094 | adox eax, ebx
|
|---|
| 1095 | .again:
|
|---|
| 1096 | icebp
|
|---|
| 1097 | jmp .again
|
|---|
| 1098 | BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_EBX_icebp
|
|---|
| 1099 |
|
|---|
| 1100 | %if TMPL_BITS == 64
|
|---|
| 1101 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_RBX_icebp
|
|---|
| 1102 | adox rax, rbx
|
|---|
| 1103 | .again:
|
|---|
| 1104 | icebp
|
|---|
| 1105 | jmp .again
|
|---|
| 1106 | BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_RBX_icebp
|
|---|
| 1107 | %endif
|
|---|
| 1108 |
|
|---|
| 1109 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp
|
|---|
| 1110 | adox eax, dword [fs:xBX]
|
|---|
| 1111 | .again:
|
|---|
| 1112 | icebp
|
|---|
| 1113 | jmp .again
|
|---|
| 1114 | BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp
|
|---|
| 1115 |
|
|---|
| 1116 | %if TMPL_BITS == 64
|
|---|
| 1117 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp
|
|---|
| 1118 | adox rax, qword [fs:xBX]
|
|---|
| 1119 | .again:
|
|---|
| 1120 | icebp
|
|---|
| 1121 | jmp .again
|
|---|
| 1122 | BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp
|
|---|
| 1123 | %endif
|
|---|
| 1124 |
|
|---|
| 1125 |
|
|---|
| 1126 | ;
|
|---|
| 1127 | ; MOVBE
|
|---|
| 1128 | ;
|
|---|
| 1129 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_AX_word_FSxBX_icebp
|
|---|
| 1130 | movbe ax, word [fs:xBX]
|
|---|
| 1131 | .again:
|
|---|
| 1132 | icebp
|
|---|
| 1133 | jmp .again
|
|---|
| 1134 | BS3_PROC_END_CMN bs3CpuInstr2_movbe_AX_word_FSxBX_icebp
|
|---|
| 1135 |
|
|---|
| 1136 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_word_FSxBX_AX_icebp
|
|---|
| 1137 | movbe word [fs:xBX], ax
|
|---|
| 1138 | .again:
|
|---|
| 1139 | icebp
|
|---|
| 1140 | jmp .again
|
|---|
| 1141 | BS3_PROC_END_CMN bs3CpuInstr2_movbe_word_FSxBX_AX_icebp
|
|---|
| 1142 |
|
|---|
| 1143 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_EAX_dword_FSxBX_icebp
|
|---|
| 1144 | movbe eax, dword [fs:xBX]
|
|---|
| 1145 | .again:
|
|---|
| 1146 | icebp
|
|---|
| 1147 | jmp .again
|
|---|
| 1148 | BS3_PROC_END_CMN bs3CpuInstr2_movbe_EAX_dword_FSxBX_icebp
|
|---|
| 1149 |
|
|---|
| 1150 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_dword_FSxBX_EAX_icebp
|
|---|
| 1151 | movbe dword [fs:xBX], eax
|
|---|
| 1152 | .again:
|
|---|
| 1153 | icebp
|
|---|
| 1154 | jmp .again
|
|---|
| 1155 | BS3_PROC_END_CMN bs3CpuInstr2_movbe_dword_FSxBX_EAX_icebp
|
|---|
| 1156 |
|
|---|
| 1157 | %if TMPL_BITS == 64
|
|---|
| 1158 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_RAX_qword_FSxBX_icebp
|
|---|
| 1159 | movbe rax, qword [fs:xBX]
|
|---|
| 1160 | .again:
|
|---|
| 1161 | icebp
|
|---|
| 1162 | jmp .again
|
|---|
| 1163 | BS3_PROC_END_CMN bs3CpuInstr2_movbe_RAX_qword_FSxBX_icebp
|
|---|
| 1164 |
|
|---|
| 1165 | BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_qword_FSxBX_RAX_icebp
|
|---|
| 1166 | movbe qword [fs:xBX], rax
|
|---|
| 1167 | .again:
|
|---|
| 1168 | icebp
|
|---|
| 1169 | jmp .again
|
|---|
| 1170 | BS3_PROC_END_CMN bs3CpuInstr2_movbe_qword_FSxBX_RAX_icebp
|
|---|
| 1171 | %endif
|
|---|
| 1172 |
|
|---|
| 1173 |
|
|---|
| 1174 | ;
|
|---|
| 1175 | ; CMPXCHG8B
|
|---|
| 1176 | ;
|
|---|
| 1177 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1178 | cmpxchg8b [fs:xDI]
|
|---|
| 1179 | .again:
|
|---|
| 1180 | icebp
|
|---|
| 1181 | jmp .again
|
|---|
| 1182 | BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg8b_FSxDI_icebp
|
|---|
| 1183 |
|
|---|
| 1184 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1185 | lock cmpxchg8b [fs:xDI]
|
|---|
| 1186 | .again:
|
|---|
| 1187 | icebp
|
|---|
| 1188 | jmp .again
|
|---|
| 1189 | BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg8b_FSxDI_icebp
|
|---|
| 1190 |
|
|---|
| 1191 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1192 | o16 cmpxchg8b [fs:xDI]
|
|---|
| 1193 | .again:
|
|---|
| 1194 | icebp
|
|---|
| 1195 | jmp .again
|
|---|
| 1196 | BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg8b_FSxDI_icebp
|
|---|
| 1197 |
|
|---|
| 1198 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1199 | db 0f0h, 066h
|
|---|
| 1200 | cmpxchg8b [fs:xDI]
|
|---|
| 1201 | .again:
|
|---|
| 1202 | icebp
|
|---|
| 1203 | jmp .again
|
|---|
| 1204 | BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg8b_FSxDI_icebp
|
|---|
| 1205 |
|
|---|
| 1206 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1207 | repz cmpxchg8b [fs:xDI]
|
|---|
| 1208 | .again:
|
|---|
| 1209 | icebp
|
|---|
| 1210 | jmp .again
|
|---|
| 1211 | BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg8b_FSxDI_icebp
|
|---|
| 1212 |
|
|---|
| 1213 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1214 | db 0f0h, 0f3h
|
|---|
| 1215 | cmpxchg8b [fs:xDI]
|
|---|
| 1216 | .again:
|
|---|
| 1217 | icebp
|
|---|
| 1218 | jmp .again
|
|---|
| 1219 | BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg8b_FSxDI_icebp
|
|---|
| 1220 |
|
|---|
| 1221 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1222 | repnz cmpxchg8b [fs:xDI]
|
|---|
| 1223 | .again:
|
|---|
| 1224 | icebp
|
|---|
| 1225 | jmp .again
|
|---|
| 1226 | BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg8b_FSxDI_icebp
|
|---|
| 1227 |
|
|---|
| 1228 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
|
|---|
| 1229 | db 0f0h, 0f2h
|
|---|
| 1230 | cmpxchg8b [fs:xDI]
|
|---|
| 1231 | .again:
|
|---|
| 1232 | icebp
|
|---|
| 1233 | jmp .again
|
|---|
| 1234 | BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg8b_FSxDI_icebp
|
|---|
| 1235 |
|
|---|
| 1236 |
|
|---|
| 1237 | ;
|
|---|
| 1238 | ; CMPXCHG16B
|
|---|
| 1239 | ;
|
|---|
| 1240 | %if TMPL_BITS == 64
|
|---|
| 1241 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1242 | cmpxchg16b [rdi]
|
|---|
| 1243 | .again:
|
|---|
| 1244 | ud2
|
|---|
| 1245 | jmp .again
|
|---|
| 1246 | AssertCompile(.again - BS3_LAST_LABEL == 4)
|
|---|
| 1247 | BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2
|
|---|
| 1248 |
|
|---|
| 1249 |
|
|---|
| 1250 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1251 | lock cmpxchg16b [rdi]
|
|---|
| 1252 | .again:
|
|---|
| 1253 | ud2
|
|---|
| 1254 | jmp .again
|
|---|
| 1255 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1256 | BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
|
|---|
| 1257 |
|
|---|
| 1258 |
|
|---|
| 1259 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1260 | o16 cmpxchg16b [rdi]
|
|---|
| 1261 | .again:
|
|---|
| 1262 | ud2
|
|---|
| 1263 | jmp .again
|
|---|
| 1264 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1265 | BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
|
|---|
| 1266 |
|
|---|
| 1267 |
|
|---|
| 1268 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1269 | db 0f0h, 066h
|
|---|
| 1270 | cmpxchg16b [rdi]
|
|---|
| 1271 | .again:
|
|---|
| 1272 | ud2
|
|---|
| 1273 | jmp .again
|
|---|
| 1274 | AssertCompile(.again - BS3_LAST_LABEL == 6)
|
|---|
| 1275 | BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
|
|---|
| 1276 |
|
|---|
| 1277 |
|
|---|
| 1278 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1279 | repz cmpxchg16b [rdi]
|
|---|
| 1280 | .again:
|
|---|
| 1281 | ud2
|
|---|
| 1282 | jmp .again
|
|---|
| 1283 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1284 | BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
|
|---|
| 1285 |
|
|---|
| 1286 |
|
|---|
| 1287 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1288 | db 0f0h, 0f3h
|
|---|
| 1289 | cmpxchg16b [rdi]
|
|---|
| 1290 | .again:
|
|---|
| 1291 | ud2
|
|---|
| 1292 | jmp .again
|
|---|
| 1293 | AssertCompile(.again - BS3_LAST_LABEL == 6)
|
|---|
| 1294 | BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
|
|---|
| 1295 |
|
|---|
| 1296 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1297 | repnz cmpxchg16b [rdi]
|
|---|
| 1298 | .again:
|
|---|
| 1299 | ud2
|
|---|
| 1300 | jmp .again
|
|---|
| 1301 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1302 | BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
|
|---|
| 1303 |
|
|---|
| 1304 |
|
|---|
| 1305 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
|
|---|
| 1306 | db 0f0h, 0f2h
|
|---|
| 1307 | cmpxchg16b [rdi]
|
|---|
| 1308 | .again:
|
|---|
| 1309 | ud2
|
|---|
| 1310 | jmp .again
|
|---|
| 1311 | AssertCompile(.again - BS3_LAST_LABEL == 6)
|
|---|
| 1312 | BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
|
|---|
| 1313 |
|
|---|
| 1314 |
|
|---|
| 1315 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
|
|---|
| 1316 | wrfsbase rbx
|
|---|
| 1317 | .again:
|
|---|
| 1318 | ud2
|
|---|
| 1319 | jmp .again
|
|---|
| 1320 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1321 | BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2
|
|---|
| 1322 |
|
|---|
| 1323 |
|
|---|
| 1324 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
|
|---|
| 1325 | wrfsbase ebx
|
|---|
| 1326 | .again:
|
|---|
| 1327 | ud2
|
|---|
| 1328 | jmp .again
|
|---|
| 1329 | AssertCompile(.again - BS3_LAST_LABEL == 4)
|
|---|
| 1330 | BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2
|
|---|
| 1331 |
|
|---|
| 1332 |
|
|---|
| 1333 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
|
|---|
| 1334 | wrgsbase rbx
|
|---|
| 1335 | .again:
|
|---|
| 1336 | ud2
|
|---|
| 1337 | jmp .again
|
|---|
| 1338 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1339 | BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2
|
|---|
| 1340 |
|
|---|
| 1341 |
|
|---|
| 1342 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
|
|---|
| 1343 | wrgsbase ebx
|
|---|
| 1344 | .again:
|
|---|
| 1345 | ud2
|
|---|
| 1346 | jmp .again
|
|---|
| 1347 | AssertCompile(.again - BS3_LAST_LABEL == 4)
|
|---|
| 1348 | BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2
|
|---|
| 1349 |
|
|---|
| 1350 |
|
|---|
| 1351 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
|
|---|
| 1352 | wrfsbase rbx
|
|---|
| 1353 | mov ebx, 0
|
|---|
| 1354 | rdfsbase rcx
|
|---|
| 1355 | .again:
|
|---|
| 1356 | ud2
|
|---|
| 1357 | jmp .again
|
|---|
| 1358 | AssertCompile(.again - BS3_LAST_LABEL == 15)
|
|---|
| 1359 | BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2
|
|---|
| 1360 |
|
|---|
| 1361 |
|
|---|
| 1362 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
|
|---|
| 1363 | wrfsbase ebx
|
|---|
| 1364 | mov ebx, 0
|
|---|
| 1365 | rdfsbase ecx
|
|---|
| 1366 | .again:
|
|---|
| 1367 | ud2
|
|---|
| 1368 | jmp .again
|
|---|
| 1369 | AssertCompile(.again - BS3_LAST_LABEL == 13)
|
|---|
| 1370 | BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2
|
|---|
| 1371 |
|
|---|
| 1372 |
|
|---|
| 1373 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
|
|---|
| 1374 | wrgsbase rbx
|
|---|
| 1375 | mov ebx, 0
|
|---|
| 1376 | rdgsbase rcx
|
|---|
| 1377 | .again:
|
|---|
| 1378 | ud2
|
|---|
| 1379 | jmp .again
|
|---|
| 1380 | AssertCompile(.again - BS3_LAST_LABEL == 15)
|
|---|
| 1381 | BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2
|
|---|
| 1382 |
|
|---|
| 1383 |
|
|---|
| 1384 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
|
|---|
| 1385 | wrgsbase ebx
|
|---|
| 1386 | mov ebx, 0
|
|---|
| 1387 | rdgsbase ecx
|
|---|
| 1388 | .again:
|
|---|
| 1389 | ud2
|
|---|
| 1390 | jmp .again
|
|---|
| 1391 | AssertCompile(.again - BS3_LAST_LABEL == 13)
|
|---|
| 1392 | BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2
|
|---|
| 1393 |
|
|---|
| 1394 |
|
|---|
| 1395 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
|
|---|
| 1396 | rdfsbase rbx
|
|---|
| 1397 | .again:
|
|---|
| 1398 | ud2
|
|---|
| 1399 | jmp .again
|
|---|
| 1400 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1401 | BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2
|
|---|
| 1402 |
|
|---|
| 1403 |
|
|---|
| 1404 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
|
|---|
| 1405 | rdfsbase ebx
|
|---|
| 1406 | .again:
|
|---|
| 1407 | ud2
|
|---|
| 1408 | jmp .again
|
|---|
| 1409 | AssertCompile(.again - BS3_LAST_LABEL == 4)
|
|---|
| 1410 | BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2
|
|---|
| 1411 |
|
|---|
| 1412 |
|
|---|
| 1413 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
|
|---|
| 1414 | rdgsbase rbx
|
|---|
| 1415 | .again:
|
|---|
| 1416 | ud2
|
|---|
| 1417 | jmp .again
|
|---|
| 1418 | AssertCompile(.again - BS3_LAST_LABEL == 5)
|
|---|
| 1419 | BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2
|
|---|
| 1420 |
|
|---|
| 1421 |
|
|---|
| 1422 | BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
|
|---|
| 1423 | rdgsbase ebx
|
|---|
| 1424 | .again:
|
|---|
| 1425 | ud2
|
|---|
| 1426 | jmp .again
|
|---|
| 1427 | AssertCompile(.again - BS3_LAST_LABEL == 4)
|
|---|
| 1428 | BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2
|
|---|
| 1429 |
|
|---|
| 1430 |
|
|---|
| 1431 | ;; @todo figure out this fudge. sigh.
|
|---|
| 1432 | times (348) db 0cch ; fudge to avoid 'rderr' during boot.
|
|---|
| 1433 |
|
|---|
| 1434 | %endif ; TMPL_BITS == 64
|
|---|
| 1435 |
|
|---|
| 1436 |
|
|---|
| 1437 | %endif ; BS3_INSTANTIATING_CMN
|
|---|
| 1438 |
|
|---|
| 1439 | %include "bs3kit-template-footer.mac" ; reset environment
|
|---|
| 1440 |
|
|---|
