1 | /* $Id: bs3-cpu-generated-1.h 66404 2017-04-03 15:21:56Z vboxsync $ */
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2 | /** @file
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3 | * BS3Kit - bs3-cpu-generated-1, common header file.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2007-2016 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * The contents of this file may alternatively be used under the terms
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18 | * of the Common Development and Distribution License Version 1.0
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19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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20 | * VirtualBox OSE distribution, in which case the provisions of the
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21 | * CDDL are applicable instead of those of the GPL.
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22 | *
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23 | * You may elect to license modified versions of this file under the
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24 | * terms and conditions of either the GPL or the CDDL or both.
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25 | */
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26 |
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27 |
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28 | #ifndef ___bs3_cpu_generated_1_h___
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29 | #define ___bs3_cpu_generated_1_h___
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30 |
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31 | #include <bs3kit.h>
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32 | #include <iprt/assert.h>
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33 |
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34 |
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35 | /**
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36 | * Operand details.
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37 | *
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38 | * Currently simply using the encoding from the reference manuals.
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39 | */
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40 | typedef enum BS3CG1OP
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41 | {
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42 | BS3CG1OP_INVALID = 0,
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43 |
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44 | BS3CG1OP_Eb,
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45 | BS3CG1OP_Ev,
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46 | BS3CG1OP_Wss,
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47 | BS3CG1OP_Wsd,
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48 | BS3CG1OP_Wps,
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49 | BS3CG1OP_Wpd,
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50 | BS3CG1OP_Wdq,
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51 | BS3CG1OP_WqZxReg,
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52 |
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53 | BS3CG1OP_Gb,
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54 | BS3CG1OP_Gv,
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55 | BS3CG1OP_Uq,
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56 | BS3CG1OP_UqHi,
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57 | BS3CG1OP_Vss,
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58 | BS3CG1OP_Vsd,
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59 | BS3CG1OP_Vps,
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60 | BS3CG1OP_Vpd,
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61 | BS3CG1OP_Vq,
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62 | BS3CG1OP_Vdq,
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63 |
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64 | BS3CG1OP_Ib,
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65 | BS3CG1OP_Iz,
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66 |
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67 | BS3CG1OP_AL,
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68 | BS3CG1OP_rAX,
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69 |
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70 | BS3CG1OP_Ma,
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71 | BS3CG1OP_MbRO,
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72 | BS3CG1OP_MdRO,
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73 | BS3CG1OP_MdWO,
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74 | BS3CG1OP_Mq,
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75 |
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76 | BS3CG1OP_END
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77 | } BS3CG1OP;
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78 | /** Pointer to a const operand enum. */
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79 | typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
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80 |
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81 |
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82 | /**
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83 | * Instruction encoding format.
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84 | *
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85 | * This duplicates some of the info in the operand array, however it makes it
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86 | * easier to figure out encoding variations.
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87 | */
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88 | typedef enum BS3CG1ENC
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89 | {
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90 | BS3CG1ENC_INVALID = 0,
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91 |
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92 | BS3CG1ENC_MODRM_Eb_Gb,
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93 | BS3CG1ENC_MODRM_Ev_Gv,
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94 | BS3CG1ENC_MODRM_Wss_Vss,
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95 | BS3CG1ENC_MODRM_Wsd_Vsd,
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96 | BS3CG1ENC_MODRM_Wps_Vps,
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97 | BS3CG1ENC_MODRM_Wpd_Vpd,
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98 | BS3CG1ENC_MODRM_WqZxReg_Vq,
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99 |
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100 | BS3CG1ENC_MODRM_Gb_Eb,
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101 | BS3CG1ENC_MODRM_Gv_Ev,
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102 | BS3CG1ENC_MODRM_Gv_Ma, /**< bound instruction */
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103 | BS3CG1ENC_MODRM_Vq_UqHi,
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104 | BS3CG1ENC_MODRM_Vq_Mq,
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105 | BS3CG1ENC_MODRM_Vdq_Wdq,
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106 | BS3CG1ENC_MODRM_MbRO,
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107 | BS3CG1ENC_MODRM_MdRO,
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108 | BS3CG1ENC_MODRM_MdWO,
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109 |
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110 | BS3CG1ENC_FIXED,
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111 | BS3CG1ENC_FIXED_AL_Ib,
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112 | BS3CG1ENC_FIXED_rAX_Iz,
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113 |
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114 | BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */
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115 | BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */
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116 |
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117 | BS3CG1ENC_END
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118 | } BS3CG1ENC;
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119 |
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120 |
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121 | /**
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122 | * Prefix sensitivitiy kind.
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123 | */
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124 | typedef enum BS3CG1PFXKIND
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125 | {
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126 | BS3CG1PFXKIND_INVALID = 0,
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127 |
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128 | BS3CG1PFXKIND_NO_F2_F3_66, /**< No 66, F2 or F3 prefixes allowed as that would alter the meaning. */
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129 | BS3CG1PFXKIND_REQ_F2, /**< Requires F2 (REPNE) prefix as part of the instr encoding. */
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130 | BS3CG1PFXKIND_REQ_F3, /**< Requires F3 (REPE) prefix as part of the instr encoding. */
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131 | BS3CG1PFXKIND_REQ_66, /**< Requires 66 (OP SIZE) prefix as part of the instr encoding. */
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132 |
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133 | /** @todo more work to be done here... */
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134 | BS3CG1PFXKIND_MODRM,
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135 | BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
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136 |
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137 | BS3CG1PFXKIND_END
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138 | } BS3CG1PFXKIND;
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139 |
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140 | /**
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141 | * CPU selection or CPU ID.
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142 | */
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143 | typedef enum BS3CG1CPU
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144 | {
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145 | /** Works with an CPU. */
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146 | BS3CG1CPU_ANY = 0,
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147 | BS3CG1CPU_GE_80186,
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148 | BS3CG1CPU_GE_80286,
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149 | BS3CG1CPU_GE_80386,
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150 | BS3CG1CPU_GE_80486,
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151 | BS3CG1CPU_GE_Pentium,
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152 |
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153 | BS3CG1CPU_SSE,
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154 | BS3CG1CPU_SSE2,
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155 | BS3CG1CPU_SSE3,
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156 | BS3CG1CPU_AVX,
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157 | BS3CG1CPU_AVX2,
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158 | BS3CG1CPU_CLFSH,
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159 | BS3CG1CPU_CLFLUSHOPT,
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160 |
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161 | BS3CG1CPU_END
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162 | } BS3CG1CPU;
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163 |
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164 |
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165 | /**
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166 | * SSE & AVX exception types.
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167 | */
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168 | typedef enum BS3CG1XCPTTYPE
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169 | {
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170 | BS3CG1XCPTTYPE_NONE = 0,
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171 | /* SSE: */
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172 | BS3CG1XCPTTYPE_1,
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173 | BS3CG1XCPTTYPE_2,
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174 | BS3CG1XCPTTYPE_3,
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175 | BS3CG1XCPTTYPE_4,
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176 | BS3CG1XCPTTYPE_4UA,
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177 | BS3CG1XCPTTYPE_5,
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178 | BS3CG1XCPTTYPE_6,
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179 | BS3CG1XCPTTYPE_7,
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180 | BS3CG1XCPTTYPE_8,
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181 | BS3CG1XCPTTYPE_11,
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182 | BS3CG1XCPTTYPE_12,
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183 | /* EVEX: */
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184 | BS3CG1XCPTTYPE_E1,
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185 | BS3CG1XCPTTYPE_E1NF,
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186 | BS3CG1XCPTTYPE_E2,
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187 | BS3CG1XCPTTYPE_E3,
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188 | BS3CG1XCPTTYPE_E3NF,
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189 | BS3CG1XCPTTYPE_E4,
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190 | BS3CG1XCPTTYPE_E4NF,
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191 | BS3CG1XCPTTYPE_E5,
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192 | BS3CG1XCPTTYPE_E5NF,
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193 | BS3CG1XCPTTYPE_E6,
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194 | BS3CG1XCPTTYPE_E6NF,
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195 | BS3CG1XCPTTYPE_E7NF,
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196 | BS3CG1XCPTTYPE_E9,
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197 | BS3CG1XCPTTYPE_E9NF,
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198 | BS3CG1XCPTTYPE_E10,
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199 | BS3CG1XCPTTYPE_E11,
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200 | BS3CG1XCPTTYPE_E12,
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201 | BS3CG1XCPTTYPE_E12NF,
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202 | BS3CG1XCPTTYPE_END
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203 | } BS3CG1XCPTTYPE;
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204 | AssertCompile(BS3CG1XCPTTYPE_END <= 32);
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205 |
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206 |
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207 | /**
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208 | * Generated instruction info.
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209 | */
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210 | typedef struct BS3CG1INSTR
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211 | {
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212 | /** The opcode size. */
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213 | uint32_t cbOpcodes : 2;
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214 | /** The number of operands. */
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215 | uint32_t cOperands : 2;
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216 | /** The length of the mnemonic. */
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217 | uint32_t cchMnemonic : 4;
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218 | /** Whether to advance the mnemonic array pointer. */
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219 | uint32_t fAdvanceMnemonic : 1;
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220 | /** Offset into g_abBs3Cg1Tests of the first test. */
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221 | uint32_t offTests : 23;
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222 | /** BS3CG1ENC values. */
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223 | uint32_t enmEncoding : 10;
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224 | /** BS3CG1PFXKIND values. */
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225 | uint32_t enmPrefixKind : 4;
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226 | /** CPU test / CPU ID bit test (BS3CG1CPU). */
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227 | uint32_t enmCpuTest : 6;
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228 | /** Exception type (BS3CG1XCPTTYPE) */
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229 | uint32_t enmXcptType : 5;
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230 | /** Currently unused bits. */
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231 | uint32_t uUnused : 6;
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232 | /** BS3CG1INSTR_F_XXX. */
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233 | uint32_t fFlags;
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234 | } BS3CG1INSTR;
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235 | AssertCompileSize(BS3CG1INSTR, 12);
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236 | /** Pointer to a const instruction. */
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237 | typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
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238 |
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239 |
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240 | /** @name BS3CG1INSTR_F_XXX
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241 | * @{ */
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242 | /** Defaults to SS rather than DS. */
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243 | #define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
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244 | /** Invalid instruction in 64-bit mode. */
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245 | #define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
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246 | /** Unused instruction. */
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247 | #define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
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248 | /** Invalid instruction. */
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249 | #define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
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250 | /** @} */
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251 |
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252 |
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253 | /**
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254 | * Test header.
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255 | */
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256 | typedef struct BS3CG1TESTHDR
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257 | {
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258 | /** The size of the selector program in bytes.
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259 | * This is also the offset of the input context modification program. */
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260 | uint32_t cbSelector : 8;
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261 | /** The size of the input context modification program in bytes.
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262 | * This immediately follows the selector program. */
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263 | uint32_t cbInput : 12;
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264 | /** The size of the output context modification program in bytes.
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265 | * This immediately follows the input context modification program. The
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266 | * program takes the result of the input program as starting point. */
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267 | uint32_t cbOutput : 11;
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268 | /** Indicates whether this is the last test or not. */
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269 | uint32_t fLast : 1;
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270 | } BS3CG1TESTHDR;
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271 | AssertCompileSize(BS3CG1TESTHDR, 4);
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272 | /** Pointer to a const test header. */
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273 | typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
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274 |
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275 | /** @name Opcode format for the BS3CG1 context modifier.
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276 | *
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277 | * Used by both the input and output context programs.
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278 | *
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279 | * The most common operations are encoded as a single byte opcode followed by
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280 | * one or more immediate bytes with data.
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281 | *
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282 | * @{ */
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283 | #define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
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284 | #define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
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285 | #define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
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286 | #define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
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287 | #define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
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288 | #define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
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289 | #define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
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290 | #define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
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291 | #define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /**< Separate byte encoding the value size following any destination escape byte. */
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292 |
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293 | #define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
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294 | #define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
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295 | #define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
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296 | #define BS3CG1_CTXOP_EFL UINT8_C(0x10)
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297 | #define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /**< Separate byte giving the destination follows immediately. */
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298 |
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299 | #define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /**< Whether to sign-extend (set) the immediate value. */
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300 |
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301 | #define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
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302 | #define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /**< Simple assignment operator (=) */
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303 | #define BS3CG1_CTXOP_OR UINT8_C(0x40) /**< OR assignment operator (|=). */
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304 | #define BS3CG1_CTXOP_AND UINT8_C(0x80) /**< AND assignment operator (&=). */
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305 | #define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /**< AND assignment operator of the inverted value (&~=). */
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306 | /** @} */
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307 |
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308 | /**
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309 | * Escaped destination values
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310 | *
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311 | * These are just uppercased versions of TestInOut.kdFields, where dots are
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312 | * replaced by underscores.
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313 | */
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314 | typedef enum BS3CG1DST
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315 | {
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316 | BS3CG1DST_INVALID = 0,
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317 | /* Operands. */
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318 | BS3CG1DST_OP1,
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319 | BS3CG1DST_OP2,
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320 | BS3CG1DST_OP3,
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321 | BS3CG1DST_OP4,
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322 | /* Flags. */
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323 | BS3CG1DST_EFL,
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324 | BS3CG1DST_EFL_UNDEF, /**< Special field only valid in output context modifiers: EFLAGS |= Value & Ouput.EFLAGS; */
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325 | /* 8-bit GPRs. */
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326 | BS3CG1DST_AL,
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327 | BS3CG1DST_CL,
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328 | BS3CG1DST_DL,
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329 | BS3CG1DST_BL,
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330 | BS3CG1DST_AH,
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331 | BS3CG1DST_CH,
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332 | BS3CG1DST_DH,
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333 | BS3CG1DST_BH,
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334 | BS3CG1DST_SPL,
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335 | BS3CG1DST_BPL,
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336 | BS3CG1DST_SIL,
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337 | BS3CG1DST_DIL,
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338 | BS3CG1DST_R8L,
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339 | BS3CG1DST_R9L,
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340 | BS3CG1DST_R10L,
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341 | BS3CG1DST_R11L,
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342 | BS3CG1DST_R12L,
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343 | BS3CG1DST_R13L,
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344 | BS3CG1DST_R14L,
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345 | BS3CG1DST_R15L,
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346 | /* 16-bit GPRs. */
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347 | BS3CG1DST_AX,
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348 | BS3CG1DST_CX,
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349 | BS3CG1DST_DX,
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350 | BS3CG1DST_BX,
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351 | BS3CG1DST_SP,
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352 | BS3CG1DST_BP,
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353 | BS3CG1DST_SI,
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354 | BS3CG1DST_DI,
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355 | BS3CG1DST_R8W,
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356 | BS3CG1DST_R9W,
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357 | BS3CG1DST_R10W,
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358 | BS3CG1DST_R11W,
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359 | BS3CG1DST_R12W,
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360 | BS3CG1DST_R13W,
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361 | BS3CG1DST_R14W,
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362 | BS3CG1DST_R15W,
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363 | /* 32-bit GPRs. */
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364 | BS3CG1DST_EAX,
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365 | BS3CG1DST_ECX,
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366 | BS3CG1DST_EDX,
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367 | BS3CG1DST_EBX,
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368 | BS3CG1DST_ESP,
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369 | BS3CG1DST_EBP,
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370 | BS3CG1DST_ESI,
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371 | BS3CG1DST_EDI,
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372 | BS3CG1DST_R8D,
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373 | BS3CG1DST_R9D,
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374 | BS3CG1DST_R10D,
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375 | BS3CG1DST_R11D,
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376 | BS3CG1DST_R12D,
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377 | BS3CG1DST_R13D,
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378 | BS3CG1DST_R14D,
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379 | BS3CG1DST_R15D,
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380 | /* 64-bit GPRs. */
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381 | BS3CG1DST_RAX,
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382 | BS3CG1DST_RCX,
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383 | BS3CG1DST_RDX,
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384 | BS3CG1DST_RBX,
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385 | BS3CG1DST_RSP,
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386 | BS3CG1DST_RBP,
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387 | BS3CG1DST_RSI,
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388 | BS3CG1DST_RDI,
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389 | BS3CG1DST_R8,
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390 | BS3CG1DST_R9,
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391 | BS3CG1DST_R10,
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392 | BS3CG1DST_R11,
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393 | BS3CG1DST_R12,
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394 | BS3CG1DST_R13,
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395 | BS3CG1DST_R14,
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396 | BS3CG1DST_R15,
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397 | /* 16-bit, 32-bit or 64-bit registers according to operand size. */
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398 | BS3CG1DST_OZ_RAX,
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399 | BS3CG1DST_OZ_RCX,
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400 | BS3CG1DST_OZ_RDX,
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401 | BS3CG1DST_OZ_RBX,
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402 | BS3CG1DST_OZ_RSP,
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403 | BS3CG1DST_OZ_RBP,
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404 | BS3CG1DST_OZ_RSI,
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405 | BS3CG1DST_OZ_RDI,
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406 | BS3CG1DST_OZ_R8,
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407 | BS3CG1DST_OZ_R9,
|
---|
408 | BS3CG1DST_OZ_R10,
|
---|
409 | BS3CG1DST_OZ_R11,
|
---|
410 | BS3CG1DST_OZ_R12,
|
---|
411 | BS3CG1DST_OZ_R13,
|
---|
412 | BS3CG1DST_OZ_R14,
|
---|
413 | BS3CG1DST_OZ_R15,
|
---|
414 |
|
---|
415 | /* Control registers.*/
|
---|
416 | BS3CG1DST_CR0,
|
---|
417 | BS3CG1DST_CR4,
|
---|
418 |
|
---|
419 | /* FPU registers. */
|
---|
420 | BS3CG1DST_FPU_FIRST,
|
---|
421 | BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
|
---|
422 | BS3CG1DST_FSW,
|
---|
423 | BS3CG1DST_FTW,
|
---|
424 | BS3CG1DST_FOP,
|
---|
425 | BS3CG1DST_FPUIP,
|
---|
426 | BS3CG1DST_FPUCS,
|
---|
427 | BS3CG1DST_FPUDP,
|
---|
428 | BS3CG1DST_FPUDS,
|
---|
429 | BS3CG1DST_MXCSR,
|
---|
430 | BS3CG1DST_ST0,
|
---|
431 | BS3CG1DST_ST1,
|
---|
432 | BS3CG1DST_ST2,
|
---|
433 | BS3CG1DST_ST3,
|
---|
434 | BS3CG1DST_ST4,
|
---|
435 | BS3CG1DST_ST5,
|
---|
436 | BS3CG1DST_ST6,
|
---|
437 | BS3CG1DST_ST7,
|
---|
438 | /* MMX registers. */
|
---|
439 | BS3CG1DST_MM0,
|
---|
440 | BS3CG1DST_MM1,
|
---|
441 | BS3CG1DST_MM2,
|
---|
442 | BS3CG1DST_MM3,
|
---|
443 | BS3CG1DST_MM4,
|
---|
444 | BS3CG1DST_MM5,
|
---|
445 | BS3CG1DST_MM6,
|
---|
446 | BS3CG1DST_MM7,
|
---|
447 | /* SSE registers. */
|
---|
448 | BS3CG1DST_XMM0,
|
---|
449 | BS3CG1DST_XMM1,
|
---|
450 | BS3CG1DST_XMM2,
|
---|
451 | BS3CG1DST_XMM3,
|
---|
452 | BS3CG1DST_XMM4,
|
---|
453 | BS3CG1DST_XMM5,
|
---|
454 | BS3CG1DST_XMM6,
|
---|
455 | BS3CG1DST_XMM7,
|
---|
456 | BS3CG1DST_XMM8,
|
---|
457 | BS3CG1DST_XMM9,
|
---|
458 | BS3CG1DST_XMM10,
|
---|
459 | BS3CG1DST_XMM11,
|
---|
460 | BS3CG1DST_XMM12,
|
---|
461 | BS3CG1DST_XMM13,
|
---|
462 | BS3CG1DST_XMM14,
|
---|
463 | BS3CG1DST_XMM15,
|
---|
464 | BS3CG1DST_XMM0_LO,
|
---|
465 | BS3CG1DST_XMM1_LO,
|
---|
466 | BS3CG1DST_XMM2_LO,
|
---|
467 | BS3CG1DST_XMM3_LO,
|
---|
468 | BS3CG1DST_XMM4_LO,
|
---|
469 | BS3CG1DST_XMM5_LO,
|
---|
470 | BS3CG1DST_XMM6_LO,
|
---|
471 | BS3CG1DST_XMM7_LO,
|
---|
472 | BS3CG1DST_XMM8_LO,
|
---|
473 | BS3CG1DST_XMM9_LO,
|
---|
474 | BS3CG1DST_XMM10_LO,
|
---|
475 | BS3CG1DST_XMM11_LO,
|
---|
476 | BS3CG1DST_XMM12_LO,
|
---|
477 | BS3CG1DST_XMM13_LO,
|
---|
478 | BS3CG1DST_XMM14_LO,
|
---|
479 | BS3CG1DST_XMM15_LO,
|
---|
480 | BS3CG1DST_XMM0_HI,
|
---|
481 | BS3CG1DST_XMM1_HI,
|
---|
482 | BS3CG1DST_XMM2_HI,
|
---|
483 | BS3CG1DST_XMM3_HI,
|
---|
484 | BS3CG1DST_XMM4_HI,
|
---|
485 | BS3CG1DST_XMM5_HI,
|
---|
486 | BS3CG1DST_XMM6_HI,
|
---|
487 | BS3CG1DST_XMM7_HI,
|
---|
488 | BS3CG1DST_XMM8_HI,
|
---|
489 | BS3CG1DST_XMM9_HI,
|
---|
490 | BS3CG1DST_XMM10_HI,
|
---|
491 | BS3CG1DST_XMM11_HI,
|
---|
492 | BS3CG1DST_XMM12_HI,
|
---|
493 | BS3CG1DST_XMM13_HI,
|
---|
494 | BS3CG1DST_XMM14_HI,
|
---|
495 | BS3CG1DST_XMM15_HI,
|
---|
496 | BS3CG1DST_XMM0_LO_ZX,
|
---|
497 | BS3CG1DST_XMM1_LO_ZX,
|
---|
498 | BS3CG1DST_XMM2_LO_ZX,
|
---|
499 | BS3CG1DST_XMM3_LO_ZX,
|
---|
500 | BS3CG1DST_XMM4_LO_ZX,
|
---|
501 | BS3CG1DST_XMM5_LO_ZX,
|
---|
502 | BS3CG1DST_XMM6_LO_ZX,
|
---|
503 | BS3CG1DST_XMM7_LO_ZX,
|
---|
504 | BS3CG1DST_XMM8_LO_ZX,
|
---|
505 | BS3CG1DST_XMM9_LO_ZX,
|
---|
506 | BS3CG1DST_XMM10_LO_ZX,
|
---|
507 | BS3CG1DST_XMM11_LO_ZX,
|
---|
508 | BS3CG1DST_XMM12_LO_ZX,
|
---|
509 | BS3CG1DST_XMM13_LO_ZX,
|
---|
510 | BS3CG1DST_XMM14_LO_ZX,
|
---|
511 | BS3CG1DST_XMM15_LO_ZX,
|
---|
512 | BS3CG1DST_XMM0_DW0,
|
---|
513 | BS3CG1DST_XMM1_DW0,
|
---|
514 | BS3CG1DST_XMM2_DW0,
|
---|
515 | BS3CG1DST_XMM3_DW0,
|
---|
516 | BS3CG1DST_XMM4_DW0,
|
---|
517 | BS3CG1DST_XMM5_DW0,
|
---|
518 | BS3CG1DST_XMM6_DW0,
|
---|
519 | BS3CG1DST_XMM7_DW0,
|
---|
520 | BS3CG1DST_XMM8_DW0,
|
---|
521 | BS3CG1DST_XMM9_DW0,
|
---|
522 | BS3CG1DST_XMM10_DW0,
|
---|
523 | BS3CG1DST_XMM11_DW0,
|
---|
524 | BS3CG1DST_XMM12_DW0,
|
---|
525 | BS3CG1DST_XMM13_DW0,
|
---|
526 | BS3CG1DST_XMM14_DW0,
|
---|
527 | BS3CG1DST_XMM15_DW0,
|
---|
528 | /* AVX registers. */
|
---|
529 | BS3CG1DST_YMM0,
|
---|
530 | BS3CG1DST_YMM1,
|
---|
531 | BS3CG1DST_YMM2,
|
---|
532 | BS3CG1DST_YMM3,
|
---|
533 | BS3CG1DST_YMM4,
|
---|
534 | BS3CG1DST_YMM5,
|
---|
535 | BS3CG1DST_YMM6,
|
---|
536 | BS3CG1DST_YMM7,
|
---|
537 | BS3CG1DST_YMM8,
|
---|
538 | BS3CG1DST_YMM9,
|
---|
539 | BS3CG1DST_YMM10,
|
---|
540 | BS3CG1DST_YMM11,
|
---|
541 | BS3CG1DST_YMM12,
|
---|
542 | BS3CG1DST_YMM13,
|
---|
543 | BS3CG1DST_YMM14,
|
---|
544 | BS3CG1DST_YMM15,
|
---|
545 |
|
---|
546 | /* Special fields: */
|
---|
547 | BS3CG1DST_SPECIAL_START,
|
---|
548 | BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /**< Expected exception based on input or result. */
|
---|
549 |
|
---|
550 | BS3CG1DST_END
|
---|
551 | } BS3CG1DST;
|
---|
552 | AssertCompile(BS3CG1DST_END <= 256);
|
---|
553 |
|
---|
554 | /** @name Selector opcode definitions.
|
---|
555 | *
|
---|
556 | * Selector programs are very simple, they are zero or more predicate tests
|
---|
557 | * that are ANDed together. If a predicate test fails, the test is skipped.
|
---|
558 | *
|
---|
559 | * One instruction is encoded as byte, where the first bit indicates what kind
|
---|
560 | * of test and the 7 remaining bits indicates which predicate to check.
|
---|
561 | *
|
---|
562 | * @{ */
|
---|
563 | #define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /**< The operator part (put in lower bit to reduce switch value range). */
|
---|
564 | #define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /**< Check that the predicate is true. */
|
---|
565 | #define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /**< Check that the predicate is false. */
|
---|
566 | #define BS3CG1SEL_OP_PRED_SHIFT 1 /**< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. */
|
---|
567 | /** @} */
|
---|
568 |
|
---|
569 | /**
|
---|
570 | * Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
|
---|
571 | */
|
---|
572 | typedef enum BS3CG1PRED
|
---|
573 | {
|
---|
574 | BS3CG1PRED_INVALID = 0,
|
---|
575 |
|
---|
576 | /* Operand size. */
|
---|
577 | BS3CG1PRED_SIZE_O16,
|
---|
578 | BS3CG1PRED_SIZE_O32,
|
---|
579 | BS3CG1PRED_SIZE_O64,
|
---|
580 | /* Execution ring. */
|
---|
581 | BS3CG1PRED_RING_0,
|
---|
582 | BS3CG1PRED_RING_1,
|
---|
583 | BS3CG1PRED_RING_2,
|
---|
584 | BS3CG1PRED_RING_3,
|
---|
585 | BS3CG1PRED_RING_0_THRU_2,
|
---|
586 | BS3CG1PRED_RING_1_THRU_3,
|
---|
587 | /* Basic code mode. */
|
---|
588 | BS3CG1PRED_CODE_64BIT,
|
---|
589 | BS3CG1PRED_CODE_32BIT,
|
---|
590 | BS3CG1PRED_CODE_16BIT,
|
---|
591 | /* CPU modes. */
|
---|
592 | BS3CG1PRED_MODE_REAL,
|
---|
593 | BS3CG1PRED_MODE_PROT,
|
---|
594 | BS3CG1PRED_MODE_LONG,
|
---|
595 | BS3CG1PRED_MODE_V86,
|
---|
596 | BS3CG1PRED_MODE_SMM,
|
---|
597 | BS3CG1PRED_MODE_VMX,
|
---|
598 | BS3CG1PRED_MODE_SVM,
|
---|
599 | /* Paging on/off */
|
---|
600 | BS3CG1PRED_PAGING_ON,
|
---|
601 | BS3CG1PRED_PAGING_OFF,
|
---|
602 |
|
---|
603 | BS3CG1PRED_END
|
---|
604 | } BS3CG1PRED;
|
---|
605 |
|
---|
606 |
|
---|
607 | /** The test instructions (generated). */
|
---|
608 | extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
|
---|
609 | /** The number of test instructions (generated). */
|
---|
610 | extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
|
---|
611 | /** The mnemonics (generated).
|
---|
612 | * Variable length sequence of mnemonics that runs in parallel to
|
---|
613 | * g_aBs3Cg1Instructions. */
|
---|
614 | extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
|
---|
615 | /** The opcodes (generated).
|
---|
616 | * Variable length sequence of opcode bytes that runs in parallel to
|
---|
617 | * g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
|
---|
618 | extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
|
---|
619 | /** The operands (generated).
|
---|
620 | * Variable length sequence of opcode values (BS3CG1OP) that runs in
|
---|
621 | * parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
|
---|
622 | extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
|
---|
623 | /** The test data that BS3CG1INSTR.
|
---|
624 | * In order to simplify generating these, we use a byte array. */
|
---|
625 | extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
|
---|
626 |
|
---|
627 |
|
---|
628 | #endif
|
---|
629 |
|
---|