bs3-cpu-generated-1.h@ 66403

Last change on this file since 66403 was 66391, checked in by vboxsync, 8 years ago
IEM: Implemented stmxcsr Md (0f ae !11/3).
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1	/* $Id: bs3-cpu-generated-1.h 66391 2017-04-02 14:56:59Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wsd,
48	BS3CG1OP_Wps,
49	BS3CG1OP_Wpd,
50	BS3CG1OP_Wdq,
51	BS3CG1OP_WqZxReg,
52
53	BS3CG1OP_Gb,
54	BS3CG1OP_Gv,
55	BS3CG1OP_Uq,
56	BS3CG1OP_UqHi,
57	BS3CG1OP_Vss,
58	BS3CG1OP_Vsd,
59	BS3CG1OP_Vps,
60	BS3CG1OP_Vpd,
61	BS3CG1OP_Vq,
62	BS3CG1OP_Vdq,
63
64	BS3CG1OP_Ib,
65	BS3CG1OP_Iz,
66
67	BS3CG1OP_AL,
68	BS3CG1OP_rAX,
69
70	BS3CG1OP_Ma,
71	BS3CG1OP_MbRO,
72	BS3CG1OP_MdWO,
73	BS3CG1OP_Mq,
74
75	BS3CG1OP_END
76	} BS3CG1OP;
77	/** Pointer to a const operand enum. */
78	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
79
80
81	/**
82	* Instruction encoding format.
83	*
84	* This duplicates some of the info in the operand array, however it makes it
85	* easier to figure out encoding variations.
86	*/
87	typedef enum BS3CG1ENC
88	{
89	BS3CG1ENC_INVALID = 0,
90
91	BS3CG1ENC_MODRM_Eb_Gb,
92	BS3CG1ENC_MODRM_Ev_Gv,
93	BS3CG1ENC_MODRM_Wss_Vss,
94	BS3CG1ENC_MODRM_Wsd_Vsd,
95	BS3CG1ENC_MODRM_Wps_Vps,
96	BS3CG1ENC_MODRM_Wpd_Vpd,
97	BS3CG1ENC_MODRM_WqZxReg_Vq,
98
99	BS3CG1ENC_MODRM_Gb_Eb,
100	BS3CG1ENC_MODRM_Gv_Ev,
101	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
102	BS3CG1ENC_MODRM_Vq_UqHi,
103	BS3CG1ENC_MODRM_Vq_Mq,
104	BS3CG1ENC_MODRM_Vdq_Wdq,
105	BS3CG1ENC_MODRM_MbRO,
106	BS3CG1ENC_MODRM_MdWO,
107
108	BS3CG1ENC_FIXED,
109	BS3CG1ENC_FIXED_AL_Ib,
110	BS3CG1ENC_FIXED_rAX_Iz,
111
112	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
113	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
114
115	BS3CG1ENC_END
116	} BS3CG1ENC;
117
118
119	/**
120	* Prefix sensitivitiy kind.
121	*/
122	typedef enum BS3CG1PFXKIND
123	{
124	BS3CG1PFXKIND_INVALID = 0,
125
126	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
127	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
128	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
129	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
130
131	/** @todo more work to be done here... */
132	BS3CG1PFXKIND_MODRM,
133	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
134
135	BS3CG1PFXKIND_END
136	} BS3CG1PFXKIND;
137
138	/**
139	* CPU selection or CPU ID.
140	*/
141	typedef enum BS3CG1CPU
142	{
143	/** Works with an CPU. */
144	BS3CG1CPU_ANY = 0,
145	BS3CG1CPU_GE_80186,
146	BS3CG1CPU_GE_80286,
147	BS3CG1CPU_GE_80386,
148	BS3CG1CPU_GE_80486,
149	BS3CG1CPU_GE_Pentium,
150
151	BS3CG1CPU_SSE,
152	BS3CG1CPU_SSE2,
153	BS3CG1CPU_SSE3,
154	BS3CG1CPU_AVX,
155	BS3CG1CPU_AVX2,
156	BS3CG1CPU_CLFSH,
157	BS3CG1CPU_CLFLUSHOPT,
158
159	BS3CG1CPU_END
160	} BS3CG1CPU;
161
162
163	/**
164	* SSE & AVX exception types.
165	*/
166	typedef enum BS3CG1XCPTTYPE
167	{
168	BS3CG1XCPTTYPE_NONE = 0,
169	/* SSE: */
170	BS3CG1XCPTTYPE_1,
171	BS3CG1XCPTTYPE_2,
172	BS3CG1XCPTTYPE_3,
173	BS3CG1XCPTTYPE_4,
174	BS3CG1XCPTTYPE_4UA,
175	BS3CG1XCPTTYPE_5,
176	BS3CG1XCPTTYPE_6,
177	BS3CG1XCPTTYPE_7,
178	BS3CG1XCPTTYPE_8,
179	BS3CG1XCPTTYPE_11,
180	BS3CG1XCPTTYPE_12,
181	/* EVEX: */
182	BS3CG1XCPTTYPE_E1,
183	BS3CG1XCPTTYPE_E1NF,
184	BS3CG1XCPTTYPE_E2,
185	BS3CG1XCPTTYPE_E3,
186	BS3CG1XCPTTYPE_E3NF,
187	BS3CG1XCPTTYPE_E4,
188	BS3CG1XCPTTYPE_E4NF,
189	BS3CG1XCPTTYPE_E5,
190	BS3CG1XCPTTYPE_E5NF,
191	BS3CG1XCPTTYPE_E6,
192	BS3CG1XCPTTYPE_E6NF,
193	BS3CG1XCPTTYPE_E7NF,
194	BS3CG1XCPTTYPE_E9,
195	BS3CG1XCPTTYPE_E9NF,
196	BS3CG1XCPTTYPE_E10,
197	BS3CG1XCPTTYPE_E11,
198	BS3CG1XCPTTYPE_E12,
199	BS3CG1XCPTTYPE_E12NF,
200	BS3CG1XCPTTYPE_END
201	} BS3CG1XCPTTYPE;
202	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
203
204
205	/**
206	* Generated instruction info.
207	*/
208	typedef struct BS3CG1INSTR
209	{
210	/** The opcode size. */
211	uint32_t cbOpcodes : 2;
212	/** The number of operands. */
213	uint32_t cOperands : 2;
214	/** The length of the mnemonic. */
215	uint32_t cchMnemonic : 4;
216	/** Whether to advance the mnemonic array pointer. */
217	uint32_t fAdvanceMnemonic : 1;
218	/** Offset into g_abBs3Cg1Tests of the first test. */
219	uint32_t offTests : 23;
220	/** BS3CG1ENC values. */
221	uint32_t enmEncoding : 10;
222	/** BS3CG1PFXKIND values. */
223	uint32_t enmPrefixKind : 4;
224	/** CPU test / CPU ID bit test (BS3CG1CPU). */
225	uint32_t enmCpuTest : 6;
226	/** Exception type (BS3CG1XCPTTYPE) */
227	uint32_t enmXcptType : 5;
228	/** Currently unused bits. */
229	uint32_t uUnused : 6;
230	/** BS3CG1INSTR_F_XXX. */
231	uint32_t fFlags;
232	} BS3CG1INSTR;
233	AssertCompileSize(BS3CG1INSTR, 12);
234	/** Pointer to a const instruction. */
235	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
236
237
238	/** @name BS3CG1INSTR_F_XXX
239	* @{ */
240	/** Defaults to SS rather than DS. */
241	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
242	/** Invalid instruction in 64-bit mode. */
243	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
244	/** Unused instruction. */
245	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
246	/** Invalid instruction. */
247	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
248	/** @} */
249
250
251	/**
252	* Test header.
253	*/
254	typedef struct BS3CG1TESTHDR
255	{
256	/** The size of the selector program in bytes.
257	* This is also the offset of the input context modification program. */
258	uint32_t cbSelector : 8;
259	/** The size of the input context modification program in bytes.
260	* This immediately follows the selector program. */
261	uint32_t cbInput : 12;
262	/** The size of the output context modification program in bytes.
263	* This immediately follows the input context modification program. The
264	* program takes the result of the input program as starting point. */
265	uint32_t cbOutput : 11;
266	/** Indicates whether this is the last test or not. */
267	uint32_t fLast : 1;
268	} BS3CG1TESTHDR;
269	AssertCompileSize(BS3CG1TESTHDR, 4);
270	/** Pointer to a const test header. */
271	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
272
273	/** @name Opcode format for the BS3CG1 context modifier.
274	*
275	* Used by both the input and output context programs.
276	*
277	* The most common operations are encoded as a single byte opcode followed by
278	* one or more immediate bytes with data.
279	*
280	* @{ */
281	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
282	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
283	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
284	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
285	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
286	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
287	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
288	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
289	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
290
291	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
292	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
293	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
294	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
295	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
296
297	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
298
299	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
300	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
301	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
302	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
303	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
304	/** @} */
305
306	/**
307	* Escaped destination values
308	*
309	* These are just uppercased versions of TestInOut.kdFields, where dots are
310	* replaced by underscores.
311	*/
312	typedef enum BS3CG1DST
313	{
314	BS3CG1DST_INVALID = 0,
315	/* Operands. */
316	BS3CG1DST_OP1,
317	BS3CG1DST_OP2,
318	BS3CG1DST_OP3,
319	BS3CG1DST_OP4,
320	/* Flags. */
321	BS3CG1DST_EFL,
322	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
323	/* 8-bit GPRs. */
324	BS3CG1DST_AL,
325	BS3CG1DST_CL,
326	BS3CG1DST_DL,
327	BS3CG1DST_BL,
328	BS3CG1DST_AH,
329	BS3CG1DST_CH,
330	BS3CG1DST_DH,
331	BS3CG1DST_BH,
332	BS3CG1DST_SPL,
333	BS3CG1DST_BPL,
334	BS3CG1DST_SIL,
335	BS3CG1DST_DIL,
336	BS3CG1DST_R8L,
337	BS3CG1DST_R9L,
338	BS3CG1DST_R10L,
339	BS3CG1DST_R11L,
340	BS3CG1DST_R12L,
341	BS3CG1DST_R13L,
342	BS3CG1DST_R14L,
343	BS3CG1DST_R15L,
344	/* 16-bit GPRs. */
345	BS3CG1DST_AX,
346	BS3CG1DST_CX,
347	BS3CG1DST_DX,
348	BS3CG1DST_BX,
349	BS3CG1DST_SP,
350	BS3CG1DST_BP,
351	BS3CG1DST_SI,
352	BS3CG1DST_DI,
353	BS3CG1DST_R8W,
354	BS3CG1DST_R9W,
355	BS3CG1DST_R10W,
356	BS3CG1DST_R11W,
357	BS3CG1DST_R12W,
358	BS3CG1DST_R13W,
359	BS3CG1DST_R14W,
360	BS3CG1DST_R15W,
361	/* 32-bit GPRs. */
362	BS3CG1DST_EAX,
363	BS3CG1DST_ECX,
364	BS3CG1DST_EDX,
365	BS3CG1DST_EBX,
366	BS3CG1DST_ESP,
367	BS3CG1DST_EBP,
368	BS3CG1DST_ESI,
369	BS3CG1DST_EDI,
370	BS3CG1DST_R8D,
371	BS3CG1DST_R9D,
372	BS3CG1DST_R10D,
373	BS3CG1DST_R11D,
374	BS3CG1DST_R12D,
375	BS3CG1DST_R13D,
376	BS3CG1DST_R14D,
377	BS3CG1DST_R15D,
378	/* 64-bit GPRs. */
379	BS3CG1DST_RAX,
380	BS3CG1DST_RCX,
381	BS3CG1DST_RDX,
382	BS3CG1DST_RBX,
383	BS3CG1DST_RSP,
384	BS3CG1DST_RBP,
385	BS3CG1DST_RSI,
386	BS3CG1DST_RDI,
387	BS3CG1DST_R8,
388	BS3CG1DST_R9,
389	BS3CG1DST_R10,
390	BS3CG1DST_R11,
391	BS3CG1DST_R12,
392	BS3CG1DST_R13,
393	BS3CG1DST_R14,
394	BS3CG1DST_R15,
395	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
396	BS3CG1DST_OZ_RAX,
397	BS3CG1DST_OZ_RCX,
398	BS3CG1DST_OZ_RDX,
399	BS3CG1DST_OZ_RBX,
400	BS3CG1DST_OZ_RSP,
401	BS3CG1DST_OZ_RBP,
402	BS3CG1DST_OZ_RSI,
403	BS3CG1DST_OZ_RDI,
404	BS3CG1DST_OZ_R8,
405	BS3CG1DST_OZ_R9,
406	BS3CG1DST_OZ_R10,
407	BS3CG1DST_OZ_R11,
408	BS3CG1DST_OZ_R12,
409	BS3CG1DST_OZ_R13,
410	BS3CG1DST_OZ_R14,
411	BS3CG1DST_OZ_R15,
412
413	/* FPU registers. */
414	BS3CG1DST_FPU_FIRST,
415	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
416	BS3CG1DST_FSW,
417	BS3CG1DST_FTW,
418	BS3CG1DST_FOP,
419	BS3CG1DST_FPUIP,
420	BS3CG1DST_FPUCS,
421	BS3CG1DST_FPUDP,
422	BS3CG1DST_FPUDS,
423	BS3CG1DST_MXCSR,
424	BS3CG1DST_ST0,
425	BS3CG1DST_ST1,
426	BS3CG1DST_ST2,
427	BS3CG1DST_ST3,
428	BS3CG1DST_ST4,
429	BS3CG1DST_ST5,
430	BS3CG1DST_ST6,
431	BS3CG1DST_ST7,
432	/* MMX registers. */
433	BS3CG1DST_MM0,
434	BS3CG1DST_MM1,
435	BS3CG1DST_MM2,
436	BS3CG1DST_MM3,
437	BS3CG1DST_MM4,
438	BS3CG1DST_MM5,
439	BS3CG1DST_MM6,
440	BS3CG1DST_MM7,
441	/* SSE registers. */
442	BS3CG1DST_XMM0,
443	BS3CG1DST_XMM1,
444	BS3CG1DST_XMM2,
445	BS3CG1DST_XMM3,
446	BS3CG1DST_XMM4,
447	BS3CG1DST_XMM5,
448	BS3CG1DST_XMM6,
449	BS3CG1DST_XMM7,
450	BS3CG1DST_XMM8,
451	BS3CG1DST_XMM9,
452	BS3CG1DST_XMM10,
453	BS3CG1DST_XMM11,
454	BS3CG1DST_XMM12,
455	BS3CG1DST_XMM13,
456	BS3CG1DST_XMM14,
457	BS3CG1DST_XMM15,
458	BS3CG1DST_XMM0_LO,
459	BS3CG1DST_XMM1_LO,
460	BS3CG1DST_XMM2_LO,
461	BS3CG1DST_XMM3_LO,
462	BS3CG1DST_XMM4_LO,
463	BS3CG1DST_XMM5_LO,
464	BS3CG1DST_XMM6_LO,
465	BS3CG1DST_XMM7_LO,
466	BS3CG1DST_XMM8_LO,
467	BS3CG1DST_XMM9_LO,
468	BS3CG1DST_XMM10_LO,
469	BS3CG1DST_XMM11_LO,
470	BS3CG1DST_XMM12_LO,
471	BS3CG1DST_XMM13_LO,
472	BS3CG1DST_XMM14_LO,
473	BS3CG1DST_XMM15_LO,
474	BS3CG1DST_XMM0_HI,
475	BS3CG1DST_XMM1_HI,
476	BS3CG1DST_XMM2_HI,
477	BS3CG1DST_XMM3_HI,
478	BS3CG1DST_XMM4_HI,
479	BS3CG1DST_XMM5_HI,
480	BS3CG1DST_XMM6_HI,
481	BS3CG1DST_XMM7_HI,
482	BS3CG1DST_XMM8_HI,
483	BS3CG1DST_XMM9_HI,
484	BS3CG1DST_XMM10_HI,
485	BS3CG1DST_XMM11_HI,
486	BS3CG1DST_XMM12_HI,
487	BS3CG1DST_XMM13_HI,
488	BS3CG1DST_XMM14_HI,
489	BS3CG1DST_XMM15_HI,
490	BS3CG1DST_XMM0_LO_ZX,
491	BS3CG1DST_XMM1_LO_ZX,
492	BS3CG1DST_XMM2_LO_ZX,
493	BS3CG1DST_XMM3_LO_ZX,
494	BS3CG1DST_XMM4_LO_ZX,
495	BS3CG1DST_XMM5_LO_ZX,
496	BS3CG1DST_XMM6_LO_ZX,
497	BS3CG1DST_XMM7_LO_ZX,
498	BS3CG1DST_XMM8_LO_ZX,
499	BS3CG1DST_XMM9_LO_ZX,
500	BS3CG1DST_XMM10_LO_ZX,
501	BS3CG1DST_XMM11_LO_ZX,
502	BS3CG1DST_XMM12_LO_ZX,
503	BS3CG1DST_XMM13_LO_ZX,
504	BS3CG1DST_XMM14_LO_ZX,
505	BS3CG1DST_XMM15_LO_ZX,
506	BS3CG1DST_XMM0_DW0,
507	BS3CG1DST_XMM1_DW0,
508	BS3CG1DST_XMM2_DW0,
509	BS3CG1DST_XMM3_DW0,
510	BS3CG1DST_XMM4_DW0,
511	BS3CG1DST_XMM5_DW0,
512	BS3CG1DST_XMM6_DW0,
513	BS3CG1DST_XMM7_DW0,
514	BS3CG1DST_XMM8_DW0,
515	BS3CG1DST_XMM9_DW0,
516	BS3CG1DST_XMM10_DW0,
517	BS3CG1DST_XMM11_DW0,
518	BS3CG1DST_XMM12_DW0,
519	BS3CG1DST_XMM13_DW0,
520	BS3CG1DST_XMM14_DW0,
521	BS3CG1DST_XMM15_DW0,
522	/* AVX registers. */
523	BS3CG1DST_YMM0,
524	BS3CG1DST_YMM1,
525	BS3CG1DST_YMM2,
526	BS3CG1DST_YMM3,
527	BS3CG1DST_YMM4,
528	BS3CG1DST_YMM5,
529	BS3CG1DST_YMM6,
530	BS3CG1DST_YMM7,
531	BS3CG1DST_YMM8,
532	BS3CG1DST_YMM9,
533	BS3CG1DST_YMM10,
534	BS3CG1DST_YMM11,
535	BS3CG1DST_YMM12,
536	BS3CG1DST_YMM13,
537	BS3CG1DST_YMM14,
538	BS3CG1DST_YMM15,
539
540	/* Special fields: */
541	BS3CG1DST_SPECIAL_START,
542	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
543
544	BS3CG1DST_END
545	} BS3CG1DST;
546	AssertCompile(BS3CG1DST_END <= 256);
547
548	/** @name Selector opcode definitions.
549	*
550	* Selector programs are very simple, they are zero or more predicate tests
551	* that are ANDed together. If a predicate test fails, the test is skipped.
552	*
553	* One instruction is encoded as byte, where the first bit indicates what kind
554	* of test and the 7 remaining bits indicates which predicate to check.
555	*
556	* @{ */
557	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
558	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
559	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
560	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
561	/** @} */
562
563	/**
564	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
565	*/
566	typedef enum BS3CG1PRED
567	{
568	BS3CG1PRED_INVALID = 0,
569
570	/* Operand size. */
571	BS3CG1PRED_SIZE_O16,
572	BS3CG1PRED_SIZE_O32,
573	BS3CG1PRED_SIZE_O64,
574	/* Execution ring. */
575	BS3CG1PRED_RING_0,
576	BS3CG1PRED_RING_1,
577	BS3CG1PRED_RING_2,
578	BS3CG1PRED_RING_3,
579	BS3CG1PRED_RING_0_THRU_2,
580	BS3CG1PRED_RING_1_THRU_3,
581	/* Basic code mode. */
582	BS3CG1PRED_CODE_64BIT,
583	BS3CG1PRED_CODE_32BIT,
584	BS3CG1PRED_CODE_16BIT,
585	/* CPU modes. */
586	BS3CG1PRED_MODE_REAL,
587	BS3CG1PRED_MODE_PROT,
588	BS3CG1PRED_MODE_LONG,
589	BS3CG1PRED_MODE_V86,
590	BS3CG1PRED_MODE_SMM,
591	BS3CG1PRED_MODE_VMX,
592	BS3CG1PRED_MODE_SVM,
593	/* Paging on/off */
594	BS3CG1PRED_PAGING_ON,
595	BS3CG1PRED_PAGING_OFF,
596
597	BS3CG1PRED_END
598	} BS3CG1PRED;
599
600
601	/** The test instructions (generated). */
602	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
603	/** The number of test instructions (generated). */
604	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
605	/** The mnemonics (generated).
606	* Variable length sequence of mnemonics that runs in parallel to
607	* g_aBs3Cg1Instructions. */
608	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
609	/** The opcodes (generated).
610	* Variable length sequence of opcode bytes that runs in parallel to
611	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
612	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
613	/** The operands (generated).
614	* Variable length sequence of opcode values (BS3CG1OP) that runs in
615	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
616	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
617	/** The test data that BS3CG1INSTR.
618	* In order to simplify generating these, we use a byte array. */
619	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
620
621
622	#endif
623

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66403

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