bs3-cpu-basic-2-template.c@ 60422

Last change on this file since 60422 was 60321, checked in by vboxsync, 9 years ago
bs3kit: 386 fixes.
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1	/* $Id: bs3-cpu-basic-2-template.c 60321 2016-04-05 00:33:14Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-basic-2, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifdef BS3_INSTANTIATING_MODE
29
30	/*********************************************************************************************************************************
31	* Header Files *
32	*********************************************************************************************************************************/
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35
36
37	/*********************************************************************************************************************************
38	* Defined Constants And Macros *
39	*********************************************************************************************************************************/
40	# undef MyBs3Idt
41	# undef MY_SYS_SEL_R0_CS
42	# undef MY_SYS_SEL_R0_CS_CNF
43	# undef MY_SYS_SEL_R0_DS
44	# undef MY_SYS_SEL_R0_SS
45	# if BS3_MODE_IS_16BIT_SYS(TMPL_MODE)
46	# define MyBs3Idt Bs3Idt16
47	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS16
48	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS16_CNF
49	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS16
50	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_SS16
51	# elif BS3_MODE_IS_32BIT_SYS(TMPL_MODE)
52	# define MyBs3Idt Bs3Idt32
53	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS32
54	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS32_CNF
55	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS32
56	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_SS32
57	# elif BS3_MODE_IS_64BIT_SYS(TMPL_MODE)
58	# define MyBs3Idt Bs3Idt64
59	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS64
60	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS64_CNF
61	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS64
62	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_DS64
63	# else
64	# error "TMPL_MODE"
65	# endif
66	#undef CHECK_MEMBER
67	#define CHECK_MEMBER(a_szName, a_szFmt, a_Actual, a_Expected) \
68	do \
69	{ \
70	if ((a_Actual) == (a_Expected)) { /* likely */ } \
71	else bs3CpuBasic2_FailedF(a_szName "=" a_szFmt " expected " a_szFmt, (a_Actual), (a_Expected)); \
72	} while (0)
73
74
75	/*********************************************************************************************************************************
76	* Structures and Typedefs *
77	*********************************************************************************************************************************/
78	#ifndef DONE_MODE_TYPES
79	#define DONE_MODE_TYPES
80	typedef struct BS3CB2INVLDESCTYPE
81	{
82	uint8_t u4Type;
83	uint8_t u1DescType;
84	} BS3CB2INVLDESCTYPE;
85	#endif
86
87
88	/*********************************************************************************************************************************
89	* External Symbols *
90	*********************************************************************************************************************************/
91	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int80)(void);
92	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int81)(void);
93	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int82)(void);
94	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int83)(void);
95	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_ud2)(void);
96	#ifndef DOXYGEN_RUNNING
97	# define g_bs3CpuBasic2_ud2_FlatAddr BS3_DATA_NM(g_bs3CpuBasic2_ud2_FlatAddr)
98	#endif
99	extern uint32_t g_bs3CpuBasic2_ud2_FlatAddr;
100
101
102	/*********************************************************************************************************************************
103	* Global Variables *
104	*********************************************************************************************************************************/
105	#if TMPL_MODE == BS3_MODE_RM \|\| TMPL_MODE == BS3_MODE_PE16_32 \|\| TMPL_MODE == BS3_MODE_LM64
106	#define g_pszTestMode BS3_CMN_NM(g_pszTestMode)
107	static const char BS3_FAR g_pszTestMode = (const char )1;
108	#define g_bTestMode BS3_CMN_NM(g_bTestMode)
109	static uint8_t g_bTestMode = 1;
110	#define g_f16BitSys BS3_CMN_NM(g_f16BitSys)
111	static bool g_f16BitSys = 1;
112
113	/** Table containing invalid CS selector types. */
114	static const BS3CB2INVLDESCTYPE g_aInvalidCsTypes[] =
115	{
116	{ X86_SEL_TYPE_RO, 1 },
117	{ X86_SEL_TYPE_RO_ACC, 1 },
118	{ X86_SEL_TYPE_RW, 1 },
119	{ X86_SEL_TYPE_RW_ACC, 1 },
120	{ X86_SEL_TYPE_RO_DOWN, 1 },
121	{ X86_SEL_TYPE_RO_DOWN_ACC, 1 },
122	{ X86_SEL_TYPE_RW_DOWN, 1 },
123	{ X86_SEL_TYPE_RW_DOWN_ACC, 1 },
124	{ 0, 0 },
125	{ 1, 0 },
126	{ 2, 0 },
127	{ 3, 0 },
128	{ 4, 0 },
129	{ 5, 0 },
130	{ 6, 0 },
131	{ 7, 0 },
132	{ 8, 0 },
133	{ 9, 0 },
134	{ 10, 0 },
135	{ 11, 0 },
136	{ 12, 0 },
137	{ 13, 0 },
138	{ 14, 0 },
139	{ 15, 0 },
140	};
141
142	/** Table containing invalid SS selector types. */
143	static const BS3CB2INVLDESCTYPE g_aInvalidSsTypes[] =
144	{
145	{ X86_SEL_TYPE_EO, 1 },
146	{ X86_SEL_TYPE_EO_ACC, 1 },
147	{ X86_SEL_TYPE_ER, 1 },
148	{ X86_SEL_TYPE_ER_ACC, 1 },
149	{ X86_SEL_TYPE_EO_CONF, 1 },
150	{ X86_SEL_TYPE_EO_CONF_ACC, 1 },
151	{ X86_SEL_TYPE_ER_CONF, 1 },
152	{ X86_SEL_TYPE_ER_CONF_ACC, 1 },
153	{ 0, 0 },
154	{ 1, 0 },
155	{ 2, 0 },
156	{ 3, 0 },
157	{ 4, 0 },
158	{ 5, 0 },
159	{ 6, 0 },
160	{ 7, 0 },
161	{ 8, 0 },
162	{ 9, 0 },
163	{ 10, 0 },
164	{ 11, 0 },
165	{ 12, 0 },
166	{ 13, 0 },
167	{ 14, 0 },
168	{ 15, 0 },
169	};
170
171	#endif
172
173	#if TMPL_MODE == BS3_MODE_RM \|\| TMPL_MODE == BS3_MODE_PE16_32 \|\| TMPL_MODE == BS3_MODE_LM64
174
175	/**
176	* Wrapper around Bs3TestFailedF that prefixes the error with g_usBs3TestStep
177	* and g_pszTestMode.
178	*/
179	#define bs3CpuBasic2_FailedF BS3_CMN_NM(bs3CpuBasic2_FailedF)
180	void bs3CpuBasic2_FailedF(const char *pszFormat, ...)
181	{
182	va_list va;
183
184	char szTmp[168];
185	va_start(va, pszFormat);
186	Bs3StrPrintfV(szTmp, sizeof(szTmp), pszFormat, va);
187	va_end(va);
188
189	Bs3TestFailedF("%u - %s: %s", g_usBs3TestStep, g_pszTestMode, szTmp);
190	}
191
192
193	/**
194	* Compares trap stuff.
195	*/
196	#define bs3CpuBasic2_CompareIntCtx1 BS3_CMN_NM(bs3CpuBasic2_CompareIntCtx1)
197	void bs3CpuBasic2_CompareIntCtx1(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint8_t bXcpt)
198	{
199	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
200	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
201	CHECK_MEMBER("bErrCd", "%#06RX64", pTrapCtx->uErrCd, 0);
202	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 2 /int xx/, 0 /cbSpAdjust/, 0 /fExtraEfl/, g_pszTestMode, g_usBs3TestStep);
203	if (Bs3TestSubErrorCount() != cErrorsBefore)
204	{
205	Bs3TrapPrintFrame(pTrapCtx);
206	#if 1
207	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
208	Bs3TestPrintf("Halting in CompareTrapCtx1: bXcpt=%#x\n", bXcpt);
209	ASMHalt();
210	#endif
211	}
212	}
213
214
215	/**
216	* Compares trap stuff.
217	*/
218	#define bs3CpuBasic2_CompareTrapCtx2 BS3_CMN_NM(bs3CpuBasic2_CompareTrapCtx2)
219	void bs3CpuBasic2_CompareTrapCtx2(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t cbIpAdjust, uint8_t bXcpt,
220	uint16_t uHandlerCs)
221	{
222	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
223	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
224	CHECK_MEMBER("bErrCd", "%#06RX64", pTrapCtx->uErrCd, 0);
225	CHECK_MEMBER("uHandlerCs", "%#06x", pTrapCtx->uHandlerCs, uHandlerCs);
226	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, cbIpAdjust, 0 /cbSpAdjust/, 0 /fExtraEfl/, g_pszTestMode, g_usBs3TestStep);
227	if (Bs3TestSubErrorCount() != cErrorsBefore)
228	{
229	Bs3TrapPrintFrame(pTrapCtx);
230	#if 1
231	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
232	Bs3TestPrintf("Halting in CompareTrapCtx2: bXcpt=%#x\n", bXcpt);
233	ASMHalt();
234	#endif
235	}
236	}
237
238	/**
239	* Compares a CPU trap.
240	*/
241	#define bs3CpuBasic2_CompareCpuTrapCtx BS3_CMN_NM(bs3CpuBasic2_CompareCpuTrapCtx)
242	BS3_DECL(void) bs3CpuBasic2_CompareCpuTrapCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, uint8_t bXcpt,
243	bool f486ResumeFlagHint)
244	{
245	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
246	uint32_t fExtraEfl;
247
248	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
249	CHECK_MEMBER("bErrCd", "%#06RX16", (uint16_t)pTrapCtx->uErrCd, (uint16_t)uErrCd); /* 486 only writes a word */
250
251	fExtraEfl = X86_EFL_RF;
252	if ( g_f16BitSys
253	\|\| ( !f486ResumeFlagHint
254	&& (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) <= BS3CPU_80486 ) )
255	fExtraEfl = 0;
256	else
257	fExtraEfl = X86_EFL_RF;
258	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 0 /cbIpAdjust/, 0 /cbSpAdjust/, fExtraEfl, g_pszTestMode, g_usBs3TestStep);
259	if (Bs3TestSubErrorCount() != cErrorsBefore)
260	{
261	Bs3TrapPrintFrame(pTrapCtx);
262	#if 1
263	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
264	Bs3TestPrintf("Halting: bXcpt=%#x uErrCd=%#x\n", bXcpt, uErrCd);
265	ASMHalt();
266	#endif
267	}
268	}
269
270
271	/**
272	* Compares \#GP trap.
273	*/
274	#define bs3CpuBasic2_CompareGpCtx BS3_CMN_NM(bs3CpuBasic2_CompareGpCtx)
275	void bs3CpuBasic2_CompareGpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
276	{
277	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_GP, true /f486ResumeFlagHint/);
278	}
279
280	/**
281	* Compares \#NP trap.
282	*/
283	#define bs3CpuBasic2_CompareNpCtx BS3_CMN_NM(bs3CpuBasic2_CompareNpCtx)
284	void bs3CpuBasic2_CompareNpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
285	{
286	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_NP, true /f486ResumeFlagHint/);
287	}
288
289	/**
290	* Compares \#SS trap.
291	*/
292	#define bs3CpuBasic2_CompareSsCtx BS3_CMN_NM(bs3CpuBasic2_CompareSsCtx)
293	void bs3CpuBasic2_CompareSsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, bool f486ResumeFlagHint)
294	{
295	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_SS, f486ResumeFlagHint);
296	}
297
298	/**
299	* Compares \#TS trap.
300	*/
301	#define bs3CpuBasic2_CompareTsCtx BS3_CMN_NM(bs3CpuBasic2_CompareTsCtx)
302	void bs3CpuBasic2_CompareTsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
303	{
304	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_TS, false /f486ResumeFlagHint/);
305	}
306
307	/**
308	* Compares \#PF trap.
309	*/
310	#define bs3CpuBasic2_ComparePfCtx BS3_CMN_NM(bs3CpuBasic2_ComparePfCtx)
311	void bs3CpuBasic2_ComparePfCtx(PCBS3TRAPFRAME pTrapCtx, PBS3REGCTX pStartCtx, uint16_t uErrCd, uint64_t uCr2Expected)
312	{
313	uint64_t const uCr2Saved = pStartCtx->cr2.u;
314	pStartCtx->cr2.u = uCr2Expected;
315	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_PF, true /f486ResumeFlagHint/);
316	pStartCtx->cr2.u = uCr2Saved;
317	}
318
319	/**
320	* Compares \#UD trap.
321	*/
322	#define bs3CpuBasic2_CompareUdCtx BS3_CMN_NM(bs3CpuBasic2_CompareUdCtx)
323	void bs3CpuBasic2_CompareUdCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx)
324	{
325	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /no error code/, X86_XCPT_UD, true /f486ResumeFlagHint/);
326	}
327
328
329	#define bs3CpuBasic2_RaiseXcpt1Common BS3_CMN_NM(bs3CpuBasic2_RaiseXcpt1Common)
330	static void bs3CpuBasic2_RaiseXcpt1Common(bool const g_f16BitSys,
331	uint16_t const uSysR0Cs, uint16_t const uSysR0CsConf, uint16_t const uSysR0Ss,
332	PX86DESC const paIdt, unsigned const cIdteShift)
333	{
334	BS3TRAPFRAME TrapCtx;
335	BS3REGCTX Ctx80;
336	BS3REGCTX Ctx81;
337	BS3REGCTX Ctx82;
338	BS3REGCTX Ctx83;
339	BS3REGCTX CtxTmp;
340	BS3REGCTX CtxTmp2;
341	PBS3REGCTX apCtx8x[4];
342	unsigned iCtx;
343	unsigned iRing;
344	unsigned iDpl;
345	unsigned iRpl;
346	unsigned i, j, k;
347	uint32_t uExpected;
348	bool const f486Plus = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486;
349	# if TMPL_BITS == 16
350	bool const f386Plus = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386;
351	# else
352	bool const f386Plus = true;
353	int rc;
354	uint8_t *pbIdtCopyAlloc;
355	PX86DESC pIdtCopy;
356	const unsigned cbIdte = 1 << (3 + cIdteShift);
357	RTCCUINTXREG uCr0Saved = ASMGetCR0();
358	RTGDTR GdtrSaved;
359	# endif
360	RTIDTR IdtrSaved;
361	RTIDTR Idtr;
362
363	ASMGetIDTR(&IdtrSaved);
364	# if TMPL_BITS != 16
365	ASMGetGDTR(&GdtrSaved);
366	# endif
367
368	/* make sure they're allocated */
369	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
370	Bs3MemZero(&Ctx80, sizeof(Ctx80));
371	Bs3MemZero(&Ctx81, sizeof(Ctx81));
372	Bs3MemZero(&Ctx82, sizeof(Ctx82));
373	Bs3MemZero(&Ctx83, sizeof(Ctx83));
374	Bs3MemZero(&CtxTmp, sizeof(CtxTmp));
375	Bs3MemZero(&CtxTmp2, sizeof(CtxTmp2));
376
377	/* Context array. */
378	apCtx8x[0] = &Ctx80;
379	apCtx8x[1] = &Ctx81;
380	apCtx8x[2] = &Ctx82;
381	apCtx8x[3] = &Ctx83;
382
383	# if TMPL_BITS != 16
384	/* Allocate memory for playing around with the IDT. */
385	pbIdtCopyAlloc = NULL;
386	if (BS3_MODE_IS_PAGED(g_bTestMode))
387	pbIdtCopyAlloc = Bs3MemAlloc(BS3MEMKIND_FLAT32, 12*_1K);
388	# endif
389
390	/*
391	* IDT entry 80 thru 83 are assigned DPLs according to the number.
392	* (We'll be useing more, but this'll do for now.)
393	*/
394	paIdt[0x80 << cIdteShift].Gate.u2Dpl = 0;
395	paIdt[0x81 << cIdteShift].Gate.u2Dpl = 1;
396	paIdt[0x82 << cIdteShift].Gate.u2Dpl = 2;
397	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 3;
398
399	Bs3RegCtxSave(&Ctx80);
400	Ctx80.rsp.u -= 0x300;
401	Ctx80.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int80));
402	# if TMPL_BITS == 32
403	g_uBs3TrapEipHint = Ctx80.rip.u32;
404	# endif
405	Bs3MemCpy(&Ctx81, &Ctx80, sizeof(Ctx80));
406	Ctx81.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int81));
407	Bs3MemCpy(&Ctx82, &Ctx80, sizeof(Ctx80));
408	Ctx82.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int82));
409	Bs3MemCpy(&Ctx83, &Ctx80, sizeof(Ctx80));
410	Ctx83.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int83));
411
412	/*
413	* Check that all the above gates work from ring-0.
414	*/
415	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
416	{
417	g_usBs3TestStep = iCtx;
418	# if TMPL_BITS == 32
419	g_uBs3TrapEipHint = apCtx8x[iCtx]->rip.u32;
420	# endif
421	Bs3TrapSetJmpAndRestore(apCtx8x[iCtx], &TrapCtx);
422	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, apCtx8x[iCtx], 0x80+iCtx /bXcpt/);
423	}
424
425	/*
426	* Check that the gate DPL checks works.
427	*/
428	g_usBs3TestStep = 100;
429	for (iRing = 0; iRing <= 3; iRing++)
430	{
431	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
432	{
433	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
434	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
435	# if TMPL_BITS == 32
436	g_uBs3TrapEipHint = CtxTmp.rip.u32;
437	# endif
438	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
439	if (iCtx < iRing)
440	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
441	else
442	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
443	g_usBs3TestStep++;
444	}
445	}
446
447	/*
448	* Modify the gate CS value and run the handler at a different CPL.
449	* Throw RPL variations into the mix (completely ignored) together
450	* with gate presence.
451	* 1. CPL <= GATE.DPL
452	* 2. GATE.P
453	* 3. GATE.CS.DPL <= CPL (non-conforming segments)
454	*/
455	g_usBs3TestStep = 1000;
456	for (i = 0; i <= 3; i++)
457	{
458	for (iRing = 0; iRing <= 3; iRing++)
459	{
460	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
461	{
462	# if TMPL_BITS == 32
463	g_uBs3TrapEipHint = apCtx8x[iCtx]->rip.u32;
464	# endif
465	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
466	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
467
468	for (j = 0; j <= 3; j++)
469	{
470	uint16_t const uCs = (uSysR0Cs \| j) + (i << BS3_SEL_RING_SHIFT);
471	for (k = 0; k < 2; k++)
472	{
473	g_usBs3TestStep++;
474	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
475	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
476	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = k;
477	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
478	/Bs3TrapPrintFrame(&TrapCtx);/
479	if (iCtx < iRing)
480	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
481	else if (k == 0)
482	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
483	else if (i > iRing)
484	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
485	else
486	{
487	uint16_t uExpectedCs = uCs & X86_SEL_MASK_OFF_RPL;
488	if (i <= iCtx && i <= iRing)
489	uExpectedCs \|= i;
490	bs3CpuBasic2_CompareTrapCtx2(&TrapCtx, &CtxTmp, 2 /int 8xh/, 0x80 + iCtx /bXcpt/, uExpectedCs);
491	}
492	}
493	}
494
495	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
496	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
497	}
498	}
499	}
500	BS3_ASSERT(g_usBs3TestStep < 1600);
501
502	/*
503	* Various CS and SS related faults
504	*
505	* We temporarily reconfigure gate 80 and 83 with new CS selectors, the
506	* latter have a CS.DPL of 2 for testing ring transisions and SS loading
507	* without making it impossible to handle faults.
508	*/
509	g_usBs3TestStep = 1600;
510	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
511	Bs3GdteTestPage00.Gen.u1Present = 0;
512	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
513	paIdt[0x80 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_00;
514
515	/* CS.PRESENT = 0 */
516	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
517	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
518	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
519	bs3CpuBasic2_FailedF("selector was accessed");
520	g_usBs3TestStep++;
521
522	/* Check that GATE.DPL is checked before CS.PRESENT. */
523	for (iRing = 1; iRing < 4; iRing++)
524	{
525	Bs3MemCpy(&CtxTmp, &Ctx80, sizeof(CtxTmp));
526	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
527	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
528	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, (0x80 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
529	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
530	bs3CpuBasic2_FailedF("selector was accessed");
531	g_usBs3TestStep++;
532	}
533
534	/* CS.DPL mismatch takes precedence over CS.PRESENT = 0. */
535	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
536	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
537	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
538	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
539	bs3CpuBasic2_FailedF("CS selector was accessed");
540	g_usBs3TestStep++;
541	for (iDpl = 1; iDpl < 4; iDpl++)
542	{
543	Bs3GdteTestPage00.Gen.u2Dpl = iDpl;
544	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
545	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
546	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
547	bs3CpuBasic2_FailedF("CS selector was accessed");
548	g_usBs3TestStep++;
549	}
550
551	/* 1608: Check all the invalid CS selector types alone. */
552	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
553	for (i = 0; i < RT_ELEMENTS(g_aInvalidCsTypes); i++)
554	{
555	Bs3GdteTestPage00.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
556	Bs3GdteTestPage00.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
557	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
558	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
559	if (Bs3GdteTestPage00.Gen.u4Type != g_aInvalidCsTypes[i].u4Type)
560	bs3CpuBasic2_FailedF("Invalid CS type %#x/%u -> %#x/%u\n",
561	g_aInvalidCsTypes[i].u4Type, g_aInvalidCsTypes[i].u1DescType,
562	Bs3GdteTestPage00.Gen.u4Type, Bs3GdteTestPage00.Gen.u1DescType);
563	g_usBs3TestStep++;
564
565	/* Incorrect CS.TYPE takes precedence over CS.PRESENT = 0. */
566	Bs3GdteTestPage00.Gen.u1Present = 0;
567	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
568	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
569	Bs3GdteTestPage00.Gen.u1Present = 1;
570	g_usBs3TestStep++;
571	}
572
573	/* Fix CS again. */
574	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
575
576	/* 1632: Test SS. */
577	if (!BS3_MODE_IS_64BIT_SYS(g_bTestMode))
578	{
579	uint16_t BS3_FAR *puTssSs2 = BS3_MODE_IS_16BIT_SYS(g_bTestMode) ? &Bs3Tss16.ss2 : &Bs3Tss32.ss2;
580	uint16_t const uSavedSs2 = *puTssSs2;
581	X86DESC const SavedGate83 = paIdt[0x83 << cIdteShift];
582
583	/* Make the handler execute in ring-2. */
584	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
585	Bs3GdteTestPage02.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
586	paIdt[0x83 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_02 \| 2;
587
588	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
589	Bs3RegCtxConvertToRingX(&CtxTmp, 3); /* yeah, from 3 so SS:xSP is reloaded. */
590	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
591	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
592	if (!(Bs3GdteTestPage02.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
593	bs3CpuBasic2_FailedF("CS selector was not access");
594	g_usBs3TestStep++;
595
596	/* Create a SS.DPL=2 stack segment and check that SS2.RPL matters and
597	that we get #SS if the selector isn't present. */
598	i = 0; /* used for cycling thru invalid CS types */
599	for (k = 0; k < 10; k++)
600	{
601	/* k=0: present,
602	k=1: not-present,
603	k=2: present but very low limit,
604	k=3: not-present, low limit.
605	k=4: present, read-only.
606	k=5: not-present, read-only.
607	k=6: present, code-selector.
608	k=7: not-present, code-selector.
609	k=8: present, read-write / no access + system (=LDT).
610	k=9: not-present, read-write / no access + system (=LDT).
611	*/
612	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
613	Bs3GdteTestPage03.Gen.u1Present = !(k & 1);
614	if (k >= 8)
615	{
616	Bs3GdteTestPage03.Gen.u1DescType = 0; /* system */
617	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RW; /* = LDT */
618	}
619	else if (k >= 6)
620	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_ER;
621	else if (k >= 4)
622	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RO;
623	else if (k >= 2)
624	{
625	Bs3GdteTestPage03.Gen.u16LimitLow = 0x400;
626	Bs3GdteTestPage03.Gen.u4LimitHigh = 0;
627	Bs3GdteTestPage03.Gen.u1Granularity = 0;
628	}
629
630	for (iDpl = 0; iDpl < 4; iDpl++)
631	{
632	Bs3GdteTestPage03.Gen.u2Dpl = iDpl;
633
634	for (iRpl = 0; iRpl < 4; iRpl++)
635	{
636	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| iRpl;
637	//Bs3TestPrintf("k=%u iDpl=%u iRpl=%u step=%u\n", k, iDpl, iRpl, g_usBs3TestStep);
638	Bs3GdteTestPage02.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
639	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
640	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
641	if (iRpl != 2 \|\| iRpl != iDpl \|\| k >= 4)
642	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
643	else if (k != 0)
644	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03,
645	k == 2 /f486ResumeFlagHint/);
646	else
647	{
648	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
649	if (TrapCtx.uHandlerSs != (BS3_SEL_TEST_PAGE_03 \| 2))
650	bs3CpuBasic2_FailedF("uHandlerSs=%#x expected %#x\n", TrapCtx.uHandlerSs, BS3_SEL_TEST_PAGE_03 \| 2);
651	}
652	if (!(Bs3GdteTestPage02.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
653	bs3CpuBasic2_FailedF("CS selector was not access");
654	if ( TrapCtx.bXcpt == 0x83
655	\|\| (TrapCtx.bXcpt == X86_XCPT_SS && k == 2) )
656	{
657	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
658	bs3CpuBasic2_FailedF("SS selector was not accessed");
659	}
660	else if (Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
661	bs3CpuBasic2_FailedF("SS selector was accessed");
662	g_usBs3TestStep++;
663
664	/* Modify the gate DPL to check that this is checked before SS.DPL and SS.PRESENT. */
665	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 2;
666	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
667	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, (0x83 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
668	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 3;
669	g_usBs3TestStep++;
670
671	/* Check the the CS.DPL check is done before the SS ones. Restoring the ring-0 INT 83
672	context triggers the CS.DPL < CPL check. */
673	Bs3TrapSetJmpAndRestore(&Ctx83, &TrapCtx);
674	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx83, BS3_SEL_TEST_PAGE_02);
675	g_usBs3TestStep++;
676
677	/* Now mark the CS selector not present and check that that also triggers before SS stuff. */
678	Bs3GdteTestPage02.Gen.u1Present = 0;
679	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
680	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_02);
681	Bs3GdteTestPage02.Gen.u1Present = 1;
682	g_usBs3TestStep++;
683
684	/* Make the CS selector some invalid type and check it triggers before SS stuff. */
685	Bs3GdteTestPage02.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
686	Bs3GdteTestPage02.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
687	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
688	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_02);
689	Bs3GdteTestPage02.Gen.u4Type = X86_SEL_TYPE_ER_ACC;
690	Bs3GdteTestPage02.Gen.u1DescType = 1;
691	g_usBs3TestStep++;
692
693	/* Now, make the CS selector limit too small and that it triggers after SS trouble. */
694	Bs3GdteTestPage02.Gen.u16LimitLow = 0;
695	Bs3GdteTestPage02.Gen.u4LimitHigh = 0;
696	Bs3GdteTestPage02.Gen.u1Granularity = 0;
697	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
698	if (iRpl != 2 \|\| iRpl != iDpl \|\| k >= 4)
699	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
700	else if (k != 0)
701	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, k == 2 /f486ResumeFlagHint/);
702	else
703	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/);
704	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
705	g_usBs3TestStep++;
706	}
707	}
708	}
709
710	/* Check all the invalid SS selector types alone. */
711	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
712	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
713	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| 2;
714	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
715	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
716	g_usBs3TestStep++;
717	for (i = 0; i < RT_ELEMENTS(g_aInvalidSsTypes); i++)
718	{
719	Bs3GdteTestPage03.Gen.u4Type = g_aInvalidSsTypes[i].u4Type;
720	Bs3GdteTestPage03.Gen.u1DescType = g_aInvalidSsTypes[i].u1DescType;
721	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
722	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
723	if (Bs3GdteTestPage03.Gen.u4Type != g_aInvalidSsTypes[i].u4Type)
724	bs3CpuBasic2_FailedF("Invalid SS type %#x/%u -> %#x/%u\n",
725	g_aInvalidSsTypes[i].u4Type, g_aInvalidSsTypes[i].u1DescType,
726	Bs3GdteTestPage03.Gen.u4Type, Bs3GdteTestPage03.Gen.u1DescType);
727	g_usBs3TestStep++;
728	}
729
730	/*
731	* Continue the SS experiments with a expand down segment. We'll use
732	* the same setup as we already have with gate 83h being DPL and
733	* having CS.DPL=2.
734	*
735	* Expand down segments are weird. The valid area is practically speaking
736	* reversed. So, a 16-bit segment with a limit of 0x6000 will have valid
737	* addresses from 0xffff thru 0x6001.
738	*
739	* So, with expand down segments we can more easily cut partially into the
740	* pushing of the iret frame and trigger more interesting behavior than
741	* with regular "expand up" segments where the whole pushing area is either
742	* all fine or not not fine.
743	*/
744	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
745	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
746	Bs3GdteTestPage03.Gen.u2Dpl = 2;
747	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RW_DOWN;
748	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| 2;
749
750	/* First test, limit = max --> no bytes accessible --> #GP */
751	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
752	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, true /f486ResumeFlagHint/);
753
754	/* Second test, limit = 0 --> all by zero byte accessible --> works */
755	Bs3GdteTestPage03.Gen.u16LimitLow = 0;
756	Bs3GdteTestPage03.Gen.u4LimitHigh = 0;
757	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
758	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
759
760	/* Modify the gate handler to be a dummy that immediately does UD2
761	and triggers #UD, then advance the limit down till we get the #UD. */
762	Bs3GdteTestPage03.Gen.u1Granularity = 0;
763
764	Bs3MemCpy(&CtxTmp2, &CtxTmp, sizeof(CtxTmp2)); /* #UD result context */
765	if (g_f16BitSys)
766	{
767	CtxTmp2.rip.u = g_bs3CpuBasic2_ud2_FlatAddr - BS3_ADDR_BS3TEXT16;
768	Bs3Trap16SetGate(0x83, X86_SEL_TYPE_SYS_286_INT_GATE, 3, BS3_SEL_TEST_PAGE_02, CtxTmp2.rip.u16, 0 /cParams/);
769	CtxTmp2.rsp.u = Bs3Tss16.sp2 - 2*5;
770	}
771	else
772	{
773	CtxTmp2.rip.u = g_bs3CpuBasic2_ud2_FlatAddr;
774	Bs3Trap32SetGate(0x83, X86_SEL_TYPE_SYS_386_INT_GATE, 3, BS3_SEL_TEST_PAGE_02, CtxTmp2.rip.u32, 0 /cParams/);
775	CtxTmp2.rsp.u = Bs3Tss32.esp2 - 4*5;
776	}
777	CtxTmp2.bMode = g_bTestMode; /* g_bBs3CurrentMode not changed by the UD2 handler. */
778	CtxTmp2.cs = BS3_SEL_TEST_PAGE_02 \| 2;
779	CtxTmp2.ss = BS3_SEL_TEST_PAGE_03 \| 2;
780	CtxTmp2.bCpl = 2;
781
782	/* test run. */
783	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
784	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
785	g_usBs3TestStep++;
786
787	/* Real run. */
788	i = (g_f16BitSys ? 2 : 4) * 6 + 1;
789	while (i-- > 0)
790	{
791	Bs3GdteTestPage03.Gen.u16LimitLow = CtxTmp2.rsp.u16 + i - 1;
792	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
793	if (i > 0)
794	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, true /f486ResumeFlagHint/);
795	else
796	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
797	g_usBs3TestStep++;
798	}
799
800	/* Do a run where we do the same-ring kind of access. */
801	Bs3RegCtxConvertToRingX(&CtxTmp, 2);
802	if (g_f16BitSys)
803	{
804	CtxTmp2.rsp.u32 = CtxTmp.rsp.u32 - 2*3;
805	i = 2*3 - 1;
806	}
807	else
808	{
809	CtxTmp2.rsp.u32 = CtxTmp.rsp.u32 - 4*3;
810	i = 4*3 - 1;
811	}
812	CtxTmp.ss = BS3_SEL_TEST_PAGE_03 \| 2;
813	CtxTmp2.ds = CtxTmp.ds;
814	CtxTmp2.es = CtxTmp.es;
815	CtxTmp2.fs = CtxTmp.fs;
816	CtxTmp2.gs = CtxTmp.gs;
817	while (i-- > 0)
818	{
819	Bs3GdteTestPage03.Gen.u16LimitLow = CtxTmp2.rsp.u16 + i - 1;
820	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
821	if (i > 0)
822	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, 0 /BS3_SEL_TEST_PAGE_03/, true /f486ResumeFlagHint/);
823	else
824	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
825	g_usBs3TestStep++;
826	}
827
828	*puTssSs2 = uSavedSs2;
829	paIdt[0x83 << cIdteShift] = SavedGate83;
830	}
831	paIdt[0x80 << cIdteShift].Gate.u16Sel = uSysR0Cs;
832	BS3_ASSERT(g_usBs3TestStep < 3000);
833
834	/*
835	* Modify the gate CS value with a conforming segment.
836	*/
837	g_usBs3TestStep = 3000;
838	for (i = 0; i <= 3; i++) /* cs.dpl */
839	{
840	for (iRing = 0; iRing <= 3; iRing++)
841	{
842	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
843	{
844	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
845	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
846	# if TMPL_BITS == 32
847	g_uBs3TrapEipHint = CtxTmp.rip.u32;
848	# endif
849
850	for (j = 0; j <= 3; j++) /* rpl */
851	{
852	uint16_t const uCs = (uSysR0CsConf \| j) + (i << BS3_SEL_RING_SHIFT);
853	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
854	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
855	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
856	//Bs3TestPrintf("%u/%u/%u/%u: cs=%04x hcs=%04x xcpt=%02x\n", i, iRing, iCtx, j, uCs, TrapCtx.uHandlerCs, TrapCtx.bXcpt);
857	/Bs3TrapPrintFrame(&TrapCtx);/
858	g_usBs3TestStep++;
859	if (iCtx < iRing)
860	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
861	else if (i > iRing)
862	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
863	else
864	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
865	}
866	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
867	}
868	}
869	}
870	BS3_ASSERT(g_usBs3TestStep < 3500);
871
872	/*
873	* The gates must be 64-bit in long mode.
874	*/
875	if (cIdteShift != 0)
876	{
877	g_usBs3TestStep = 3500;
878	for (i = 0; i <= 3; i++)
879	{
880	for (iRing = 0; iRing <= 3; iRing++)
881	{
882	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
883	{
884	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
885	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
886
887	for (j = 0; j < 2; j++)
888	{
889	static const uint16_t s_auCSes[2] = { BS3_SEL_R0_CS16, BS3_SEL_R0_CS32 };
890	uint16_t uCs = (s_auCSes[j] \| i) + (i << BS3_SEL_RING_SHIFT);
891	g_usBs3TestStep++;
892	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
893	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
894	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
895	/Bs3TrapPrintFrame(&TrapCtx);/
896	if (iCtx < iRing)
897	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
898	else
899	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
900	}
901	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
902	}
903	}
904	}
905	BS3_ASSERT(g_usBs3TestStep < 4000);
906	}
907
908	/*
909	* IDT limit check.
910	*/
911	g_usBs3TestStep = 5000;
912	i = (0x80 << (cIdteShift + 3)) - 1;
913	j = (0x82 << (cIdteShift + 3)) - 1;
914	k = (0x83 << (cIdteShift + 3)) - 1;
915	for (; i <= k; i++, g_usBs3TestStep++)
916	{
917	Idtr = IdtrSaved;
918	Idtr.cbIdt = i;
919	ASMSetIDTR(&Idtr);
920	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
921	if (i < j)
922	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx81, (0x81 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
923	else
924	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
925	}
926	ASMSetIDTR(&IdtrSaved);
927	BS3_ASSERT(g_usBs3TestStep < 5100);
928
929	# if TMPL_BITS != 16 /* Only do the paging related stuff in 32-bit and 64-bit modes. */
930
931	/*
932	* IDT page not present. Placing the IDT copy such that 0x80 is on the
933	* first page and 0x81 is on the second page. We need proceed to move
934	* it down byte by byte to check that any inaccessible byte means #PF.
935	*
936	* Note! We must reload the alternative IDTR for each run as any kind of
937	* printing to the string (like error reporting) will cause a switch
938	* to real mode and back, reloading the default IDTR.
939	*/
940	g_usBs3TestStep = 5200;
941	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
942	{
943	uint32_t const uCr2Expected = Bs3SelPtrToFlat(pbIdtCopyAlloc) + _4K;
944	for (j = 0; j < cbIdte; j++)
945	{
946	pIdtCopy = (PX86DESC)&pbIdtCopyAlloc[_4K - cbIdte * 0x81 - j];
947	Bs3MemCpy(pIdtCopy, paIdt, cbIdte * 256);
948
949	Idtr.cbIdt = IdtrSaved.cbIdt;
950	Idtr.pIdt = Bs3SelPtrToFlat(pIdtCopy);
951
952	ASMSetIDTR(&Idtr);
953	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
954	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
955	g_usBs3TestStep++;
956
957	ASMSetIDTR(&Idtr);
958	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
959	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
960	g_usBs3TestStep++;
961
962	rc = Bs3PagingProtect(uCr2Expected, _4K, 0 /fSet/, X86_PTE_P /fClear/);
963	if (RT_SUCCESS(rc))
964	{
965	ASMSetIDTR(&Idtr);
966	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
967	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
968	g_usBs3TestStep++;
969
970	ASMSetIDTR(&Idtr);
971	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
972	if (f486Plus)
973	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /uErrCd/, uCr2Expected);
974	else
975	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, X86_TRAP_PF_RW /uErrCd/, uCr2Expected + 4 - RT_MIN(j, 4));
976	g_usBs3TestStep++;
977
978	Bs3PagingProtect(uCr2Expected, _4K, X86_PTE_P /fSet/, 0 /fClear/);
979
980	/* Check if that the entry type is checked after the whole IDTE has been cleared for #PF. */
981	pIdtCopy[0x80 << cIdteShift].Gate.u4Type = 0;
982	rc = Bs3PagingProtect(uCr2Expected, _4K, 0 /fSet/, X86_PTE_P /fClear/);
983	if (RT_SUCCESS(rc))
984	{
985	ASMSetIDTR(&Idtr);
986	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
987	if (f486Plus)
988	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /uErrCd/, uCr2Expected);
989	else
990	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, X86_TRAP_PF_RW /uErrCd/, uCr2Expected + 4 - RT_MIN(j, 4));
991	g_usBs3TestStep++;
992
993	Bs3PagingProtect(uCr2Expected, _4K, X86_PTE_P /fSet/, 0 /fClear/);
994	}
995	}
996	else
997	Bs3TestPrintf("Bs3PagingProtectPtr: %d\n", i);
998
999	ASMSetIDTR(&IdtrSaved);
1000	}
1001	}
1002
1003	/*
1004	* The read/write and user/supervisor bits the IDT PTEs are irrelevant.
1005	*/
1006	g_usBs3TestStep = 5300;
1007	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
1008	{
1009	Bs3MemCpy(pbIdtCopyAlloc, paIdt, cbIdte * 256);
1010	Idtr.cbIdt = IdtrSaved.cbIdt;
1011	Idtr.pIdt = Bs3SelPtrToFlat(pbIdtCopyAlloc);
1012
1013	ASMSetIDTR(&Idtr);
1014	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
1015	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
1016	g_usBs3TestStep++;
1017
1018	rc = Bs3PagingProtect(Idtr.pIdt, _4K, 0 /fSet/, X86_PTE_RW \| X86_PTE_US /fClear/);
1019	if (RT_SUCCESS(rc))
1020	{
1021	ASMSetIDTR(&Idtr);
1022	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
1023	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
1024	g_usBs3TestStep++;
1025
1026	Bs3PagingProtect(Idtr.pIdt, _4K, X86_PTE_RW \| X86_PTE_US /fSet/, 0 /fClear/);
1027	}
1028	ASMSetIDTR(&IdtrSaved);
1029	}
1030
1031	/*
1032	* Check that CS.u1Accessed is set to 1. Use the test page selector #0 and #3 together
1033	* with interrupt gates 80h and 83h, respectively.
1034	*/
1035	/** @todo Throw in SS.u1Accessed too. */
1036	g_usBs3TestStep = 5400;
1037	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
1038	{
1039	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
1040	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1041	paIdt[0x80 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_00;
1042
1043	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Cs + (3 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
1044	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1045	paIdt[0x83 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_03; /* rpl is ignored, so leave it as zero. */
1046
1047	/* Check that the CS.A bit is being set on a general basis and that
1048	the special CS values work with out generic handler code. */
1049	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1050	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1051	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1052	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed", Bs3GdteTestPage00.Gen.u4Type);
1053	g_usBs3TestStep++;
1054
1055	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1056	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1057	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1058	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1059	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1060	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1061	if (TrapCtx.uHandlerCs != (BS3_SEL_TEST_PAGE_03 \| 3))
1062	bs3CpuBasic2_FailedF("uHandlerCs=%#x, expected %#x", TrapCtx.uHandlerCs, (BS3_SEL_TEST_PAGE_03 \| 3));
1063	g_usBs3TestStep++;
1064
1065	/*
1066	* Now check that setting CS.u1Access to 1 does __NOT__ trigger a page
1067	* fault due to the RW bit being zero.
1068	* (We check both with with and without the WP bit if 80486.)
1069	*/
1070	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
1071	ASMSetCR0(uCr0Saved \| X86_CR0_WP);
1072
1073	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1074	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1075	rc = Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, 0 /fSet/, X86_PTE_RW /fClear/);
1076	if (RT_SUCCESS(rc))
1077	{
1078	/* ring-0 handler */
1079	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1080	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1081	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1082	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1083	g_usBs3TestStep++;
1084
1085	/* ring-3 handler */
1086	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1087	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1088	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1089	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1090	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1091	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1092	g_usBs3TestStep++;
1093
1094	/* clear WP and repeat the above. */
1095	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
1096	ASMSetCR0(uCr0Saved & ~X86_CR0_WP);
1097	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* (No need to RW the page - ring-0, WP=0.) */
1098	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* (No need to RW the page - ring-0, WP=0.) */
1099
1100	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1101	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1102	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1103	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1104	g_usBs3TestStep++;
1105
1106	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1107	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1108	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1109	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!n", Bs3GdteTestPage03.Gen.u4Type);
1110	g_usBs3TestStep++;
1111
1112	Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, X86_PTE_RW /fSet/, 0 /fClear/);
1113	}
1114
1115	ASMSetCR0(uCr0Saved);
1116
1117	/*
1118	* While we're here, check that if the CS GDT entry is a non-present
1119	* page we do get a #PF with the rigth error code and CR2.
1120	*/
1121	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* Just for fun, really a pointless gesture. */
1122	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1123	rc = Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, 0 /fSet/, X86_PTE_P /fClear/);
1124	if (RT_SUCCESS(rc))
1125	{
1126	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1127	if (f486Plus)
1128	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, 0 /uErrCd/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00);
1129	else
1130	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, X86_TRAP_PF_RW, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00 + 4);
1131	g_usBs3TestStep++;
1132
1133	/* Do it from ring-3 to check ErrCd, which doesn't set X86_TRAP_PF_US it turns out. */
1134	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1135	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1136	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1137
1138	if (f486Plus)
1139	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03);
1140	else
1141	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, X86_TRAP_PF_RW, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03 + 4);
1142	g_usBs3TestStep++;
1143
1144	Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, X86_PTE_P /fSet/, 0 /fClear/);
1145	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
1146	bs3CpuBasic2_FailedF("u4Type=%#x, accessed! #1", Bs3GdteTestPage00.Gen.u4Type);
1147	if (Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
1148	bs3CpuBasic2_FailedF("u4Type=%#x, accessed! #2", Bs3GdteTestPage03.Gen.u4Type);
1149	}
1150
1151	/* restore */
1152	paIdt[0x80 << cIdteShift].Gate.u16Sel = uSysR0Cs;
1153	paIdt[0x83 << cIdteShift].Gate.u16Sel = uSysR0Cs;// + (3 << BS3_SEL_RING_SHIFT) + 3;
1154	}
1155
1156	# endif /* 32 \|\| 64*/
1157
1158	/*
1159	* Check broad EFLAGS effects.
1160	*/
1161	g_usBs3TestStep = 5600;
1162	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
1163	{
1164	for (iRing = 0; iRing < 4; iRing++)
1165	{
1166	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
1167	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
1168
1169	/* all set */
1170	CtxTmp.rflags.u32 &= X86_EFL_VM \| X86_EFL_1;
1171	CtxTmp.rflags.u32 \|= X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF /* \| X86_EFL_TF / /\| X86_EFL_IF*/
1172	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL /* \| X86_EFL_NT*/;
1173	if (f486Plus)
1174	CtxTmp.rflags.u32 \|= X86_EFL_AC;
1175	if (f486Plus && !g_f16BitSys)
1176	CtxTmp.rflags.u32 \|= X86_EFL_RF;
1177	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
1178	CtxTmp.rflags.u32 \|= X86_EFL_VIF \| X86_EFL_VIP;
1179	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1180	CtxTmp.rflags.u32 &= ~X86_EFL_RF;
1181
1182	if (iCtx >= iRing)
1183	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
1184	else
1185	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1186	uExpected = CtxTmp.rflags.u32
1187	& ( X86_EFL_1 \| X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_DF
1188	\| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP
1189	\| X86_EFL_ID /\| X86_EFL_TF/ /\| X86_EFL_IF/ /\| X86_EFL_RF/ );
1190	if (TrapCtx.fHandlerRfl != uExpected)
1191	bs3CpuBasic2_FailedF("unexpected handler rflags value: %RX64 expected %RX32; CtxTmp.rflags=%RX64 Ctx.rflags=%RX64\n",
1192	TrapCtx.fHandlerRfl, uExpected, CtxTmp.rflags.u, TrapCtx.Ctx.rflags.u);
1193	g_usBs3TestStep++;
1194
1195	/* all cleared */
1196	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80286)
1197	CtxTmp.rflags.u32 = apCtx8x[iCtx]->rflags.u32 & (X86_EFL_RA1_MASK \| UINT16_C(0xf000));
1198	else
1199	CtxTmp.rflags.u32 = apCtx8x[iCtx]->rflags.u32 & (X86_EFL_VM \| X86_EFL_RA1_MASK);
1200	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1201	if (iCtx >= iRing)
1202	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
1203	else
1204	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1205	uExpected = CtxTmp.rflags.u32;
1206	if (TrapCtx.fHandlerRfl != uExpected)
1207	bs3CpuBasic2_FailedF("unexpected handler rflags value: %RX64 expected %RX32; CtxTmp.rflags=%RX64 Ctx.rflags=%RX64\n",
1208	TrapCtx.fHandlerRfl, uExpected, CtxTmp.rflags.u, TrapCtx.Ctx.rflags.u);
1209	g_usBs3TestStep++;
1210	}
1211	}
1212
1213	/** @todo CS.LIMIT / canonical(CS) */
1214
1215
1216	/*
1217	* Check invalid gate types.
1218	*/
1219	g_usBs3TestStep = 32000;
1220	for (iRing = 0; iRing <= 3; iRing++)
1221	{
1222	static const uint16_t s_auCSes[] = { BS3_SEL_R0_CS16, BS3_SEL_R0_CS32, BS3_SEL_R0_CS64,
1223	BS3_SEL_TSS16, BS3_SEL_TSS32, BS3_SEL_TSS64, 0, BS3_SEL_SPARE_1f };
1224	static uint16_t const s_auInvlTypes64[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
1225	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
1226	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f };
1227	static uint16_t const s_auInvlTypes32[] = { 0, 1, 2, 3, 8, 9, 10, 11, 13,
1228	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
1229	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
1230	/286:/ 12, 14, 15 };
1231	uint16_t const * const pauInvTypes = cIdteShift != 0 ? s_auInvlTypes64 : s_auInvlTypes32;
1232	uint16_t const cInvTypes = cIdteShift != 0 ? RT_ELEMENTS(s_auInvlTypes64)
1233	: f386Plus ? RT_ELEMENTS(s_auInvlTypes32) - 3 : RT_ELEMENTS(s_auInvlTypes32);
1234
1235
1236	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
1237	{
1238	unsigned iType;
1239
1240	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
1241	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
1242	# if TMPL_BITS == 32
1243	g_uBs3TrapEipHint = CtxTmp.rip.u32;
1244	# endif
1245	for (iType = 0; iType < cInvTypes; iType++)
1246	{
1247	uint8_t const bSavedType = paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type;
1248	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1DescType = pauInvTypes[iType] >> 4;
1249	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type = pauInvTypes[iType] & 0xf;
1250
1251	for (i = 0; i < 4; i++)
1252	{
1253	for (j = 0; j < RT_ELEMENTS(s_auCSes); j++)
1254	{
1255	uint16_t uCs = (unsigned)(s_auCSes[j] - BS3_SEL_R0_FIRST) < (unsigned)(4 << BS3_SEL_RING_SHIFT)
1256	? (s_auCSes[j] \| i) + (i << BS3_SEL_RING_SHIFT)
1257	: s_auCSes[j] \| i;
1258	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x type=%#x\n", g_usBs3TestStep, iCtx, iRing, i, uCs, pauInvTypes[iType]);/
1259	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
1260	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1261	g_usBs3TestStep++;
1262	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1263
1264	/* Mark it not-present to check that invalid type takes precedence. */
1265	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 0;
1266	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1267	g_usBs3TestStep++;
1268	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1269	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
1270	}
1271	}
1272
1273	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = MY_SYS_SEL_R0_CS;
1274	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type = bSavedType;
1275	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1DescType = 0;
1276	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
1277	}
1278	}
1279	}
1280	BS3_ASSERT(g_usBs3TestStep < 62000U && g_usBs3TestStep > 32000U);
1281
1282
1283	/** @todo
1284	* - Run \#PF and \#GP (and others?) at CPLs other than zero.
1285	* - Quickly generate all faults.
1286	* - All the peculiarities v8086.
1287	*/
1288
1289	# if TMPL_BITS != 16
1290	Bs3MemFree(pbIdtCopyAlloc, 12*_1K);
1291	# endif
1292	}
1293
1294	#endif /* once for each bitcount */
1295
1296
1297	#if TMPL_MODE == BS3_MODE_PE16 \|\| TMPL_MODE == BS3_MODE_PE16_32
1298
1299	/**
1300	* Worker for bs3CpuBasic2_TssGateEsp that tests the INT 80 from outer rings.
1301	*/
1302	#define bs3CpuBasic2_TssGateEsp_AltStackOuterRing BS3_CMN_NM(bs3CpuBasic2_TssGateEsp_AltStackOuterRing)
1303	void bs3CpuBasic2_TssGateEsp_AltStackOuterRing(PCBS3REGCTX pCtx, uint8_t bRing, uint8_t *pbAltStack, size_t cbAltStack,
1304	bool f16BitStack, bool f16BitTss, bool f16BitHandler, unsigned uLine)
1305	{
1306	uint8_t const cbIretFrame = f16BitHandler ? 52 : 54;
1307	BS3REGCTX Ctx2;
1308	BS3TRAPFRAME TrapCtx;
1309	uint8_t *pbTmp;
1310	g_usBs3TestStep = uLine;
1311
1312	Bs3MemCpy(&Ctx2, pCtx, sizeof(Ctx2));
1313	Bs3RegCtxConvertToRingX(&Ctx2, bRing);
1314
1315	if (pbAltStack)
1316	{
1317	Ctx2.rsp.u = Bs3SelPtrToFlat(pbAltStack + 0x1980);
1318	Bs3MemZero(pbAltStack, cbAltStack);
1319	}
1320
1321	Bs3TrapSetJmpAndRestore(&Ctx2, &TrapCtx);
1322
1323	if (!f16BitStack && f16BitTss)
1324	Ctx2.rsp.u &= UINT16_MAX;
1325
1326	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx2, 0x80 /bXcpt/);
1327	CHECK_MEMBER("bCpl", "%u", TrapCtx.Ctx.bCpl, bRing);
1328	CHECK_MEMBER("cbIretFrame", "%#x", TrapCtx.cbIretFrame, cbIretFrame);
1329
1330	if (pbAltStack)
1331	{
1332	uint64_t uExpectedRsp = (f16BitTss ? Bs3Tss16.sp0 : Bs3Tss32.esp0) - cbIretFrame;
1333	if (f16BitStack)
1334	{
1335	uExpectedRsp &= UINT16_MAX;
1336	uExpectedRsp \|= Ctx2.rsp.u & ~(uint64_t)UINT16_MAX;
1337	}
1338	if ( TrapCtx.uHandlerRsp != uExpectedRsp
1339	\|\| TrapCtx.uHandlerSs != (f16BitTss ? Bs3Tss16.ss0 : Bs3Tss32.ss0))
1340	bs3CpuBasic2_FailedF("handler SS:ESP=%04x:%08RX64, expected %04x:%08RX16",
1341	TrapCtx.uHandlerSs, TrapCtx.uHandlerRsp, Bs3Tss16.ss0, uExpectedRsp);
1342
1343	pbTmp = (uint8_t *)ASMMemFirstNonZero(pbAltStack, cbAltStack);
1344	if ((f16BitStack \|\| TrapCtx.uHandlerRsp <= UINT16_MAX) && pbTmp != NULL)
1345	bs3CpuBasic2_FailedF("someone touched the alt stack (%p) with SS:ESP=%04x:%#RX32: %p=%02x",
1346	pbAltStack, Ctx2.ss, Ctx2.rsp.u32, pbTmp, *pbTmp);
1347	else if (!f16BitStack && TrapCtx.uHandlerRsp > UINT16_MAX && pbTmp == NULL)
1348	bs3CpuBasic2_FailedF("the alt stack (%p) was not used SS:ESP=%04x:%#RX32\n", pbAltStack, Ctx2.ss, Ctx2.rsp.u32);
1349	}
1350	}
1351
1352	#define bs3CpuBasic2_TssGateEspCommon BS3_CMN_NM(bs3CpuBasic2_TssGateEspCommon)
1353	void bs3CpuBasic2_TssGateEspCommon(bool const g_f16BitSys, PX86DESC const paIdt, unsigned const cIdteShift)
1354	{
1355	BS3TRAPFRAME TrapCtx;
1356	BS3REGCTX Ctx;
1357	BS3REGCTX Ctx2;
1358	# if TMPL_BITS == 16
1359	uint8_t *pbTmp;
1360	# endif
1361
1362	/* make sure they're allocated */
1363	Bs3MemZero(&Ctx, sizeof(Ctx));
1364	Bs3MemZero(&Ctx2, sizeof(Ctx2));
1365	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
1366
1367	Bs3RegCtxSave(&Ctx);
1368	Ctx.rsp.u -= 0x80;
1369	Ctx.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int80));
1370	# if TMPL_BITS == 32
1371	g_uBs3TrapEipHint = Ctx.rip.u32;
1372	# endif
1373
1374	/*
1375	* We'll be using IDT entry 80 and 81 here. The first one will be
1376	* accessible from all DPLs, the latter not. So, start with setting
1377	* the DPLs.
1378	*/
1379	paIdt[0x80 << cIdteShift].Gate.u2Dpl = 3;
1380	paIdt[0x81 << cIdteShift].Gate.u2Dpl = 0;
1381
1382	/*
1383	* Check that the basic stuff works first.
1384	*/
1385	Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
1386	g_usBs3TestStep = __LINE__;
1387	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx, 0x80 /bXcpt/);
1388
1389	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1390	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 2, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1391	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 3, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1392
1393	/*
1394	* Check that the upper part of ESP is preserved when doing .
1395	*/
1396	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1397	{
1398	size_t const cbAltStack = _8K;
1399	uint8_t *pbAltStack = Bs3MemAllocZ(BS3MEMKIND_TILED, cbAltStack);
1400	if (pbAltStack)
1401	{
1402	/* same ring */
1403	g_usBs3TestStep = __LINE__;
1404	Bs3MemCpy(&Ctx2, &Ctx, sizeof(Ctx2));
1405	Ctx2.rsp.u = Bs3SelPtrToFlat(pbAltStack + 0x1980);
1406	if (Bs3TrapSetJmp(&TrapCtx))
1407	Bs3RegCtxRestore(&Ctx2, 0); /* (does not return) */
1408	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx2, 0x80 /bXcpt/);
1409	# if TMPL_BITS == 16
1410	if ((pbTmp = (uint8_t *)ASMMemFirstNonZero(pbAltStack, cbAltStack)) != NULL)
1411	bs3CpuBasic2_FailedF("someone touched the alt stack (%p) with SS:ESP=%04x:%#RX32: %p=%02x\n",
1412	pbAltStack, Ctx2.ss, Ctx2.rsp.u32, pbTmp, *pbTmp);
1413	# else
1414	if (ASMMemIsZero(pbAltStack, cbAltStack))
1415	bs3CpuBasic2_FailedF("alt stack wasn't used despite SS:ESP=%04x:%#RX32\n", Ctx2.ss, Ctx2.rsp.u32);
1416	# endif
1417
1418	/* Different rings (load SS0:SP0 from TSS). */
1419	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1420	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1421	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 2, pbAltStack, cbAltStack,
1422	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1423	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 3, pbAltStack, cbAltStack,
1424	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1425
1426	/* Different rings but switch the SS bitness in the TSS. */
1427	if (g_f16BitSys)
1428	{
1429	Bs3Tss16.ss0 = BS3_SEL_R0_SS32;
1430	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1431	false, g_f16BitSys, g_f16BitSys, __LINE__);
1432	Bs3Tss16.ss0 = BS3_SEL_R0_SS16;
1433	}
1434	else
1435	{
1436	Bs3Tss32.ss0 = BS3_SEL_R0_SS16;
1437	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1438	true, g_f16BitSys, g_f16BitSys, __LINE__);
1439	Bs3Tss32.ss0 = BS3_SEL_R0_SS32;
1440	}
1441
1442	Bs3MemFree(pbAltStack, cbAltStack);
1443	}
1444	else
1445	Bs3TestPrintf("%s: Skipping ESP check, alloc failed\n", g_pszTestMode);
1446	}
1447	else
1448	Bs3TestPrintf("%s: Skipping ESP check, CPU too old\n", g_pszTestMode);
1449	}
1450
1451	#endif
1452
1453
1454	BS3_DECL(uint8_t) TMPL_NM(bs3CpuBasic2_TssGateEsp)(uint8_t bMode)
1455	{
1456	uint8_t bRet = 0;
1457
1458	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1459	g_bTestMode = bMode;
1460	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1461
1462	#if TMPL_MODE == BS3_MODE_PE16 \
1463	\|\| TMPL_MODE == BS3_MODE_PE16_32 \
1464	\|\| TMPL_MODE == BS3_MODE_PP16 \
1465	\|\| TMPL_MODE == BS3_MODE_PP16_32 \
1466	\|\| TMPL_MODE == BS3_MODE_PAE16 \
1467	\|\| TMPL_MODE == BS3_MODE_PAE16_32 \
1468	\|\| TMPL_MODE == BS3_MODE_PE32
1469	bs3CpuBasic2_TssGateEspCommon(BS3_MODE_IS_16BIT_SYS(TMPL_MODE),
1470	(PX86DESC)MyBs3Idt,
1471	BS3_MODE_IS_64BIT_SYS(TMPL_MODE) ? 1 : 0);
1472	#else
1473	bRet = BS3TESTDOMODE_SKIPPED;
1474	#endif
1475
1476	/*
1477	* Re-initialize the IDT.
1478	*/
1479	TMPL_NM(Bs3TrapInit)();
1480	return bRet;
1481	}
1482
1483
1484	BS3_DECL(uint8_t) TMPL_NM(bs3CpuBasic2_RaiseXcpt1)(uint8_t bMode)
1485	{
1486	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1487	g_bTestMode = bMode;
1488	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1489
1490	#if !BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
1491
1492	/*
1493	* Pass to common worker which is only compiled once per mode.
1494	*/
1495	bs3CpuBasic2_RaiseXcpt1Common(BS3_MODE_IS_16BIT_SYS(TMPL_MODE),
1496	MY_SYS_SEL_R0_CS,
1497	MY_SYS_SEL_R0_CS_CNF,
1498	MY_SYS_SEL_R0_SS,
1499	(PX86DESC)MyBs3Idt,
1500	BS3_MODE_IS_64BIT_SYS(TMPL_MODE) ? 1 : 0);
1501
1502	/*
1503	* Re-initialize the IDT.
1504	*/
1505	TMPL_NM(Bs3TrapInit)();
1506	return 0;
1507	#elif TMPL_MODE == BS3_MODE_RM
1508
1509	/*
1510	* Check
1511	*/
1512	/** @todo check */
1513	return BS3TESTDOMODE_SKIPPED;
1514
1515	#else
1516	return BS3TESTDOMODE_SKIPPED;
1517	#endif
1518	}
1519
1520
1521
1522
1523	BS3_DECL(uint8_t) TMPL_NM(bs3CpuBasic2_iret)(uint8_t bMode)
1524	{
1525	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1526	g_bTestMode = bMode;
1527	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1528
1529	return BS3TESTDOMODE_SKIPPED;
1530	}
1531
1532
1533	#endif /* BS3_INSTANTIATING_MODE */
1534

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c@ 60422

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