| 1 | /* $Id: bs3-apic-1.c 93115 2022-01-01 11:31:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * BS3Kit - bs3-apic-1, 16-bit C code.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2007-2022 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * The contents of this file may alternatively be used under the terms
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| 18 | * of the Common Development and Distribution License Version 1.0
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| 19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | * VirtualBox OSE distribution, in which case the provisions of the
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| 21 | * CDDL are applicable instead of those of the GPL.
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| 22 | *
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| 23 | * You may elect to license modified versions of this file under the
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| 24 | * terms and conditions of either the GPL or the CDDL or both.
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| 25 | */
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| 26 |
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| 27 |
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| 28 | /*********************************************************************************************************************************
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| 29 | * Header Files *
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| 30 | *********************************************************************************************************************************/
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| 31 | #include <bs3kit.h>
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| 32 | #include <iprt/asm-amd64-x86.h>
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| 33 | #include <iprt/x86.h>
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| 34 |
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| 35 |
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| 36 | BS3_DECL(void) Main_rm()
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| 37 | {
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| 38 | Bs3InitAll_rm();
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| 39 | Bs3TestInit("bs3-apic-1");
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| 40 | Bs3TestPrintf("g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
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| 41 |
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| 42 | /*
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| 43 | * Check that there is an APIC
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| 44 | */
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| 45 | if (!(g_uBs3CpuDetected & BS3CPU_F_CPUID))
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| 46 | Bs3TestFailed("CPUID not supported");
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| 47 | else if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR))
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| 48 | Bs3TestFailed("No APIC: RDMSR/WRMSR not supported!");
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| 49 | else if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_APIC))
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| 50 | Bs3TestFailed("No APIC: CPUID(1) does not have EDX_APIC set!\n");
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| 51 | else
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| 52 | {
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| 53 | uint64_t uApicBase2;
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| 54 | uint64_t uApicBase = ASMRdMsr(MSR_IA32_APICBASE);
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| 55 | Bs3TestPrintf("MSR_IA32_APICBASE=%#RX64 %s, %s cpu%s\n",
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| 56 | uApicBase,
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| 57 | uApicBase & MSR_IA32_APICBASE_EN ? "enabled" : "disabled",
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| 58 | uApicBase & MSR_IA32_APICBASE_EXTD ? "bootstrap" : "slave",
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| 59 | uApicBase & MSR_IA32_APICBASE_EXTD ? ", x2apic" : "",
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| 60 | (uApicBase & X86_PAGE_4K_BASE_MASK) == MSR_IA32_APICBASE_ADDR ? ", !non-default address!" : "");
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| 61 |
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| 62 | /* Disable the APIC (according to wiki.osdev.org/APIC, disabling the
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| 63 | APIC could require a CPU reset to re-enable it, but it works for us): */
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| 64 | ASMWrMsr(MSR_IA32_APICBASE, uApicBase & ~(uint64_t)MSR_IA32_APICBASE_EN);
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| 65 | uApicBase2 = ASMRdMsr(MSR_IA32_APICBASE);
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| 66 | if (uApicBase2 == (uApicBase & ~(uint64_t)MSR_IA32_APICBASE_EN))
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| 67 | Bs3TestPrintf("Disabling worked.\n");
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| 68 | else
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| 69 | Bs3TestFailedF("Disabling the APIC did not work (%#RX64)", uApicBase2);
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| 70 |
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| 71 | /* Enabling the APIC: */
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| 72 | ASMWrMsr(MSR_IA32_APICBASE, uApicBase | MSR_IA32_APICBASE_EN);
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| 73 | uApicBase2 = ASMRdMsr(MSR_IA32_APICBASE);
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| 74 | if (uApicBase2 == (uApicBase | MSR_IA32_APICBASE_EN))
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| 75 | Bs3TestPrintf("Enabling worked.\n");
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| 76 | else
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| 77 | Bs3TestFailedF("Enabling the APIC did not work (%#RX64)", uApicBase2);
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| 78 | }
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| 79 |
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| 80 | Bs3TestTerm();
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| 81 | Bs3Shutdown();
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| 82 | }
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| 83 |
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