1 | ; $Id: bootsector2-cpu-instr-1-template.mac 96407 2022-08-22 17:43:14Z vboxsync $
|
---|
2 | ;; @file
|
---|
3 | ; Bootsector test for misc instruction - multi mode template.
|
---|
4 | ;
|
---|
5 |
|
---|
6 | ;
|
---|
7 | ; Copyright (C) 2007-2022 Oracle and/or its affiliates.
|
---|
8 | ;
|
---|
9 | ; This file is part of VirtualBox base platform packages, as
|
---|
10 | ; available from https://www.virtualbox.org.
|
---|
11 | ;
|
---|
12 | ; This program is free software; you can redistribute it and/or
|
---|
13 | ; modify it under the terms of the GNU General Public License
|
---|
14 | ; as published by the Free Software Foundation, in version 3 of the
|
---|
15 | ; License.
|
---|
16 | ;
|
---|
17 | ; This program is distributed in the hope that it will be useful, but
|
---|
18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
|
---|
19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
---|
20 | ; General Public License for more details.
|
---|
21 | ;
|
---|
22 | ; You should have received a copy of the GNU General Public License
|
---|
23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
|
---|
24 | ;
|
---|
25 | ; The contents of this file may alternatively be used under the terms
|
---|
26 | ; of the Common Development and Distribution License Version 1.0
|
---|
27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
|
---|
28 | ; in the VirtualBox distribution, in which case the provisions of the
|
---|
29 | ; CDDL are applicable instead of those of the GPL.
|
---|
30 | ;
|
---|
31 | ; You may elect to license modified versions of this file under the
|
---|
32 | ; terms and conditions of either the GPL or the CDDL or both.
|
---|
33 | ;
|
---|
34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
|
---|
35 | ;
|
---|
36 |
|
---|
37 |
|
---|
38 | %include "bootsector2-template-header.mac"
|
---|
39 |
|
---|
40 |
|
---|
41 |
|
---|
42 | ;;
|
---|
43 | ; Memory fence instructions (SSE2).
|
---|
44 | ;
|
---|
45 | ; @uses No registers, but BS2_SEL_SPARE0 is trashed.
|
---|
46 | ;
|
---|
47 | BEGINPROC TMPL_NM(TestMemFences)
|
---|
48 | push xBP
|
---|
49 | mov xBP, xSP
|
---|
50 | push sAX
|
---|
51 | push xBX
|
---|
52 | push xCX
|
---|
53 | push xDX
|
---|
54 | push xDI
|
---|
55 | push xSI
|
---|
56 | sub xSP, 80h ; iret stack frame space.
|
---|
57 | mov xSI, xSP ; Save the stack register.
|
---|
58 |
|
---|
59 | mov xAX, .s_szSubTestName
|
---|
60 | call TMPL_NM_CMN(TestSub)
|
---|
61 |
|
---|
62 | ;
|
---|
63 | ; SSE2 supported?
|
---|
64 | ;
|
---|
65 | mov eax, 1
|
---|
66 | xor ecx, ecx
|
---|
67 | cpuid
|
---|
68 | test edx, X86_CPUID_FEATURE_EDX_SSE2
|
---|
69 | jz .skip
|
---|
70 |
|
---|
71 | ;
|
---|
72 | ; Check that the standard instruction encodings work.
|
---|
73 | ;
|
---|
74 | mov xBX, [xSP + 10h]
|
---|
75 | mov [xSP], xAX
|
---|
76 | mfence
|
---|
77 | mov [xSP], xCX
|
---|
78 | mov xBX, [xSP + 08h]
|
---|
79 | sfence
|
---|
80 | mov [xSP], xDX
|
---|
81 | mov xBX, [xSP]
|
---|
82 | lfence
|
---|
83 | mov bx, [xSP + 04h]
|
---|
84 |
|
---|
85 |
|
---|
86 | ;
|
---|
87 | ; The instruction encodings in the intel manual may open the RM as well
|
---|
88 | ; as prefixes open to interpretation. AMD sets RM=0 in their docs.
|
---|
89 | ;
|
---|
90 | ; lfence = 0f,ea,e8
|
---|
91 | ; mfence = 0f,ea,f0
|
---|
92 | ; sfence = 0f,ea,f8
|
---|
93 | ; (RM is the lower 3 bits of the last byte.)
|
---|
94 |
|
---|
95 | %assign MY_RM 0xe8
|
---|
96 | %rep 18h
|
---|
97 | db 0fh, 0aeh, MY_RM
|
---|
98 | db X86_OP_PRF_CS, 0fh, 0aeh, MY_RM
|
---|
99 | db X86_OP_PRF_DS, 0fh, 0aeh, MY_RM
|
---|
100 | db X86_OP_PRF_ES, 0fh, 0aeh, MY_RM
|
---|
101 | db X86_OP_PRF_FS, 0fh, 0aeh, MY_RM
|
---|
102 | db X86_OP_PRF_GS, 0fh, 0aeh, MY_RM
|
---|
103 | db X86_OP_PRF_SS, 0fh, 0aeh, MY_RM
|
---|
104 | db X86_OP_PRF_SIZE_ADDR, 0fh, 0aeh, MY_RM
|
---|
105 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
106 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
107 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
108 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
109 | %ifdef TMPL_64BIT
|
---|
110 | %assign MY_REX 0x40
|
---|
111 | %rep 10h
|
---|
112 | ; Rex prefixes doesn't change anything.
|
---|
113 | db MY_REX, 0fh, 0aeh, MY_RM
|
---|
114 | db X86_OP_PRF_CS, MY_REX, 0fh, 0aeh, MY_RM
|
---|
115 | db X86_OP_PRF_DS, MY_REX, 0fh, 0aeh, MY_RM
|
---|
116 | db X86_OP_PRF_ES, MY_REX, 0fh, 0aeh, MY_RM
|
---|
117 | db X86_OP_PRF_FS, MY_REX, 0fh, 0aeh, MY_RM
|
---|
118 | db X86_OP_PRF_GS, MY_REX, 0fh, 0aeh, MY_RM
|
---|
119 | db X86_OP_PRF_SS, MY_REX, 0fh, 0aeh, MY_RM
|
---|
120 | db X86_OP_PRF_SIZE_ADDR, MY_REX, 0fh, 0aeh, MY_RM
|
---|
121 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
122 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
123 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
124 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
|
---|
125 | %assign MY_REX (MY_REX + 1)
|
---|
126 | %endrep
|
---|
127 | %endif
|
---|
128 | %assign MY_RM (MY_RM + 1)
|
---|
129 | %endrep
|
---|
130 |
|
---|
131 | ;
|
---|
132 | ; Done.
|
---|
133 | ;
|
---|
134 | call TMPL_NM_CMN(TestSubDone)
|
---|
135 | .done:
|
---|
136 | mov xSP, xSI
|
---|
137 | add xSP, 80h
|
---|
138 | pop xSI
|
---|
139 | pop xDI
|
---|
140 | pop xDX
|
---|
141 | pop xCX
|
---|
142 | pop xBX
|
---|
143 | pop sAX
|
---|
144 | leave
|
---|
145 | ret
|
---|
146 |
|
---|
147 | .skip:
|
---|
148 | mov xAX, .s_szSse2Missing
|
---|
149 | call TMPL_NM_CMN(TestSubDone)
|
---|
150 | jmp .done
|
---|
151 |
|
---|
152 | .s_szSubTestName:
|
---|
153 | db TMPL_MODE_STR, ', mfence et al.', 0
|
---|
154 | .s_szSse2Missing:
|
---|
155 | db 'SSE2 is missing', 0
|
---|
156 | ENDPROC TMPL_NM(TestMemFences)
|
---|
157 |
|
---|
158 |
|
---|
159 | ;;
|
---|
160 | ; Proving intel manual wrong about using REX.X for BSWAP R8-R15 on 64-bit.
|
---|
161 | ; Checking the 'undefined' 16-bit bswap behavior.
|
---|
162 | ;
|
---|
163 | ; @uses No registers, but BS2_SEL_SPARE0 is trashed.
|
---|
164 | ;
|
---|
165 | BEGINPROC TMPL_NM(TestBSwap)
|
---|
166 | push xBP
|
---|
167 | mov xBP, xSP
|
---|
168 | push sAX
|
---|
169 | push xBX
|
---|
170 | push xCX
|
---|
171 | push xDX
|
---|
172 | push xDI
|
---|
173 | push xSI
|
---|
174 | sub xSP, 80h ; iret stack frame space.
|
---|
175 | mov xSI, xSP ; Save the stack register.
|
---|
176 |
|
---|
177 | mov xAX, .s_szSubTestName
|
---|
178 | call TMPL_NM_CMN(TestSub)
|
---|
179 |
|
---|
180 | ;
|
---|
181 | ; Assert sanity.
|
---|
182 | ;
|
---|
183 | mov eax, 11223344h
|
---|
184 | bswap eax
|
---|
185 | TEST_ASSERT_SIMPLE eax, 44332211h, jz, "32-bit BSWAP EAX"
|
---|
186 |
|
---|
187 | ;
|
---|
188 | ; Buggy manual (325383-041US, December 2011).
|
---|
189 | ;
|
---|
190 | %ifdef TMPL_64BIT
|
---|
191 | push r8
|
---|
192 |
|
---|
193 | mov r8d, 55667788h
|
---|
194 | mov eax, 55667788h
|
---|
195 | db X86_OP_REX_X
|
---|
196 | bswap eax ; does it access r8 or eax?
|
---|
197 | TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.X BSWAP EAX - Wrong EAX."
|
---|
198 | TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.X BSWAP EAX - Wrong R8."
|
---|
199 |
|
---|
200 | mov r8d, 55667788h
|
---|
201 | mov eax, 55667788h
|
---|
202 | db X86_OP_REX_R
|
---|
203 | bswap eax ; does it access r8 or eax?
|
---|
204 | TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.R BSWAP EAX - Wrong EAX."
|
---|
205 | TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.R BSWAP EAX - Wrong R8."
|
---|
206 |
|
---|
207 | mov r8d, 55667788h
|
---|
208 | mov eax, 55667788h
|
---|
209 | db X86_OP_REX_B
|
---|
210 | bswap eax ; does it access r8 or eax?
|
---|
211 | TEST_ASSERT_SIMPLE rax, 55667788h, jz, "REX.B BSWAP R8D - Wrong RAX."
|
---|
212 | TEST_ASSERT_SIMPLE r8d, 88776655h, jz, "REX.B BSWAP R8D - Wrong R8D."
|
---|
213 |
|
---|
214 | pop r8
|
---|
215 | %endif
|
---|
216 |
|
---|
217 | ;
|
---|
218 | ; 'Undefined' 16-bit behavior.
|
---|
219 | ;
|
---|
220 | ; Zeroing of the lower 16-bits has been observed on:
|
---|
221 | ; - Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz
|
---|
222 | ;
|
---|
223 | %ifndef TestBSwap16_defined
|
---|
224 | %define TestBSwap16_defined
|
---|
225 | %macro TestBSwap16 3,
|
---|
226 | mov %3, %2 ; save the primary register.
|
---|
227 | %ifdef TMPL_64BIT
|
---|
228 | mov %2, 0ffffffff98765432h ; Set the upper bit as well.
|
---|
229 | %else
|
---|
230 | mov %2, 98765432h
|
---|
231 | %endif
|
---|
232 | %ifndef TMPL_16BIT
|
---|
233 | db X86_OP_PRF_SIZE_OP
|
---|
234 | %endif
|
---|
235 | bswap %1
|
---|
236 | xchg %2, %3 ; Restore and save the result (xSP).
|
---|
237 | TEST_ASSERT_SIMPLE %3, 98760000h, jz, "Unexpected 16-bit BSWAP error."
|
---|
238 | %endmacro
|
---|
239 | %endif
|
---|
240 |
|
---|
241 | TestBSwap16 eax, sAX, sSI
|
---|
242 | TestBSwap16 ebx, sBX, sSI
|
---|
243 | TestBSwap16 ecx, sCX, sSI
|
---|
244 | TestBSwap16 edx, sDX, sSI
|
---|
245 | TestBSwap16 esp, sSP, sSI
|
---|
246 | TestBSwap16 ebp, sBP, sSI
|
---|
247 | TestBSwap16 edi, sDI, sSI
|
---|
248 | TestBSwap16 esi, sSI, sDI
|
---|
249 | %ifdef TMPL_64BIT
|
---|
250 | TestBSwap16 r8d, r8, rax
|
---|
251 | TestBSwap16 r9d, r9, rax
|
---|
252 | TestBSwap16 r10d, r10, rax
|
---|
253 | TestBSwap16 r11d, r11, rax
|
---|
254 | TestBSwap16 r12d, r12, rax
|
---|
255 | TestBSwap16 r13d, r13, rax
|
---|
256 | TestBSwap16 r14d, r14, rax
|
---|
257 | TestBSwap16 r15d, r15, rax
|
---|
258 | %endif
|
---|
259 |
|
---|
260 | ;
|
---|
261 | ; Done.
|
---|
262 | ;
|
---|
263 | call TMPL_NM_CMN(TestSubDone)
|
---|
264 | .done:
|
---|
265 | mov xSP, xSI
|
---|
266 | add xSP, 80h
|
---|
267 | pop xSI
|
---|
268 | pop xDI
|
---|
269 | pop xDX
|
---|
270 | pop xCX
|
---|
271 | pop xBX
|
---|
272 | pop sAX
|
---|
273 | leave
|
---|
274 | ret
|
---|
275 |
|
---|
276 | .s_szSubTestName:
|
---|
277 | db TMPL_MODE_STR, ', bswap', 0
|
---|
278 | ENDPROC TMPL_NM(TestBSwap)
|
---|
279 |
|
---|
280 |
|
---|
281 | ;;
|
---|
282 | ; Do the tests for this mode.
|
---|
283 | ;
|
---|
284 | ; @uses nothing
|
---|
285 | ;
|
---|
286 | BEGINCODELOW
|
---|
287 | BITS 16
|
---|
288 | BEGINPROC TMPL_NM(DoTestsForMode_rm)
|
---|
289 | push bp
|
---|
290 | mov bp, sp
|
---|
291 | push ax
|
---|
292 |
|
---|
293 | ;
|
---|
294 | ; Check if the mode and NX is supported, do the switch.
|
---|
295 | ;
|
---|
296 | call TMPL_NM(Bs2IsModeSupported_rm)
|
---|
297 | jz .done
|
---|
298 | call TMPL_NM(Bs2EnterMode_rm)
|
---|
299 | BITS TMPL_BITS
|
---|
300 |
|
---|
301 | ;
|
---|
302 | ; Test exception handler basics using INT3 and #BP.
|
---|
303 | ;
|
---|
304 |
|
---|
305 | call TMPL_NM(TestMemFences)
|
---|
306 | call TMPL_NM(TestBSwap)
|
---|
307 |
|
---|
308 | ;
|
---|
309 | ; Back to real mode.
|
---|
310 | ;
|
---|
311 | call TMPL_NM(Bs2ExitMode)
|
---|
312 | BITS 16
|
---|
313 | call Bs2DisableNX_r86
|
---|
314 |
|
---|
315 | .done:
|
---|
316 | pop ax
|
---|
317 | leave
|
---|
318 | ret
|
---|
319 | ENDPROC TMPL_NM(DoTestsForMode_rm)
|
---|
320 | TMPL_BEGINCODE
|
---|
321 | BITS TMPL_BITS
|
---|
322 |
|
---|
323 | %include "bootsector2-template-footer.mac"
|
---|
324 |
|
---|