VirtualBox

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bootsector2-cpu-hidden-regs-1-template.mac@ 90780

Last change on this file since 90780 was 82968, checked in by vboxsync, 5 years ago

Copyright year updates by scm.

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1; $Id: bootsector2-cpu-hidden-regs-1-template.mac 82968 2020-02-04 10:35:17Z vboxsync $
2;; @file
3; bootsector2 hidden CPU registers - multi mode template.
4;
5
6;
7; Copyright (C) 2007-2020 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; The contents of this file may alternatively be used under the terms
18; of the Common Development and Distribution License Version 1.0
19; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20; VirtualBox OSE distribution, in which case the provisions of the
21; CDDL are applicable instead of those of the GPL.
22;
23; You may elect to license modified versions of this file under the
24; terms and conditions of either the GPL or the CDDL or both.
25;
26
27
28%include "bootsector2-template-header.mac"
29
30;;
31; Helper for reporting several register values at in a sequence.
32;
33BEGINPROC TMPL_NM(TestValueRegSZZ)
34 push sAX
35 push sBX
36
37 mov xBX, xAX
38.next:
39 mov xAX, xBX
40 call TMPL_NM_CMN(TestValueReg)
41.inner_next:
42 inc xBX
43 cmp byte [xBX], 0
44 jne .inner_next
45
46 inc xBX
47 cmp byte [xBX], 0
48 je .done
49 jmp .next
50
51.done
52 pop sBX
53 pop sAX
54 ret
55ENDPROC TMPL_NM(TestValueRegSZZ)
56
57;;
58; Tests various LDTR values
59;
60BEGINPROC TMPL_NM(doLdtrTests)
61 push sAX
62
63 ; The inital LDT.
64 mov sAX, .szLdtrInitial
65 call TMPL_NM(TestValueRegSZZ)
66
67 ; Load our LDT
68 mov eax, BS2_SEL_LDT
69 lldt ax
70 mov sAX, .szLdtrValid
71 call TMPL_NM(TestValueRegSZZ)
72
73 ; NULL LDTR.
74 xor eax, eax
75 lldt ax
76 mov sAX, .szLdtr0
77 call TMPL_NM(TestValueRegSZZ)
78
79 ; NULL(1) LDTR.
80 mov eax, 1
81 lldt ax
82 mov sAX, .szLdtr1
83 call TMPL_NM(TestValueRegSZZ)
84
85 ; NULL(2) LDTR.
86 mov eax, 2
87 lldt ax
88 mov sAX, .szLdtr2
89 call TMPL_NM(TestValueRegSZZ)
90
91 ; NULL(3) LDTR.
92 mov eax, 3
93 lldt ax
94 mov sAX, .szLdtr3
95 call TMPL_NM(TestValueRegSZZ)
96
97.done
98 pop sAX
99 ret
100
101.szLdtrInitial:
102 db 'LDTR(Initial) sel:ldtr', 0
103 db 'LDTR(Initial) base:ldtr_base', 0
104 db 'LDTR(Initial) limit:ldtr_lim', 0
105 db 'LDTR(Initial) attr:ldtr_attr', 0
106 db 0
107.szLdtrValid:
108 db 'LDTR(Valid) sel:ldtr', 0
109 db 'LDTR(Valid) base:ldtr_base', 0
110 db 'LDTR(Valid) limit:ldtr_lim', 0
111 db 'LDTR(Valid) attr:ldtr_attr', 0
112 db 0
113.szLdtr0:
114 db 'LDTR(0) sel:ldtr', 0
115 db 'LDTR(0) base:ldtr_base', 0
116 db 'LDTR(0) limit:ldtr_lim', 0
117 db 'LDTR(0) attr:ldtr_attr', 0
118 db 0
119.szLdtr1:
120 db 'LDTR(1) sel:ldtr', 0
121 db 'LDTR(1) base:ldtr_base', 0
122 db 'LDTR(1) limit:ldtr_lim', 0
123 db 'LDTR(1) attr:ldtr_attr', 0
124 db 0
125.szLdtr2:
126 db 'LDTR(2) sel:ldtr', 0
127 db 'LDTR(2) base:ldtr_base', 0
128 db 'LDTR(2) limit:ldtr_lim', 0
129 db 'LDTR(2) attr:ldtr_attr', 0
130 db 0
131.szLdtr3:
132 db 'LDTR(3) sel:ldtr', 0
133 db 'LDTR(3) base:ldtr_base', 0
134 db 'LDTR(3) limit:ldtr_lim', 0
135 db 'LDTR(3) attr:ldtr_attr', 0
136 db 0
137ENDPROC TMPL_NM(doLdtrTests)
138
139
140;;
141; Tests various LDTR values
142;
143BEGINPROC TMPL_NM(doTrTests)
144 push sAX
145
146 ; Initial TR values.
147 mov sAX, .szTrInitial
148 call TMPL_NM(TestValueRegSZZ)
149 jmp .next1
150.szTrInitial:
151 db 'TR(Initial) sel:tr', 0
152 db 'TR(Initial) base:tr_base', 0
153 db 'TR(Initial) limit:tr_lim', 0
154 db 'TR(Initial) attr:tr_attr', 0
155 db 0
156.next1:
157
158 ; Our TR.
159%ifdef TMPL_CMN_LM
160 mov ax, BS2_SEL_TSS64
161 ltr ax
162 mov sAX, .szTrTss64
163 call TMPL_NM(TestValueRegSZZ)
164 jmp .next2
165.szTrTss64:
166 db 'TR(64) sel:tr', 0
167 db 'TR(64) base:tr_base', 0
168 db 'TR(64) limit:tr_lim', 0
169 db 'TR(64) attr:tr_attr', 0
170 db 0
171
172%elifdef TMPL_PP32
173 mov ax, BS2_SEL_TSS32
174 ltr ax
175 mov sAX, .szTrTss32
176 call TMPL_NM(TestValueRegSZZ)
177 jmp .next2
178.szTrTss32:
179 db 'TR(32) sel:tr', 0
180 db 'TR(32) base:tr_base', 0
181 db 'TR(32) limit:tr_lim', 0
182 db 'TR(32) attr:tr_attr', 0
183 db 0
184;%elifdef TMPL_PP16
185; mov ax, BS2_SEL_TSS16
186; mov sAX, .szTrTss16
187; call TMPL_NM(TestValueRegSZZ)
188%endif
189.next2:
190
191 ; Note! Loading 0 into TR is not possible, unlike with LDTR.
192
193.done
194 pop sAX
195 ret
196ENDPROC TMPL_NM(doTrTests)
197
198
199;;
200; Test loading of NULL selectors.
201;
202BEGINPROC TMPL_NM(doNullSelTests)
203 push sAX
204 push xBX
205 push gs
206
207 mov ax, ss
208 mov gs, ax
209 mov sAX, .szGsSs
210 call TMPL_NM(TestValueRegSZZ)
211
212 xor eax, eax
213 mov gs, ax
214 mov sAX, .szGs0
215 call TMPL_NM(TestValueRegSZZ)
216
217 mov ax, 3
218 mov gs, ax
219 mov sAX, .szGs3
220 call TMPL_NM(TestValueRegSZZ)
221
222%ifdef TMPL_64BIT
223 pushf
224 cli
225 mov bx, ss
226 mov ax, 0
227 mov ss, ax
228 mov sAX, .szSs0
229 call TMPL_NM(TestValueRegSZZ)
230 mov ss, bx
231 popf
232
233 call TMPL_NM_CMN(Bs2ToRing2)
234 mov bx, ss
235 mov ax, 2
236 mov ss, ax
237 mov sAX, .szSs1Ring2
238 call TMPL_NM(TestValueRegSZZ)
239 mov ss, bx
240
241 test byte [g_fCpuAmd], 1
242 jz .not_amd
243 mov ax, 3
244 mov ss, ax
245 mov sAX, .szSs3Ring2
246 call TMPL_NM(TestValueRegSZZ)
247
248.not_amd:
249 call TMPL_NM_CMN(Bs2ToRing0)
250
251%endif
252
253 pop gs
254 pop xBX
255 pop sAX
256 ret
257
258.szGsSs:
259 db 'GS(ss) sel:gs', 0
260 db 'GS(ss) base:gs_base', 0
261 db 'GS(ss) limit:gs_lim', 0
262 db 'GS(ss) attr:gs_attr', 0
263 db 0
264.szGs0:
265 db 'GS(0) sel:gs', 0
266 db 'GS(0) base:gs_base', 0
267 db 'GS(0) limit:gs_lim', 0
268 db 'GS(0) attr:gs_attr', 0
269 db 0
270.szGs3:
271 db 'GS(3) sel:gs', 0
272 db 'GS(3) base:gs_base', 0
273 db 'GS(3) limit:gs_lim', 0
274 db 'GS(3) attr:gs_attr', 0
275 db 0
276%ifdef TMPL_64BIT
277.szSs0:
278 db 'SS(0) sel:ss', 0
279 db 'SS(0) base:ss_base', 0
280 db 'SS(0) limit:ss_lim', 0
281 db 'SS(0) attr:ss_attr', 0
282 db 0
283.szSs1Ring2
284 db 'ring-2 SS(2) sel:ss', 0
285 db 'ring-2 SS(2) base:ss_base', 0
286 db 'ring-2 SS(2) limit:ss_lim', 0
287 db 'ring-2 SS(2) attr:ss_attr', 0
288 db 0
289.szSs3Ring2
290 db 'ring-2 SS(3) sel:ss', 0
291 db 'ring-2 SS(3) base:ss_base', 0
292 db 'ring-2 SS(3) limit:ss_lim', 0
293 db 'ring-2 SS(3) attr:ss_attr', 0
294 db 0
295%endif
296ENDPROC TMPL_NM(doNullSelTests)
297
298
299BEGINPROC TMPL_NM(doTestsWorker)
300 push sAX
301
302 mov xAX, .s_szSubTest
303 call TMPL_NM_CMN(TestSub)
304 call TMPL_NM(doLdtrTests)
305 call TMPL_NM(doTrTests)
306 call TMPL_NM(doNullSelTests)
307
308.done
309 pop sAX
310 ret
311
312.s_szSubTest:
313 db TMPL_MODE_STR, 0
314ENDPROC TMPL_NM(doTestsWorker)
315
316
317;;
318; Do the tests for this mode.
319;
320; @uses nothing
321;
322BEGINCODELOW
323BITS 16
324BEGINPROC TMPL_NM(doTests_rm)
325 call TMPL_NM(Bs2IsModeSupported_rm)
326 jz .done
327 call TMPL_NM(Bs2EnterMode_rm)
328BITS TMPL_BITS
329
330 call TMPL_NM(doTestsWorker)
331
332 call TMPL_NM(Bs2ExitMode)
333BITS 16
334.done:
335 ret
336ENDPROC TMPL_NM(doTests_rm)
337TMPL_BEGINCODE
338BITS TMPL_BITS
339
340
341%include "bootsector2-template-footer.mac"
342
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