tstX86-1A.asm@ 40040

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1	; $Id: tstX86-1A.asm 40037 2012-02-08 11:35:44Z vboxsync $
2	;; @file
3	; X86 instruction set exploration/testcase #1.
4	;
5
6	;
7	; Copyright (C) 2011-2012 Oracle Corporation
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17
18
19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
20	; Header Files ;
21	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
22	%include "iprt/asmdefs.mac"
23	%include "iprt/x86.mac"
24
25	;; @todo Move this to a header?
26	struc TRAPINFO
27	.uTrapPC RTCCPTR_RES 1
28	.uResumePC RTCCPTR_RES 1
29	.u8TrapNo resb 1
30	.cbInstr resb 1
31	.au8Padding resb (RTCCPTR_CB*2 - 2)
32	endstruc
33
34
35	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
36	; Global Variables ;
37	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38	BEGINDATA
39	extern NAME(g_pbEfPage)
40	extern NAME(g_pbEfExecPage)
41
42	GLOBALNAME g_szAlpha
43	db "abcdefghijklmnopqrstuvwxyz", 0
44	g_szAlpha_end:
45	%define g_cchAlpha (g_szAlpha_end - NAME(g_szAlpha))
46	db 0, 0, 0,
47
48	;;
49	; The last global data item. We build this as we write the code.
50	GLOBALNAME g_aTrapInfo
51
52
53	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54	; Defined Constants And Macros ;
55	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
56	%define X86_XCPT_UD 6
57	%define X86_XCPT_GP 13
58	%define X86_XCPT_PF 14
59
60	%define PAGE_SIZE 0x1000
61
62	;; Reference a variable
63	%ifdef RT_ARCH_AMD64
64	%define REF(a_Name) [a_Name wrt rip]
65	%else
66	%define REF(a_Name) [a_Name]
67	%endif
68
69	;; Reference a global variable
70	%ifdef RT_ARCH_AMD64
71	%define REF_GLOBAL(a_Name) [NAME(a_Name) wrt rip]
72	%else
73	%define REF_GLOBAL(a_Name) [NAME(a_Name)]
74	%endif
75
76	;;
77	; Macro for recording a trapping instruction (simple).
78	;
79	; @param 1 The trap number.
80	; @param 2+ The instruction which should trap.
81	%macro ShouldTrap 2+
82	%%trap:
83	%2
84	%%trap_end:
85	mov eax, __LINE__
86	jmp .return
87	BEGINDATA
88	%%trapinfo: istruc TRAPINFO
89	at TRAPINFO.uTrapPC, RTCCPTR_DEF %%trap
90	at TRAPINFO.uResumePC, RTCCPTR_DEF %%resume
91	at TRAPINFO.u8TrapNo, db %1
92	at TRAPINFO.cbInstr, db (%%trap_end - %%trap)
93	iend
94	BEGINCODE
95	%%resume:
96	%endmacro
97
98
99	;;
100	; Function prologue saving all registers except EAX.
101	;
102	%macro SAVE_ALL_PROLOGUE 0
103	push xBP
104	mov xBP, xSP
105	pushf
106	push xBX
107	push xCX
108	push xDX
109	push xSI
110	push xDI
111	%ifdef RT_ARCH_AMD64
112	push r8
113	push r9
114	push r10
115	push r11
116	push r12
117	push r13
118	push r14
119	push r15
120	%endif
121	%endmacro
122
123
124	;;
125	; Function epilogue restoring all regisers except EAX.
126	;
127	%macro SAVE_ALL_EPILOGUE 0
128	%ifdef RT_ARCH_AMD64
129	pop r15
130	pop r14
131	pop r13
132	pop r12
133	pop r11
134	pop r10
135	pop r9
136	pop r8
137	%endif
138	pop xDI
139	pop xSI
140	pop xDX
141	pop xCX
142	pop xBX
143	popf
144	leave
145	%endmacro
146
147
148
149
150	BEGINCODE
151
152	;;
153	; Loads all general registers except xBP and xSP with unique values.
154	;
155	x861_LoadUniqueRegValues:
156	%ifdef RT_ARCH_AMD64
157	mov rax, 00000000000000000h
158	mov rcx, 01111111111111111h
159	mov rdx, 02222222222222222h
160	mov rbx, 03333333333333333h
161	mov rsi, 06666666666666666h
162	mov rdi, 07777777777777777h
163	mov r8, 08888888888888888h
164	mov r9, 09999999999999999h
165	mov r10, 0aaaaaaaaaaaaaaaah
166	mov r11, 0bbbbbbbbbbbbbbbbh
167	mov r12, 0cccccccccccccccch
168	mov r13, 0ddddddddddddddddh
169	mov r14, 0eeeeeeeeeeeeeeeeh
170	mov r15, 0ffffffffffffffffh
171	%else
172	mov eax, 000000000h
173	mov ecx, 011111111h
174	mov edx, 022222222h
175	mov ebx, 033333333h
176	mov esi, 066666666h
177	mov edi, 077777777h
178	%endif
179	ret
180	; end x861_LoadUniqueRegValues
181
182
183	;;
184	; Clears all general registers except xBP and xSP.
185	;
186	x861_ClearRegisters:
187	xor eax, eax
188	xor ebx, ebx
189	xor ecx, ecx
190	xor edx, edx
191	xor esi, esi
192	xor edi, edi
193	%ifdef RT_ARCH_AMD64
194	xor r8, r8
195	xor r9, r9
196	xor r10, r10
197	xor r11, r11
198	xor r12, r12
199	xor r13, r13
200	xor r14, r14
201	xor r15, r15
202	%endif
203	ret
204	; x861_ClearRegisters
205
206
207	;;
208	; Loads all general, MMX and SSE registers except xBP and xSP with unique values.
209	;
210	x861_LoadUniqueRegValuesSSE:
211	movq mm0, REF(._mm0)
212	movq mm1, REF(._mm1)
213	movq mm2, REF(._mm2)
214	movq mm3, REF(._mm3)
215	movq mm4, REF(._mm4)
216	movq mm5, REF(._mm5)
217	movq mm6, REF(._mm6)
218	movq mm7, REF(._mm7)
219	movdqu xmm0, REF(._xmm0)
220	movdqu xmm1, REF(._xmm1)
221	movdqu xmm2, REF(._xmm2)
222	movdqu xmm3, REF(._xmm3)
223	movdqu xmm4, REF(._xmm4)
224	movdqu xmm5, REF(._xmm5)
225	movdqu xmm6, REF(._xmm6)
226	movdqu xmm7, REF(._xmm7)
227	%ifdef RT_ARCH_AMD64
228	movdqu xmm8, REF(._xmm8)
229	movdqu xmm9, REF(._xmm9)
230	movdqu xmm10, REF(._xmm10)
231	movdqu xmm11, REF(._xmm11)
232	movdqu xmm12, REF(._xmm12)
233	movdqu xmm13, REF(._xmm13)
234	movdqu xmm14, REF(._xmm14)
235	movdqu xmm15, REF(._xmm15)
236	%endif
237	call x861_LoadUniqueRegValues
238	ret
239	._mm0: times 8 db 040h
240	._mm1: times 8 db 041h
241	._mm2: times 8 db 042h
242	._mm3: times 8 db 043h
243	._mm4: times 8 db 044h
244	._mm5: times 8 db 045h
245	._mm6: times 8 db 046h
246	._mm7: times 8 db 047h
247	._xmm0: times 16 db 080h
248	._xmm1: times 16 db 081h
249	._xmm2: times 16 db 082h
250	._xmm3: times 16 db 083h
251	._xmm4: times 16 db 084h
252	._xmm5: times 16 db 085h
253	._xmm6: times 16 db 086h
254	._xmm7: times 16 db 087h
255	%ifdef RT_ARCH_AMD64
256	._xmm8: times 16 db 088h
257	._xmm9: times 16 db 089h
258	._xmm10: times 16 db 08ah
259	._xmm11: times 16 db 08bh
260	._xmm12: times 16 db 08ch
261	._xmm13: times 16 db 08dh
262	._xmm14: times 16 db 08eh
263	._xmm15: times 16 db 08fh
264	%endif
265	; end x861_LoadUniqueRegValuesSSE
266
267
268	;;
269	; Clears all general, MMX and SSE registers except xBP and xSP.
270	;
271	x861_ClearRegistersSSE:
272	call x861_ClearRegisters
273	movq mm0, REF(.zero)
274	movq mm1, REF(.zero)
275	movq mm2, REF(.zero)
276	movq mm3, REF(.zero)
277	movq mm4, REF(.zero)
278	movq mm5, REF(.zero)
279	movq mm6, REF(.zero)
280	movq mm7, REF(.zero)
281	movdqu xmm0, REF(.zero)
282	movdqu xmm1, REF(.zero)
283	movdqu xmm2, REF(.zero)
284	movdqu xmm3, REF(.zero)
285	movdqu xmm4, REF(.zero)
286	movdqu xmm5, REF(.zero)
287	movdqu xmm6, REF(.zero)
288	movdqu xmm7, REF(.zero)
289	%ifdef RT_ARCH_AMD64
290	movdqu xmm8, REF(.zero)
291	movdqu xmm9, REF(.zero)
292	movdqu xmm10, REF(.zero)
293	movdqu xmm11, REF(.zero)
294	movdqu xmm12, REF(.zero)
295	movdqu xmm13, REF(.zero)
296	movdqu xmm14, REF(.zero)
297	movdqu xmm15, REF(.zero)
298	%endif
299	call x861_LoadUniqueRegValues
300	ret
301
302	ret
303	.zero times 16 db 000h
304	; x861_ClearRegistersSSE
305
306
307	BEGINPROC x861_Test1
308	push xBP
309	mov xBP, xSP
310	pushf
311	push xBX
312	push xCX
313	push xDX
314	push xSI
315	push xDI
316	%ifdef RT_ARCH_AMD64
317	push r8
318	push r9
319	push r10
320	push r11
321	push r12
322	push r13
323	push r14
324	push r15
325	%endif
326
327	;
328	; Odd push behavior
329	;
330	%if 0 ; Seems to be so on AMD only
331	%ifdef RT_ARCH_X86
332	; upper word of a 'push cs' is cleared.
333	mov eax, __LINE__
334	mov dword [esp - 4], 0f0f0f0fh
335	push cs
336	pop ecx
337	mov bx, cs
338	and ebx, 0000ffffh
339	cmp ecx, ebx
340	jne .failed
341
342	; upper word of a 'push ds' is cleared.
343	mov eax, __LINE__
344	mov dword [esp - 4], 0f0f0f0fh
345	push ds
346	pop ecx
347	mov bx, ds
348	and ebx, 0000ffffh
349	cmp ecx, ebx
350	jne .failed
351
352	; upper word of a 'push es' is cleared.
353	mov eax, __LINE__
354	mov dword [esp - 4], 0f0f0f0fh
355	push es
356	pop ecx
357	mov bx, es
358	and ebx, 0000ffffh
359	cmp ecx, ebx
360	jne .failed
361	%endif ; RT_ARCH_X86
362
363	; The upper part of a 'push fs' is cleared.
364	mov eax, __LINE__
365	xor ecx, ecx
366	not xCX
367	push xCX
368	pop xCX
369	push fs
370	pop xCX
371	mov bx, fs
372	and ebx, 0000ffffh
373	cmp xCX, xBX
374	jne .failed
375
376	; The upper part of a 'push gs' is cleared.
377	mov eax, __LINE__
378	xor ecx, ecx
379	not xCX
380	push xCX
381	pop xCX
382	push gs
383	pop xCX
384	mov bx, gs
385	and ebx, 0000ffffh
386	cmp xCX, xBX
387	jne .failed
388	%endif
389
390	%ifdef RT_ARCH_AMD64
391	; REX.B works with 'push r64'.
392	call x861_LoadUniqueRegValues
393	mov eax, __LINE__
394	push rcx
395	pop rdx
396	cmp rdx, rcx
397	jne .failed
398
399	call x861_LoadUniqueRegValues
400	mov eax, __LINE__
401	db 041h ; REX.B
402	push rcx
403	pop rdx
404	cmp rdx, r9
405	jne .failed
406
407	call x861_LoadUniqueRegValues
408	mov eax, __LINE__
409	db 042h ; REX.X
410	push rcx
411	pop rdx
412	cmp rdx, rcx
413	jne .failed
414
415	call x861_LoadUniqueRegValues
416	mov eax, __LINE__
417	db 044h ; REX.R
418	push rcx
419	pop rdx
420	cmp rdx, rcx
421	jne .failed
422
423	call x861_LoadUniqueRegValues
424	mov eax, __LINE__
425	db 048h ; REX.W
426	push rcx
427	pop rdx
428	cmp rdx, rcx
429	jne .failed
430
431	call x861_LoadUniqueRegValues
432	mov eax, __LINE__
433	db 04fh ; REX.*
434	push rcx
435	pop rdx
436	cmp rdx, r9
437	jne .failed
438	%endif
439
440	;
441	; Zero extening when moving from a segreg as well as memory access sizes.
442	;
443	call x861_LoadUniqueRegValues
444	mov eax, __LINE__
445	mov ecx, ds
446	shr xCX, 16
447	cmp xCX, 0
448	jnz .failed
449
450	%ifdef RT_ARCH_AMD64
451	call x861_LoadUniqueRegValues
452	mov eax, __LINE__
453	mov rcx, ds
454	shr rcx, 16
455	cmp rcx, 0
456	jnz .failed
457	%endif
458
459	call x861_LoadUniqueRegValues
460	mov eax, __LINE__
461	mov xDX, xCX
462	mov cx, ds
463	shr xCX, 16
464	shr xDX, 16
465	cmp xCX, xDX
466	jnz .failed
467
468	; Loading is always a word access.
469	mov eax, __LINE__
470	mov xDI, REF_GLOBAL(g_pbEfPage)
471	lea xDI, [xDI + 0x1000 - 2]
472	mov xDX, es
473	mov [xDI], dx
474	mov es, [xDI] ; should not crash
475
476	; Saving is always a word access.
477	mov eax, __LINE__
478	mov xDI, REF_GLOBAL(g_pbEfPage)
479	mov dword [xDI + 0x1000 - 4], -1
480	mov [xDI + 0x1000 - 2], ss ; Should not crash.
481	mov bx, ss
482	mov cx, [xDI + 0x1000 - 2]
483	cmp cx, bx
484	jne .failed
485
486	%ifdef RT_ARCH_AMD64
487	; Check that the rex.R and rex.W bits don't have any influence over a memory write.
488	call x861_ClearRegisters
489	mov eax, __LINE__
490	mov xDI, REF_GLOBAL(g_pbEfPage)
491	mov dword [xDI + 0x1000 - 4], -1
492	db 04ah
493	mov [xDI + 0x1000 - 2], ss ; Should not crash.
494	mov bx, ss
495	mov cx, [xDI + 0x1000 - 2]
496	cmp cx, bx
497	jne .failed
498	%endif
499
500
501	;
502	; Check what happens when both string prefixes are used.
503	;
504	cld
505	mov dx, ds
506	mov es, dx
507
508	; check that repne scasb (al=0) behaves like expected.
509	lea xDI, REF_GLOBAL(g_szAlpha)
510	xor eax, eax ; find the end
511	mov ecx, g_cchAlpha + 1
512	repne scasb
513	cmp ecx, 1
514	mov eax, __LINE__
515	jne .failed
516
517	; check that repe scasb (al=0) behaves like expected.
518	lea xDI, REF_GLOBAL(g_szAlpha)
519	xor eax, eax ; find the end
520	mov ecx, g_cchAlpha + 1
521	repe scasb
522	cmp ecx, g_cchAlpha
523	mov eax, __LINE__
524	jne .failed
525
526	; repne is last, it wins.
527	lea xDI, REF_GLOBAL(g_szAlpha)
528	xor eax, eax ; find the end
529	mov ecx, g_cchAlpha + 1
530	db 0f3h ; repe - ignored
531	db 0f2h ; repne
532	scasb
533	cmp ecx, 1
534	mov eax, __LINE__
535	jne .failed
536
537	; repe is last, it wins.
538	lea xDI, REF_GLOBAL(g_szAlpha)
539	xor eax, eax ; find the end
540	mov ecx, g_cchAlpha + 1
541	db 0f2h ; repne - ignored
542	db 0f3h ; repe
543	scasb
544	cmp ecx, g_cchAlpha
545	mov eax, __LINE__
546	jne .failed
547
548	;
549	; Check if stosb works with both prefixes.
550	;
551	cld
552	mov dx, ds
553	mov es, dx
554	mov xDI, REF_GLOBAL(g_pbEfPage)
555	xor eax, eax
556	mov ecx, 01000h
557	rep stosb
558
559	mov xDI, REF_GLOBAL(g_pbEfPage)
560	mov ecx, 4
561	mov eax, 0ffh
562	db 0f2h ; repne
563	stosb
564	mov eax, __LINE__
565	cmp ecx, 0
566	jne .failed
567	mov eax, __LINE__
568	mov xDI, REF_GLOBAL(g_pbEfPage)
569	cmp dword [xDI], 0ffffffffh
570	jne .failed
571	cmp dword [xDI+4], 0
572	jne .failed
573
574	mov xDI, REF_GLOBAL(g_pbEfPage)
575	mov ecx, 4
576	mov eax, 0feh
577	db 0f3h ; repe
578	stosb
579	mov eax, __LINE__
580	cmp ecx, 0
581	jne .failed
582	mov eax, __LINE__
583	mov xDI, REF_GLOBAL(g_pbEfPage)
584	cmp dword [xDI], 0fefefefeh
585	jne .failed
586	cmp dword [xDI+4], 0
587	jne .failed
588
589	;
590	; String operations shouldn't crash because of an invalid address if rCX is 0.
591	;
592	mov eax, __LINE__
593	cld
594	mov dx, ds
595	mov es, dx
596	mov xDI, REF_GLOBAL(g_pbEfPage)
597	xor xCX, xCX
598	rep stosb ; no trap
599
600	;
601	; INS/OUTS will trap in ring-3 even when rCX is 0. (ASSUMES IOPL < 3)
602	;
603	mov eax, __LINE__
604	cld
605	mov dx, ss
606	mov ss, dx
607	mov xDI, xSP
608	xor xCX, xCX
609	ShouldTrap X86_XCPT_GP, rep insb
610
611	;
612	; SMSW can get to the whole of CR0.
613	;
614	mov eax, __LINE__
615	xor xBX, xBX
616	smsw xBX
617	test ebx, X86_CR0_PG
618	jz .failed
619	test ebx, X86_CR0_PE
620	jz .failed
621
622	;
623	; Will the CPU decode the whole r/m+sib stuff before signalling a lock
624	; prefix error? Use the EF exec page and a LOCK ADD CL,[rDI + disp32]
625	; instruction at the very end of it.
626	;
627	mov eax, __LINE__
628	mov xDI, REF_GLOBAL(g_pbEfExecPage)
629	add xDI, 1000h - 8h
630	mov byte [xDI+0], 0f0h
631	mov byte [xDI+1], 002h
632	mov byte [xDI+2], 08fh
633	mov dword [xDI+3], 000000000h
634	mov byte [xDI+7], 0cch
635	ShouldTrap X86_XCPT_UD, call xDI
636
637	mov eax, __LINE__
638	mov xDI, REF_GLOBAL(g_pbEfExecPage)
639	add xDI, 1000h - 7h
640	mov byte [xDI+0], 0f0h
641	mov byte [xDI+1], 002h
642	mov byte [xDI+2], 08Fh
643	mov dword [xDI+3], 000000000h
644	ShouldTrap X86_XCPT_UD, call xDI
645
646	mov eax, __LINE__
647	mov xDI, REF_GLOBAL(g_pbEfExecPage)
648	add xDI, 1000h - 4h
649	mov byte [xDI+0], 0f0h
650	mov byte [xDI+1], 002h
651	mov byte [xDI+2], 08Fh
652	mov byte [xDI+3], 000h
653	ShouldTrap X86_XCPT_PF, call xDI
654
655	mov eax, __LINE__
656	mov xDI, REF_GLOBAL(g_pbEfExecPage)
657	add xDI, 1000h - 6h
658	mov byte [xDI+0], 0f0h
659	mov byte [xDI+1], 002h
660	mov byte [xDI+2], 08Fh
661	mov byte [xDI+3], 00h
662	mov byte [xDI+4], 00h
663	mov byte [xDI+5], 00h
664	ShouldTrap X86_XCPT_PF, call xDI
665
666	mov eax, __LINE__
667	mov xDI, REF_GLOBAL(g_pbEfExecPage)
668	add xDI, 1000h - 5h
669	mov byte [xDI+0], 0f0h
670	mov byte [xDI+1], 002h
671	mov byte [xDI+2], 08Fh
672	mov byte [xDI+3], 00h
673	mov byte [xDI+4], 00h
674	ShouldTrap X86_XCPT_PF, call xDI
675
676	mov eax, __LINE__
677	mov xDI, REF_GLOBAL(g_pbEfExecPage)
678	add xDI, 1000h - 4h
679	mov byte [xDI+0], 0f0h
680	mov byte [xDI+1], 002h
681	mov byte [xDI+2], 08Fh
682	mov byte [xDI+3], 00h
683	ShouldTrap X86_XCPT_PF, call xDI
684
685	mov eax, __LINE__
686	mov xDI, REF_GLOBAL(g_pbEfExecPage)
687	add xDI, 1000h - 3h
688	mov byte [xDI+0], 0f0h
689	mov byte [xDI+1], 002h
690	mov byte [xDI+2], 08Fh
691	ShouldTrap X86_XCPT_PF, call xDI
692
693	mov eax, __LINE__
694	mov xDI, REF_GLOBAL(g_pbEfExecPage)
695	add xDI, 1000h - 2h
696	mov byte [xDI+0], 0f0h
697	mov byte [xDI+1], 002h
698	ShouldTrap X86_XCPT_PF, call xDI
699
700	mov eax, __LINE__
701	mov xDI, REF_GLOBAL(g_pbEfExecPage)
702	add xDI, 1000h - 1h
703	mov byte [xDI+0], 0f0h
704	ShouldTrap X86_XCPT_PF, call xDI
705
706
707
708	.success:
709	xor eax, eax
710	.return:
711	%ifdef RT_ARCH_AMD64
712	pop r15
713	pop r14
714	pop r13
715	pop r12
716	pop r11
717	pop r10
718	pop r9
719	pop r8
720	%endif
721	pop xDI
722	pop xSI
723	pop xDX
724	pop xCX
725	pop xBX
726	popf
727	leave
728	ret
729
730	.failed2:
731	mov eax, -1
732	.failed:
733	jmp .return
734	ENDPROC x861_Test1
735
736
737
738	;;
739	; Tests the effect of prefix order in group 14.
740	;
741	BEGINPROC x861_Test2
742	SAVE_ALL_PROLOGUE
743
744	; Check testcase preconditions.
745	call x861_LoadUniqueRegValuesSSE
746	mov eax, __LINE__
747	db 00Fh, 073h, 0D0h, 080h ; psrlq mm0, 128
748	call .check_mm0_zero_and_xmm0_nz
749
750	call x861_LoadUniqueRegValuesSSE
751	mov eax, __LINE__
752	db 066h, 00Fh, 073h, 0D0h, 080h ; psrlq xmm0, 128
753	call .check_xmm0_zero_and_mm0_nz
754
755
756	;
757	; Real test - Inject other prefixes before the 066h and see what
758	; happens.
759	;
760
761	; General checks that order does not matter, etc.
762	call x861_LoadUniqueRegValuesSSE
763	mov eax, __LINE__
764	db 026h, 066h, 00Fh, 073h, 0D0h, 080h
765	call .check_xmm0_zero_and_mm0_nz
766
767	call x861_LoadUniqueRegValuesSSE
768	mov eax, __LINE__
769	db 066h, 026h, 00Fh, 073h, 0D0h, 080h
770	call .check_xmm0_zero_and_mm0_nz
771
772	call x861_LoadUniqueRegValuesSSE
773	mov eax, __LINE__
774	db 066h, 067h, 00Fh, 073h, 0D0h, 080h
775	call .check_xmm0_zero_and_mm0_nz
776
777	call x861_LoadUniqueRegValuesSSE
778	mov eax, __LINE__
779	db 067h, 066h, 00Fh, 073h, 0D0h, 080h
780	call .check_xmm0_zero_and_mm0_nz
781
782	call x861_LoadUniqueRegValuesSSE
783	mov eax, __LINE__
784	db 067h, 066h, 065h, 00Fh, 073h, 0D0h, 080h
785	call .check_xmm0_zero_and_mm0_nz
786
787	%ifdef RT_ARCH_AMD64
788	call x861_LoadUniqueRegValuesSSE
789	mov eax, __LINE__
790	db 048h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.W
791	call .check_xmm0_zero_and_mm0_nz
792
793	call x861_LoadUniqueRegValuesSSE
794	mov eax, __LINE__
795	db 044h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.R
796	call .check_xmm0_zero_and_mm0_nz
797
798	call x861_LoadUniqueRegValuesSSE
799	mov eax, __LINE__
800	db 042h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.X
801	call .check_xmm0_zero_and_mm0_nz
802
803	; Actually for REX, order does matter if the prefix is used.
804	call x861_LoadUniqueRegValuesSSE
805	mov eax, __LINE__
806	db 041h, 066h, 00Fh, 073h, 0D0h, 080h ; REX.B
807	call .check_xmm0_zero_and_mm0_nz
808
809	call x861_LoadUniqueRegValuesSSE
810	mov eax, __LINE__
811	db 066h, 041h, 00Fh, 073h, 0D0h, 080h ; REX.B
812	call .check_xmm8_zero_and_xmm0_nz
813	%endif
814
815	; Check all ignored prefixes (repeates some of the above).
816	call x861_LoadUniqueRegValuesSSE
817	mov eax, __LINE__
818	db 066h, 026h, 00Fh, 073h, 0D0h, 080h ; es
819	call .check_xmm0_zero_and_mm0_nz
820
821	call x861_LoadUniqueRegValuesSSE
822	mov eax, __LINE__
823	db 066h, 065h, 00Fh, 073h, 0D0h, 080h ; gs
824	call .check_xmm0_zero_and_mm0_nz
825
826	call x861_LoadUniqueRegValuesSSE
827	mov eax, __LINE__
828	db 066h, 064h, 00Fh, 073h, 0D0h, 080h ; fs
829	call .check_xmm0_zero_and_mm0_nz
830
831	call x861_LoadUniqueRegValuesSSE
832	mov eax, __LINE__
833	db 066h, 02eh, 00Fh, 073h, 0D0h, 080h ; cs
834	call .check_xmm0_zero_and_mm0_nz
835
836	call x861_LoadUniqueRegValuesSSE
837	mov eax, __LINE__
838	db 066h, 036h, 00Fh, 073h, 0D0h, 080h ; ss
839	call .check_xmm0_zero_and_mm0_nz
840
841	call x861_LoadUniqueRegValuesSSE
842	mov eax, __LINE__
843	db 066h, 03eh, 00Fh, 073h, 0D0h, 080h ; ds
844	call .check_xmm0_zero_and_mm0_nz
845
846	call x861_LoadUniqueRegValuesSSE
847	mov eax, __LINE__
848	db 066h, 067h, 00Fh, 073h, 0D0h, 080h ; addr size
849	call .check_xmm0_zero_and_mm0_nz
850
851	%ifdef RT_ARCH_AMD64
852	call x861_LoadUniqueRegValuesSSE
853	mov eax, __LINE__
854	db 066h, 048h, 00Fh, 073h, 0D0h, 080h ; REX.W
855	call .check_xmm0_zero_and_mm0_nz
856
857	call x861_LoadUniqueRegValuesSSE
858	mov eax, __LINE__
859	db 066h, 044h, 00Fh, 073h, 0D0h, 080h ; REX.R
860	call .check_xmm0_zero_and_mm0_nz
861
862	call x861_LoadUniqueRegValuesSSE
863	mov eax, __LINE__
864	db 066h, 042h, 00Fh, 073h, 0D0h, 080h ; REX.X
865	call .check_xmm0_zero_and_mm0_nz
866
867	call x861_LoadUniqueRegValuesSSE
868	mov eax, __LINE__
869	db 066h, 041h, 00Fh, 073h, 0D0h, 080h ; REX.B - has actual effect on the instruction.
870	call .check_xmm8_zero_and_xmm0_nz
871	%endif
872
873	; Repeated prefix until we hit the max opcode limit.
874	call x861_LoadUniqueRegValuesSSE
875	mov eax, __LINE__
876	db 066h, 066h, 00Fh, 073h, 0D0h, 080h
877	call .check_xmm0_zero_and_mm0_nz
878
879	call x861_LoadUniqueRegValuesSSE
880	mov eax, __LINE__
881	db 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
882	call .check_xmm0_zero_and_mm0_nz
883
884	call x861_LoadUniqueRegValuesSSE
885	mov eax, __LINE__
886	db 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
887	call .check_xmm0_zero_and_mm0_nz
888
889	call x861_LoadUniqueRegValuesSSE
890	mov eax, __LINE__
891	db 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
892	call .check_xmm0_zero_and_mm0_nz
893
894	ShouldTrap X86_XCPT_GP, db 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 066h, 00Fh, 073h, 0D0h, 080h
895
896	%ifdef RT_ARCH_AMD64
897	; Repeated REX is parsed, but only the last byte matters.
898	call x861_LoadUniqueRegValuesSSE
899	mov eax, __LINE__
900	db 066h, 041h, 048h, 00Fh, 073h, 0D0h, 080h ; REX.B, REX.W
901	call .check_xmm0_zero_and_mm0_nz
902
903	call x861_LoadUniqueRegValuesSSE
904	mov eax, __LINE__
905	db 066h, 048h, 041h, 00Fh, 073h, 0D0h, 080h ; REX.B, REX.W
906	call .check_xmm8_zero_and_xmm0_nz
907
908	call x861_LoadUniqueRegValuesSSE
909	mov eax, __LINE__
910	db 066h, 048h, 044h, 042h, 048h, 044h, 042h, 048h, 044h, 042h, 041h, 00Fh, 073h, 0D0h, 080h
911	call .check_xmm8_zero_and_xmm0_nz
912
913	call x861_LoadUniqueRegValuesSSE
914	mov eax, __LINE__
915	db 066h, 041h, 041h, 041h, 041h, 041h, 041h, 041h, 041h, 041h, 04eh, 00Fh, 073h, 0D0h, 080h
916	call .check_xmm0_zero_and_mm0_nz
917	%endif
918
919	; Undefined sequences with prefixes that counts.
920	ShouldTrap X86_XCPT_UD, db 0f0h, 066h, 00Fh, 073h, 0D0h, 080h ; LOCK
921	ShouldTrap X86_XCPT_UD, db 0f2h, 066h, 00Fh, 073h, 0D0h, 080h ; REPNZ
922	ShouldTrap X86_XCPT_UD, db 0f3h, 066h, 00Fh, 073h, 0D0h, 080h ; REPZ
923	ShouldTrap X86_XCPT_UD, db 066h, 0f2h, 00Fh, 073h, 0D0h, 080h
924	ShouldTrap X86_XCPT_UD, db 066h, 0f3h, 00Fh, 073h, 0D0h, 080h
925	ShouldTrap X86_XCPT_UD, db 066h, 0f3h, 0f2h, 00Fh, 073h, 0D0h, 080h
926	ShouldTrap X86_XCPT_UD, db 066h, 0f2h, 0f3h, 00Fh, 073h, 0D0h, 080h
927	ShouldTrap X86_XCPT_UD, db 0f2h, 066h, 0f3h, 00Fh, 073h, 0D0h, 080h
928	ShouldTrap X86_XCPT_UD, db 0f3h, 066h, 0f2h, 00Fh, 073h, 0D0h, 080h
929	ShouldTrap X86_XCPT_UD, db 0f3h, 0f2h, 066h, 00Fh, 073h, 0D0h, 080h
930	ShouldTrap X86_XCPT_UD, db 0f2h, 0f3h, 066h, 00Fh, 073h, 0D0h, 080h
931	ShouldTrap X86_XCPT_UD, db 0f0h, 0f2h, 066h, 0f3h, 00Fh, 073h, 0D0h, 080h
932	ShouldTrap X86_XCPT_UD, db 0f0h, 0f3h, 066h, 0f2h, 00Fh, 073h, 0D0h, 080h
933	ShouldTrap X86_XCPT_UD, db 0f0h, 0f3h, 0f2h, 066h, 00Fh, 073h, 0D0h, 080h
934	ShouldTrap X86_XCPT_UD, db 0f0h, 0f2h, 0f3h, 066h, 00Fh, 073h, 0D0h, 080h
935
936	.success:
937	xor eax, eax
938	.return:
939	SAVE_ALL_EPILOGUE
940	ret
941
942	.check_xmm0_zero_and_mm0_nz:
943	sub xSP, 20h
944	movdqu [xSP], xmm0
945	cmp dword [xSP], 0
946	jne .failed3
947	cmp dword [xSP + 4], 0
948	jne .failed3
949	cmp dword [xSP + 8], 0
950	jne .failed3
951	cmp dword [xSP + 12], 0
952	jne .failed3
953	movq [xSP], mm0
954	cmp dword [xSP], 0
955	je .failed3
956	cmp dword [xSP + 4], 0
957	je .failed3
958	add xSP, 20h
959	ret
960
961	.check_mm0_zero_and_xmm0_nz:
962	sub xSP, 20h
963	movq [xSP], mm0
964	cmp dword [xSP], 0
965	jne .failed3
966	cmp dword [xSP + 4], 0
967	jne .failed3
968	movdqu [xSP], xmm0
969	cmp dword [xSP], 0
970	je .failed3
971	cmp dword [xSP + 4], 0
972	je .failed3
973	cmp dword [xSP + 8], 0
974	je .failed3
975	cmp dword [xSP + 12], 0
976	je .failed3
977	add xSP, 20h
978	ret
979
980	%ifdef RT_ARCH_AMD64
981	.check_xmm8_zero_and_xmm0_nz:
982	sub xSP, 20h
983	movdqu [xSP], xmm8
984	cmp dword [xSP], 0
985	jne .failed3
986	cmp dword [xSP + 4], 0
987	jne .failed3
988	cmp dword [xSP + 8], 0
989	jne .failed3
990	cmp dword [xSP + 12], 0
991	jne .failed3
992	movdqu [xSP], xmm0
993	cmp dword [xSP], 0
994	je .failed3
995	cmp dword [xSP + 4], 0
996	je .failed3
997	cmp dword [xSP + 8], 0
998	je .failed3
999	cmp dword [xSP + 12], 0
1000	je .failed3
1001	add xSP, 20h
1002	ret
1003	%endif
1004
1005	.failed3:
1006	add xSP, 20h + xS
1007	jmp .return
1008
1009
1010	ENDPROC x861_Test2
1011
1012
1013	;;
1014	; Tests how much fxsave and fxrstor actually accesses of their 512 memory
1015	; operand.
1016	;
1017	BEGINPROC x861_Test3
1018	SAVE_ALL_PROLOGUE
1019	call x861_LoadUniqueRegValuesSSE
1020	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1021
1022	; Check testcase preconditions.
1023	fxsave [xDI]
1024	fxrstor [xDI]
1025
1026	add xDI, PAGE_SIZE - 512
1027	mov xSI, xDI
1028	fxsave [xDI]
1029	fxrstor [xDI]
1030
1031	; 464:511 are available to software use. Check that they are left
1032	; untouched by fxsave.
1033	mov eax, 0aabbccddh
1034	mov ecx, 512 / 4
1035	cld
1036	rep stosd
1037	mov xDI, xSI
1038	fxsave [xDI]
1039
1040	mov ebx, 512
1041	.chech_software_area_loop:
1042	cmp [xDI + xBX - 4], eax
1043	jne .chech_software_area_done
1044	sub ebx, 4
1045	jmp .chech_software_area_loop
1046	.chech_software_area_done:
1047	cmp ebx, 464
1048	mov eax, __LINE__
1049	ja .return
1050
1051	; Check that a save + restore + save cycle yield the same results.
1052	mov xBX, REF_GLOBAL(g_pbEfExecPage)
1053	mov xDI, xBX
1054	mov eax, 066778899h
1055	mov ecx, 512 * 2 / 4
1056	cld
1057	rep stosd
1058	fxsave [xBX]
1059
1060	call x861_ClearRegistersSSE
1061	mov xBX, REF_GLOBAL(g_pbEfExecPage)
1062	fxrstor [xBX]
1063
1064	fxsave [xBX + 512]
1065	mov xSI, xBX
1066	lea xDI, [xBX + 512]
1067	mov ecx, 512
1068	cld
1069	repe cmpsb
1070	mov eax, __LINE__
1071	jnz .return
1072
1073
1074	; 464:511 are available to software use. Let see how carefully access
1075	; to the full 512 bytes are checked...
1076	call x861_LoadUniqueRegValuesSSE
1077	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1078	add xDI, PAGE_SIZE - 512
1079	ShouldTrap X86_XCPT_PF, fxsave [xDI + 16]
1080	ShouldTrap X86_XCPT_PF, fxsave [xDI + 32]
1081	ShouldTrap X86_XCPT_PF, fxsave [xDI + 48]
1082	ShouldTrap X86_XCPT_PF, fxsave [xDI + 64]
1083	ShouldTrap X86_XCPT_PF, fxsave [xDI + 80]
1084	ShouldTrap X86_XCPT_PF, fxsave [xDI + 96]
1085	ShouldTrap X86_XCPT_PF, fxsave [xDI + 128]
1086	ShouldTrap X86_XCPT_PF, fxsave [xDI + 144]
1087	ShouldTrap X86_XCPT_PF, fxsave [xDI + 160]
1088	ShouldTrap X86_XCPT_PF, fxsave [xDI + 176]
1089	ShouldTrap X86_XCPT_PF, fxsave [xDI + 192]
1090	ShouldTrap X86_XCPT_PF, fxsave [xDI + 208]
1091	ShouldTrap X86_XCPT_PF, fxsave [xDI + 224]
1092	ShouldTrap X86_XCPT_PF, fxsave [xDI + 240]
1093	ShouldTrap X86_XCPT_PF, fxsave [xDI + 256]
1094	ShouldTrap X86_XCPT_PF, fxsave [xDI + 384]
1095	ShouldTrap X86_XCPT_PF, fxsave [xDI + 432]
1096	ShouldTrap X86_XCPT_PF, fxsave [xDI + 496]
1097
1098	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 16]
1099	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 32]
1100	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 48]
1101	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 64]
1102	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 80]
1103	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 96]
1104	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 128]
1105	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 144]
1106	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 160]
1107	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 176]
1108	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 192]
1109	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 208]
1110	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 224]
1111	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 240]
1112	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 256]
1113	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 384]
1114	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 432]
1115	ShouldTrap X86_XCPT_PF, fxrstor [xDI + 496]
1116
1117	; Unaligned accesses will cause #GP(0). This takes precedence over #PF.
1118	ShouldTrap X86_XCPT_GP, fxsave [xDI + 1]
1119	ShouldTrap X86_XCPT_GP, fxsave [xDI + 2]
1120	ShouldTrap X86_XCPT_GP, fxsave [xDI + 3]
1121	ShouldTrap X86_XCPT_GP, fxsave [xDI + 4]
1122	ShouldTrap X86_XCPT_GP, fxsave [xDI + 5]
1123	ShouldTrap X86_XCPT_GP, fxsave [xDI + 6]
1124	ShouldTrap X86_XCPT_GP, fxsave [xDI + 7]
1125	ShouldTrap X86_XCPT_GP, fxsave [xDI + 8]
1126	ShouldTrap X86_XCPT_GP, fxsave [xDI + 9]
1127	ShouldTrap X86_XCPT_GP, fxsave [xDI + 10]
1128	ShouldTrap X86_XCPT_GP, fxsave [xDI + 11]
1129	ShouldTrap X86_XCPT_GP, fxsave [xDI + 12]
1130	ShouldTrap X86_XCPT_GP, fxsave [xDI + 13]
1131	ShouldTrap X86_XCPT_GP, fxsave [xDI + 14]
1132	ShouldTrap X86_XCPT_GP, fxsave [xDI + 15]
1133
1134	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 1]
1135	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 2]
1136	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 3]
1137	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 4]
1138	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 5]
1139	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 6]
1140	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 7]
1141	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 8]
1142	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 9]
1143	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 10]
1144	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 11]
1145	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 12]
1146	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 13]
1147	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 14]
1148	ShouldTrap X86_XCPT_GP, fxrstor [xDI + 15]
1149
1150	; Lets check what a FP in fxsave changes ... nothing on intel.
1151	mov ebx, 16
1152	.fxsave_pf_effect_loop:
1153	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1154	add xDI, PAGE_SIZE - 512 * 2
1155	mov xSI, xDI
1156	mov eax, 066778899h
1157	mov ecx, 512 * 2 / 4
1158	cld
1159	rep stosd
1160
1161	ShouldTrap X86_XCPT_PF, fxsave [xSI + PAGE_SIZE - 512 + xBX]
1162
1163	mov ecx, 512 / 4
1164	lea xDI, [xSI + 512]
1165	cld
1166	repz cmpsd
1167	lea xAX, [xBX + 20000]
1168	jnz .return
1169
1170	add ebx, 16
1171	cmp ebx, 512
1172	jbe .fxsave_pf_effect_loop
1173
1174	; Lets check that a FP in fxrstor does not have any effect on the FPU or SSE state.
1175	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1176	mov ecx, PAGE_SIZE / 4
1177	mov eax, 0ffaa33cch
1178	cld
1179	rep stosd
1180
1181	call x861_LoadUniqueRegValuesSSE
1182	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1183	fxsave [xDI]
1184
1185	call x861_ClearRegistersSSE
1186	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1187	fxsave [xDI + 512]
1188
1189	mov ebx, 16
1190	.fxrstor_pf_effect_loop:
1191	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1192	mov xSI, xDI
1193	lea xDI, [xDI + PAGE_SIZE - 512 + xBX]
1194	mov ecx, 512
1195	sub ecx, ebx
1196	cld
1197	rep movsb ; copy unique state to end of page.
1198
1199	push xBX
1200	call x861_ClearRegistersSSE
1201	pop xBX
1202	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1203	ShouldTrap X86_XCPT_PF, fxrstor [xDI + PAGE_SIZE - 512 + xBX] ; try load unique state
1204
1205	mov xDI, REF_GLOBAL(g_pbEfExecPage)
1206	lea xSI, [xDI + 512] ; point it to the clean state, which is what we expect.
1207	lea xDI, [xDI + 1024]
1208	fxsave [xDI] ; save whatever the fpu state currently is.
1209	mov ecx, 512 / 4
1210	cld
1211	repe cmpsd
1212	lea xAX, [xBX + 40000]
1213	jnz .return ; it shouldn't be modified by faulting fxrstor, i.e. a clean state.
1214
1215	add ebx, 16
1216	cmp ebx, 512
1217	jbe .fxrstor_pf_effect_loop
1218
1219	.success:
1220	xor eax, eax
1221	.return:
1222	SAVE_ALL_EPILOGUE
1223	ret
1224	ENDPROC x861_Test3
1225
1226
1227	;;
1228	; Tests various multibyte NOP sequences.
1229	;
1230	BEGINPROC x861_Test4
1231	SAVE_ALL_PROLOGUE
1232	call x861_ClearRegisters
1233
1234	; Intel recommended sequences.
1235	nop
1236	db 066h, 090h
1237	db 00fh, 01fh, 000h
1238	db 00fh, 01fh, 040h, 000h
1239	db 00fh, 01fh, 044h, 000h, 000h
1240	db 066h, 00fh, 01fh, 044h, 000h, 000h
1241	db 00fh, 01fh, 080h, 000h, 000h, 000h, 000h
1242	db 00fh, 01fh, 084h, 000h, 000h, 000h, 000h, 000h
1243	db 066h, 00fh, 01fh, 084h, 000h, 000h, 000h, 000h, 000h
1244
1245	; Check that the NOPs are allergic to lock prefixing.
1246	ShouldTrap X86_XCPT_UD, db 0f0h, 090h ; lock prefixed NOP.
1247	ShouldTrap X86_XCPT_UD, db 0f0h, 066h, 090h ; lock prefixed two byte NOP.
1248	ShouldTrap X86_XCPT_UD, db 0f0h, 00fh, 01fh, 000h ; lock prefixed three byte NOP.
1249
1250	; Check the range of instructions that AMD marks as NOPs.
1251	%macro TST_NOP 1
1252	db 00fh, %1, 000h
1253	db 00fh, %1, 040h, 000h
1254	db 00fh, %1, 044h, 000h, 000h
1255	db 066h, 00fh, %1, 044h, 000h, 000h
1256	db 00fh, %1, 080h, 000h, 000h, 000h, 000h
1257	db 00fh, %1, 084h, 000h, 000h, 000h, 000h, 000h
1258	db 066h, 00fh, %1, 084h, 000h, 000h, 000h, 000h, 000h
1259	ShouldTrap X86_XCPT_UD, db 0f0h, 00fh, %1, 000h
1260	%endmacro
1261	TST_NOP 019h
1262	TST_NOP 01ah
1263	TST_NOP 01bh
1264	TST_NOP 01ch
1265	TST_NOP 01dh
1266	TST_NOP 01eh
1267	TST_NOP 01fh
1268
1269	; The AMD P group, intel marks this as a NOP.
1270	TST_NOP 00dh
1271
1272	.success:
1273	xor eax, eax
1274	.return:
1275	SAVE_ALL_EPILOGUE
1276	ret
1277	ENDPROC x861_Test4
1278
1279
1280
1281	;;
1282	; Tests some odd floating point instruction encodings.
1283	;
1284	BEGINPROC x861_Test5
1285	SAVE_ALL_PROLOGUE
1286
1287	; standard stuff...
1288	fld dword REF(.r32V1)
1289	fld qword REF(.r64V1)
1290	fld tword REF(.r80V1)
1291
1292	ShouldTrap X86_XCPT_UD, db 0d9h, 008h
1293	ShouldTrap X86_XCPT_UD, db 0d9h, 009h
1294	ShouldTrap X86_XCPT_UD, db 0d9h, 00ah
1295	ShouldTrap X86_XCPT_UD, db 0d9h, 00bh
1296	ShouldTrap X86_XCPT_UD, db 0d9h, 00ch
1297	ShouldTrap X86_XCPT_UD, db 0d9h, 00dh
1298	ShouldTrap X86_XCPT_UD, db 0d9h, 00eh
1299	ShouldTrap X86_XCPT_UD, db 0d9h, 00fh
1300
1301	ShouldTrap X86_XCPT_UD, db 0d9h, 0d1h
1302	ShouldTrap X86_XCPT_UD, db 0d9h, 0d2h
1303	ShouldTrap X86_XCPT_UD, db 0d9h, 0d3h
1304	ShouldTrap X86_XCPT_UD, db 0d9h, 0d4h
1305	ShouldTrap X86_XCPT_UD, db 0d9h, 0d5h
1306	ShouldTrap X86_XCPT_UD, db 0d9h, 0d6h
1307	ShouldTrap X86_XCPT_UD, db 0d9h, 0d7h
1308	db 0d9h, 0d8h ; fnop?
1309	db 0d9h, 0d9h ; fnop?
1310	db 0d9h, 0dah ; fnop?
1311	db 0d9h, 0dbh ; fnop?
1312	db 0d9h, 0dch ; fnop?
1313	db 0d9h, 0ddh ; fnop?
1314	db 0d9h, 0deh ; fnop?
1315	db 0d9h, 0dfh ; fnop?
1316	ShouldTrap X86_XCPT_UD, db 0d9h, 0e2h
1317	ShouldTrap X86_XCPT_UD, db 0d9h, 0e3h
1318	ShouldTrap X86_XCPT_UD, db 0d9h, 0e6h
1319	ShouldTrap X86_XCPT_UD, db 0d9h, 0e7h
1320	ShouldTrap X86_XCPT_UD, db 0d9h, 0efh
1321
1322
1323	.success:
1324	xor eax, eax
1325	.return:
1326	SAVE_ALL_EPILOGUE
1327	ret
1328
1329	.r32V1: dd 3.2
1330	.r64V1: dq 6.4
1331	.r80V1: dt 8.0
1332
1333	ENDPROC x861_Test5
1334
1335
1336	;;
1337	; Terminate the trap info array with a NIL entry.
1338	BEGINDATA
1339	GLOBALNAME g_aTrapInfoEnd
1340	istruc TRAPINFO
1341	at TRAPINFO.uTrapPC, RTCCPTR_DEF 0
1342	at TRAPINFO.uResumePC, RTCCPTR_DEF 0
1343	at TRAPINFO.u8TrapNo, db 0
1344	at TRAPINFO.cbInstr, db 0
1345	iend
1346

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source: vbox/trunk/src/VBox/VMM/testcase/tstX86-1A.asm@ 40040

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