VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 94249

Last change on this file since 94249 was 93922, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 EPT VM-exit handling with HM ring-0 code.
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1/* $Id: PGMInternal.h 93922 2022-02-24 15:14:31Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/avl.h>
42#include <iprt/critsect.h>
43#include <iprt/list-off32.h>
44#include <iprt/sha.h>
45#include <iprt/cpp/hardavlrange.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Check and skip global PDEs for non-global flushes
62 */
63#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
64
65/**
66 * Optimization for PAE page tables that are modified often
67 */
68//#if 0 /* disabled again while debugging */
69#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
70//#endif
71
72/**
73 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
74 */
75#define PGM_WITH_LARGE_PAGES
76
77/**
78 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
79 * VMX_EXIT_EPT_MISCONFIG.
80 */
81#define PGM_WITH_MMIO_OPTIMIZATIONS
82
83/**
84 * Sync N pages instead of a whole page table
85 */
86#define PGM_SYNC_N_PAGES
87
88/**
89 * Number of pages to sync during a page fault
90 *
91 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
92 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
93 *
94 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
95 * world switch overhead, so let's sync more.
96 */
97#ifdef IN_RING0
98/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
99 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
100 * but ~5% fewer faults.
101 */
102# define PGM_SYNC_NR_PAGES 32
103#else
104# define PGM_SYNC_NR_PAGES 8
105#endif
106
107/**
108 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
109 */
110#define PGM_MAX_PHYSCACHE_ENTRIES 64
111#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
112
113
114/** @def PGMPOOL_CFG_MAX_GROW
115 * The maximum number of pages to add to the pool in one go.
116 */
117#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
118
119/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
120 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
121 */
122#ifdef VBOX_STRICT
123# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
124#endif
125
126/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
127 * Enables the experimental lazy page allocation code. */
128#ifdef DOXYGEN_RUNNING
129# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130#endif
131
132/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
133 * Enables real write monitoring of pages, i.e. mapping them read-only and
134 * only making them writable when getting a write access \#PF. */
135#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
136
137/** @def VBOX_WITH_PGM_NEM_MODE
138 * Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
139 * details. */
140#ifdef DOXYGEN_RUNNING
141# define VBOX_WITH_PGM_NEM_MODE
142#endif
143
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** PGM specific bits in PML4 entries. */
155#define PGM_PML4_FLAGS 0
156/** PGM specific bits in PDPT entries. */
157#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
158/** @} */
159
160/** @name Page directory flags.
161 * These are placed in the three bits available for system programs in
162 * the page directory entries.
163 * @{ */
164/** Indicates the original entry was a big page.
165 * @remarks This is currently only used for statistics and can be recycled. */
166#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184
185/** @} */
186
187/** @name Defines used to indicate the shadow and guest paging in the templates.
188 * @{ */
189#define PGM_TYPE_REAL 1
190#define PGM_TYPE_PROT 2
191#define PGM_TYPE_32BIT 3
192#define PGM_TYPE_PAE 4
193#define PGM_TYPE_AMD64 5
194#define PGM_TYPE_NESTED_32BIT 6
195#define PGM_TYPE_NESTED_PAE 7
196#define PGM_TYPE_NESTED_AMD64 8
197#define PGM_TYPE_EPT 9
198#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
199#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
200#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
201/** @} */
202
203/** @name Defines used to indicate the second-level
204 * address translation (SLAT) modes in the templates.
205 * @{ */
206#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 1)
207#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 2)
208#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 3)
209#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 4)
210/** @} */
211
212/** Macro for checking if the guest is using paging.
213 * @param uGstType PGM_TYPE_*
214 * @param uShwType PGM_TYPE_*
215 * @remark ASSUMES certain order of the PGM_TYPE_* values.
216 */
217#define PGM_WITH_PAGING(uGstType, uShwType) \
218 ( (uGstType) >= PGM_TYPE_32BIT \
219 && (uShwType) < PGM_TYPE_NESTED_32BIT)
220
221/** Macro for checking if the guest supports the NX bit.
222 * @param uGstType PGM_TYPE_*
223 * @param uShwType PGM_TYPE_*
224 * @remark ASSUMES certain order of the PGM_TYPE_* values.
225 */
226#define PGM_WITH_NX(uGstType, uShwType) \
227 ( (uGstType) >= PGM_TYPE_PAE \
228 && (uShwType) < PGM_TYPE_NESTED_32BIT)
229
230/** Macro for checking for nested.
231 * @param uType PGM_TYPE_*
232 */
233#define PGM_TYPE_IS_NESTED(uType) \
234 ( (uType) == PGM_TYPE_NESTED_32BIT \
235 || (uType) == PGM_TYPE_NESTED_PAE \
236 || (uType) == PGM_TYPE_NESTED_AMD64)
237
238/** Macro for checking for nested or EPT.
239 * @param uType PGM_TYPE_*
240 */
241#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
242 ( (uType) == PGM_TYPE_NESTED_32BIT \
243 || (uType) == PGM_TYPE_NESTED_PAE \
244 || (uType) == PGM_TYPE_NESTED_AMD64 \
245 || (uType) == PGM_TYPE_EPT)
246
247
248
249/** @def PGM_HCPHYS_2_PTR
250 * Maps a HC physical page pool address to a virtual address.
251 *
252 * @returns VBox status code.
253 * @param pVM The cross context VM structure.
254 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
255 * @param HCPhys The HC physical address to map to a virtual one.
256 * @param ppv Where to store the virtual address. No need to cast
257 * this.
258 *
259 * @remark There is no need to assert on the result.
260 */
261#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
262
263/** @def PGM_GCPHYS_2_PTR_V2
264 * Maps a GC physical page address to a virtual address.
265 *
266 * @returns VBox status code.
267 * @param pVM The cross context VM structure.
268 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
269 * @param GCPhys The GC physical address to map to a virtual one.
270 * @param ppv Where to store the virtual address. No need to cast this.
271 *
272 * @remark Use with care as we don't have so much dynamic mapping space in
273 * ring-0 on 32-bit darwin and in RC.
274 * @remark There is no need to assert on the result.
275 */
276#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
277 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
278
279/** @def PGM_GCPHYS_2_PTR
280 * Maps a GC physical page address to a virtual address.
281 *
282 * @returns VBox status code.
283 * @param pVM The cross context VM structure.
284 * @param GCPhys The GC physical address to map to a virtual one.
285 * @param ppv Where to store the virtual address. No need to cast this.
286 *
287 * @remark Use with care as we don't have so much dynamic mapping space in
288 * ring-0 on 32-bit darwin and in RC.
289 * @remark There is no need to assert on the result.
290 */
291#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
292
293/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
294 * Maps a GC physical page address to a virtual address.
295 *
296 * @returns VBox status code.
297 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
298 * @param GCPhys The GC physical address to map to a virtual one.
299 * @param ppv Where to store the virtual address. No need to cast this.
300 *
301 * @remark Use with care as we don't have so much dynamic mapping space in
302 * ring-0 on 32-bit darwin and in RC.
303 * @remark There is no need to assert on the result.
304 */
305#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
306
307/** @def PGM_GCPHYS_2_PTR_EX
308 * Maps a unaligned GC physical page address to a virtual address.
309 *
310 * @returns VBox status code.
311 * @param pVM The cross context VM structure.
312 * @param GCPhys The GC physical address to map to a virtual one.
313 * @param ppv Where to store the virtual address. No need to cast this.
314 *
315 * @remark Use with care as we don't have so much dynamic mapping space in
316 * ring-0 on 32-bit darwin and in RC.
317 * @remark There is no need to assert on the result.
318 */
319#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
320 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
321
322/** @def PGM_DYNMAP_UNUSED_HINT
323 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
324 * is no longer used.
325 *
326 * For best effect only apply this to the page that was mapped most recently.
327 *
328 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
329 * @param pvPage The pool page.
330 */
331#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
332
333/** @def PGM_DYNMAP_UNUSED_HINT_VM
334 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
335 * is no longer used.
336 *
337 * For best effect only apply this to the page that was mapped most recently.
338 *
339 * @param pVM The cross context VM structure.
340 * @param pvPage The pool page.
341 */
342#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
343
344
345/** @def PGM_INVL_PG
346 * Invalidates a page.
347 *
348 * @param pVCpu The cross context virtual CPU structure.
349 * @param GCVirt The virtual address of the page to invalidate.
350 */
351#ifdef IN_RING0
352# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
353#elif defined(IN_RING3)
354# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
355#else
356# error "Not IN_RING0 or IN_RING3!"
357#endif
358
359/** @def PGM_INVL_PG_ALL_VCPU
360 * Invalidates a page on all VCPUs
361 *
362 * @param pVM The cross context VM structure.
363 * @param GCVirt The virtual address of the page to invalidate.
364 */
365#ifdef IN_RING0
366# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
367#else
368# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
369#endif
370
371/** @def PGM_INVL_BIG_PG
372 * Invalidates a 4MB page directory entry.
373 *
374 * @param pVCpu The cross context virtual CPU structure.
375 * @param GCVirt The virtual address within the page directory to invalidate.
376 */
377#ifdef IN_RING0
378# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
379#else
380# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
381#endif
382
383/** @def PGM_INVL_VCPU_TLBS()
384 * Invalidates the TLBs of the specified VCPU
385 *
386 * @param pVCpu The cross context virtual CPU structure.
387 */
388#ifdef IN_RING0
389# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
390#else
391# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
392#endif
393
394/** @def PGM_INVL_ALL_VCPU_TLBS()
395 * Invalidates the TLBs of all VCPUs
396 *
397 * @param pVM The cross context VM structure.
398 */
399#ifdef IN_RING0
400# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
401#else
402# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
403#endif
404
405
406/** @name Safer Shadow PAE PT/PTE
407 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
408 * present.
409 *
410 * @{
411 */
412#if 1
413/**
414 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
415 * invalid entries for present.
416 * @sa X86PTEPAE.
417 */
418typedef union PGMSHWPTEPAE
419{
420 /** Unsigned integer view */
421 X86PGPAEUINT uCareful;
422 /* Not other views. */
423} PGMSHWPTEPAE;
424
425# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
426# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
427# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
428# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
429# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
430# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
431# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
432# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
433# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
434# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
435# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
436# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
437# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
438# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
439# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
440# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
441
442/**
443 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
444 * invalid entries for present.
445 * @sa X86PTPAE.
446 */
447typedef struct PGMSHWPTPAE
448{
449 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
450} PGMSHWPTPAE;
451
452#else
453typedef X86PTEPAE PGMSHWPTEPAE;
454typedef X86PTPAE PGMSHWPTPAE;
455# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
456# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
457# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
458# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
459# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
460# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
461# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
462# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
463# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
464# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
465# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
466# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
467# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
468# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
469# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
470# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
471
472#endif
473
474/** Pointer to a shadow PAE PTE. */
475typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
476/** Pointer to a const shadow PAE PTE. */
477typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
478
479/** Pointer to a shadow PAE page table. */
480typedef PGMSHWPTPAE *PPGMSHWPTPAE;
481/** Pointer to a const shadow PAE page table. */
482typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
483/** @} */
484
485
486/** The physical access handler type handle count (power of two). */
487#define PGMPHYSHANDLERTYPE_COUNT 0x20
488/** Mask for getting the array index from an access handler type handle.
489 * The other handle bits are random and non-zero to avoid mixups due to zero
490 * initialized fields. */
491#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
492
493/**
494 * Physical page access handler type registration, ring-0 part.
495 */
496typedef struct PGMPHYSHANDLERTYPEINTR0
497{
498 /** The handle value for verfication. */
499 PGMPHYSHANDLERTYPE hType;
500 /** The kind of accesses we're handling. */
501 PGMPHYSHANDLERKIND enmKind;
502 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
503 uint8_t uState;
504 /** Whether to keep the PGM lock when calling the handler.
505 * @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
506 bool fKeepPgmLock;
507 /** Set if this is registered by a device instance and uUser should be
508 * translated from a device instance ID to a pointer.
509 * @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
510 bool fRing0DevInsIdx;
511 bool afPadding[1];
512 /** Pointer to the ring-0 callback function. */
513 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
514 /** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
515 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
516 /** Description / Name. For easing debugging. */
517 R0PTRTYPE(const char *) pszDesc;
518} PGMPHYSHANDLERTYPEINTR0;
519/** Pointer to a physical access handler type registration. */
520typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
521
522/**
523 * Physical page access handler type registration, shared/ring-3 part.
524 */
525typedef struct PGMPHYSHANDLERTYPEINTR3
526{
527 /** The handle value for verfication. */
528 PGMPHYSHANDLERTYPE hType;
529 /** The kind of accesses we're handling. */
530 PGMPHYSHANDLERKIND enmKind;
531 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
532 uint8_t uState;
533 /** Whether to keep the PGM lock when calling the handler.
534 * @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
535 bool fKeepPgmLock;
536 /** Set if this is registered by a device instance and uUser should be
537 * translated from a device instance ID to a pointer.
538 * @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
539 bool fRing0DevInsIdx;
540 /** Set by ring-0 if the handler is ring-0 enabled (for debug). */
541 bool fRing0Enabled : 1;
542 /** Pointer to the ring-3 callback function. */
543 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
544 /** Description / Name. For easing debugging. */
545 R3PTRTYPE(const char *) pszDesc;
546} PGMPHYSHANDLERTYPEINTR3;
547/** Pointer to a physical access handler type registration. */
548typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
549
550/** Pointer to a physical access handler type record for the current context. */
551typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
552/** Pointer to a const physical access handler type record for the current context. */
553typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
554/** Dummy physical access handler type record. */
555extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
556
557
558/**
559 * Physical page access handler structure.
560 *
561 * This is used to keep track of physical address ranges
562 * which are being monitored in some kind of way.
563 */
564typedef struct PGMPHYSHANDLER
565{
566 /** @name Tree stuff.
567 * @{ */
568 /** First address. */
569 RTGCPHYS Key;
570 /** Last address. */
571 RTGCPHYS KeyLast;
572 uint32_t idxLeft;
573 uint32_t idxRight;
574 uint8_t cHeight;
575 /** @} */
576 uint8_t abPadding[3];
577 /** Number of pages to update. */
578 uint32_t cPages;
579 /** Set if we have pages that have been aliased. */
580 uint32_t cAliasedPages;
581 /** Set if we have pages that have temporarily been disabled. */
582 uint32_t cTmpOffPages;
583 /** Registered handler type handle.
584 * @note Marked volatile to prevent re-reading after validation. */
585 PGMPHYSHANDLERTYPE volatile hType;
586 /** User argument for the handlers. */
587 uint64_t uUser;
588 /** Description / Name. For easing debugging. */
589 R3PTRTYPE(const char *) pszDesc;
590 /** Profiling of this handler.
591 * @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
592 STAMPROFILE Stat;
593} PGMPHYSHANDLER;
594AssertCompileSize(PGMPHYSHANDLER, 12*8);
595/** Pointer to a physical page access handler structure. */
596typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
597
598/**
599 * Gets the type record for a physical handler (no reference added).
600 * @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
601 * @param a_pVM The cross context VM structure.
602 * @param a_pPhysHandler Pointer to the physical handler structure
603 * (PGMPHYSHANDLER).
604 */
605#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
606 pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
607
608/**
609 * Gets the type record for a physical handler, never returns NULL.
610 *
611 * @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
612 * @param a_pVM The cross context VM structure.
613 * @param a_pPhysHandler Pointer to the physical handler structure
614 * (PGMPHYSHANDLER).
615 */
616#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
617 pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
618
619/** Physical access handler allocator. */
620typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
621
622/** Physical access handler tree. */
623typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
624/** Pointer to a physical access handler tree. */
625typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
626
627
628/**
629 * A Physical Guest Page tracking structure.
630 *
631 * The format of this structure is complicated because we have to fit a lot
632 * of information into as few bits as possible. The format is also subject
633 * to change (there is one coming up soon). Which means that for we'll be
634 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
635 * accesses to the structure.
636 */
637typedef union PGMPAGE
638{
639 /** Structured view. */
640 struct
641 {
642 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
643 uint64_t u2HandlerPhysStateY : 2;
644 /** 3:2 - Paging structure needed to map the page
645 * (PGM_PAGE_PDE_TYPE_*). */
646 uint64_t u2PDETypeY : 2;
647 /** 4 - Unused (was used by FTE for dirty tracking). */
648 uint64_t fUnused1 : 1;
649 /** 5 - Flag indicating that a write monitored page was written to
650 * when set. */
651 uint64_t fWrittenToY : 1;
652 /** 7:6 - Unused. */
653 uint64_t u2Unused0 : 2;
654 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
655 uint64_t u2Unused1 : 2;
656 /** 11:10 - NEM state bits. */
657 uint64_t u2NemStateY : 2;
658 /** 12:48 - The host physical frame number (shift left to get the
659 * address). */
660 uint64_t HCPhysFN : 36;
661 /** 50:48 - The page state. */
662 uint64_t uStateY : 3;
663 /** 51:53 - The page type (PGMPAGETYPE). */
664 uint64_t uTypeY : 3;
665 /** 63:54 - PTE index for usage tracking (page pool). */
666 uint64_t u10PteIdx : 10;
667
668 /** The GMM page ID.
669 * @remarks In the current implementation, MMIO2 and pages aliased to
670 * MMIO2 pages will be exploiting this field to calculate the
671 * ring-3 mapping address corresponding to the page.
672 * Later we may consider including MMIO2 management into GMM. */
673 uint32_t idPage;
674 /** Usage tracking (page pool). */
675 uint16_t u16TrackingY;
676 /** The number of read locks on this page. */
677 uint8_t cReadLocksY;
678 /** The number of write locks on this page. */
679 uint8_t cWriteLocksY;
680 } s;
681
682 /** 64-bit integer view. */
683 uint64_t au64[2];
684 /** 16-bit view. */
685 uint32_t au32[4];
686 /** 16-bit view. */
687 uint16_t au16[8];
688 /** 8-bit view. */
689 uint8_t au8[16];
690} PGMPAGE;
691AssertCompileSize(PGMPAGE, 16);
692/** Pointer to a physical guest page. */
693typedef PGMPAGE *PPGMPAGE;
694/** Pointer to a const physical guest page. */
695typedef const PGMPAGE *PCPGMPAGE;
696/** Pointer to a physical guest page pointer. */
697typedef PPGMPAGE *PPPGMPAGE;
698
699
700/**
701 * Clears the page structure.
702 * @param a_pPage Pointer to the physical guest page tracking structure.
703 */
704#define PGM_PAGE_CLEAR(a_pPage) \
705 do { \
706 (a_pPage)->au64[0] = 0; \
707 (a_pPage)->au64[1] = 0; \
708 } while (0)
709
710/**
711 * Initializes the page structure.
712 * @param a_pPage Pointer to the physical guest page tracking structure.
713 * @param a_HCPhys The host physical address of the page.
714 * @param a_idPage The (GMM) page ID of the page.
715 * @param a_uType The page type (PGMPAGETYPE).
716 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
717 */
718#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
719 do { \
720 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
721 AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
722 (a_pPage)->au64[0] = SetHCPhysTmp; \
723 (a_pPage)->au64[1] = 0; \
724 (a_pPage)->s.idPage = (a_idPage); \
725 (a_pPage)->s.uStateY = (a_uState); \
726 (a_pPage)->s.uTypeY = (a_uType); \
727 } while (0)
728
729/**
730 * Initializes the page structure of a ZERO page.
731 * @param a_pPage Pointer to the physical guest page tracking structure.
732 * @param a_pVM The VM handle (for getting the zero page address).
733 * @param a_uType The page type (PGMPAGETYPE).
734 */
735#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
736 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
737
738
739/** @name The Page state, PGMPAGE::uStateY.
740 * @{ */
741/** The zero page.
742 * This is a per-VM page that's never ever mapped writable. */
743#define PGM_PAGE_STATE_ZERO 0U
744/** A allocated page.
745 * This is a per-VM page allocated from the page pool (or wherever
746 * we get MMIO2 pages from if the type is MMIO2).
747 */
748#define PGM_PAGE_STATE_ALLOCATED 1U
749/** A allocated page that's being monitored for writes.
750 * The shadow page table mappings are read-only. When a write occurs, the
751 * fWrittenTo member is set, the page remapped as read-write and the state
752 * moved back to allocated. */
753#define PGM_PAGE_STATE_WRITE_MONITORED 2U
754/** The page is shared, aka. copy-on-write.
755 * This is a page that's shared with other VMs. */
756#define PGM_PAGE_STATE_SHARED 3U
757/** The page is ballooned, so no longer available for this VM. */
758#define PGM_PAGE_STATE_BALLOONED 4U
759/** @} */
760
761
762/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
763#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
764# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
765#else
766# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
767#endif
768
769/**
770 * Gets the page state.
771 * @returns page state (PGM_PAGE_STATE_*).
772 * @param a_pPage Pointer to the physical guest page tracking structure.
773 *
774 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
775 * builds.
776 */
777#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
778#if defined(__GNUC__) && defined(VBOX_STRICT)
779# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
780#else
781# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
782#endif
783
784/**
785 * Sets the page state.
786 * @param a_pVM The VM handle, only used for lock ownership assertions.
787 * @param a_pPage Pointer to the physical guest page tracking structure.
788 * @param a_uState The new page state.
789 */
790#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
791 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
792
793
794/**
795 * Gets the host physical address of the guest page.
796 * @returns host physical address (RTHCPHYS).
797 * @param a_pPage Pointer to the physical guest page tracking structure.
798 *
799 * @remarks In strict builds on gcc platforms, this macro will make some ugly
800 * assumption about a valid pVM variable/parameter being in the
801 * current context. It will use this pVM variable to assert that the
802 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
803 * pVM is not around.
804 */
805#if 0
806# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
807# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
808#else
809# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
810# if defined(__GNUC__) && defined(VBOX_STRICT)
811# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
812# else
813# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
814# endif
815#endif
816
817/**
818 * Sets the host physical address of the guest page.
819 *
820 * @param a_pVM The VM handle, only used for lock ownership assertions.
821 * @param a_pPage Pointer to the physical guest page tracking structure.
822 * @param a_HCPhys The new host physical address.
823 */
824#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
825 do { \
826 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
827 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
828 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
829 PGM_PAGE_ASSERT_LOCK(a_pVM); \
830 } while (0)
831
832/**
833 * Get the Page ID.
834 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
835 * @param a_pPage Pointer to the physical guest page tracking structure.
836 */
837#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
838
839/**
840 * Sets the Page ID.
841 * @param a_pVM The VM handle, only used for lock ownership assertions.
842 * @param a_pPage Pointer to the physical guest page tracking structure.
843 * @param a_idPage The new page ID.
844 */
845#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
846 do { \
847 (a_pPage)->s.idPage = (a_idPage); \
848 PGM_PAGE_ASSERT_LOCK(a_pVM); \
849 } while (0)
850
851/**
852 * Get the Chunk ID.
853 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
854 * @param a_pPage Pointer to the physical guest page tracking structure.
855 */
856#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
857
858/**
859 * Get the index of the page within the allocation chunk.
860 * @returns The page index.
861 * @param a_pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
864
865/**
866 * Gets the page type.
867 * @returns The page type.
868 * @param a_pPage Pointer to the physical guest page tracking structure.
869 *
870 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
871 * builds.
872 */
873#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
874#if defined(__GNUC__) && defined(VBOX_STRICT)
875# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
876#else
877# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
878#endif
879
880/**
881 * Sets the page type.
882 *
883 * @param a_pVM The VM handle, only used for lock ownership assertions.
884 * @param a_pPage Pointer to the physical guest page tracking structure.
885 * @param a_enmType The new page type (PGMPAGETYPE).
886 */
887#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
888 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
889
890/**
891 * Gets the page table index
892 * @returns The page table index.
893 * @param a_pPage Pointer to the physical guest page tracking structure.
894 */
895#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
896
897/**
898 * Sets the page table index.
899 * @param a_pVM The VM handle, only used for lock ownership assertions.
900 * @param a_pPage Pointer to the physical guest page tracking structure.
901 * @param a_iPte New page table index.
902 */
903#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
904 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
905
906/**
907 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
908 * @returns true/false.
909 * @param a_pPage Pointer to the physical guest page tracking structure.
910 */
911#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
912
913/**
914 * Checks if the page is marked for MMIO, including both aliases.
915 * @returns true/false.
916 * @param a_pPage Pointer to the physical guest page tracking structure.
917 */
918#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
919 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
920 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
921 )
922
923/**
924 * Checks if the page is marked for MMIO, including special aliases.
925 * @returns true/false.
926 * @param a_pPage Pointer to the physical guest page tracking structure.
927 */
928#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
929 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
930
931/**
932 * Checks if the page is a special aliased MMIO page.
933 * @returns true/false.
934 * @param a_pPage Pointer to the physical guest page tracking structure.
935 */
936#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
937
938/**
939 * Checks if the page is backed by the ZERO page.
940 * @returns true/false.
941 * @param a_pPage Pointer to the physical guest page tracking structure.
942 */
943#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
944
945/**
946 * Checks if the page is backed by a SHARED page.
947 * @returns true/false.
948 * @param a_pPage Pointer to the physical guest page tracking structure.
949 */
950#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
951
952/**
953 * Checks if the page is ballooned.
954 * @returns true/false.
955 * @param a_pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
958
959/**
960 * Checks if the page is allocated.
961 * @returns true/false.
962 * @param a_pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
965
966/**
967 * Marks the page as written to (for GMM change monitoring).
968 * @param a_pVM The VM handle, only used for lock ownership assertions.
969 * @param a_pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
972 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
973
974/**
975 * Clears the written-to indicator.
976 * @param a_pVM The VM handle, only used for lock ownership assertions.
977 * @param a_pPage Pointer to the physical guest page tracking structure.
978 */
979#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
980 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
981
982/**
983 * Checks if the page was marked as written-to.
984 * @returns true/false.
985 * @param a_pPage Pointer to the physical guest page tracking structure.
986 */
987#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
988
989
990/** @name PT usage values (PGMPAGE::u2PDEType).
991 *
992 * @{ */
993/** Either as a PT or PDE. */
994#define PGM_PAGE_PDE_TYPE_DONTCARE 0
995/** Must use a page table to map the range. */
996#define PGM_PAGE_PDE_TYPE_PT 1
997/** Can use a page directory entry to map the continuous range. */
998#define PGM_PAGE_PDE_TYPE_PDE 2
999/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1000#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1001/** @} */
1002
1003/**
1004 * Set the PDE type of the page
1005 * @param a_pVM The VM handle, only used for lock ownership assertions.
1006 * @param a_pPage Pointer to the physical guest page tracking structure.
1007 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1008 */
1009#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1010 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1011
1012/**
1013 * Checks if the page was marked being part of a large page
1014 * @returns true/false.
1015 * @param a_pPage Pointer to the physical guest page tracking structure.
1016 */
1017#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1018
1019/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1020 *
1021 * @remarks The values are assigned in order of priority, so we can calculate
1022 * the correct state for a page with different handlers installed.
1023 * @{ */
1024/** No handler installed. */
1025#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1026/** Monitoring is temporarily disabled. */
1027#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1028/** Write access is monitored. */
1029#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1030/** All access is monitored. */
1031#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1032/** @} */
1033
1034/**
1035 * Gets the physical access handler state of a page.
1036 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1037 * @param a_pPage Pointer to the physical guest page tracking structure.
1038 */
1039#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1040
1041/**
1042 * Sets the physical access handler state of a page.
1043 * @param a_pPage Pointer to the physical guest page tracking structure.
1044 * @param a_uState The new state value.
1045 */
1046#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1047 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1048
1049/**
1050 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1051 * @returns true/false
1052 * @param a_pPage Pointer to the physical guest page tracking structure.
1053 */
1054#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1055 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1056
1057/**
1058 * Checks if the page has any active physical access handlers.
1059 * @returns true/false
1060 * @param a_pPage Pointer to the physical guest page tracking structure.
1061 */
1062#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1063 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1064
1065/**
1066 * Checks if the page has any access handlers, including temporarily disabled ones.
1067 * @returns true/false
1068 * @param a_pPage Pointer to the physical guest page tracking structure.
1069 */
1070#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1071 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1072
1073/**
1074 * Checks if the page has any active access handlers.
1075 * @returns true/false
1076 * @param a_pPage Pointer to the physical guest page tracking structure.
1077 */
1078#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1079 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1080
1081/**
1082 * Checks if the page has any active access handlers catching all accesses.
1083 * @returns true/false
1084 * @param a_pPage Pointer to the physical guest page tracking structure.
1085 */
1086#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1087 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1088
1089
1090/** @def PGM_PAGE_GET_TRACKING
1091 * Gets the packed shadow page pool tracking data associated with a guest page.
1092 * @returns uint16_t containing the data.
1093 * @param a_pPage Pointer to the physical guest page tracking structure.
1094 */
1095#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1096#if defined(__GNUC__) && defined(VBOX_STRICT)
1097# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1098#else
1099# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1100#endif
1101
1102/** @def PGM_PAGE_SET_TRACKING
1103 * Sets the packed shadow page pool tracking data associated with a guest page.
1104 * @param a_pVM The VM handle, only used for lock ownership assertions.
1105 * @param a_pPage Pointer to the physical guest page tracking structure.
1106 * @param a_u16TrackingData The tracking data to store.
1107 */
1108#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1109 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1110
1111/** @def PGM_PAGE_GET_TD_CREFS
1112 * Gets the @a cRefs tracking data member.
1113 * @returns cRefs.
1114 * @param a_pPage Pointer to the physical guest page tracking structure.
1115 */
1116#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1117 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1118#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1119 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1120
1121/** @def PGM_PAGE_GET_TD_IDX
1122 * Gets the @a idx tracking data member.
1123 * @returns idx.
1124 * @param a_pPage Pointer to the physical guest page tracking structure.
1125 */
1126#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1127 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1128#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1129 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1130
1131
1132/** Max number of locks on a page. */
1133#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1134
1135/** Get the read lock count.
1136 * @returns count.
1137 * @param a_pPage Pointer to the physical guest page tracking structure.
1138 */
1139#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1140
1141/** Get the write lock count.
1142 * @returns count.
1143 * @param a_pPage Pointer to the physical guest page tracking structure.
1144 */
1145#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1146
1147/** Decrement the read lock counter.
1148 * @param a_pPage Pointer to the physical guest page tracking structure.
1149 */
1150#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1151
1152/** Decrement the write lock counter.
1153 * @param a_pPage Pointer to the physical guest page tracking structure.
1154 */
1155#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1156
1157/** Increment the read lock counter.
1158 * @param a_pPage Pointer to the physical guest page tracking structure.
1159 */
1160#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1161
1162/** Increment the write lock counter.
1163 * @param a_pPage Pointer to the physical guest page tracking structure.
1164 */
1165#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1166
1167
1168/** Gets the NEM state.
1169 * @returns NEM state value (two bits).
1170 * @param a_pPage Pointer to the physical guest page tracking structure.
1171 */
1172#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1173
1174/** Sets the NEM state.
1175 * @param a_pPage Pointer to the physical guest page tracking structure.
1176 * @param a_u2State The NEM state value (specific to NEM impl.).
1177 */
1178#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1179 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1180
1181
1182#if 0
1183/** Enables sanity checking of write monitoring using CRC-32. */
1184# define PGMLIVESAVERAMPAGE_WITH_CRC32
1185#endif
1186
1187/**
1188 * Per page live save tracking data.
1189 */
1190typedef struct PGMLIVESAVERAMPAGE
1191{
1192 /** Number of times it has been dirtied. */
1193 uint32_t cDirtied : 24;
1194 /** Whether it is currently dirty. */
1195 uint32_t fDirty : 1;
1196 /** Ignore the page.
1197 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1198 * deal with these after pausing the VM and DevPCI have said it bit about
1199 * remappings. */
1200 uint32_t fIgnore : 1;
1201 /** Was a ZERO page last time around. */
1202 uint32_t fZero : 1;
1203 /** Was a SHARED page last time around. */
1204 uint32_t fShared : 1;
1205 /** Whether the page is/was write monitored in a previous pass. */
1206 uint32_t fWriteMonitored : 1;
1207 /** Whether the page is/was write monitored earlier in this pass. */
1208 uint32_t fWriteMonitoredJustNow : 1;
1209 /** Bits reserved for future use. */
1210 uint32_t u2Reserved : 2;
1211#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1212 /** CRC-32 for the page. This is for internal consistency checks. */
1213 uint32_t u32Crc;
1214#endif
1215} PGMLIVESAVERAMPAGE;
1216#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1217AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1218#else
1219AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1220#endif
1221/** Pointer to the per page live save tracking data. */
1222typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1223
1224/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1225#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1226
1227
1228/**
1229 * RAM range for GC Phys to HC Phys conversion.
1230 *
1231 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1232 * conversions too, but we'll let MM handle that for now.
1233 *
1234 * This structure is used by linked lists in both GC and HC.
1235 */
1236typedef struct PGMRAMRANGE
1237{
1238 /** Start of the range. Page aligned. */
1239 RTGCPHYS GCPhys;
1240 /** Size of the range. (Page aligned of course). */
1241 RTGCPHYS cb;
1242 /** Pointer to the next RAM range - for R3. */
1243 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1244 /** Pointer to the next RAM range - for R0. */
1245 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1246 /** PGM_RAM_RANGE_FLAGS_* flags. */
1247 uint32_t fFlags;
1248 /** NEM specific info, UINT32_MAX if not used. */
1249 uint32_t uNemRange;
1250 /** Last address in the range (inclusive). Page aligned (-1). */
1251 RTGCPHYS GCPhysLast;
1252 /** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1253 R3PTRTYPE(void *) pvR3;
1254 /** Live save per page tracking data. */
1255 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1256 /** The range description. */
1257 R3PTRTYPE(const char *) pszDesc;
1258 /** Pointer to self - R0 pointer. */
1259 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1260
1261 /** Pointer to the left search three node - ring-3 context. */
1262 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1263 /** Pointer to the right search three node - ring-3 context. */
1264 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1265 /** Pointer to the left search three node - ring-0 context. */
1266 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1267 /** Pointer to the right search three node - ring-0 context. */
1268 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1269
1270 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1271#if HC_ARCH_BITS == 32
1272 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1273#endif
1274 /** Array of physical guest page tracking structures.
1275 * @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1276 PGMPAGE aPages[1];
1277} PGMRAMRANGE;
1278/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1279typedef PGMRAMRANGE *PPGMRAMRANGE;
1280
1281/** @name PGMRAMRANGE::fFlags
1282 * @{ */
1283/** The RAM range is floating around as an independent guest mapping. */
1284#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1285/** Ad hoc RAM range for an ROM mapping. */
1286#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1287/** Ad hoc RAM range for an MMIO mapping. */
1288#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1289/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1290#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1291/** @} */
1292
1293/** Tests if a RAM range is an ad hoc one or not.
1294 * @returns true/false.
1295 * @param pRam The RAM range.
1296 */
1297#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1298 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1299
1300/** The number of entries in the RAM range TLBs (there is one for each
1301 * context). Must be a power of two. */
1302#define PGM_RAMRANGE_TLB_ENTRIES 8
1303
1304/**
1305 * Calculates the RAM range TLB index for the physical address.
1306 *
1307 * @returns RAM range TLB index.
1308 * @param a_GCPhys The guest physical address.
1309 */
1310#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1311
1312/**
1313 * Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1314 * mapping address.
1315 */
1316#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1317 ( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1318
1319
1320/**
1321 * Per page tracking structure for ROM image.
1322 *
1323 * A ROM image may have a shadow page, in which case we may have two pages
1324 * backing it. This structure contains the PGMPAGE for both while
1325 * PGMRAMRANGE have a copy of the active one. It is important that these
1326 * aren't out of sync in any regard other than page pool tracking data.
1327 */
1328typedef struct PGMROMPAGE
1329{
1330 /** The page structure for the virgin ROM page. */
1331 PGMPAGE Virgin;
1332 /** The page structure for the shadow RAM page. */
1333 PGMPAGE Shadow;
1334 /** The current protection setting. */
1335 PGMROMPROT enmProt;
1336 /** Live save status information. Makes use of unused alignment space. */
1337 struct
1338 {
1339 /** The previous protection value. */
1340 uint8_t u8Prot;
1341 /** Written to flag set by the handler. */
1342 bool fWrittenTo;
1343 /** Whether the shadow page is dirty or not. */
1344 bool fDirty;
1345 /** Whether it was dirtied in the recently. */
1346 bool fDirtiedRecently;
1347 } LiveSave;
1348} PGMROMPAGE;
1349AssertCompileSizeAlignment(PGMROMPAGE, 8);
1350/** Pointer to a ROM page tracking structure. */
1351typedef PGMROMPAGE *PPGMROMPAGE;
1352
1353
1354/**
1355 * A registered ROM image.
1356 *
1357 * This is needed to keep track of ROM image since they generally intrude
1358 * into a PGMRAMRANGE. It also keeps track of additional info like the
1359 * two page sets (read-only virgin and read-write shadow), the current
1360 * state of each page.
1361 *
1362 * Because access handlers cannot easily be executed in a different
1363 * context, the ROM ranges needs to be accessible and in all contexts.
1364 */
1365typedef struct PGMROMRANGE
1366{
1367 /** Pointer to the next range - R3. */
1368 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1369 /** Pointer to the next range - R0. */
1370 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1371 /** Pointer to the this range - R0. */
1372 R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1373 /** Address of the range. */
1374 RTGCPHYS GCPhys;
1375 /** Address of the last byte in the range. */
1376 RTGCPHYS GCPhysLast;
1377 /** Size of the range. */
1378 RTGCPHYS cb;
1379 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1380 uint8_t fFlags;
1381 /** The saved state range ID. */
1382 uint8_t idSavedState;
1383 /** Alignment padding. */
1384 uint8_t au8Alignment[2];
1385 /** The size bits pvOriginal points to. */
1386 uint32_t cbOriginal;
1387 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1388 * This is used for strictness checks. */
1389 R3PTRTYPE(const void *) pvOriginal;
1390 /** The ROM description. */
1391 R3PTRTYPE(const char *) pszDesc;
1392#ifdef VBOX_WITH_PGM_NEM_MODE
1393 /** In simplified memory mode this provides alternate backing for shadowed ROMs.
1394 * - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1395 * - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1396 * - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1397 * - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1398 R3PTRTYPE(uint8_t *) pbR3Alternate;
1399 RTR3PTR pvAlignment2;
1400#endif
1401 /** The per page tracking structures. */
1402 PGMROMPAGE aPages[1];
1403} PGMROMRANGE;
1404/** Pointer to a ROM range. */
1405typedef PGMROMRANGE *PPGMROMRANGE;
1406
1407
1408/**
1409 * Live save per page data for an MMIO2 page.
1410 *
1411 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1412 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1413 * CRC-32 for detecting changes as well as special handling of zero pages. This
1414 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1415 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1416 * because of speed (2.5x and 6x slower).)
1417 *
1418 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1419 * save but normally is disabled. Since we can write monitor guest
1420 * accesses on our own, we only need this for host accesses. Shouldn't be
1421 * too difficult for DevVGA, VMMDev might be doable, the planned
1422 * networking fun will be fun since it involves ring-0.
1423 */
1424typedef struct PGMLIVESAVEMMIO2PAGE
1425{
1426 /** Set if the page is considered dirty. */
1427 bool fDirty;
1428 /** The number of scans this page has remained unchanged for.
1429 * Only updated for dirty pages. */
1430 uint8_t cUnchangedScans;
1431 /** Whether this page was zero at the last scan. */
1432 bool fZero;
1433 /** Alignment padding. */
1434 bool fReserved;
1435 /** CRC-32 for the first half of the page.
1436 * This is used together with u32CrcH2 to quickly detect changes in the page
1437 * during the non-final passes. */
1438 uint32_t u32CrcH1;
1439 /** CRC-32 for the second half of the page. */
1440 uint32_t u32CrcH2;
1441 /** SHA-1 for the saved page.
1442 * This is used in the final pass to skip pages without changes. */
1443 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1444} PGMLIVESAVEMMIO2PAGE;
1445/** Pointer to a live save status data for an MMIO2 page. */
1446typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1447
1448/**
1449 * A registered MMIO2 (= Device RAM) range.
1450 *
1451 * There are a few reason why we need to keep track of these registrations. One
1452 * of them is the deregistration & cleanup stuff, while another is that the
1453 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1454 * range list.
1455 *
1456 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1457 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1458 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1459 * overlap we will free all the existing RAM pages and put in the ram range
1460 * pages instead.
1461 */
1462typedef struct PGMREGMMIO2RANGE
1463{
1464 /** The owner of the range. (a device) */
1465 PPDMDEVINSR3 pDevInsR3;
1466 /** Pointer to the ring-3 mapping of the allocation. */
1467 RTR3PTR pvR3;
1468#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1469 /** Pointer to the ring-0 mapping of the allocation. */
1470 RTR0PTR pvR0;
1471#endif
1472 /** Pointer to the next range - R3. */
1473 R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1474 /** Flags (PGMREGMMIO2RANGE_F_XXX). */
1475 uint16_t fFlags;
1476 /** The sub device number (internal PCI config (CFGM) number). */
1477 uint8_t iSubDev;
1478 /** The PCI region number. */
1479 uint8_t iRegion;
1480 /** The saved state range ID. */
1481 uint8_t idSavedState;
1482 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1483 uint8_t idMmio2;
1484 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1485#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1486 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1487#else
1488 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1489#endif
1490 /** The real size.
1491 * This may be larger than indicated by RamRange.cb if the range has been
1492 * reduced during saved state loading. */
1493 RTGCPHYS cbReal;
1494 /** Pointer to the physical handler for MMIO.
1495 * If NEM is responsible for tracking dirty pages in simple memory mode, this
1496 * will be NULL. */
1497 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1498 /** Live save per page tracking data for MMIO2. */
1499 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1500 /** The associated RAM range. */
1501 PGMRAMRANGE RamRange;
1502} PGMREGMMIO2RANGE;
1503AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1504/** Pointer to a MMIO2 or pre-registered MMIO range. */
1505typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1506
1507/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1508 * @{ */
1509/** Set if this is the first chunk in the MMIO2 range. */
1510#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1511/** Set if this is the last chunk in the MMIO2 range. */
1512#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1513/** Set if the whole range is mapped. */
1514#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1515/** Set if it's overlapping, clear if not. */
1516#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1517/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1518#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1519/** Set if the access handler is registered. */
1520#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1521/** Set if dirty page tracking is currently enabled. */
1522#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1523/** Set if there are dirty pages in the range. */
1524#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1525/** @} */
1526
1527
1528/** @name Internal MMIO2 constants.
1529 * @{ */
1530/** The maximum number of MMIO2 ranges. */
1531#define PGM_MMIO2_MAX_RANGES 32
1532/** The maximum number of pages in a MMIO2 range. */
1533#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1534/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1535#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1536/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1537#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1538/** Gets the MMIO2 page index from an MMIO2 page ID. */
1539#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1540/** @} */
1541
1542
1543
1544/**
1545 * PGMPhysRead/Write cache entry
1546 */
1547typedef struct PGMPHYSCACHEENTRY
1548{
1549 /** R3 pointer to physical page. */
1550 R3PTRTYPE(uint8_t *) pbR3;
1551 /** GC Physical address for cache entry */
1552 RTGCPHYS GCPhys;
1553#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1554 RTGCPHYS u32Padding0; /**< alignment padding. */
1555#endif
1556} PGMPHYSCACHEENTRY;
1557
1558/**
1559 * PGMPhysRead/Write cache to reduce REM memory access overhead
1560 */
1561typedef struct PGMPHYSCACHE
1562{
1563 /** Bitmap of valid cache entries */
1564 uint64_t aEntries;
1565 /** Cache entries */
1566 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1567} PGMPHYSCACHE;
1568
1569
1570/** @name Ring-3 page mapping TLBs
1571 * @{ */
1572
1573/** Pointer to an allocation chunk ring-3 mapping. */
1574typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1575/** Pointer to an allocation chunk ring-3 mapping pointer. */
1576typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1577
1578/**
1579 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1580 *
1581 * The primary tree (Core) uses the chunk id as key.
1582 */
1583typedef struct PGMCHUNKR3MAP
1584{
1585 /** The key is the chunk id. */
1586 AVLU32NODECORE Core;
1587 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1588 * selection. */
1589 uint32_t iLastUsed;
1590 /** The current reference count. */
1591 uint32_t volatile cRefs;
1592 /** The current permanent reference count. */
1593 uint32_t volatile cPermRefs;
1594 /** The mapping address. */
1595 void *pv;
1596} PGMCHUNKR3MAP;
1597
1598/**
1599 * Allocation chunk ring-3 mapping TLB entry.
1600 */
1601typedef struct PGMCHUNKR3MAPTLBE
1602{
1603 /** The chunk id. */
1604 uint32_t volatile idChunk;
1605#if HC_ARCH_BITS == 64
1606 uint32_t u32Padding; /**< alignment padding. */
1607#endif
1608 /** The chunk map. */
1609 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1610} PGMCHUNKR3MAPTLBE;
1611/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1612typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1613
1614/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1615 * @remark Must be a power of two value. */
1616#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1617
1618/**
1619 * Allocation chunk ring-3 mapping TLB.
1620 *
1621 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1622 * At first glance this might look kinda odd since AVL trees are
1623 * supposed to give the most optimal lookup times of all trees
1624 * due to their balancing. However, take a tree with 1023 nodes
1625 * in it, that's 10 levels, meaning that most searches has to go
1626 * down 9 levels before they find what they want. This isn't fast
1627 * compared to a TLB hit. There is the factor of cache misses,
1628 * and of course the problem with trees and branch prediction.
1629 * This is why we use TLBs in front of most of the trees.
1630 *
1631 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1632 * difficult when we switch to the new inlined AVL trees (from kStuff).
1633 */
1634typedef struct PGMCHUNKR3MAPTLB
1635{
1636 /** The TLB entries. */
1637 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1638} PGMCHUNKR3MAPTLB;
1639
1640/**
1641 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1642 * @returns Chunk TLB index.
1643 * @param idChunk The Chunk ID.
1644 */
1645#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1646
1647
1648/**
1649 * Ring-3 guest page mapping TLB entry.
1650 * @remarks used in ring-0 as well at the moment.
1651 */
1652typedef struct PGMPAGER3MAPTLBE
1653{
1654 /** Address of the page. */
1655 RTGCPHYS volatile GCPhys;
1656 /** The guest page. */
1657 R3PTRTYPE(PPGMPAGE) volatile pPage;
1658 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1659 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1660 /** The address */
1661 R3PTRTYPE(void *) volatile pv;
1662#if HC_ARCH_BITS == 32
1663 uint32_t u32Padding; /**< alignment padding. */
1664#endif
1665} PGMPAGER3MAPTLBE;
1666/** Pointer to an entry in the HC physical TLB. */
1667typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1668
1669
1670/** The number of entries in the ring-3 guest page mapping TLB.
1671 * @remarks The value must be a power of two. */
1672#define PGM_PAGER3MAPTLB_ENTRIES 256
1673
1674/**
1675 * Ring-3 guest page mapping TLB.
1676 * @remarks used in ring-0 as well at the moment.
1677 */
1678typedef struct PGMPAGER3MAPTLB
1679{
1680 /** The TLB entries. */
1681 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1682} PGMPAGER3MAPTLB;
1683/** Pointer to the ring-3 guest page mapping TLB. */
1684typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1685
1686/**
1687 * Calculates the index of the TLB entry for the specified guest page.
1688 * @returns Physical TLB index.
1689 * @param GCPhys The guest physical address.
1690 */
1691#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1692
1693/** @} */
1694
1695
1696/** @name Ring-0 page mapping TLB
1697 * @{ */
1698/**
1699 * Ring-0 guest page mapping TLB entry.
1700 */
1701typedef struct PGMPAGER0MAPTLBE
1702{
1703 /** Address of the page. */
1704 RTGCPHYS volatile GCPhys;
1705 /** The guest page. */
1706 R0PTRTYPE(PPGMPAGE) volatile pPage;
1707 /** The address */
1708 R0PTRTYPE(void *) volatile pv;
1709} PGMPAGER0MAPTLBE;
1710/** Pointer to an entry in the HC physical TLB. */
1711typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1712
1713
1714/** The number of entries in the ring-3 guest page mapping TLB.
1715 * @remarks The value must be a power of two. */
1716#define PGM_PAGER0MAPTLB_ENTRIES 256
1717
1718/**
1719 * Ring-3 guest page mapping TLB.
1720 * @remarks used in ring-0 as well at the moment.
1721 */
1722typedef struct PGMPAGER0MAPTLB
1723{
1724 /** The TLB entries. */
1725 PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1726} PGMPAGER0MAPTLB;
1727/** Pointer to the ring-3 guest page mapping TLB. */
1728typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1729
1730/**
1731 * Calculates the index of the TLB entry for the specified guest page.
1732 * @returns Physical TLB index.
1733 * @param GCPhys The guest physical address.
1734 */
1735#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1736/** @} */
1737
1738
1739/** @name Context neutral page mapper TLB.
1740 *
1741 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1742 * code is writting in a kind of context neutral way. Time will show whether
1743 * this actually makes sense or not...
1744 *
1745 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1746 * context ends up using a global mapping cache on some platforms
1747 * (darwin).
1748 *
1749 * @{ */
1750/** @typedef PPGMPAGEMAPTLB
1751 * The page mapper TLB pointer type for the current context. */
1752/** @typedef PPGMPAGEMAPTLB
1753 * The page mapper TLB entry pointer type for the current context. */
1754/** @typedef PPGMPAGEMAPTLB
1755 * The page mapper TLB entry pointer pointer type for the current context. */
1756/** @def PGM_PAGEMAPTLB_ENTRIES
1757 * The number of TLB entries in the page mapper TLB for the current context. */
1758/** @def PGM_PAGEMAPTLB_IDX
1759 * Calculate the TLB index for a guest physical address.
1760 * @returns The TLB index.
1761 * @param GCPhys The guest physical address. */
1762/** @typedef PPGMPAGEMAP
1763 * Pointer to a page mapper unit for current context. */
1764/** @typedef PPPGMPAGEMAP
1765 * Pointer to a page mapper unit pointer for current context. */
1766#if defined(IN_RING0)
1767typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1768typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1769typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1770# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1771# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1772typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1773typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1774#else
1775typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1776typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1777typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1778# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1779# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1780typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1781typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1782#endif
1783/** @} */
1784
1785
1786/** @name PGM Pool Indexes.
1787 * Aka. the unique shadow page identifier.
1788 * @{ */
1789/** NIL page pool IDX. */
1790#define NIL_PGMPOOL_IDX 0
1791/** The first normal index. There used to be 5 fictive pages up front, now
1792 * there is only the NIL page. */
1793#define PGMPOOL_IDX_FIRST 1
1794/** The last valid index. (inclusive, 14 bits) */
1795#define PGMPOOL_IDX_LAST 0x3fff
1796/** @} */
1797
1798/** The NIL index for the parent chain. */
1799#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1800#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1801
1802/**
1803 * Node in the chain linking a shadowed page to it's parent (user).
1804 */
1805#pragma pack(1)
1806typedef struct PGMPOOLUSER
1807{
1808 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1809 uint16_t iNext;
1810 /** The user page index. */
1811 uint16_t iUser;
1812 /** Index into the user table. */
1813 uint32_t iUserTable;
1814} PGMPOOLUSER, *PPGMPOOLUSER;
1815typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1816#pragma pack()
1817
1818
1819/** The NIL index for the phys ext chain. */
1820#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1821/** The NIL pte index for a phys ext chain slot. */
1822#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1823
1824/**
1825 * Node in the chain of physical cross reference extents.
1826 * @todo Calling this an 'extent' is not quite right, find a better name.
1827 * @todo find out the optimal size of the aidx array
1828 */
1829#pragma pack(1)
1830typedef struct PGMPOOLPHYSEXT
1831{
1832 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1833 uint16_t iNext;
1834 /** Alignment. */
1835 uint16_t u16Align;
1836 /** The user page index. */
1837 uint16_t aidx[3];
1838 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1839 uint16_t apte[3];
1840} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1841typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1842#pragma pack()
1843
1844
1845/**
1846 * The kind of page that's being shadowed.
1847 */
1848typedef enum PGMPOOLKIND
1849{
1850 /** The virtual invalid 0 entry. */
1851 PGMPOOLKIND_INVALID = 0,
1852 /** The entry is free (=unused). */
1853 PGMPOOLKIND_FREE,
1854
1855 /** Shw: 32-bit page table; Gst: no paging. */
1856 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1857 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1858 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1859 /** Shw: 32-bit page table; Gst: 4MB page. */
1860 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1861 /** Shw: PAE page table; Gst: no paging. */
1862 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1863 /** Shw: PAE page table; Gst: 32-bit page table. */
1864 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1865 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1866 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1867 /** Shw: PAE page table; Gst: PAE page table. */
1868 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1869 /** Shw: PAE page table; Gst: 2MB page. */
1870 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1871
1872 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1873 PGMPOOLKIND_32BIT_PD,
1874 /** Shw: 32-bit page directory. Gst: no paging. */
1875 PGMPOOLKIND_32BIT_PD_PHYS,
1876 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1877 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1878 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1879 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1880 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1881 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1882 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1883 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1884 /** Shw: PAE page directory; Gst: PAE page directory. */
1885 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1886 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1887 PGMPOOLKIND_PAE_PD_PHYS,
1888
1889 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1890 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1891 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1892 PGMPOOLKIND_PAE_PDPT,
1893 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1894 PGMPOOLKIND_PAE_PDPT_PHYS,
1895
1896 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1897 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1898 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
1899 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1900 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1901 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1902 /** Shw: 64-bit page directory table; Gst: no paging. */
1903 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1904
1905 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1906 PGMPOOLKIND_64BIT_PML4,
1907
1908 /** Shw: EPT page directory pointer table; Gst: no paging. */
1909 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1910 /** Shw: EPT page directory table; Gst: no paging. */
1911 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1912 /** Shw: EPT page table; Gst: no paging. */
1913 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1914
1915 /** Shw: Root Nested paging table. */
1916 PGMPOOLKIND_ROOT_NESTED,
1917
1918 /** The last valid entry. */
1919 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1920} PGMPOOLKIND;
1921
1922/**
1923 * The access attributes of the page; only applies to big pages.
1924 */
1925typedef enum
1926{
1927 PGMPOOLACCESS_DONTCARE = 0,
1928 PGMPOOLACCESS_USER_RW,
1929 PGMPOOLACCESS_USER_R,
1930 PGMPOOLACCESS_USER_RW_NX,
1931 PGMPOOLACCESS_USER_R_NX,
1932 PGMPOOLACCESS_SUPERVISOR_RW,
1933 PGMPOOLACCESS_SUPERVISOR_R,
1934 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1935 PGMPOOLACCESS_SUPERVISOR_R_NX
1936} PGMPOOLACCESS;
1937
1938/**
1939 * The tracking data for a page in the pool.
1940 */
1941typedef struct PGMPOOLPAGE
1942{
1943 /** AVL node code with the (HC) physical address of this page. */
1944 AVLOHCPHYSNODECORE Core;
1945 /** Pointer to the R3 mapping of the page. */
1946 R3PTRTYPE(void *) pvPageR3;
1947 /** Pointer to the R0 mapping of the page. */
1948 R0PTRTYPE(void *) pvPageR0;
1949 /** The guest physical address. */
1950 RTGCPHYS GCPhys;
1951 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1952 uint8_t enmKind;
1953 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1954 uint8_t enmAccess;
1955 /** This supplements enmKind and enmAccess */
1956 bool fA20Enabled : 1;
1957
1958 /** Used to indicate that the page is zeroed. */
1959 bool fZeroed : 1;
1960 /** Used to indicate that a PT has non-global entries. */
1961 bool fSeenNonGlobal : 1;
1962 /** Used to indicate that we're monitoring writes to the guest page. */
1963 bool fMonitored : 1;
1964 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1965 * (All pages are in the age list.) */
1966 bool fCached : 1;
1967 /** This is used by the R3 access handlers when invoked by an async thread.
1968 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1969 bool volatile fReusedFlushPending : 1;
1970 /** Used to mark the page as dirty (write monitoring is temporarily
1971 * off). */
1972 bool fDirty : 1;
1973 bool fPadding1 : 1;
1974 bool fPadding2;
1975
1976 /** The index of this page. */
1977 uint16_t idx;
1978 /** The next entry in the list this page currently resides in.
1979 * It's either in the free list or in the GCPhys hash. */
1980 uint16_t iNext;
1981 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1982 uint16_t iUserHead;
1983 /** The number of present entries. */
1984 uint16_t cPresent;
1985 /** The first entry in the table which is present. */
1986 uint16_t iFirstPresent;
1987 /** The number of modifications to the monitored page. */
1988 uint16_t cModifications;
1989 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1990 uint16_t iModifiedNext;
1991 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1992 uint16_t iModifiedPrev;
1993 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1994 uint16_t iMonitoredNext;
1995 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1996 uint16_t iMonitoredPrev;
1997 /** The next page in the age list. */
1998 uint16_t iAgeNext;
1999 /** The previous page in the age list. */
2000 uint16_t iAgePrev;
2001 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2002 uint8_t idxDirtyEntry;
2003
2004 /** @name Access handler statistics to determine whether the guest is
2005 * (re)initializing a page table.
2006 * @{ */
2007 RTGCPTR GCPtrLastAccessHandlerRip;
2008 RTGCPTR GCPtrLastAccessHandlerFault;
2009 uint64_t cLastAccessHandler;
2010 /** @} */
2011 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2012 uint32_t volatile cLocked;
2013#if GC_ARCH_BITS == 64
2014 uint32_t u32Alignment3;
2015#endif
2016# ifdef VBOX_STRICT
2017 RTGCPTR GCPtrDirtyFault;
2018# endif
2019} PGMPOOLPAGE;
2020/** Pointer to a pool page. */
2021typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2022/** Pointer to a const pool page. */
2023typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2024/** Pointer to a pool page pointer. */
2025typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2026
2027
2028/** The hash table size. */
2029# define PGMPOOL_HASH_SIZE 0x40
2030/** The hash function. */
2031# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2032
2033
2034/**
2035 * The shadow page pool instance data.
2036 *
2037 * It's all one big allocation made at init time, except for the
2038 * pages that is. The user nodes follows immediately after the
2039 * page structures.
2040 */
2041typedef struct PGMPOOL
2042{
2043 /** The VM handle - R3 Ptr. */
2044 PVMR3 pVMR3;
2045 /** The VM handle - R0 Ptr. */
2046 R0PTRTYPE(PVMCC) pVMR0;
2047 /** The ring-3 pointer to this structure. */
2048 R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2049 /** The ring-0 pointer to this structure. */
2050 R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2051 /** The max pool size. This includes the special IDs. */
2052 uint16_t cMaxPages;
2053 /** The current pool size. */
2054 uint16_t cCurPages;
2055 /** The head of the free page list. */
2056 uint16_t iFreeHead;
2057 /* Padding. */
2058 uint16_t u16Padding;
2059 /** Head of the chain of free user nodes. */
2060 uint16_t iUserFreeHead;
2061 /** The number of user nodes we've allocated. */
2062 uint16_t cMaxUsers;
2063 /** The number of present page table entries in the entire pool. */
2064 uint32_t cPresent;
2065 /** Pointer to the array of user nodes - R3 pointer. */
2066 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2067 /** Pointer to the array of user nodes - R0 pointer. */
2068 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2069 /** Head of the chain of free phys ext nodes. */
2070 uint16_t iPhysExtFreeHead;
2071 /** The number of user nodes we've allocated. */
2072 uint16_t cMaxPhysExts;
2073 uint32_t u32Padding0b;
2074 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2075 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2076 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2077 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2078 /** Hash table for GCPhys addresses. */
2079 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2080 /** The head of the age list. */
2081 uint16_t iAgeHead;
2082 /** The tail of the age list. */
2083 uint16_t iAgeTail;
2084 /** Set if the cache is enabled. */
2085 bool fCacheEnabled;
2086 /** Alignment padding. */
2087 bool afPadding1[3];
2088 /** Head of the list of modified pages. */
2089 uint16_t iModifiedHead;
2090 /** The current number of modified pages. */
2091 uint16_t cModifiedPages;
2092 /** Alignment padding. */
2093 uint32_t u32Padding2;
2094 /** Physical access handler type registration handle. */
2095 PGMPHYSHANDLERTYPE hAccessHandlerType;
2096 /** Next available slot (in aDirtyPages). */
2097 uint32_t idxFreeDirtyPage;
2098 /** Number of active dirty pages. */
2099 uint32_t cDirtyPages;
2100 /** Array of current dirty pgm pool page indices. */
2101 uint16_t aidxDirtyPages[16];
2102 /** Array running in parallel to aidxDirtyPages with the page data. */
2103 struct
2104 {
2105 uint64_t aPage[512];
2106 } aDirtyPages[16];
2107
2108 /** The number of pages currently in use. */
2109 uint16_t cUsedPages;
2110#ifdef VBOX_WITH_STATISTICS
2111 /** The high water mark for cUsedPages. */
2112 uint16_t cUsedPagesHigh;
2113 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2114 /** Profiling pgmPoolAlloc(). */
2115 STAMPROFILEADV StatAlloc;
2116 /** Profiling pgmR3PoolClearDoIt(). */
2117 STAMPROFILE StatClearAll;
2118 /** Profiling pgmR3PoolReset(). */
2119 STAMPROFILE StatR3Reset;
2120 /** Profiling pgmPoolFlushPage(). */
2121 STAMPROFILE StatFlushPage;
2122 /** Profiling pgmPoolFree(). */
2123 STAMPROFILE StatFree;
2124 /** Counting explicit flushes by PGMPoolFlushPage(). */
2125 STAMCOUNTER StatForceFlushPage;
2126 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2127 STAMCOUNTER StatForceFlushDirtyPage;
2128 /** Counting flushes for reused pages. */
2129 STAMCOUNTER StatForceFlushReused;
2130 /** Profiling time spent zeroing pages. */
2131 STAMPROFILE StatZeroPage;
2132 /** Profiling of pgmPoolTrackDeref. */
2133 STAMPROFILE StatTrackDeref;
2134 /** Profiling pgmTrackFlushGCPhysPT. */
2135 STAMPROFILE StatTrackFlushGCPhysPT;
2136 /** Profiling pgmTrackFlushGCPhysPTs. */
2137 STAMPROFILE StatTrackFlushGCPhysPTs;
2138 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2139 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2140 /** Number of times we've been out of user records. */
2141 STAMCOUNTER StatTrackFreeUpOneUser;
2142 /** Nr of flushed entries. */
2143 STAMCOUNTER StatTrackFlushEntry;
2144 /** Nr of updated entries. */
2145 STAMCOUNTER StatTrackFlushEntryKeep;
2146 /** Profiling deref activity related tracking GC physical pages. */
2147 STAMPROFILE StatTrackDerefGCPhys;
2148 /** Number of linear searches for a HCPhys in the ram ranges. */
2149 STAMCOUNTER StatTrackLinearRamSearches;
2150 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2151 STAMCOUNTER StamTrackPhysExtAllocFailures;
2152
2153 /** Profiling the RC/R0 \#PF access handler. */
2154 STAMPROFILE StatMonitorPfRZ;
2155 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2156 STAMPROFILE StatMonitorPfRZHandled;
2157 /** Times we've failed interpreting the instruction. */
2158 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2159 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2160 STAMPROFILE StatMonitorPfRZFlushPage;
2161 /** Times we've detected a page table reinit. */
2162 STAMCOUNTER StatMonitorPfRZFlushReinit;
2163 /** Counting flushes for pages that are modified too often. */
2164 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2165 /** Times we've detected fork(). */
2166 STAMCOUNTER StatMonitorPfRZFork;
2167 /** Times we've failed interpreting a patch code instruction. */
2168 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2169 /** Times we've failed interpreting a patch code instruction during flushing. */
2170 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2171 /** The number of times we've seen rep prefixes we can't handle. */
2172 STAMCOUNTER StatMonitorPfRZRepPrefix;
2173 /** Profiling the REP STOSD cases we've handled. */
2174 STAMPROFILE StatMonitorPfRZRepStosd;
2175
2176 /** Profiling the R0/RC regular access handler. */
2177 STAMPROFILE StatMonitorRZ;
2178 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2179 STAMPROFILE StatMonitorRZFlushPage;
2180 /** Per access size counts indexed by size minus 1, last for larger. */
2181 STAMCOUNTER aStatMonitorRZSizes[16+3];
2182 /** Missaligned access counts indexed by offset - 1. */
2183 STAMCOUNTER aStatMonitorRZMisaligned[7];
2184
2185 /** Nr of handled PT faults. */
2186 STAMCOUNTER StatMonitorRZFaultPT;
2187 /** Nr of handled PD faults. */
2188 STAMCOUNTER StatMonitorRZFaultPD;
2189 /** Nr of handled PDPT faults. */
2190 STAMCOUNTER StatMonitorRZFaultPDPT;
2191 /** Nr of handled PML4 faults. */
2192 STAMCOUNTER StatMonitorRZFaultPML4;
2193
2194 /** Profiling the R3 access handler. */
2195 STAMPROFILE StatMonitorR3;
2196 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2197 STAMPROFILE StatMonitorR3FlushPage;
2198 /** Per access size counts indexed by size minus 1, last for larger. */
2199 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2200 /** Missaligned access counts indexed by offset - 1. */
2201 STAMCOUNTER aStatMonitorR3Misaligned[7];
2202 /** Nr of handled PT faults. */
2203 STAMCOUNTER StatMonitorR3FaultPT;
2204 /** Nr of handled PD faults. */
2205 STAMCOUNTER StatMonitorR3FaultPD;
2206 /** Nr of handled PDPT faults. */
2207 STAMCOUNTER StatMonitorR3FaultPDPT;
2208 /** Nr of handled PML4 faults. */
2209 STAMCOUNTER StatMonitorR3FaultPML4;
2210
2211 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2212 STAMCOUNTER StatResetDirtyPages;
2213 /** Times we've called pgmPoolAddDirtyPage. */
2214 STAMCOUNTER StatDirtyPage;
2215 /** Times we've had to flush duplicates for dirty page management. */
2216 STAMCOUNTER StatDirtyPageDupFlush;
2217 /** Times we've had to flush because of overflow. */
2218 STAMCOUNTER StatDirtyPageOverFlowFlush;
2219
2220 /** The high water mark for cModifiedPages. */
2221 uint16_t cModifiedPagesHigh;
2222 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2223
2224 /** The number of cache hits. */
2225 STAMCOUNTER StatCacheHits;
2226 /** The number of cache misses. */
2227 STAMCOUNTER StatCacheMisses;
2228 /** The number of times we've got a conflict of 'kind' in the cache. */
2229 STAMCOUNTER StatCacheKindMismatches;
2230 /** Number of times we've been out of pages. */
2231 STAMCOUNTER StatCacheFreeUpOne;
2232 /** The number of cacheable allocations. */
2233 STAMCOUNTER StatCacheCacheable;
2234 /** The number of uncacheable allocations. */
2235 STAMCOUNTER StatCacheUncacheable;
2236#else
2237 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2238#endif
2239 /** Profiling PGMR0PoolGrow(). */
2240 STAMPROFILE StatGrow;
2241 /** The AVL tree for looking up a page by its HC physical address. */
2242 AVLOHCPHYSTREE HCPhysTree;
2243 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2244 /** Array of pages. (cMaxPages in length)
2245 * The Id is the index into thist array.
2246 */
2247 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2248} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2249AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2250AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2251AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2252#ifdef VBOX_WITH_STATISTICS
2253AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2254#endif
2255AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2256
2257
2258/** @def PGMPOOL_PAGE_2_PTR
2259 * Maps a pool page pool into the current context.
2260 *
2261 * @returns VBox status code.
2262 * @param a_pVM Pointer to the VM.
2263 * @param a_pPage The pool page.
2264 *
2265 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2266 * small page window employeed by that function. Be careful.
2267 * @remark There is no need to assert on the result.
2268 */
2269#if defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2270# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2271DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2272{
2273 RT_NOREF(pszCaller);
2274 AssertPtr(a_pPage);
2275 AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2276 ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2277 a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2278 return a_pPage->CTX_SUFF(pvPage);
2279}
2280#else
2281# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2282#endif
2283
2284
2285/** @def PGMPOOL_PAGE_2_PTR_V2
2286 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2287 *
2288 * @returns VBox status code.
2289 * @param a_pVM Pointer to the VM.
2290 * @param a_pVCpu The current CPU.
2291 * @param a_pPage The pool page.
2292 *
2293 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2294 * small page window employeed by that function. Be careful.
2295 * @remark There is no need to assert on the result.
2296 */
2297#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2298
2299
2300/** @name Per guest page tracking data.
2301 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2302 * is to use more bits for it and split it up later on. But for now we'll play
2303 * safe and change as little as possible.
2304 *
2305 * The 16-bit word has two parts:
2306 *
2307 * The first 14-bit forms the @a idx field. It is either the index of a page in
2308 * the shadow page pool, or and index into the extent list.
2309 *
2310 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2311 * shadow page pool references to the page. If cRefs equals
2312 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2313 * (misnomer) table and not the shadow page pool.
2314 *
2315 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2316 * the 16-bit word.
2317 *
2318 * @{ */
2319/** The shift count for getting to the cRefs part. */
2320#define PGMPOOL_TD_CREFS_SHIFT 14
2321/** The mask applied after shifting the tracking data down by
2322 * PGMPOOL_TD_CREFS_SHIFT. */
2323#define PGMPOOL_TD_CREFS_MASK 0x3
2324/** The cRefs value used to indicate that the idx is the head of a
2325 * physical cross reference list. */
2326#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2327/** The shift used to get idx. */
2328#define PGMPOOL_TD_IDX_SHIFT 0
2329/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2330#define PGMPOOL_TD_IDX_MASK 0x3fff
2331/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2332 * simply too many mappings of this page. */
2333#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2334
2335/** @def PGMPOOL_TD_MAKE
2336 * Makes a 16-bit tracking data word.
2337 *
2338 * @returns tracking data.
2339 * @param cRefs The @a cRefs field. Must be within bounds!
2340 * @param idx The @a idx field. Must also be within bounds! */
2341#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2342
2343/** @def PGMPOOL_TD_GET_CREFS
2344 * Get the @a cRefs field from a tracking data word.
2345 *
2346 * @returns The @a cRefs field
2347 * @param u16 The tracking data word.
2348 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2349 * non-zero @a u16. */
2350#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2351
2352/** @def PGMPOOL_TD_GET_IDX
2353 * Get the @a idx field from a tracking data word.
2354 *
2355 * @returns The @a idx field
2356 * @param u16 The tracking data word. */
2357#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2358/** @} */
2359
2360
2361
2362/** @name A20 gate macros
2363 * @{ */
2364#define PGM_WITH_A20
2365#ifdef PGM_WITH_A20
2366# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2367# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2368# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2369 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2370# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2371#else
2372# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2373# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2374# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2375# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2376#endif
2377/** @} */
2378
2379
2380/**
2381 * Guest page table walk for the AMD64 mode.
2382 */
2383typedef struct PGMPTWALKGSTAMD64
2384{
2385 PX86PML4 pPml4;
2386 PX86PML4E pPml4e;
2387 X86PML4E Pml4e;
2388
2389 PX86PDPT pPdpt;
2390 PX86PDPE pPdpe;
2391 X86PDPE Pdpe;
2392
2393 PX86PDPAE pPd;
2394 PX86PDEPAE pPde;
2395 X86PDEPAE Pde;
2396
2397 PX86PTPAE pPt;
2398 PX86PTEPAE pPte;
2399 X86PTEPAE Pte;
2400} PGMPTWALKGSTAMD64;
2401/** Pointer to a AMD64 guest page table walk. */
2402typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2403/** Pointer to a const AMD64 guest page table walk. */
2404typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2405
2406/**
2407 * Guest page table walk for the EPT mode.
2408 */
2409typedef struct PGMPTWALKGSTEPT
2410{
2411 PEPTPML4 pPml4;
2412 PEPTPML4E pPml4e;
2413 EPTPML4E Pml4e;
2414
2415 PEPTPDPT pPdpt;
2416 PEPTPDPTE pPdpte;
2417 EPTPDPTE Pdpte;
2418
2419 PEPTPD pPd;
2420 PEPTPDE pPde;
2421 EPTPDE Pde;
2422
2423 PEPTPT pPt;
2424 PEPTPTE pPte;
2425 EPTPTE Pte;
2426} PGMPTWALKGSTEPT;
2427/** Pointer to an EPT guest page table walk. */
2428typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2429/** Pointer to a const EPT guest page table walk. */
2430typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2431
2432/**
2433 * Guest page table walk for the PAE mode.
2434 */
2435typedef struct PGMPTWALKGSTPAE
2436{
2437 PX86PDPT pPdpt;
2438 PX86PDPE pPdpe;
2439 X86PDPE Pdpe;
2440
2441 PX86PDPAE pPd;
2442 PX86PDEPAE pPde;
2443 X86PDEPAE Pde;
2444
2445 PX86PTPAE pPt;
2446 PX86PTEPAE pPte;
2447 X86PTEPAE Pte;
2448} PGMPTWALKGSTPAE;
2449/** Pointer to a PAE guest page table walk. */
2450typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2451/** Pointer to a const AMD64 guest page table walk. */
2452typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2453
2454/**
2455 * Guest page table walk for the 32-bit mode.
2456 */
2457typedef struct PGMPTWALKGST32BIT
2458{
2459 PX86PD pPd;
2460 PX86PDE pPde;
2461 X86PDE Pde;
2462
2463 PX86PT pPt;
2464 PX86PTE pPte;
2465 X86PTE Pte;
2466} PGMPTWALKGST32BIT;
2467/** Pointer to a 32-bit guest page table walk. */
2468typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2469/** Pointer to a const 32-bit guest page table walk. */
2470typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2471
2472/**
2473 * Which part of PGMPTWALKGST that is valid.
2474 */
2475typedef enum PGMPTWALKGSTTYPE
2476{
2477 /** Customary invalid 0 value. */
2478 PGMPTWALKGSTTYPE_INVALID = 0,
2479 /** PGMPTWALKGST::u.Amd64 is valid. */
2480 PGMPTWALKGSTTYPE_AMD64,
2481 /** PGMPTWALKGST::u.Pae is valid. */
2482 PGMPTWALKGSTTYPE_PAE,
2483 /** PGMPTWALKGST::u.Legacy is valid. */
2484 PGMPTWALKGSTTYPE_32BIT,
2485 /** PGMPTWALKGST::u.Ept is valid. */
2486 PGMPTWALKGSTTYPE_EPT,
2487 /** Customary 32-bit type hack. */
2488 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2489} PGMPTWALKGSTTYPE;
2490
2491/**
2492 * Combined guest page table walk result.
2493 */
2494typedef struct PGMPTWALKGST
2495{
2496 union
2497 {
2498 /** The page walker for AMD64. */
2499 PGMPTWALKGSTAMD64 Amd64;
2500 /** The page walker for PAE (32-bit). */
2501 PGMPTWALKGSTPAE Pae;
2502 /** The page walker for 32-bit paging (called legacy due to C naming
2503 * convension). */
2504 PGMPTWALKGST32BIT Legacy;
2505 /** The page walker for EPT (SLAT). */
2506 PGMPTWALKGSTEPT Ept;
2507 } u;
2508 /** Indicates which part of the union is valid. */
2509 PGMPTWALKGSTTYPE enmType;
2510} PGMPTWALKGST;
2511/** Pointer to a combined guest page table walk result. */
2512typedef PGMPTWALKGST *PPGMPTWALKGST;
2513/** Pointer to a read-only combined guest page table walk result. */
2514typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2515
2516
2517/** @name Paging mode macros
2518 * @{
2519 */
2520#ifdef IN_RING3
2521# define PGM_CTX(a,b) a##R3##b
2522# define PGM_CTX_STR(a,b) a "R3" b
2523# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2524#elif defined(IN_RING0)
2525# define PGM_CTX(a,b) a##R0##b
2526# define PGM_CTX_STR(a,b) a "R0" b
2527# define PGM_CTX_DECL(type) VMMDECL(type)
2528#else
2529# error "Not IN_RING3 or IN_RING0!"
2530#endif
2531
2532#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2533#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2534#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2535#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2536#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2537#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2538#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2539#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2540#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2541#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2542#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2543#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2544#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2545#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2546#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2547#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2548
2549#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2550#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2551#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2552#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2553
2554#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2555#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2556#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2557#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2558#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2559#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2560#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2561#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2562#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2563#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2564#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2565#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2566#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2567#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2568#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2569#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2570#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2571#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2572#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2573#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2574#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2575#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2576#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2577#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2578#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2579
2580/* Shw_Gst */
2581#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2582#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2583#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2584#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2585#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2586#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2587#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2588#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2589#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2590#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2591#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2592#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2593#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2594#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2595#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2596#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2597#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2598#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2599#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2600#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2601#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2602#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2603#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2604#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2605#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2606#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2607#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2608#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2609#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2610#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2611#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2612#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2613#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2614#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2615
2616#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2617#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2618#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2619#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2620#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2621#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2622#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2623#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2624#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2625#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2626#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2627#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2628#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2629#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2630#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2631#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2632#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2633#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2634#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2635#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2636#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2637#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2638#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2639#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2640#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2641#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2642#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2643#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2644
2645#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2646#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2647#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2648#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2649#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2650#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2651#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2652#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2653#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2654#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2655#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2656#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2657#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2658#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2659#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2660#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2661#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2662#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2663#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2664#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2665#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2666#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2667#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2668#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2669#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2670#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2671#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2672#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2673#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2674
2675#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2676/** @} */
2677
2678
2679/**
2680 * Function pointers for guest paging.
2681 */
2682typedef struct PGMMODEDATAGST
2683{
2684 /** The guest mode type. */
2685 uint32_t uType;
2686 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2687 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2688 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2689 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2690#ifdef IN_RING3
2691 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2692#endif
2693} PGMMODEDATAGST;
2694
2695/** The length of g_aPgmGuestModeData. */
2696#if VBOX_WITH_64_BITS_GUESTS
2697# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2698#else
2699# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2700#endif
2701/** The guest mode data array. */
2702extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2703
2704
2705/**
2706 * Function pointers for shadow paging.
2707 */
2708typedef struct PGMMODEDATASHW
2709{
2710 /** The shadow mode type. */
2711 uint32_t uType;
2712 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2713 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2714 uint64_t fMask, uint32_t fOpFlags));
2715 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2716 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2717#ifdef IN_RING3
2718 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2719#endif
2720} PGMMODEDATASHW;
2721
2722/** The length of g_aPgmShadowModeData. */
2723#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2724/** The shadow mode data array. */
2725extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2726
2727
2728/**
2729 * Function pointers for guest+shadow paging.
2730 */
2731typedef struct PGMMODEDATABTH
2732{
2733 /** The shadow mode type. */
2734 uint32_t uShwType;
2735 /** The guest mode type. */
2736 uint32_t uGstType;
2737
2738 DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2739 DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2740 DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2741 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2742 DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2743 DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2744 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2745#ifndef IN_RING3
2746 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2747 DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNested,
2748 bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2749 bool *pfLockTaken));
2750#endif
2751#ifdef VBOX_STRICT
2752 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2753#endif
2754} PGMMODEDATABTH;
2755
2756/** The length of g_aPgmBothModeData. */
2757#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2758/** The guest+shadow mode data array. */
2759extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2760
2761
2762#ifdef VBOX_WITH_STATISTICS
2763/**
2764 * PGM statistics.
2765 */
2766typedef struct PGMSTATS
2767{
2768 /* R3 only: */
2769 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2770 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2771
2772 /* R3+RZ */
2773 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2774 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2775 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2776 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2777 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2778 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2779 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2780 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2781 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2782 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2783 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2784 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2785 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2786 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2787 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2788 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2789 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2790 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2791 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2792 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2793 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2794 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2795/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2796 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2797 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2798/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2799
2800 /* RC only: */
2801 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2802 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2803
2804 STAMCOUNTER StatRZPhysRead;
2805 STAMCOUNTER StatRZPhysReadBytes;
2806 STAMCOUNTER StatRZPhysWrite;
2807 STAMCOUNTER StatRZPhysWriteBytes;
2808 STAMCOUNTER StatR3PhysRead;
2809 STAMCOUNTER StatR3PhysReadBytes;
2810 STAMCOUNTER StatR3PhysWrite;
2811 STAMCOUNTER StatR3PhysWriteBytes;
2812 STAMCOUNTER StatRCPhysRead;
2813 STAMCOUNTER StatRCPhysReadBytes;
2814 STAMCOUNTER StatRCPhysWrite;
2815 STAMCOUNTER StatRCPhysWriteBytes;
2816
2817 STAMCOUNTER StatRZPhysSimpleRead;
2818 STAMCOUNTER StatRZPhysSimpleReadBytes;
2819 STAMCOUNTER StatRZPhysSimpleWrite;
2820 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2821 STAMCOUNTER StatR3PhysSimpleRead;
2822 STAMCOUNTER StatR3PhysSimpleReadBytes;
2823 STAMCOUNTER StatR3PhysSimpleWrite;
2824 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2825 STAMCOUNTER StatRCPhysSimpleRead;
2826 STAMCOUNTER StatRCPhysSimpleReadBytes;
2827 STAMCOUNTER StatRCPhysSimpleWrite;
2828 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2829
2830 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2831 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2832 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2833 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2834 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2835 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2836 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2837
2838 STAMPROFILE StatLargePageAlloc2; /**< Time spent setting up newly allocated large pages. */
2839 STAMPROFILE StatLargePageSetup; /**< Time spent setting up newly allocated large pages. */
2840 /** pgmPhysIsValidLargePage profiling - R3 */
2841 STAMPROFILE StatR3IsValidLargePage;
2842 /** pgmPhysIsValidLargePage profiling - RZ*/
2843 STAMPROFILE StatRZIsValidLargePage;
2844
2845 STAMPROFILE StatChunkAging;
2846 STAMPROFILE StatChunkFindCandidate;
2847 STAMPROFILE StatChunkUnmap;
2848 STAMPROFILE StatChunkMap;
2849} PGMSTATS;
2850#endif /* VBOX_WITH_STATISTICS */
2851
2852
2853/**
2854 * PGM Data (part of VM)
2855 */
2856typedef struct PGM
2857{
2858 /** The zero page. */
2859 uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2860 /** The MMIO placeholder page. */
2861 uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2862
2863 /** @name The zero page (abPagePg).
2864 * @{ */
2865 /** The host physical address of the zero page. */
2866 RTHCPHYS HCPhysZeroPg;
2867 /** @}*/
2868
2869 /** @name The Invalid MMIO page (abMmioPg).
2870 * This page is filled with 0xfeedface.
2871 * @{ */
2872 /** The host physical address of the invalid MMIO page. */
2873 RTHCPHYS HCPhysMmioPg;
2874 /** The host pysical address of the invalid MMIO page plus all invalid
2875 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2876 * @remarks Check fLessThan52PhysicalAddressBits before use. */
2877 RTHCPHYS HCPhysInvMmioPg;
2878 /** @} */
2879
2880 /** @cfgm{/RamPreAlloc, boolean, false}
2881 * Indicates whether the base RAM should all be allocated before starting
2882 * the VM (default), or if it should be allocated when first written to.
2883 */
2884 bool fRamPreAlloc;
2885#ifdef VBOX_WITH_PGM_NEM_MODE
2886 /** Set if we're operating in NEM memory mode.
2887 *
2888 * NEM mode implies that memory is allocated in big chunks for each RAM range
2889 * rather than on demand page by page. Memory is also not locked and PGM has
2890 * therefore no physical addresses for them. Page sharing is out of the
2891 * question. Ballooning depends on the native execution engine, but probably
2892 * pointless as well. */
2893 bool fNemMode;
2894# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2895#else
2896# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2897#endif
2898 /** Indicates whether write monitoring is currently in use.
2899 * This is used to prevent conflicts between live saving and page sharing
2900 * detection. */
2901 bool fPhysWriteMonitoringEngaged;
2902 /** Set if the CPU has less than 52-bit physical address width.
2903 * This is used */
2904 bool fLessThan52PhysicalAddressBits;
2905 /** Set when nested paging is active.
2906 * This is meant to save calls to HMIsNestedPagingActive and let the
2907 * compilers optimize the code better. Whether we use nested paging or
2908 * not is something we find out during VMM initialization and we won't
2909 * change this later on. */
2910 bool fNestedPaging;
2911 /** We're not in a state which permits writes to guest memory.
2912 * (Only used in strict builds.) */
2913 bool fNoMorePhysWrites;
2914 /** @cfgm{/PageFusionAllowed, boolean, false}
2915 * Whether page fusion is allowed. */
2916 bool fPageFusionAllowed;
2917 /** @cfgm{/PGM/PciPassThrough, boolean, false}
2918 * Whether PCI passthrough is enabled. */
2919 bool fPciPassthrough;
2920 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2921 uint8_t cMmio2Regions;
2922 /** Restore original ROM page content when resetting after loading state.
2923 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2924 * enables the VM to start using an updated ROM without requiring powering
2925 * down the VM, just rebooting or resetting it. */
2926 bool fRestoreRomPagesOnReset;
2927 /** Whether to automatically clear all RAM pages on reset. */
2928 bool fZeroRamPagesOnReset;
2929 /** Large page enabled flag. */
2930 bool fUseLargePages;
2931 /** Alignment padding. */
2932#ifndef VBOX_WITH_PGM_NEM_MODE
2933 bool afAlignment3[1];
2934#endif
2935 /** The host paging mode. (This is what SUPLib reports.) */
2936 SUPPAGINGMODE enmHostMode;
2937 bool afAlignment3b[2];
2938
2939 /** Generation ID for the RAM ranges. This member is incremented everytime
2940 * a RAM range is linked or unlinked. */
2941 uint32_t volatile idRamRangesGen;
2942
2943 /** Physical access handler type for ROM protection. */
2944 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2945 /** Physical access handler type for MMIO2 dirty page tracing. */
2946 PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
2947
2948 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2949 RTGCPHYS GCPhys4MBPSEMask;
2950 /** Mask containing the invalid bits of a guest physical address.
2951 * @remarks this does not stop at bit 52. */
2952 RTGCPHYS GCPhysInvAddrMask;
2953
2954
2955 /** RAM range TLB for R3. */
2956 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2957 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2958 * This is sorted by physical address and contains no overlapping ranges. */
2959 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2960 /** Root of the RAM range search tree for ring-3. */
2961 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2962 /** Shadow Page Pool - R3 Ptr. */
2963 R3PTRTYPE(PPGMPOOL) pPoolR3;
2964 /** Pointer to the list of ROM ranges - for R3.
2965 * This is sorted by physical address and contains no overlapping ranges. */
2966 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2967 /** Pointer to the list of MMIO2 ranges - for R3.
2968 * Registration order. */
2969 R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
2970 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
2971 R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
2972
2973 /** RAM range TLB for R0. */
2974 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
2975 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
2976 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
2977 /** Root of the RAM range search tree for ring-0. */
2978 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
2979 /** Shadow Page Pool - R0 Ptr. */
2980 R0PTRTYPE(PPGMPOOL) pPoolR0;
2981 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2982 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2983 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
2984 R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
2985
2986 /** Hack: Number of deprecated page mapping locks taken by the current lock
2987 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
2988 uint32_t cDeprecatedPageLocks;
2989
2990 /** Registered physical access handler types. */
2991 uint32_t cPhysHandlerTypes;
2992 /** Physical access handler types.
2993 * Initialized to callback causing guru meditations and invalid enmKind. */
2994 PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
2995 /** Physical handler allocator, ring-3 edition. */
2996#ifdef IN_RING3
2997 PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
2998#else
2999 RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3000#endif
3001 /** The pointer to the ring-3 mapping of the physical access handler tree. */
3002 R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3003 /** Caching the last physical handler we looked. */
3004 uint32_t idxLastPhysHandler;
3005
3006 uint32_t au64Padding3[5];
3007
3008 /** PGM critical section.
3009 * This protects the physical, ram ranges, and the page flag updating (some of
3010 * it anyway).
3011 */
3012 PDMCRITSECT CritSectX;
3013
3014 /**
3015 * Data associated with managing the ring-3 mappings of the allocation chunks.
3016 */
3017 struct
3018 {
3019 /** The chunk mapping TLB. */
3020 PGMCHUNKR3MAPTLB Tlb;
3021 /** The chunk tree, ordered by chunk id. */
3022 R3PTRTYPE(PAVLU32NODECORE) pTree;
3023#if HC_ARCH_BITS == 32
3024 uint32_t u32Alignment0;
3025#endif
3026 /** The number of mapped chunks. */
3027 uint32_t c;
3028 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3029 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3030 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3031 uint32_t cMax;
3032 /** The current time. This is incremented whenever a chunk is inserted. */
3033 uint32_t iNow;
3034 /** Alignment padding. */
3035 uint32_t au32Alignment1[3];
3036 } ChunkR3Map;
3037
3038 /** The page mapping TLB for ring-3. */
3039 PGMPAGER3MAPTLB PhysTlbR3;
3040 /** The page mapping TLB for ring-0. */
3041 PGMPAGER0MAPTLB PhysTlbR0;
3042
3043 /** The number of handy pages. */
3044 uint32_t cHandyPages;
3045
3046 /** The number of large handy pages. */
3047 uint32_t cLargeHandyPages;
3048
3049 /**
3050 * Array of handy pages.
3051 *
3052 * This array is used in a two way communication between pgmPhysAllocPage
3053 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3054 * an intermediary.
3055 *
3056 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3057 * (The current size of 32 pages, means 128 KB of handy memory.)
3058 */
3059 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3060
3061 /**
3062 * Array of large handy pages. (currently size 1)
3063 *
3064 * This array is used in a two way communication between pgmPhysAllocLargePage
3065 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3066 * an intermediary.
3067 */
3068 GMMPAGEDESC aLargeHandyPage[1];
3069 /** When to try allocate large pages again after a failure. */
3070 uint64_t nsLargePageRetry;
3071 /** Number of repeated long allocation times. */
3072 uint32_t cLargePageLongAllocRepeats;
3073 uint32_t uPadding5;
3074
3075 /**
3076 * Live save data.
3077 */
3078 struct
3079 {
3080 /** Per type statistics. */
3081 struct
3082 {
3083 /** The number of ready pages. */
3084 uint32_t cReadyPages;
3085 /** The number of dirty pages. */
3086 uint32_t cDirtyPages;
3087 /** The number of ready zero pages. */
3088 uint32_t cZeroPages;
3089 /** The number of write monitored pages. */
3090 uint32_t cMonitoredPages;
3091 } Rom,
3092 Mmio2,
3093 Ram;
3094 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3095 uint32_t cIgnoredPages;
3096 /** Indicates that a live save operation is active. */
3097 bool fActive;
3098 /** Padding. */
3099 bool afReserved[2];
3100 /** The next history index. */
3101 uint8_t iDirtyPagesHistory;
3102 /** History of the total amount of dirty pages. */
3103 uint32_t acDirtyPagesHistory[64];
3104 /** Short term dirty page average. */
3105 uint32_t cDirtyPagesShort;
3106 /** Long term dirty page average. */
3107 uint32_t cDirtyPagesLong;
3108 /** The number of saved pages. This is used to get some kind of estimate of the
3109 * link speed so we can decide when we're done. It is reset after the first
3110 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3111 * zero pages. */
3112 uint64_t cSavedPages;
3113 /** The nanosecond timestamp when cSavedPages was 0. */
3114 uint64_t uSaveStartNS;
3115 /** Pages per second (for statistics). */
3116 uint32_t cPagesPerSecond;
3117 uint32_t cAlignment;
3118 } LiveSave;
3119
3120 /** @name Error injection.
3121 * @{ */
3122 /** Inject handy page allocation errors pretending we're completely out of
3123 * memory. */
3124 bool volatile fErrInjHandyPages;
3125 /** Padding. */
3126 bool afReserved[3];
3127 /** @} */
3128
3129 /** @name Release Statistics
3130 * @{ */
3131 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3132 uint32_t cPrivatePages; /**< The number of private pages. */
3133 uint32_t cSharedPages; /**< The number of shared pages. */
3134 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3135 uint32_t cZeroPages; /**< The number of zero backed pages. */
3136 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3137 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3138 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3139 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3140 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3141 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3142 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3143 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3144 uint32_t cLargePages; /**< The number of large pages. */
3145 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3146/* uint32_t aAlignment4[1]; */
3147
3148 STAMPROFILE StatLargePageAlloc; /**< Time spent by the host OS for large page allocation. */
3149 STAMCOUNTER StatLargePageAllocFailed; /**< Count allocation failures. */
3150 STAMCOUNTER StatLargePageOverflow; /**< The number of times allocating a large pages takes more than the allowed period. */
3151 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3152 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3153 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3154 STAMCOUNTER StatLargePageTlbFlush; /**< The number of a full VCPU TLB flush was required after allocation. */
3155 STAMCOUNTER StatLargePageZeroEvict; /**< The number of zero page mappings we had to evict when allocating a large page. */
3156
3157 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3158
3159 STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /**< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. */
3160 /** @} */
3161
3162#ifdef VBOX_WITH_STATISTICS
3163 /** These are optional statistics that used to be on the hyper heap. */
3164 PGMSTATS Stats;
3165#endif
3166} PGM;
3167#ifndef IN_TSTVMSTRUCTGC /* HACK */
3168AssertCompileMemberAlignment(PGM, CritSectX, 8);
3169AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3170AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3171AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3172AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3173AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3174#endif /* !IN_TSTVMSTRUCTGC */
3175/** Pointer to the PGM instance data. */
3176typedef PGM *PPGM;
3177
3178
3179#ifdef VBOX_WITH_STATISTICS
3180/**
3181 * Per CPU statistis for PGM (used to be on the heap).
3182 */
3183typedef struct PGMCPUSTATS
3184{
3185 /* Common */
3186 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3187 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3188
3189 /* R0 only: */
3190 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3191 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3192
3193 /* RZ only: */
3194 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3195 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3196 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3197 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3198 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3199 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3200 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3201 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3202 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3203 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3204 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3205 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3206 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3207 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3208 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3209 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3210 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3211 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3212 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3213 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3214 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3215 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3216 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3217 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3218 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3219 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3220 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3221 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3222 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3223 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3224 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3225 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3226 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3227 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3228 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3229 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3230 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3231 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3232 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3233 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3234 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3235 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3236 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3237 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3238 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3239 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3240 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3241 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3242 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3243 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3244 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3245 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3246 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3247 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3248 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3249 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3250 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3251 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3252 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3253 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3254 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3255 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3256 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3257 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3258 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3259 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3260 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3261 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3262 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3263 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3264
3265 /* HC - R3 and (maybe) R0: */
3266
3267 /* RZ & R3: */
3268 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3269 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3270 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3271 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3272 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3273 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3274 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3275 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3276 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3277 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3278 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3279 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3280 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3281 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3282 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3283 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3284 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3285 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3286 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3287 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3288 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3289 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3290 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3291 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3292 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3293 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3294 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3295 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3296 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3297 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3298 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3299 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3300 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3301 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3302 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3303 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3304 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3305 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3306 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3307 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3308 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3309 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3310 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3311 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3312 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3313 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3314 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3315
3316 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3317 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3318 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3319 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3320 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3321 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3322 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3323 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3324 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3325 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3326 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3327 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3328 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3329 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3330 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3331 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3332 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3333 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3334 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3335 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3336 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3337 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3338 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3339 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3340 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3341 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3342 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3343 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3344 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3345 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3346 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3347 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3348 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3349 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3350 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3351 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3352 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3353 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3354 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3355 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3356 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3357 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3358 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3359 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3360 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3361 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3362} PGMCPUSTATS;
3363#endif /* VBOX_WITH_STATISTICS */
3364
3365
3366/**
3367 * PGMCPU Data (part of VMCPU).
3368 */
3369typedef struct PGMCPU
3370{
3371 /** A20 gate mask.
3372 * Our current approach to A20 emulation is to let REM do it and don't bother
3373 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3374 * But whould need arrise, we'll subject physical addresses to this mask. */
3375 RTGCPHYS GCPhysA20Mask;
3376 /** A20 gate state - boolean! */
3377 bool fA20Enabled;
3378 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3379 bool fNoExecuteEnabled;
3380 /** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3381 * active. */
3382 bool fPaePdpesAndCr3MappedR3;
3383 bool fPaePdpesAndCr3MappedR0;
3384
3385 /** What needs syncing (PGM_SYNC_*).
3386 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3387 * PGMFlushTLB, and PGMR3Load. */
3388 uint32_t fSyncFlags;
3389
3390 /** The shadow paging mode. */
3391 PGMMODE enmShadowMode;
3392 /** The guest paging mode. */
3393 PGMMODE enmGuestMode;
3394 /** The guest second level address translation mode. */
3395 PGMSLAT enmGuestSlatMode;
3396 /** Guest mode data table index (PGM_TYPE_XXX). */
3397 uint8_t volatile idxGuestModeData;
3398 /** Shadow mode data table index (PGM_TYPE_XXX). */
3399 uint8_t volatile idxShadowModeData;
3400 /** Both mode data table index (complicated). */
3401 uint8_t volatile idxBothModeData;
3402 /** Alignment padding. */
3403 uint8_t abPadding[1];
3404
3405 /** The guest CR3.
3406 * When SLAT is active, this is the translated physical address.
3407 * When SLAT is inactive, this is the physical address in CR3. */
3408 RTGCPHYS GCPhysCR3;
3409
3410 /** The nested-guest CR3.
3411 * When SLAT is active, this is CR3 prior to translation.
3412 * When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3413 RTGCPHYS GCPhysNstGstCR3;
3414
3415 /** The cached guest CR3 when it has been mapped in PAE mode.
3416 * This allows us to skip remapping the CR3 and PAE PDPEs
3417 * (in PGMFlushTLB or similar) when it was already done as
3418 * part of MOV CRx instruction emulation.
3419 */
3420 RTGCPHYS GCPhysPaeCR3;
3421
3422 /** @name 32-bit Guest Paging.
3423 * @{ */
3424 /** The guest's page directory, R3 pointer. */
3425 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3426 /** The guest's page directory, R0 pointer. */
3427 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3428 /** Mask containing the MBZ bits of a big page PDE. */
3429 uint32_t fGst32BitMbzBigPdeMask;
3430 /** Set if the page size extension (PSE) is enabled. */
3431 bool fGst32BitPageSizeExtension;
3432 /** Alignment padding. */
3433 bool afAlignment2[3];
3434 /** @} */
3435
3436 /** @name PAE Guest Paging.
3437 * @{ */
3438 /** The guest's page directory pointer table, R3 pointer. */
3439 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3440 /** The guest's page directory pointer table, R0 pointer. */
3441 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3442
3443 /** The guest's page directories, R3 pointers.
3444 * These are individual pointers and don't have to be adjacent.
3445 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3446 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3447 /** The guest's page directories, R0 pointers.
3448 * Same restrictions as apGstPaePDsR3. */
3449 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3450 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3451 RTGCPHYS aGCPhysGstPaePDs[4];
3452 /** The physical addresses of the monitored guest page directories (PAE). */
3453 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3454 /** Mask containing the MBZ PTE bits. */
3455 uint64_t fGstPaeMbzPteMask;
3456 /** Mask containing the MBZ PDE bits. */
3457 uint64_t fGstPaeMbzPdeMask;
3458 /** Mask containing the MBZ big page PDE bits. */
3459 uint64_t fGstPaeMbzBigPdeMask;
3460 /** Mask containing the MBZ PDPE bits. */
3461 uint64_t fGstPaeMbzPdpeMask;
3462 /** @} */
3463
3464 /** @name AMD64 Guest Paging.
3465 * @{ */
3466 /** The guest's page directory pointer table, R3 pointer. */
3467 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3468 /** The guest's page directory pointer table, R0 pointer. */
3469 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3470 /** Mask containing the MBZ PTE bits. */
3471 uint64_t fGstAmd64MbzPteMask;
3472 /** Mask containing the MBZ PDE bits. */
3473 uint64_t fGstAmd64MbzPdeMask;
3474 /** Mask containing the MBZ big page PDE bits. */
3475 uint64_t fGstAmd64MbzBigPdeMask;
3476 /** Mask containing the MBZ PDPE bits. */
3477 uint64_t fGstAmd64MbzPdpeMask;
3478 /** Mask containing the MBZ big page PDPE bits. */
3479 uint64_t fGstAmd64MbzBigPdpeMask;
3480 /** Mask containing the MBZ PML4E bits. */
3481 uint64_t fGstAmd64MbzPml4eMask;
3482 /** Mask containing the PDPE bits that we shadow. */
3483 uint64_t fGstAmd64ShadowedPdpeMask;
3484 /** Mask containing the PML4E bits that we shadow. */
3485 uint64_t fGstAmd64ShadowedPml4eMask;
3486 /** @} */
3487
3488 /** @name PAE and AMD64 Guest Paging.
3489 * @{ */
3490 /** Mask containing the PTE bits that we shadow. */
3491 uint64_t fGst64ShadowedPteMask;
3492 /** Mask containing the PDE bits that we shadow. */
3493 uint64_t fGst64ShadowedPdeMask;
3494 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3495 uint64_t fGst64ShadowedBigPdeMask;
3496 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3497 uint64_t fGst64ShadowedBigPde4PteMask;
3498 /** @} */
3499
3500 /** @name EPT Guest Paging.
3501 * @{ */
3502 /** The guest's page directory pointer table, R3 pointer. */
3503 R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3504 /** The guest's page directory pointer table, R0 pointer. */
3505 R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3506 /** The guest's EPT pointer (copy of virtual VMCS). */
3507 uint64_t uEptPtr;
3508 /** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3509 * change through the lifetime of the VM. */
3510 uint64_t uEptVpidCapMsr;
3511 /** Mask containing the MBZ PTE bits. */
3512 uint64_t fGstEptMbzPteMask;
3513 /** Mask containing the MBZ PDE bits. */
3514 uint64_t fGstEptMbzPdeMask;
3515 /** Mask containing the MBZ big page (2M) PDE bits. */
3516 uint64_t fGstEptMbzBigPdeMask;
3517 /** Mask containing the MBZ PDPTE bits. */
3518 uint64_t fGstEptMbzPdpteMask;
3519 /** Mask containing the MBZ big page (1G) PDPTE bits. */
3520 uint64_t fGstEptMbzBigPdpteMask;
3521 /** Mask containing the MBZ PML4E bits. */
3522 uint64_t fGstEptMbzPml4eMask;
3523 /** Mask to determine whether an entry is present. */
3524 uint64_t fGstEptPresentMask;
3525 /** @} */
3526
3527 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3528 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3529 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3530 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3531
3532 /** For saving stack space, the disassembler state is allocated here instead of
3533 * on the stack. */
3534 DISCPUSTATE DisState;
3535
3536 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3537 uint64_t cNetwareWp0Hacks;
3538
3539 /** Count the number of pgm pool access handler calls. */
3540 uint64_t cPoolAccessHandler;
3541
3542 /** @name Release Statistics
3543 * @{ */
3544 /** The number of times the guest has switched mode since last reset or statistics reset. */
3545 STAMCOUNTER cGuestModeChanges;
3546 /** The number of times the guest has switched mode since last reset or statistics reset. */
3547 STAMCOUNTER cA20Changes;
3548 /** @} */
3549
3550#ifdef VBOX_WITH_STATISTICS
3551 /** These are statistics that used to be on the hyper heap. */
3552 PGMCPUSTATS Stats;
3553#endif
3554} PGMCPU;
3555/** Pointer to the per-cpu PGM data. */
3556typedef PGMCPU *PPGMCPU;
3557
3558
3559/** @name PGM::fSyncFlags Flags
3560 * @note Was part of saved state a long time ago.
3561 * @{
3562 */
3563/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3564/** Always sync CR3. */
3565#define PGM_SYNC_ALWAYS RT_BIT(1)
3566/** Check guest mapping in SyncCR3. */
3567#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3568/** Clear the page pool (a light weight flush). */
3569#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3570#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3571/** @} */
3572
3573
3574#if defined(IN_RING0) || defined(DOXYGEN_RUNNING)
3575
3576/**
3577 * PGM GVMCPU instance data.
3578 */
3579typedef struct PGMR0PERVCPU
3580{
3581# ifdef VBOX_WITH_STATISTICS
3582 /** R0: Which statistic this \#PF should be attributed to. */
3583 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3584# endif
3585 uint64_t u64Dummy;
3586} PGMR0PERVCPU;
3587
3588
3589/**
3590 * PGM GVM instance data.
3591 */
3592typedef struct PGMR0PERVM
3593{
3594 /** @name PGM Pool related stuff.
3595 * @{ */
3596 /** Critical section for serializing pool growth. */
3597 RTCRITSECT PoolGrowCritSect;
3598 /** The memory objects for the pool pages. */
3599 RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3600 /** The ring-3 mapping objects for the pool pages. */
3601 RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3602 /** @} */
3603
3604 /** Physical access handler types for ring-0.
3605 * Initialized to callback causing return to ring-3 and invalid enmKind. */
3606 PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3607 /** Physical handler allocator, ring-3 edition. */
3608 PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3609 /** The pointer to the ring-3 mapping of the physical access handler tree. */
3610 PPGMPHYSHANDLERTREE pPhysHandlerTree;
3611 /** The allocation object for the physical access handler tree. */
3612 RTR0MEMOBJ hPhysHandlerMemObj;
3613 /** The ring-3 mapping object for the physicall access handler tree. */
3614 RTR0MEMOBJ hPhysHandlerMapObj;
3615} PGMR0PERVM;
3616
3617#endif /* IN_RING0 || DOXYGEN_RUNNING */
3618
3619RT_C_DECLS_BEGIN
3620
3621#if defined(VBOX_STRICT)
3622int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3623# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3624# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3625#else
3626int pgmLock(PVMCC pVM, bool fVoid);
3627# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3628# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3629#endif
3630void pgmUnlock(PVMCC pVM);
3631# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3632/**
3633 * Asserts that the caller owns the PDM lock.
3634 * This is the internal variant of PGMIsLockOwner.
3635 * @param a_pVM Pointer to the VM.
3636 */
3637#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3638/**
3639 * Asserts that the caller owns the PDM lock.
3640 * This is the internal variant of PGMIsLockOwner.
3641 * @param a_pVM Pointer to the VM.
3642 * @param a_pVCpu The current CPU handle.
3643 */
3644#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3645
3646uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t *pcEntries, uint32_t *pcbTreeAndBitmap);
3647int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3648 R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3649int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3650int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3651int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3652int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3653void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3654bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3655void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3656DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3657DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3658DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3659#ifndef IN_RING3
3660DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3661DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3662#endif
3663
3664int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3665
3666int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3667int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3668#ifdef IN_RING0
3669int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3670int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3671#endif
3672int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3673int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3674int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3675void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3676int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3677int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3678int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3679int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3680int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3681int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3682int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3683int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3684int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3685int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3686void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3687DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3688DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3689#ifndef IN_RING3
3690DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3691DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3692#endif
3693int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3694 PGMPAGETYPE enmNewType);
3695void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3696void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3697void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3698PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3699PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3700PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3701int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3702int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3703#ifdef VBOX_WITH_NATIVE_NEM
3704void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3705#endif
3706
3707#ifdef IN_RING3
3708void pgmR3PhysRelinkRamRanges(PVM pVM);
3709int pgmR3PhysRamPreAllocate(PVM pVM);
3710int pgmR3PhysRamReset(PVM pVM);
3711int pgmR3PhysRomReset(PVM pVM);
3712int pgmR3PhysRamZeroAll(PVM pVM);
3713int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3714int pgmR3PhysRamTerm(PVM pVM);
3715void pgmR3PhysRomTerm(PVM pVM);
3716void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3717
3718int pgmR3PoolInit(PVM pVM);
3719void pgmR3PoolRelocate(PVM pVM);
3720void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3721void pgmR3PoolReset(PVM pVM);
3722void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3723DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3724void pgmR3PoolWriteProtectPages(PVM pVM);
3725
3726#endif /* IN_RING3 */
3727#ifdef IN_RING0
3728int pgmR0PoolInitVM(PGVM pGVM);
3729#endif
3730int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3731 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3732void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3733void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3734int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3735void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3736PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3737PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3738int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3739int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3740bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3741void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3742int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3743void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3744uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3745void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3746void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3747void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3748PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3749#ifndef IN_RING3
3750DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3751#endif
3752
3753void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3754void pgmPoolResetDirtyPages(PVMCC pVM);
3755void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3756
3757/** Gets the ring-0 pointer for the given pool page. */
3758DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3759{
3760#ifdef IN_RING3
3761 size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3762# ifdef VBOX_STRICT
3763 size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3764 AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3765 AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3766# endif
3767 return pPool->pPoolR0 + offPage;
3768#else
3769 RT_NOREF(pPool);
3770 return pPage;
3771#endif
3772}
3773
3774/** Gets the ring-3 pointer for the given pool page. */
3775DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3776{
3777#ifdef IN_RING3
3778 RT_NOREF(pPool);
3779 return pPage;
3780#else
3781 size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3782# ifdef VBOX_STRICT
3783 size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3784 AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3785 AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3786# endif
3787 return pPool->pPoolR3 + offPage;
3788#endif
3789}
3790
3791int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3792int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3793void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3794
3795int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3796int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3797int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3798
3799int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3800int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3801int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3802int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3803#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3804int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3805#endif
3806int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3807int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3808
3809# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3810FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3811FNDBGCCMD pgmR3CmdShowSharedModules;
3812# endif
3813
3814void pgmLogState(PVM pVM);
3815
3816RT_C_DECLS_END
3817
3818/** @} */
3819
3820#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3821
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