VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 80161

Last change on this file since 80161 was 80135, checked in by vboxsync, 5 years ago

PGM: Split the phys guest->host TLB into separate ring-0 and ring-3 entities and align it properly. bugref:9511 bugref:9517
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1/* $Id: PGMInternal.h 80135 2019-08-05 15:05:33Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Indicates that there are no guest mappings in the shadow tables.
62 *
63 * Note! In ring-3 the macro is also used to exclude the managment of the
64 * intermediate context page tables. On 32-bit systems we use the intermediate
65 * context to support 64-bit guest execution. Thus, we cannot fully make it
66 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67 *
68 * In raw-mode context there are by design always guest mappings (the code is
69 * executed from one), while in ring-0 there are none at all. Neither context
70 * manages the page tables for intermediate switcher context, that's all done in
71 * ring-3.
72 *
73 * Update 6.1: It is always defined now, in pgm.h
74 */
75#if defined(IN_RING0) \
76 || ( !defined(VBOX_WITH_RAW_MODE) \
77 && ( HC_ARCH_BITS != 32 \
78 || !defined(VBOX_WITH_64_BITS_GUESTS) \
79 ) \
80 )
81# undef PGM_WITHOUT_MAPPINGS
82# define PGM_WITHOUT_MAPPINGS
83#endif
84
85/**
86 * Check and skip global PDEs for non-global flushes
87 */
88#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90/**
91 * Optimization for PAE page tables that are modified often
92 */
93//#if 0 /* disabled again while debugging */
94#ifndef IN_RC
95# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
96#endif
97//#endif
98
99/**
100 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
101 */
102#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
103# define PGM_WITH_LARGE_PAGES
104#endif
105
106/**
107 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
108 * VMX_EXIT_EPT_MISCONFIG.
109 */
110#if 1 /* testing */
111# define PGM_WITH_MMIO_OPTIMIZATIONS
112#endif
113
114/**
115 * Sync N pages instead of a whole page table
116 */
117#define PGM_SYNC_N_PAGES
118
119/**
120 * Number of pages to sync during a page fault
121 *
122 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
123 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
124 *
125 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
126 * world switch overhead, so let's sync more.
127 */
128# ifdef IN_RING0
129/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
130 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
131 * but ~5% fewer faults.
132 */
133# define PGM_SYNC_NR_PAGES 32
134#else
135# define PGM_SYNC_NR_PAGES 8
136#endif
137
138/**
139 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
140 */
141#define PGM_MAX_PHYSCACHE_ENTRIES 64
142#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
143
144
145/** @def PGMPOOL_CFG_MAX_GROW
146 * The maximum number of pages to add to the pool in one go.
147 */
148#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
149
150/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
151 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
152 */
153#ifdef VBOX_STRICT
154# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
155#endif
156
157/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
158 * Enables the experimental lazy page allocation code. */
159#ifdef DOXYGEN_RUNNING
160# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
161#endif
162
163/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164 * Enables real write monitoring of pages, i.e. mapping them read-only and
165 * only making them writable when getting a write access \#PF. */
166#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
167
168/** @} */
169
170
171/** @name PDPT and PML4 flags.
172 * These are placed in the three bits available for system programs in
173 * the PDPT and PML4 entries.
174 * @{ */
175/** The entry is a permanent one and it's must always be present.
176 * Never free such an entry. */
177#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
178/** Mapping (hypervisor allocated pagetable). */
179#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
180/** @} */
181
182/** @name Page directory flags.
183 * These are placed in the three bits available for system programs in
184 * the page directory entries.
185 * @{ */
186/** Indicates the original entry was a big page.
187 * @remarks This is currently only used for statistics and can be recycled. */
188#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
189/** Mapping (hypervisor allocated pagetable). */
190#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
191/** Made read-only to facilitate dirty bit tracking. */
192#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
193/** @} */
194
195/** @name Page flags.
196 * These are placed in the three bits available for system programs in
197 * the page entries.
198 * @{ */
199/** Made read-only to facilitate dirty bit tracking. */
200#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
201
202#ifndef PGM_PTFLAGS_CSAM_VALIDATED
203/** Scanned and approved by CSAM (tm).
204 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
205 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
206#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
207#endif
208
209/** @} */
210
211/** @name Defines used to indicate the shadow and guest paging in the templates.
212 * @{ */
213#define PGM_TYPE_REAL 1
214#define PGM_TYPE_PROT 2
215#define PGM_TYPE_32BIT 3
216#define PGM_TYPE_PAE 4
217#define PGM_TYPE_AMD64 5
218#define PGM_TYPE_NESTED_32BIT 6
219#define PGM_TYPE_NESTED_PAE 7
220#define PGM_TYPE_NESTED_AMD64 8
221#define PGM_TYPE_EPT 9
222#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
223#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
224#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
225/** @} */
226
227/** Macro for checking if the guest is using paging.
228 * @param uGstType PGM_TYPE_*
229 * @param uShwType PGM_TYPE_*
230 * @remark ASSUMES certain order of the PGM_TYPE_* values.
231 */
232#define PGM_WITH_PAGING(uGstType, uShwType) \
233 ( (uGstType) >= PGM_TYPE_32BIT \
234 && (uShwType) < PGM_TYPE_NESTED_32BIT)
235
236/** Macro for checking if the guest supports the NX bit.
237 * @param uGstType PGM_TYPE_*
238 * @param uShwType PGM_TYPE_*
239 * @remark ASSUMES certain order of the PGM_TYPE_* values.
240 */
241#define PGM_WITH_NX(uGstType, uShwType) \
242 ( (uGstType) >= PGM_TYPE_PAE \
243 && (uShwType) < PGM_TYPE_NESTED_32BIT)
244
245/** Macro for checking for nested or EPT.
246 * @param uType PGM_TYPE_*
247 */
248#define PGM_TYPE_IS_NESTED(uType) \
249 ( (uType) == PGM_TYPE_NESTED_32BIT \
250 || (uType) == PGM_TYPE_NESTED_PAE \
251 || (uType) == PGM_TYPE_NESTED_AMD64)
252
253/** Macro for checking for nested or EPT.
254 * @param uType PGM_TYPE_*
255 */
256#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
257 ( (uType) == PGM_TYPE_NESTED_32BIT \
258 || (uType) == PGM_TYPE_NESTED_PAE \
259 || (uType) == PGM_TYPE_NESTED_AMD64 \
260 || (uType) == PGM_TYPE_EPT)
261
262
263
264/** @def PGM_HCPHYS_2_PTR
265 * Maps a HC physical page pool address to a virtual address.
266 *
267 * @returns VBox status code.
268 * @param pVM The cross context VM structure.
269 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
270 * @param HCPhys The HC physical address to map to a virtual one.
271 * @param ppv Where to store the virtual address. No need to cast
272 * this.
273 *
274 * @remark Use with care as we don't have so much dynamic mapping space in
275 * ring-0 on 32-bit darwin and in RC.
276 * @remark There is no need to assert on the result.
277 */
278#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
279# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
280 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
281#else
282# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
283 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
284#endif
285
286/** @def PGM_GCPHYS_2_PTR_V2
287 * Maps a GC physical page address to a virtual address.
288 *
289 * @returns VBox status code.
290 * @param pVM The cross context VM structure.
291 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
292 * @param GCPhys The GC physical address to map to a virtual one.
293 * @param ppv Where to store the virtual address. No need to cast this.
294 *
295 * @remark Use with care as we don't have so much dynamic mapping space in
296 * ring-0 on 32-bit darwin and in RC.
297 * @remark There is no need to assert on the result.
298 */
299#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
300# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
301 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
302#else
303# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
304 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
305#endif
306
307/** @def PGM_GCPHYS_2_PTR
308 * Maps a GC physical page address to a virtual address.
309 *
310 * @returns VBox status code.
311 * @param pVM The cross context VM structure.
312 * @param GCPhys The GC physical address to map to a virtual one.
313 * @param ppv Where to store the virtual address. No need to cast this.
314 *
315 * @remark Use with care as we don't have so much dynamic mapping space in
316 * ring-0 on 32-bit darwin and in RC.
317 * @remark There is no need to assert on the result.
318 */
319#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
320
321/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
322 * Maps a GC physical page address to a virtual address.
323 *
324 * @returns VBox status code.
325 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
326 * @param GCPhys The GC physical address to map to a virtual one.
327 * @param ppv Where to store the virtual address. No need to cast this.
328 *
329 * @remark Use with care as we don't have so much dynamic mapping space in
330 * ring-0 on 32-bit darwin and in RC.
331 * @remark There is no need to assert on the result.
332 */
333#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
334
335/** @def PGM_GCPHYS_2_PTR_EX
336 * Maps a unaligned GC physical page address to a virtual address.
337 *
338 * @returns VBox status code.
339 * @param pVM The cross context VM structure.
340 * @param GCPhys The GC physical address to map to a virtual one.
341 * @param ppv Where to store the virtual address. No need to cast this.
342 *
343 * @remark Use with care as we don't have so much dynamic mapping space in
344 * ring-0 on 32-bit darwin and in RC.
345 * @remark There is no need to assert on the result.
346 */
347#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
348# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
349 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
350#else
351# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
352 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
353#endif
354
355/** @def PGM_DYNMAP_UNUSED_HINT
356 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
357 * is no longer used.
358 *
359 * For best effect only apply this to the page that was mapped most recently.
360 *
361 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
362 * @param pvPage The pool page.
363 */
364#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
365# ifdef LOG_ENABLED
366# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
367# else
368# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
369# endif
370#else
371# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
372#endif
373
374/** @def PGM_DYNMAP_UNUSED_HINT_VM
375 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
376 * is no longer used.
377 *
378 * For best effect only apply this to the page that was mapped most recently.
379 *
380 * @param pVM The cross context VM structure.
381 * @param pvPage The pool page.
382 */
383#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
384
385
386/** @def PGM_INVL_PG
387 * Invalidates a page.
388 *
389 * @param pVCpu The cross context virtual CPU structure.
390 * @param GCVirt The virtual address of the page to invalidate.
391 */
392#ifdef IN_RC
393# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
394#elif defined(IN_RING0)
395# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
396#else
397# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
398#endif
399
400/** @def PGM_INVL_PG_ALL_VCPU
401 * Invalidates a page on all VCPUs
402 *
403 * @param pVM The cross context VM structure.
404 * @param GCVirt The virtual address of the page to invalidate.
405 */
406#ifdef IN_RC
407# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
408#elif defined(IN_RING0)
409# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
410#else
411# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
412#endif
413
414/** @def PGM_INVL_BIG_PG
415 * Invalidates a 4MB page directory entry.
416 *
417 * @param pVCpu The cross context virtual CPU structure.
418 * @param GCVirt The virtual address within the page directory to invalidate.
419 */
420#ifdef IN_RC
421# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
422#elif defined(IN_RING0)
423# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
424#else
425# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
426#endif
427
428/** @def PGM_INVL_VCPU_TLBS()
429 * Invalidates the TLBs of the specified VCPU
430 *
431 * @param pVCpu The cross context virtual CPU structure.
432 */
433#ifdef IN_RC
434# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
435#elif defined(IN_RING0)
436# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
437#else
438# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
439#endif
440
441/** @def PGM_INVL_ALL_VCPU_TLBS()
442 * Invalidates the TLBs of all VCPUs
443 *
444 * @param pVM The cross context VM structure.
445 */
446#ifdef IN_RC
447# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
448#elif defined(IN_RING0)
449# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
450#else
451# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
452#endif
453
454
455/** @name Safer Shadow PAE PT/PTE
456 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
457 * present.
458 *
459 * @{
460 */
461#if 1
462/**
463 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
464 * invalid entries for present.
465 * @sa X86PTEPAE.
466 */
467typedef union PGMSHWPTEPAE
468{
469 /** Unsigned integer view */
470 X86PGPAEUINT uCareful;
471 /* Not other views. */
472} PGMSHWPTEPAE;
473
474# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
475# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
476# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
477# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
478# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
479# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
480# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
481# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
482# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
483# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
484# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
485# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
486# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
487# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
488# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
489# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
490
491/**
492 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
493 * invalid entries for present.
494 * @sa X86PTPAE.
495 */
496typedef struct PGMSHWPTPAE
497{
498 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
499} PGMSHWPTPAE;
500
501#else
502typedef X86PTEPAE PGMSHWPTEPAE;
503typedef X86PTPAE PGMSHWPTPAE;
504# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
505# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
506# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
507# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
508# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
509# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
510# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
511# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
512# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
513# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
514# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
515# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
516# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
517# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
518# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
519# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
520
521#endif
522
523/** Pointer to a shadow PAE PTE. */
524typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
525/** Pointer to a const shadow PAE PTE. */
526typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
527
528/** Pointer to a shadow PAE page table. */
529typedef PGMSHWPTPAE *PPGMSHWPTPAE;
530/** Pointer to a const shadow PAE page table. */
531typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
532/** @} */
533
534#ifndef PGM_WITHOUT_MAPPINGS
535
536/** Size of the GCPtrConflict array in PGMMAPPING.
537 * @remarks Must be a power of two. */
538# define PGMMAPPING_CONFLICT_MAX 8
539
540/**
541 * Structure for tracking GC Mappings.
542 *
543 * This structure is used by linked list in both GC and HC.
544 */
545typedef struct PGMMAPPING
546{
547 /** Pointer to next entry. */
548 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
549 /** Pointer to next entry. */
550 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
551 /** Pointer to next entry. */
552 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
553 /** Indicate whether this entry is finalized. */
554 bool fFinalized;
555 /** Start Virtual address. */
556 RTGCPTR GCPtr;
557 /** Last Virtual address (inclusive). */
558 RTGCPTR GCPtrLast;
559 /** Range size (bytes). */
560 RTGCPTR cb;
561 /** Pointer to relocation callback function. */
562 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
563 /** User argument to the callback. */
564 R3PTRTYPE(void *) pvUser;
565 /** Mapping description / name. For easing debugging. */
566 R3PTRTYPE(const char *) pszDesc;
567 /** Last 8 addresses that caused conflicts. */
568 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
569 /** Number of conflicts for this hypervisor mapping. */
570 uint32_t cConflicts;
571 /** Number of page tables. */
572 uint32_t cPTs;
573
574 /** Array of page table mapping data. Each entry
575 * describes one page table. The array can be longer
576 * than the declared length.
577 */
578 struct
579 {
580 /** The HC physical address of the page table. */
581 RTHCPHYS HCPhysPT;
582 /** The HC physical address of the first PAE page table. */
583 RTHCPHYS HCPhysPaePT0;
584 /** The HC physical address of the second PAE page table. */
585 RTHCPHYS HCPhysPaePT1;
586 /** The HC virtual address of the 32-bit page table. */
587 R3PTRTYPE(PX86PT) pPTR3;
588 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
589 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
590 /** The RC virtual address of the 32-bit page table. */
591 RCPTRTYPE(PX86PT) pPTRC;
592 /** The RC virtual address of the two PAE page table. */
593 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
594 /** The R0 virtual address of the 32-bit page table. */
595 R0PTRTYPE(PX86PT) pPTR0;
596 /** The R0 virtual address of the two PAE page table. */
597 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
598 } aPTs[1];
599} PGMMAPPING;
600/** Pointer to structure for tracking GC Mappings. */
601typedef struct PGMMAPPING *PPGMMAPPING;
602
603#endif /* !PGM_WITHOUT_MAPPINGS */
604
605
606/**
607 * Physical page access handler type registration.
608 */
609typedef struct PGMPHYSHANDLERTYPEINT
610{
611 /** Number of references. */
612 uint32_t volatile cRefs;
613 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
614 uint32_t u32Magic;
615 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
616 RTLISTOFF32NODE ListNode;
617 /** The kind of accesses we're handling. */
618 PGMPHYSHANDLERKIND enmKind;
619 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
620 uint32_t uState;
621 /** Pointer to RC callback function. */
622 RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
623 /** Pointer to RC callback function for \#PFs. */
624 RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
625 /** Pointer to R3 callback function. */
626 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
627 /** Pointer to R0 callback function. */
628 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
629 /** Pointer to R0 callback function for \#PFs. */
630 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
631 /** Description / Name. For easing debugging. */
632 R3PTRTYPE(const char *) pszDesc;
633} PGMPHYSHANDLERTYPEINT;
634/** Pointer to a physical access handler type registration. */
635typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
636/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
637#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
638/** Magic value for the physical handler callbacks. */
639#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
640
641/**
642 * Converts a handle to a pointer.
643 * @returns PPGMPHYSHANDLERTYPEINT
644 * @param a_pVM The cross context VM structure.
645 * @param a_hType Physical access handler type handle.
646 */
647#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
648
649
650/**
651 * Physical page access handler structure.
652 *
653 * This is used to keep track of physical address ranges
654 * which are being monitored in some kind of way.
655 */
656typedef struct PGMPHYSHANDLER
657{
658 AVLROGCPHYSNODECORE Core;
659 /** Number of pages to update. */
660 uint32_t cPages;
661 /** Set if we have pages that have been aliased. */
662 uint32_t cAliasedPages;
663 /** Set if we have pages that have temporarily been disabled. */
664 uint32_t cTmpOffPages;
665 /** Registered handler type handle (heap offset). */
666 PGMPHYSHANDLERTYPE hType;
667 /** User argument for RC handlers. */
668 RCPTRTYPE(void *) pvUserRC;
669#if HC_ARCH_BITS == 64
670 RTRCPTR Padding0; /**< Explicit alignment padding. */
671#endif
672 /** User argument for R3 handlers. */
673 R3PTRTYPE(void *) pvUserR3;
674 /** User argument for R0 handlers. */
675 R0PTRTYPE(void *) pvUserR0;
676 /** Description / Name. For easing debugging. */
677 R3PTRTYPE(const char *) pszDesc;
678#ifdef VBOX_WITH_STATISTICS
679 /** Profiling of this handler. */
680 STAMPROFILE Stat;
681#endif
682} PGMPHYSHANDLER;
683/** Pointer to a physical page access handler structure. */
684typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
685
686/**
687 * Gets the type record for a physical handler (no reference added).
688 * @returns PPGMPHYSHANDLERTYPEINT
689 * @param a_pVM The cross context VM structure.
690 * @param a_pPhysHandler Pointer to the physical handler structure
691 * (PGMPHYSHANDLER).
692 */
693#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
694
695
696#ifdef VBOX_WITH_RAW_MODE
697
698/**
699 * Cache node for the physical addresses covered by a virtual handler.
700 */
701typedef struct PGMPHYS2VIRTHANDLER
702{
703 /** Core node for the tree based on physical ranges. */
704 AVLROGCPHYSNODECORE Core;
705 /** Offset from this struct to the PGMVIRTHANDLER structure. */
706 int32_t offVirtHandler;
707 /** Offset of the next alias relative to this one.
708 * Bit 0 is used for indicating whether we're in the tree.
709 * Bit 1 is used for indicating that we're the head node.
710 */
711 int32_t offNextAlias;
712} PGMPHYS2VIRTHANDLER;
713/** Pointer to a phys to virtual handler structure. */
714typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
715
716/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
717 * node is in the tree. */
718# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
719/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
720 * node is in the head of an alias chain.
721 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
722# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
723/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
724# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
725
726
727/**
728 * Virtual page access handler type registration.
729 */
730typedef struct PGMVIRTANDLERTYPEINT
731{
732 /** Number of references. */
733 uint32_t volatile cRefs;
734 /** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
735 uint32_t u32Magic;
736 /** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
737 RTLISTOFF32NODE ListNode;
738 /** The kind of accesses we're handling. */
739 PGMVIRTHANDLERKIND enmKind;
740 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
741 uint32_t uState;
742 /** Whether the pvUserRC argument should be automatically relocated or not. */
743 bool fRelocUserRC;
744 bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
745 /** Pointer to RC callback function. */
746 RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
747 /** Pointer to RC callback function for \#PFs. */
748 RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
749 /** Pointer to the R3 callback function for invalidation. */
750 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
751 /** Pointer to R3 callback function. */
752 R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
753 /** Description / Name. For easing debugging. */
754 R3PTRTYPE(const char *) pszDesc;
755} PGMVIRTHANDLERTYPEINT;
756/** Pointer to a virtual access handler type registration. */
757typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
758/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
759# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
760/** Magic value for the virtual handler callbacks. */
761# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
762
763/**
764 * Converts a handle to a pointer.
765 * @returns PPGMVIRTHANDLERTYPEINT
766 * @param a_pVM The cross context VM structure.
767 * @param a_hType Vitual access handler type handle.
768 */
769# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
770
771
772/**
773 * Virtual page access handler structure.
774 *
775 * This is used to keep track of virtual address ranges
776 * which are being monitored in some kind of way.
777 */
778typedef struct PGMVIRTHANDLER
779{
780 /** Core node for the tree based on virtual ranges. */
781 AVLROGCPTRNODECORE Core;
782 /** Size of the range (in bytes). */
783 uint32_t cb;
784 /** Number of cache pages. */
785 uint32_t cPages;
786 /** Registered handler type handle (heap offset). */
787 PGMVIRTHANDLERTYPE hType;
788 /** User argument for RC handlers. */
789 RCPTRTYPE(void *) pvUserRC;
790 /** User argument for R3 handlers. */
791 R3PTRTYPE(void *) pvUserR3;
792 /** Description / Name. For easing debugging. */
793 R3PTRTYPE(const char *) pszDesc;
794# ifdef VBOX_WITH_STATISTICS
795 /** Profiling of this handler. */
796 STAMPROFILE Stat;
797# endif
798 /** Array of cached physical addresses for the monitored ranged. */
799 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
800} PGMVIRTHANDLER;
801/** Pointer to a virtual page access handler structure. */
802typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
803
804/**
805 * Gets the type record for a virtual handler (no reference added).
806 * @returns PPGMVIRTHANDLERTYPEINT
807 * @param a_pVM The cross context VM structure.
808 * @param a_pVirtHandler Pointer to the virtual handler structure
809 * (PGMVIRTHANDLER).
810 */
811# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
812
813#endif /* VBOX_WITH_RAW_MODE */
814
815
816/**
817 * A Physical Guest Page tracking structure.
818 *
819 * The format of this structure is complicated because we have to fit a lot
820 * of information into as few bits as possible. The format is also subject
821 * to change (there is one coming up soon). Which means that for we'll be
822 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
823 * accesses to the structure.
824 */
825typedef union PGMPAGE
826{
827 /** Structured view. */
828 struct
829 {
830 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
831 uint64_t u2HandlerPhysStateY : 2;
832 /** 3:2 - Paging structure needed to map the page
833 * (PGM_PAGE_PDE_TYPE_*). */
834 uint64_t u2PDETypeY : 2;
835 /** 4 - Unused (was used by FTE for dirty tracking). */
836 uint64_t fUnused1 : 1;
837 /** 5 - Flag indicating that a write monitored page was written to
838 * when set. */
839 uint64_t fWrittenToY : 1;
840 /** 7:6 - Unused. */
841 uint64_t u2Unused0 : 2;
842 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
843 uint64_t u2HandlerVirtStateY : 2;
844 /** 11:10 - NEM state bits. */
845 uint64_t u2NemStateY : 2;
846 /** 12:48 - The host physical frame number (shift left to get the
847 * address). */
848 uint64_t HCPhysFN : 36;
849 /** 50:48 - The page state. */
850 uint64_t uStateY : 3;
851 /** 51:53 - The page type (PGMPAGETYPE). */
852 uint64_t uTypeY : 3;
853 /** 63:54 - PTE index for usage tracking (page pool). */
854 uint64_t u10PteIdx : 10;
855
856 /** The GMM page ID.
857 * @remarks In the current implementation, MMIO2 and pages aliased to
858 * MMIO2 pages will be exploiting this field to calculate the
859 * ring-3 mapping address corresponding to the page.
860 * Later we may consider including MMIO2 management into GMM. */
861 uint32_t idPage;
862 /** Usage tracking (page pool). */
863 uint16_t u16TrackingY;
864 /** The number of read locks on this page. */
865 uint8_t cReadLocksY;
866 /** The number of write locks on this page. */
867 uint8_t cWriteLocksY;
868 } s;
869
870 /** 64-bit integer view. */
871 uint64_t au64[2];
872 /** 16-bit view. */
873 uint32_t au32[4];
874 /** 16-bit view. */
875 uint16_t au16[8];
876 /** 8-bit view. */
877 uint8_t au8[16];
878} PGMPAGE;
879AssertCompileSize(PGMPAGE, 16);
880/** Pointer to a physical guest page. */
881typedef PGMPAGE *PPGMPAGE;
882/** Pointer to a const physical guest page. */
883typedef const PGMPAGE *PCPGMPAGE;
884/** Pointer to a physical guest page pointer. */
885typedef PPGMPAGE *PPPGMPAGE;
886
887
888/**
889 * Clears the page structure.
890 * @param a_pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_CLEAR(a_pPage) \
893 do { \
894 (a_pPage)->au64[0] = 0; \
895 (a_pPage)->au64[1] = 0; \
896 } while (0)
897
898/**
899 * Initializes the page structure.
900 * @param a_pPage Pointer to the physical guest page tracking structure.
901 * @param a_HCPhys The host physical address of the page.
902 * @param a_idPage The (GMM) page ID of the page.
903 * @param a_uType The page type (PGMPAGETYPE).
904 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
905 */
906#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
907 do { \
908 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
909 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
910 (a_pPage)->au64[0] = SetHCPhysTmp; \
911 (a_pPage)->au64[1] = 0; \
912 (a_pPage)->s.idPage = (a_idPage); \
913 (a_pPage)->s.uStateY = (a_uState); \
914 (a_pPage)->s.uTypeY = (a_uType); \
915 } while (0)
916
917/**
918 * Initializes the page structure of a ZERO page.
919 * @param a_pPage Pointer to the physical guest page tracking structure.
920 * @param a_pVM The VM handle (for getting the zero page address).
921 * @param a_uType The page type (PGMPAGETYPE).
922 */
923#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
924 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
925
926
927/** @name The Page state, PGMPAGE::uStateY.
928 * @{ */
929/** The zero page.
930 * This is a per-VM page that's never ever mapped writable. */
931#define PGM_PAGE_STATE_ZERO 0U
932/** A allocated page.
933 * This is a per-VM page allocated from the page pool (or wherever
934 * we get MMIO2 pages from if the type is MMIO2).
935 */
936#define PGM_PAGE_STATE_ALLOCATED 1U
937/** A allocated page that's being monitored for writes.
938 * The shadow page table mappings are read-only. When a write occurs, the
939 * fWrittenTo member is set, the page remapped as read-write and the state
940 * moved back to allocated. */
941#define PGM_PAGE_STATE_WRITE_MONITORED 2U
942/** The page is shared, aka. copy-on-write.
943 * This is a page that's shared with other VMs. */
944#define PGM_PAGE_STATE_SHARED 3U
945/** The page is ballooned, so no longer available for this VM. */
946#define PGM_PAGE_STATE_BALLOONED 4U
947/** @} */
948
949
950/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
951#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
952# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
953#else
954# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
955#endif
956
957/**
958 * Gets the page state.
959 * @returns page state (PGM_PAGE_STATE_*).
960 * @param a_pPage Pointer to the physical guest page tracking structure.
961 *
962 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
963 * builds.
964 */
965#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
966#if defined(__GNUC__) && defined(VBOX_STRICT)
967# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
968#else
969# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
970#endif
971
972/**
973 * Sets the page state.
974 * @param a_pVM The VM handle, only used for lock ownership assertions.
975 * @param a_pPage Pointer to the physical guest page tracking structure.
976 * @param a_uState The new page state.
977 */
978#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
979 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
980
981
982/**
983 * Gets the host physical address of the guest page.
984 * @returns host physical address (RTHCPHYS).
985 * @param a_pPage Pointer to the physical guest page tracking structure.
986 *
987 * @remarks In strict builds on gcc platforms, this macro will make some ugly
988 * assumption about a valid pVM variable/parameter being in the
989 * current context. It will use this pVM variable to assert that the
990 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
991 * pVM is not around.
992 */
993#if 0
994# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
995# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
996#else
997# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
998# if defined(__GNUC__) && defined(VBOX_STRICT)
999# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
1000# else
1001# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
1002# endif
1003#endif
1004
1005/**
1006 * Sets the host physical address of the guest page.
1007 *
1008 * @param a_pVM The VM handle, only used for lock ownership assertions.
1009 * @param a_pPage Pointer to the physical guest page tracking structure.
1010 * @param a_HCPhys The new host physical address.
1011 */
1012#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
1013 do { \
1014 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
1015 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
1016 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
1017 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1018 } while (0)
1019
1020/**
1021 * Get the Page ID.
1022 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1023 * @param a_pPage Pointer to the physical guest page tracking structure.
1024 */
1025#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1026
1027/**
1028 * Sets the Page ID.
1029 * @param a_pVM The VM handle, only used for lock ownership assertions.
1030 * @param a_pPage Pointer to the physical guest page tracking structure.
1031 * @param a_idPage The new page ID.
1032 */
1033#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1034 do { \
1035 (a_pPage)->s.idPage = (a_idPage); \
1036 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1037 } while (0)
1038
1039/**
1040 * Get the Chunk ID.
1041 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1042 * @param a_pPage Pointer to the physical guest page tracking structure.
1043 */
1044#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1045
1046/**
1047 * Get the index of the page within the allocation chunk.
1048 * @returns The page index.
1049 * @param a_pPage Pointer to the physical guest page tracking structure.
1050 */
1051#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1052
1053/**
1054 * Gets the page type.
1055 * @returns The page type.
1056 * @param a_pPage Pointer to the physical guest page tracking structure.
1057 *
1058 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1059 * builds.
1060 */
1061#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1062#if defined(__GNUC__) && defined(VBOX_STRICT)
1063# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1064#else
1065# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1066#endif
1067
1068/**
1069 * Sets the page type.
1070 *
1071 * @param a_pVM The VM handle, only used for lock ownership assertions.
1072 * @param a_pPage Pointer to the physical guest page tracking structure.
1073 * @param a_enmType The new page type (PGMPAGETYPE).
1074 */
1075#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1076 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1077
1078/**
1079 * Gets the page table index
1080 * @returns The page table index.
1081 * @param a_pPage Pointer to the physical guest page tracking structure.
1082 */
1083#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1084
1085/**
1086 * Sets the page table index.
1087 * @param a_pVM The VM handle, only used for lock ownership assertions.
1088 * @param a_pPage Pointer to the physical guest page tracking structure.
1089 * @param a_iPte New page table index.
1090 */
1091#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1092 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1093
1094/**
1095 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
1096 * @returns true/false.
1097 * @param a_pPage Pointer to the physical guest page tracking structure.
1098 */
1099#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1100
1101/**
1102 * Checks if the page is marked for MMIO, including both aliases.
1103 * @returns true/false.
1104 * @param a_pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1107 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1108 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1109 )
1110
1111/**
1112 * Checks if the page is marked for MMIO, including special aliases.
1113 * @returns true/false.
1114 * @param a_pPage Pointer to the physical guest page tracking structure.
1115 */
1116#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1117 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1118
1119/**
1120 * Checks if the page is a special aliased MMIO page.
1121 * @returns true/false.
1122 * @param a_pPage Pointer to the physical guest page tracking structure.
1123 */
1124#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1125
1126/**
1127 * Checks if the page is backed by the ZERO page.
1128 * @returns true/false.
1129 * @param a_pPage Pointer to the physical guest page tracking structure.
1130 */
1131#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1132
1133/**
1134 * Checks if the page is backed by a SHARED page.
1135 * @returns true/false.
1136 * @param a_pPage Pointer to the physical guest page tracking structure.
1137 */
1138#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1139
1140/**
1141 * Checks if the page is ballooned.
1142 * @returns true/false.
1143 * @param a_pPage Pointer to the physical guest page tracking structure.
1144 */
1145#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1146
1147/**
1148 * Checks if the page is allocated.
1149 * @returns true/false.
1150 * @param a_pPage Pointer to the physical guest page tracking structure.
1151 */
1152#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1153
1154/**
1155 * Marks the page as written to (for GMM change monitoring).
1156 * @param a_pVM The VM handle, only used for lock ownership assertions.
1157 * @param a_pPage Pointer to the physical guest page tracking structure.
1158 */
1159#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1160 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1161
1162/**
1163 * Clears the written-to indicator.
1164 * @param a_pVM The VM handle, only used for lock ownership assertions.
1165 * @param a_pPage Pointer to the physical guest page tracking structure.
1166 */
1167#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1168 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1169
1170/**
1171 * Checks if the page was marked as written-to.
1172 * @returns true/false.
1173 * @param a_pPage Pointer to the physical guest page tracking structure.
1174 */
1175#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1176
1177
1178/** @name PT usage values (PGMPAGE::u2PDEType).
1179 *
1180 * @{ */
1181/** Either as a PT or PDE. */
1182#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1183/** Must use a page table to map the range. */
1184#define PGM_PAGE_PDE_TYPE_PT 1
1185/** Can use a page directory entry to map the continuous range. */
1186#define PGM_PAGE_PDE_TYPE_PDE 2
1187/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1188#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1189/** @} */
1190
1191/**
1192 * Set the PDE type of the page
1193 * @param a_pVM The VM handle, only used for lock ownership assertions.
1194 * @param a_pPage Pointer to the physical guest page tracking structure.
1195 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1196 */
1197#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1198 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1199
1200/**
1201 * Checks if the page was marked being part of a large page
1202 * @returns true/false.
1203 * @param a_pPage Pointer to the physical guest page tracking structure.
1204 */
1205#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1206
1207/** Enabled optimized access handler tests.
1208 * These optimizations makes ASSUMPTIONS about the state values and the s1
1209 * layout. When enabled, the compiler should normally generate more compact
1210 * code.
1211 */
1212#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1213
1214/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1215 *
1216 * @remarks The values are assigned in order of priority, so we can calculate
1217 * the correct state for a page with different handlers installed.
1218 * @{ */
1219/** No handler installed. */
1220#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1221/** Monitoring is temporarily disabled. */
1222#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1223/** Write access is monitored. */
1224#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1225/** All access is monitored. */
1226#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1227/** @} */
1228
1229/**
1230 * Gets the physical access handler state of a page.
1231 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1232 * @param a_pPage Pointer to the physical guest page tracking structure.
1233 */
1234#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1235
1236/**
1237 * Sets the physical access handler state of a page.
1238 * @param a_pPage Pointer to the physical guest page tracking structure.
1239 * @param a_uState The new state value.
1240 */
1241#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1242 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1243
1244/**
1245 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1246 * @returns true/false
1247 * @param a_pPage Pointer to the physical guest page tracking structure.
1248 */
1249#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1250 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1251
1252/**
1253 * Checks if the page has any active physical access handlers.
1254 * @returns true/false
1255 * @param a_pPage Pointer to the physical guest page tracking structure.
1256 */
1257#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1258 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1259
1260
1261/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1262 *
1263 * @remarks The values are assigned in order of priority, so we can calculate
1264 * the correct state for a page with different handlers installed.
1265 * @{ */
1266/** No handler installed. */
1267#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1268/* 1 is reserved so the lineup is identical with the physical ones. */
1269/** Write access is monitored. */
1270#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1271/** All access is monitored. */
1272#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1273/** @} */
1274
1275/**
1276 * Gets the virtual access handler state of a page.
1277 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1278 * @param a_pPage Pointer to the physical guest page tracking structure.
1279 */
1280#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1281
1282/**
1283 * Sets the virtual access handler state of a page.
1284 * @param a_pPage Pointer to the physical guest page tracking structure.
1285 * @param a_uState The new state value.
1286 */
1287#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1288 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1289
1290/**
1291 * Checks if the page has any virtual access handlers.
1292 * @returns true/false
1293 * @param a_pPage Pointer to the physical guest page tracking structure.
1294 */
1295#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1296 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1297
1298/**
1299 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1300 * virtual handlers.
1301 * @returns true/false
1302 * @param a_pPage Pointer to the physical guest page tracking structure.
1303 */
1304#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1305 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1306
1307
1308/**
1309 * Checks if the page has any access handlers, including temporarily disabled ones.
1310 * @returns true/false
1311 * @param a_pPage Pointer to the physical guest page tracking structure.
1312 */
1313#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1314# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1315 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1316#else
1317# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1318 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1319 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1320#endif
1321
1322/**
1323 * Checks if the page has any active access handlers.
1324 * @returns true/false
1325 * @param a_pPage Pointer to the physical guest page tracking structure.
1326 */
1327#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1328# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1329 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1330#else
1331# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1332 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1333 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1334#endif
1335
1336/**
1337 * Checks if the page has any active access handlers catching all accesses.
1338 * @returns true/false
1339 * @param a_pPage Pointer to the physical guest page tracking structure.
1340 */
1341#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1342# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1343 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1344 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1345#else
1346# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1347 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1348 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1349#endif
1350
1351
1352/** @def PGM_PAGE_GET_TRACKING
1353 * Gets the packed shadow page pool tracking data associated with a guest page.
1354 * @returns uint16_t containing the data.
1355 * @param a_pPage Pointer to the physical guest page tracking structure.
1356 */
1357#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1358#if defined(__GNUC__) && defined(VBOX_STRICT)
1359# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1360#else
1361# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1362#endif
1363
1364/** @def PGM_PAGE_SET_TRACKING
1365 * Sets the packed shadow page pool tracking data associated with a guest page.
1366 * @param a_pVM The VM handle, only used for lock ownership assertions.
1367 * @param a_pPage Pointer to the physical guest page tracking structure.
1368 * @param a_u16TrackingData The tracking data to store.
1369 */
1370#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1371 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1372
1373/** @def PGM_PAGE_GET_TD_CREFS
1374 * Gets the @a cRefs tracking data member.
1375 * @returns cRefs.
1376 * @param a_pPage Pointer to the physical guest page tracking structure.
1377 */
1378#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1379 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1380#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1381 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1382
1383/** @def PGM_PAGE_GET_TD_IDX
1384 * Gets the @a idx tracking data member.
1385 * @returns idx.
1386 * @param a_pPage Pointer to the physical guest page tracking structure.
1387 */
1388#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1389 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1390#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1391 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1392
1393
1394/** Max number of locks on a page. */
1395#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1396
1397/** Get the read lock count.
1398 * @returns count.
1399 * @param a_pPage Pointer to the physical guest page tracking structure.
1400 */
1401#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1402
1403/** Get the write lock count.
1404 * @returns count.
1405 * @param a_pPage Pointer to the physical guest page tracking structure.
1406 */
1407#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1408
1409/** Decrement the read lock counter.
1410 * @param a_pPage Pointer to the physical guest page tracking structure.
1411 */
1412#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1413
1414/** Decrement the write lock counter.
1415 * @param a_pPage Pointer to the physical guest page tracking structure.
1416 */
1417#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1418
1419/** Increment the read lock counter.
1420 * @param a_pPage Pointer to the physical guest page tracking structure.
1421 */
1422#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1423
1424/** Increment the write lock counter.
1425 * @param a_pPage Pointer to the physical guest page tracking structure.
1426 */
1427#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1428
1429
1430/** Gets the NEM state.
1431 * @returns NEM state value (two bits).
1432 * @param a_pPage Pointer to the physical guest page tracking structure.
1433 */
1434#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1435
1436/** Sets the NEM state.
1437 * @param a_pPage Pointer to the physical guest page tracking structure.
1438 * @param a_u2State The NEM state value (specific to NEM impl.).
1439 */
1440#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1441 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1442
1443
1444#if 0
1445/** Enables sanity checking of write monitoring using CRC-32. */
1446# define PGMLIVESAVERAMPAGE_WITH_CRC32
1447#endif
1448
1449/**
1450 * Per page live save tracking data.
1451 */
1452typedef struct PGMLIVESAVERAMPAGE
1453{
1454 /** Number of times it has been dirtied. */
1455 uint32_t cDirtied : 24;
1456 /** Whether it is currently dirty. */
1457 uint32_t fDirty : 1;
1458 /** Ignore the page.
1459 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1460 * deal with these after pausing the VM and DevPCI have said it bit about
1461 * remappings. */
1462 uint32_t fIgnore : 1;
1463 /** Was a ZERO page last time around. */
1464 uint32_t fZero : 1;
1465 /** Was a SHARED page last time around. */
1466 uint32_t fShared : 1;
1467 /** Whether the page is/was write monitored in a previous pass. */
1468 uint32_t fWriteMonitored : 1;
1469 /** Whether the page is/was write monitored earlier in this pass. */
1470 uint32_t fWriteMonitoredJustNow : 1;
1471 /** Bits reserved for future use. */
1472 uint32_t u2Reserved : 2;
1473#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1474 /** CRC-32 for the page. This is for internal consistency checks. */
1475 uint32_t u32Crc;
1476#endif
1477} PGMLIVESAVERAMPAGE;
1478#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1479AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1480#else
1481AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1482#endif
1483/** Pointer to the per page live save tracking data. */
1484typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1485
1486/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1487#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1488
1489
1490/**
1491 * RAM range for GC Phys to HC Phys conversion.
1492 *
1493 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1494 * conversions too, but we'll let MM handle that for now.
1495 *
1496 * This structure is used by linked lists in both GC and HC.
1497 */
1498typedef struct PGMRAMRANGE
1499{
1500 /** Start of the range. Page aligned. */
1501 RTGCPHYS GCPhys;
1502 /** Size of the range. (Page aligned of course). */
1503 RTGCPHYS cb;
1504 /** Pointer to the next RAM range - for R3. */
1505 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1506 /** Pointer to the next RAM range - for R0. */
1507 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1508 /** Pointer to the next RAM range - for RC. */
1509 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1510 /** PGM_RAM_RANGE_FLAGS_* flags. */
1511 uint32_t fFlags;
1512 /** Last address in the range (inclusive). Page aligned (-1). */
1513 RTGCPHYS GCPhysLast;
1514 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1515 R3PTRTYPE(void *) pvR3;
1516 /** Live save per page tracking data. */
1517 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1518 /** The range description. */
1519 R3PTRTYPE(const char *) pszDesc;
1520 /** Pointer to self - R0 pointer. */
1521 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1522 /** Pointer to self - RC pointer. */
1523 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1524
1525 /** Alignment padding. */
1526 RTRCPTR Alignment0;
1527 /** Pointer to the left search three node - ring-3 context. */
1528 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1529 /** Pointer to the right search three node - ring-3 context. */
1530 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1531 /** Pointer to the left search three node - ring-0 context. */
1532 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1533 /** Pointer to the right search three node - ring-0 context. */
1534 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1535 /** Pointer to the left search three node - raw-mode context. */
1536 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1537 /** Pointer to the right search three node - raw-mode context. */
1538 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1539
1540 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1541#if HC_ARCH_BITS == 32
1542 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1543#endif
1544 /** Array of physical guest page tracking structures. */
1545 PGMPAGE aPages[1];
1546} PGMRAMRANGE;
1547/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1548typedef PGMRAMRANGE *PPGMRAMRANGE;
1549
1550/** @name PGMRAMRANGE::fFlags
1551 * @{ */
1552/** The RAM range is floating around as an independent guest mapping. */
1553#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1554/** Ad hoc RAM range for an ROM mapping. */
1555#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1556/** Ad hoc RAM range for an MMIO mapping. */
1557#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1558/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1559#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1560/** @} */
1561
1562/** Tests if a RAM range is an ad hoc one or not.
1563 * @returns true/false.
1564 * @param pRam The RAM range.
1565 */
1566#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1567 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1568
1569/** The number of entries in the RAM range TLBs (there is one for each
1570 * context). Must be a power of two. */
1571#define PGM_RAMRANGE_TLB_ENTRIES 8
1572
1573/**
1574 * Calculates the RAM range TLB index for the physical address.
1575 *
1576 * @returns RAM range TLB index.
1577 * @param a_GCPhys The guest physical address.
1578 */
1579#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1580
1581
1582
1583/**
1584 * Per page tracking structure for ROM image.
1585 *
1586 * A ROM image may have a shadow page, in which case we may have two pages
1587 * backing it. This structure contains the PGMPAGE for both while
1588 * PGMRAMRANGE have a copy of the active one. It is important that these
1589 * aren't out of sync in any regard other than page pool tracking data.
1590 */
1591typedef struct PGMROMPAGE
1592{
1593 /** The page structure for the virgin ROM page. */
1594 PGMPAGE Virgin;
1595 /** The page structure for the shadow RAM page. */
1596 PGMPAGE Shadow;
1597 /** The current protection setting. */
1598 PGMROMPROT enmProt;
1599 /** Live save status information. Makes use of unused alignment space. */
1600 struct
1601 {
1602 /** The previous protection value. */
1603 uint8_t u8Prot;
1604 /** Written to flag set by the handler. */
1605 bool fWrittenTo;
1606 /** Whether the shadow page is dirty or not. */
1607 bool fDirty;
1608 /** Whether it was dirtied in the recently. */
1609 bool fDirtiedRecently;
1610 } LiveSave;
1611} PGMROMPAGE;
1612AssertCompileSizeAlignment(PGMROMPAGE, 8);
1613/** Pointer to a ROM page tracking structure. */
1614typedef PGMROMPAGE *PPGMROMPAGE;
1615
1616
1617/**
1618 * A registered ROM image.
1619 *
1620 * This is needed to keep track of ROM image since they generally intrude
1621 * into a PGMRAMRANGE. It also keeps track of additional info like the
1622 * two page sets (read-only virgin and read-write shadow), the current
1623 * state of each page.
1624 *
1625 * Because access handlers cannot easily be executed in a different
1626 * context, the ROM ranges needs to be accessible and in all contexts.
1627 */
1628typedef struct PGMROMRANGE
1629{
1630 /** Pointer to the next range - R3. */
1631 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1632 /** Pointer to the next range - R0. */
1633 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1634 /** Pointer to the next range - RC. */
1635 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1636 /** Pointer alignment */
1637 RTRCPTR RCPtrAlignment;
1638 /** Address of the range. */
1639 RTGCPHYS GCPhys;
1640 /** Address of the last byte in the range. */
1641 RTGCPHYS GCPhysLast;
1642 /** Size of the range. */
1643 RTGCPHYS cb;
1644 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1645 uint32_t fFlags;
1646 /** The saved state range ID. */
1647 uint8_t idSavedState;
1648 /** Alignment padding. */
1649 uint8_t au8Alignment[3];
1650 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1651 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1652 /** The size bits pvOriginal points to. */
1653 uint32_t cbOriginal;
1654 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1655 * This is used for strictness checks. */
1656 R3PTRTYPE(const void *) pvOriginal;
1657 /** The ROM description. */
1658 R3PTRTYPE(const char *) pszDesc;
1659 /** The per page tracking structures. */
1660 PGMROMPAGE aPages[1];
1661} PGMROMRANGE;
1662/** Pointer to a ROM range. */
1663typedef PGMROMRANGE *PPGMROMRANGE;
1664
1665
1666/**
1667 * Live save per page data for an MMIO2 page.
1668 *
1669 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1670 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1671 * CRC-32 for detecting changes as well as special handling of zero pages. This
1672 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1673 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1674 * because of speed (2.5x and 6x slower).)
1675 *
1676 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1677 * save but normally is disabled. Since we can write monitor guest
1678 * accesses on our own, we only need this for host accesses. Shouldn't be
1679 * too difficult for DevVGA, VMMDev might be doable, the planned
1680 * networking fun will be fun since it involves ring-0.
1681 */
1682typedef struct PGMLIVESAVEMMIO2PAGE
1683{
1684 /** Set if the page is considered dirty. */
1685 bool fDirty;
1686 /** The number of scans this page has remained unchanged for.
1687 * Only updated for dirty pages. */
1688 uint8_t cUnchangedScans;
1689 /** Whether this page was zero at the last scan. */
1690 bool fZero;
1691 /** Alignment padding. */
1692 bool fReserved;
1693 /** CRC-32 for the first half of the page.
1694 * This is used together with u32CrcH2 to quickly detect changes in the page
1695 * during the non-final passes. */
1696 uint32_t u32CrcH1;
1697 /** CRC-32 for the second half of the page. */
1698 uint32_t u32CrcH2;
1699 /** SHA-1 for the saved page.
1700 * This is used in the final pass to skip pages without changes. */
1701 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1702} PGMLIVESAVEMMIO2PAGE;
1703/** Pointer to a live save status data for an MMIO2 page. */
1704typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1705
1706/**
1707 * A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1708 *
1709 * There are a few reason why we need to keep track of these registrations. One
1710 * of them is the deregistration & cleanup stuff, while another is that the
1711 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1712 * range list.
1713 *
1714 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1715 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1716 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1717 * overlap we will free all the existing RAM pages and put in the ram range
1718 * pages instead.
1719 */
1720typedef struct PGMREGMMIORANGE
1721{
1722 /** The owner of the range. (a device) */
1723 PPDMDEVINSR3 pDevInsR3;
1724 /** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1725 RTR3PTR pvR3;
1726 /** Pointer to the next range - R3. */
1727 R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1728 /** Flags (PGMREGMMIORANGE_F_XXX). */
1729 uint16_t fFlags;
1730 /** The sub device number (internal PCI config (CFGM) number). */
1731 uint8_t iSubDev;
1732 /** The PCI region number. */
1733 uint8_t iRegion;
1734 /** The saved state range ID. */
1735 uint8_t idSavedState;
1736 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1737 uint8_t idMmio2;
1738 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1739 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1740 /** The real size.
1741 * This may be larger than indicated by RamRange.cb if the range has been
1742 * reduced during saved state loading. */
1743 RTGCPHYS cbReal;
1744 /** Pointer to the physical handler for MMIO. */
1745 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1746 /** Live save per page tracking data for MMIO2. */
1747 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1748 /** The associated RAM range. */
1749 PGMRAMRANGE RamRange;
1750} PGMREGMMIORANGE;
1751AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1752/** Pointer to a MMIO2 or pre-registered MMIO range. */
1753typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1754
1755/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1756 * @{ */
1757/** Set if it's an MMIO2 range. */
1758#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1759/** Set if this is the first chunk in the MMIO2 range. */
1760#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1761/** Set if this is the last chunk in the MMIO2 range. */
1762#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1763/** Set if the whole range is mapped. */
1764#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1765/** Set if it's overlapping, clear if not. */
1766#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1767/** @} */
1768
1769
1770/** @name Internal MMIO2 constants.
1771 * @{ */
1772/** The maximum number of MMIO2 ranges. */
1773#define PGM_MMIO2_MAX_RANGES 8
1774/** The maximum number of pages in a MMIO2 range. */
1775#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1776/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1777#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1778/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1779#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1780/** Gets the MMIO2 page index from an MMIO2 page ID. */
1781#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1782/** @} */
1783
1784
1785
1786/**
1787 * PGMPhysRead/Write cache entry
1788 */
1789typedef struct PGMPHYSCACHEENTRY
1790{
1791 /** R3 pointer to physical page. */
1792 R3PTRTYPE(uint8_t *) pbR3;
1793 /** GC Physical address for cache entry */
1794 RTGCPHYS GCPhys;
1795#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1796 RTGCPHYS u32Padding0; /**< alignment padding. */
1797#endif
1798} PGMPHYSCACHEENTRY;
1799
1800/**
1801 * PGMPhysRead/Write cache to reduce REM memory access overhead
1802 */
1803typedef struct PGMPHYSCACHE
1804{
1805 /** Bitmap of valid cache entries */
1806 uint64_t aEntries;
1807 /** Cache entries */
1808 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1809} PGMPHYSCACHE;
1810
1811
1812/** Pointer to an allocation chunk ring-3 mapping. */
1813typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1814/** Pointer to an allocation chunk ring-3 mapping pointer. */
1815typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1816
1817/**
1818 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1819 *
1820 * The primary tree (Core) uses the chunk id as key.
1821 */
1822typedef struct PGMCHUNKR3MAP
1823{
1824 /** The key is the chunk id. */
1825 AVLU32NODECORE Core;
1826 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1827 * selection. */
1828 uint32_t iLastUsed;
1829 /** The current reference count. */
1830 uint32_t volatile cRefs;
1831 /** The current permanent reference count. */
1832 uint32_t volatile cPermRefs;
1833 /** The mapping address. */
1834 void *pv;
1835} PGMCHUNKR3MAP;
1836
1837/**
1838 * Allocation chunk ring-3 mapping TLB entry.
1839 */
1840typedef struct PGMCHUNKR3MAPTLBE
1841{
1842 /** The chunk id. */
1843 uint32_t volatile idChunk;
1844#if HC_ARCH_BITS == 64
1845 uint32_t u32Padding; /**< alignment padding. */
1846#endif
1847 /** The chunk map. */
1848#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1849 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1850#else
1851 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1852#endif
1853} PGMCHUNKR3MAPTLBE;
1854/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1855typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1856
1857/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1858 * @remark Must be a power of two value. */
1859#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1860
1861/**
1862 * Allocation chunk ring-3 mapping TLB.
1863 *
1864 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1865 * At first glance this might look kinda odd since AVL trees are
1866 * supposed to give the most optimal lookup times of all trees
1867 * due to their balancing. However, take a tree with 1023 nodes
1868 * in it, that's 10 levels, meaning that most searches has to go
1869 * down 9 levels before they find what they want. This isn't fast
1870 * compared to a TLB hit. There is the factor of cache misses,
1871 * and of course the problem with trees and branch prediction.
1872 * This is why we use TLBs in front of most of the trees.
1873 *
1874 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1875 * difficult when we switch to the new inlined AVL trees (from kStuff).
1876 */
1877typedef struct PGMCHUNKR3MAPTLB
1878{
1879 /** The TLB entries. */
1880 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1881} PGMCHUNKR3MAPTLB;
1882
1883/**
1884 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1885 * @returns Chunk TLB index.
1886 * @param idChunk The Chunk ID.
1887 */
1888#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1889
1890
1891/**
1892 * Ring-3 guest page mapping TLB entry.
1893 * @remarks used in ring-0 as well at the moment.
1894 */
1895typedef struct PGMPAGER3MAPTLBE
1896{
1897 /** Address of the page. */
1898 RTGCPHYS volatile GCPhys;
1899 /** The guest page. */
1900#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1901 R3PTRTYPE(PPGMPAGE) volatile pPage;
1902#else
1903 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1904#endif
1905 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1906#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1907 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1908#else
1909 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1910#endif
1911 /** The address */
1912#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1913 R3PTRTYPE(void *) volatile pv;
1914#else
1915 R3R0PTRTYPE(void *) volatile pv;
1916#endif
1917#if HC_ARCH_BITS == 32
1918 uint32_t u32Padding; /**< alignment padding. */
1919#endif
1920} PGMPAGER3MAPTLBE;
1921/** Pointer to an entry in the HC physical TLB. */
1922typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1923
1924
1925/** The number of entries in the ring-3 guest page mapping TLB.
1926 * @remarks The value must be a power of two. */
1927#define PGM_PAGER3MAPTLB_ENTRIES 256
1928
1929/**
1930 * Ring-3 guest page mapping TLB.
1931 * @remarks used in ring-0 as well at the moment.
1932 */
1933typedef struct PGMPAGER3MAPTLB
1934{
1935 /** The TLB entries. */
1936 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1937} PGMPAGER3MAPTLB;
1938/** Pointer to the ring-3 guest page mapping TLB. */
1939typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1940
1941/**
1942 * Calculates the index of the TLB entry for the specified guest page.
1943 * @returns Physical TLB index.
1944 * @param GCPhys The guest physical address.
1945 */
1946#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1947
1948
1949/**
1950 * Raw-mode context dynamic mapping cache entry.
1951 *
1952 * Because of raw-mode context being reloctable and all relocations are applied
1953 * in ring-3, this has to be defined here and be RC specific.
1954 *
1955 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1956 */
1957typedef struct PGMRCDYNMAPENTRY
1958{
1959 /** The physical address of the currently mapped page.
1960 * This is duplicate for three reasons: cache locality, cache policy of the PT
1961 * mappings and sanity checks. */
1962 RTHCPHYS HCPhys;
1963 /** Pointer to the page. */
1964 RTRCPTR pvPage;
1965 /** The number of references. */
1966 int32_t volatile cRefs;
1967 /** PTE pointer union. */
1968 struct PGMRCDYNMAPENTRY_PPTE
1969 {
1970 /** PTE pointer, 32-bit legacy version. */
1971 RCPTRTYPE(PX86PTE) pLegacy;
1972 /** PTE pointer, PAE version. */
1973 RCPTRTYPE(PX86PTEPAE) pPae;
1974 } uPte;
1975} PGMRCDYNMAPENTRY;
1976/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1977typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1978
1979
1980/**
1981 * Dynamic mapping cache for the raw-mode context.
1982 *
1983 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1984 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1985 * so that we can perform relocations from PGMR3Relocate. This has the
1986 * consequence that we must have separate ring-0 and raw-mode context versions
1987 * of this struct even if they share the basic elements.
1988 *
1989 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1990 */
1991typedef struct PGMRCDYNMAP
1992{
1993 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1994 uint32_t u32Magic;
1995 /** Array for tracking and managing the pages. */
1996 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1997 /** The cache size given as a number of pages. */
1998 uint32_t cPages;
1999 /** The current load.
2000 * This does not include guard pages. */
2001 uint32_t cLoad;
2002 /** The max load ever.
2003 * This is maintained to get trigger adding of more mapping space. */
2004 uint32_t cMaxLoad;
2005 /** The number of guard pages. */
2006 uint32_t cGuardPages;
2007 /** The number of users (protected by hInitLock). */
2008 uint32_t cUsers;
2009} PGMRCDYNMAP;
2010/** Pointer to the dynamic cache for the raw-mode context. */
2011typedef PGMRCDYNMAP *PPGMRCDYNMAP;
2012
2013
2014/**
2015 * Mapping cache usage set entry.
2016 *
2017 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
2018 * the dynamic ring-0 and (to some extent) raw-mode context mapping
2019 * cache. If it's extended to include ring-3, well, then something
2020 * will have be changed here...
2021 */
2022typedef struct PGMMAPSETENTRY
2023{
2024 /** Pointer to the page. */
2025#ifndef IN_RC
2026 RTR0PTR pvPage;
2027#else
2028 RTRCPTR pvPage;
2029# if HC_ARCH_BITS == 64
2030 uint32_t u32Alignment2;
2031# endif
2032#endif
2033 /** The mapping cache index. */
2034 uint16_t iPage;
2035 /** The number of references.
2036 * The max is UINT16_MAX - 1. */
2037 uint16_t cRefs;
2038 /** The number inlined references.
2039 * The max is UINT16_MAX - 1. */
2040 uint16_t cInlinedRefs;
2041 /** Unreferences. */
2042 uint16_t cUnrefs;
2043
2044#if HC_ARCH_BITS == 32
2045 uint32_t u32Alignment1;
2046#endif
2047 /** The physical address for this entry. */
2048 RTHCPHYS HCPhys;
2049} PGMMAPSETENTRY;
2050AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2051AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2052/** Pointer to a mapping cache usage set entry. */
2053typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2054
2055/**
2056 * Mapping cache usage set.
2057 *
2058 * This is used in ring-0 and the raw-mode context to track dynamic mappings
2059 * done during exits / traps. The set is
2060 */
2061typedef struct PGMMAPSET
2062{
2063 /** The number of occupied entries.
2064 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2065 * dynamic mappings. */
2066 uint32_t cEntries;
2067 /** The start of the current subset.
2068 * This is UINT32_MAX if no subset is currently open. */
2069 uint32_t iSubset;
2070 /** The index of the current CPU, only valid if the set is open. */
2071 int32_t iCpu;
2072 uint32_t alignment;
2073 /** The entries. */
2074 PGMMAPSETENTRY aEntries[64];
2075 /** HCPhys -> iEntry fast lookup table.
2076 * Use PGMMAPSET_HASH for hashing.
2077 * The entries may or may not be valid, check against cEntries. */
2078 uint8_t aiHashTable[128];
2079} PGMMAPSET;
2080AssertCompileSizeAlignment(PGMMAPSET, 8);
2081/** Pointer to the mapping cache set. */
2082typedef PGMMAPSET *PPGMMAPSET;
2083
2084/** PGMMAPSET::cEntries value for a closed set. */
2085#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2086
2087/** Hash function for aiHashTable. */
2088#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2089
2090
2091/** @name Context neutral page mapper TLB.
2092 *
2093 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2094 * code is writting in a kind of context neutral way. Time will show whether
2095 * this actually makes sense or not...
2096 *
2097 * @todo this needs to be reconsidered and dropped/redone since the ring-0
2098 * context ends up using a global mapping cache on some platforms
2099 * (darwin).
2100 *
2101 * @{ */
2102/** @typedef PPGMPAGEMAPTLB
2103 * The page mapper TLB pointer type for the current context. */
2104/** @typedef PPGMPAGEMAPTLB
2105 * The page mapper TLB entry pointer type for the current context. */
2106/** @typedef PPGMPAGEMAPTLB
2107 * The page mapper TLB entry pointer pointer type for the current context. */
2108/** @def PGM_PAGEMAPTLB_ENTRIES
2109 * The number of TLB entries in the page mapper TLB for the current context. */
2110/** @def PGM_PAGEMAPTLB_IDX
2111 * Calculate the TLB index for a guest physical address.
2112 * @returns The TLB index.
2113 * @param GCPhys The guest physical address. */
2114/** @typedef PPGMPAGEMAP
2115 * Pointer to a page mapper unit for current context. */
2116/** @typedef PPPGMPAGEMAP
2117 * Pointer to a page mapper unit pointer for current context. */
2118#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2119// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2120// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2121// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2122# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2123# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2124 typedef void * PPGMPAGEMAP;
2125 typedef void ** PPPGMPAGEMAP;
2126//#elif IN_RING0
2127// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2128// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2129// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2130//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2131//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2132// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2133// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2134#else
2135 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2136 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2137 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2138# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2139# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2140 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2141 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2142#endif
2143/** @} */
2144
2145
2146/** @name PGM Pool Indexes.
2147 * Aka. the unique shadow page identifier.
2148 * @{ */
2149/** NIL page pool IDX. */
2150#define NIL_PGMPOOL_IDX 0
2151/** The first normal index. There used to be 5 fictive pages up front, now
2152 * there is only the NIL page. */
2153#define PGMPOOL_IDX_FIRST 1
2154/** The last valid index. (inclusive, 14 bits) */
2155#define PGMPOOL_IDX_LAST 0x3fff
2156/** @} */
2157
2158/** The NIL index for the parent chain. */
2159#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2160#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2161
2162/**
2163 * Node in the chain linking a shadowed page to it's parent (user).
2164 */
2165#pragma pack(1)
2166typedef struct PGMPOOLUSER
2167{
2168 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2169 uint16_t iNext;
2170 /** The user page index. */
2171 uint16_t iUser;
2172 /** Index into the user table. */
2173 uint32_t iUserTable;
2174} PGMPOOLUSER, *PPGMPOOLUSER;
2175typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2176#pragma pack()
2177
2178
2179/** The NIL index for the phys ext chain. */
2180#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2181/** The NIL pte index for a phys ext chain slot. */
2182#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2183
2184/**
2185 * Node in the chain of physical cross reference extents.
2186 * @todo Calling this an 'extent' is not quite right, find a better name.
2187 * @todo find out the optimal size of the aidx array
2188 */
2189#pragma pack(1)
2190typedef struct PGMPOOLPHYSEXT
2191{
2192 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2193 uint16_t iNext;
2194 /** Alignment. */
2195 uint16_t u16Align;
2196 /** The user page index. */
2197 uint16_t aidx[3];
2198 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2199 uint16_t apte[3];
2200} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2201typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2202#pragma pack()
2203
2204
2205/**
2206 * The kind of page that's being shadowed.
2207 */
2208typedef enum PGMPOOLKIND
2209{
2210 /** The virtual invalid 0 entry. */
2211 PGMPOOLKIND_INVALID = 0,
2212 /** The entry is free (=unused). */
2213 PGMPOOLKIND_FREE,
2214
2215 /** Shw: 32-bit page table; Gst: no paging. */
2216 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2217 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2218 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2219 /** Shw: 32-bit page table; Gst: 4MB page. */
2220 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2221 /** Shw: PAE page table; Gst: no paging. */
2222 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2223 /** Shw: PAE page table; Gst: 32-bit page table. */
2224 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2225 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2226 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2227 /** Shw: PAE page table; Gst: PAE page table. */
2228 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2229 /** Shw: PAE page table; Gst: 2MB page. */
2230 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2231
2232 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2233 PGMPOOLKIND_32BIT_PD,
2234 /** Shw: 32-bit page directory. Gst: no paging. */
2235 PGMPOOLKIND_32BIT_PD_PHYS,
2236 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2237 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2238 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2239 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2240 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2241 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2242 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2243 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2244 /** Shw: PAE page directory; Gst: PAE page directory. */
2245 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2246 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2247 PGMPOOLKIND_PAE_PD_PHYS,
2248
2249 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2250 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2251 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2252 PGMPOOLKIND_PAE_PDPT,
2253 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2254 PGMPOOLKIND_PAE_PDPT_PHYS,
2255
2256 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2257 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2258 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2259 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2260 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2261 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2262 /** Shw: 64-bit page directory table; Gst: no paging. */
2263 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2264
2265 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2266 PGMPOOLKIND_64BIT_PML4,
2267
2268 /** Shw: EPT page directory pointer table; Gst: no paging. */
2269 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2270 /** Shw: EPT page directory table; Gst: no paging. */
2271 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2272 /** Shw: EPT page table; Gst: no paging. */
2273 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2274
2275 /** Shw: Root Nested paging table. */
2276 PGMPOOLKIND_ROOT_NESTED,
2277
2278 /** The last valid entry. */
2279 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2280} PGMPOOLKIND;
2281
2282/**
2283 * The access attributes of the page; only applies to big pages.
2284 */
2285typedef enum
2286{
2287 PGMPOOLACCESS_DONTCARE = 0,
2288 PGMPOOLACCESS_USER_RW,
2289 PGMPOOLACCESS_USER_R,
2290 PGMPOOLACCESS_USER_RW_NX,
2291 PGMPOOLACCESS_USER_R_NX,
2292 PGMPOOLACCESS_SUPERVISOR_RW,
2293 PGMPOOLACCESS_SUPERVISOR_R,
2294 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2295 PGMPOOLACCESS_SUPERVISOR_R_NX
2296} PGMPOOLACCESS;
2297
2298/**
2299 * The tracking data for a page in the pool.
2300 */
2301typedef struct PGMPOOLPAGE
2302{
2303 /** AVL node code with the (HC) physical address of this page. */
2304 AVLOHCPHYSNODECORE Core;
2305 /** Pointer to the R3 mapping of the page. */
2306#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2307 R3PTRTYPE(void *) pvPageR3;
2308#else
2309 R3R0PTRTYPE(void *) pvPageR3;
2310#endif
2311#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2312 uint32_t Alignment0;
2313#endif
2314 /** The guest physical address. */
2315 RTGCPHYS GCPhys;
2316 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2317 uint8_t enmKind;
2318 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2319 uint8_t enmAccess;
2320 /** This supplements enmKind and enmAccess */
2321 bool fA20Enabled : 1;
2322
2323 /** Used to indicate that the page is zeroed. */
2324 bool fZeroed : 1;
2325 /** Used to indicate that a PT has non-global entries. */
2326 bool fSeenNonGlobal : 1;
2327 /** Used to indicate that we're monitoring writes to the guest page. */
2328 bool fMonitored : 1;
2329 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2330 * (All pages are in the age list.) */
2331 bool fCached : 1;
2332 /** This is used by the R3 access handlers when invoked by an async thread.
2333 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2334 bool volatile fReusedFlushPending : 1;
2335 /** Used to mark the page as dirty (write monitoring is temporarily
2336 * off). */
2337 bool fDirty : 1;
2338 bool fPadding1 : 1;
2339 bool fPadding2;
2340
2341 /** The index of this page. */
2342 uint16_t idx;
2343 /** The next entry in the list this page currently resides in.
2344 * It's either in the free list or in the GCPhys hash. */
2345 uint16_t iNext;
2346 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2347 uint16_t iUserHead;
2348 /** The number of present entries. */
2349 uint16_t cPresent;
2350 /** The first entry in the table which is present. */
2351 uint16_t iFirstPresent;
2352 /** The number of modifications to the monitored page. */
2353 uint16_t cModifications;
2354 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2355 uint16_t iModifiedNext;
2356 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2357 uint16_t iModifiedPrev;
2358 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2359 uint16_t iMonitoredNext;
2360 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2361 uint16_t iMonitoredPrev;
2362 /** The next page in the age list. */
2363 uint16_t iAgeNext;
2364 /** The previous page in the age list. */
2365 uint16_t iAgePrev;
2366 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2367 uint8_t idxDirtyEntry;
2368
2369 /** @name Access handler statistics to determine whether the guest is
2370 * (re)initializing a page table.
2371 * @{ */
2372 RTGCPTR GCPtrLastAccessHandlerRip;
2373 RTGCPTR GCPtrLastAccessHandlerFault;
2374 uint64_t cLastAccessHandler;
2375 /** @} */
2376 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2377 uint32_t volatile cLocked;
2378#if GC_ARCH_BITS == 64
2379 uint32_t u32Alignment3;
2380#endif
2381# ifdef VBOX_STRICT
2382 RTGCPTR GCPtrDirtyFault;
2383# endif
2384} PGMPOOLPAGE;
2385/** Pointer to a pool page. */
2386typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2387/** Pointer to a const pool page. */
2388typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2389/** Pointer to a pool page pointer. */
2390typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2391
2392
2393/** The hash table size. */
2394# define PGMPOOL_HASH_SIZE 0x40
2395/** The hash function. */
2396# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2397
2398
2399/**
2400 * The shadow page pool instance data.
2401 *
2402 * It's all one big allocation made at init time, except for the
2403 * pages that is. The user nodes follows immediately after the
2404 * page structures.
2405 */
2406typedef struct PGMPOOL
2407{
2408 /** The VM handle - R3 Ptr. */
2409 PVMR3 pVMR3;
2410 /** The VM handle - R0 Ptr. */
2411 PVMR0 pVMR0;
2412 /** The VM handle - RC Ptr. */
2413 PVMRC pVMRC;
2414 /** The max pool size. This includes the special IDs. */
2415 uint16_t cMaxPages;
2416 /** The current pool size. */
2417 uint16_t cCurPages;
2418 /** The head of the free page list. */
2419 uint16_t iFreeHead;
2420 /* Padding. */
2421 uint16_t u16Padding;
2422 /** Head of the chain of free user nodes. */
2423 uint16_t iUserFreeHead;
2424 /** The number of user nodes we've allocated. */
2425 uint16_t cMaxUsers;
2426 /** The number of present page table entries in the entire pool. */
2427 uint32_t cPresent;
2428 /** Pointer to the array of user nodes - RC pointer. */
2429 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2430 /** Pointer to the array of user nodes - R3 pointer. */
2431 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2432 /** Pointer to the array of user nodes - R0 pointer. */
2433 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2434 /** Head of the chain of free phys ext nodes. */
2435 uint16_t iPhysExtFreeHead;
2436 /** The number of user nodes we've allocated. */
2437 uint16_t cMaxPhysExts;
2438 /** Pointer to the array of physical xref extent - RC pointer. */
2439 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2440 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2441 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2442 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2443 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2444 /** Hash table for GCPhys addresses. */
2445 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2446 /** The head of the age list. */
2447 uint16_t iAgeHead;
2448 /** The tail of the age list. */
2449 uint16_t iAgeTail;
2450 /** Set if the cache is enabled. */
2451 bool fCacheEnabled;
2452 /** Alignment padding. */
2453 bool afPadding1[3];
2454 /** Head of the list of modified pages. */
2455 uint16_t iModifiedHead;
2456 /** The current number of modified pages. */
2457 uint16_t cModifiedPages;
2458 /** Physical access handler type registration handle. */
2459 PGMPHYSHANDLERTYPE hAccessHandlerType;
2460 /** Next available slot (in aDirtyPages). */
2461 uint32_t idxFreeDirtyPage;
2462 /** Number of active dirty pages. */
2463 uint32_t cDirtyPages;
2464 /** Array of current dirty pgm pool page indices. */
2465 uint16_t aidxDirtyPages[16];
2466 /** Array running in parallel to aidxDirtyPages with the page data. */
2467 struct
2468 {
2469 uint64_t aPage[512];
2470 } aDirtyPages[16];
2471
2472 /** The number of pages currently in use. */
2473 uint16_t cUsedPages;
2474#ifdef VBOX_WITH_STATISTICS
2475 /** The high water mark for cUsedPages. */
2476 uint16_t cUsedPagesHigh;
2477 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2478 /** Profiling pgmPoolAlloc(). */
2479 STAMPROFILEADV StatAlloc;
2480 /** Profiling pgmR3PoolClearDoIt(). */
2481 STAMPROFILE StatClearAll;
2482 /** Profiling pgmR3PoolReset(). */
2483 STAMPROFILE StatR3Reset;
2484 /** Profiling pgmPoolFlushPage(). */
2485 STAMPROFILE StatFlushPage;
2486 /** Profiling pgmPoolFree(). */
2487 STAMPROFILE StatFree;
2488 /** Counting explicit flushes by PGMPoolFlushPage(). */
2489 STAMCOUNTER StatForceFlushPage;
2490 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2491 STAMCOUNTER StatForceFlushDirtyPage;
2492 /** Counting flushes for reused pages. */
2493 STAMCOUNTER StatForceFlushReused;
2494 /** Profiling time spent zeroing pages. */
2495 STAMPROFILE StatZeroPage;
2496 /** Profiling of pgmPoolTrackDeref. */
2497 STAMPROFILE StatTrackDeref;
2498 /** Profiling pgmTrackFlushGCPhysPT. */
2499 STAMPROFILE StatTrackFlushGCPhysPT;
2500 /** Profiling pgmTrackFlushGCPhysPTs. */
2501 STAMPROFILE StatTrackFlushGCPhysPTs;
2502 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2503 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2504 /** Number of times we've been out of user records. */
2505 STAMCOUNTER StatTrackFreeUpOneUser;
2506 /** Nr of flushed entries. */
2507 STAMCOUNTER StatTrackFlushEntry;
2508 /** Nr of updated entries. */
2509 STAMCOUNTER StatTrackFlushEntryKeep;
2510 /** Profiling deref activity related tracking GC physical pages. */
2511 STAMPROFILE StatTrackDerefGCPhys;
2512 /** Number of linear searches for a HCPhys in the ram ranges. */
2513 STAMCOUNTER StatTrackLinearRamSearches;
2514 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2515 STAMCOUNTER StamTrackPhysExtAllocFailures;
2516
2517 /** Profiling the RC/R0 \#PF access handler. */
2518 STAMPROFILE StatMonitorPfRZ;
2519 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2520 STAMPROFILE StatMonitorPfRZHandled;
2521 /** Times we've failed interpreting the instruction. */
2522 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2523 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2524 STAMPROFILE StatMonitorPfRZFlushPage;
2525 /* Times we've detected a page table reinit. */
2526 STAMCOUNTER StatMonitorPfRZFlushReinit;
2527 /** Counting flushes for pages that are modified too often. */
2528 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2529 /** Times we've detected fork(). */
2530 STAMCOUNTER StatMonitorPfRZFork;
2531 /** Times we've failed interpreting a patch code instruction. */
2532 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2533 /** Times we've failed interpreting a patch code instruction during flushing. */
2534 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2535 /** The number of times we've seen rep prefixes we can't handle. */
2536 STAMCOUNTER StatMonitorPfRZRepPrefix;
2537 /** Profiling the REP STOSD cases we've handled. */
2538 STAMPROFILE StatMonitorPfRZRepStosd;
2539
2540 /** Profiling the R0/RC regular access handler. */
2541 STAMPROFILE StatMonitorRZ;
2542 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2543 STAMPROFILE StatMonitorRZFlushPage;
2544 /** Per access size counts indexed by size minus 1, last for larger. */
2545 STAMCOUNTER aStatMonitorRZSizes[16+3];
2546 /** Missaligned access counts indexed by offset - 1. */
2547 STAMCOUNTER aStatMonitorRZMisaligned[7];
2548
2549 /** Nr of handled PT faults. */
2550 STAMCOUNTER StatMonitorRZFaultPT;
2551 /** Nr of handled PD faults. */
2552 STAMCOUNTER StatMonitorRZFaultPD;
2553 /** Nr of handled PDPT faults. */
2554 STAMCOUNTER StatMonitorRZFaultPDPT;
2555 /** Nr of handled PML4 faults. */
2556 STAMCOUNTER StatMonitorRZFaultPML4;
2557
2558 /** Profiling the R3 access handler. */
2559 STAMPROFILE StatMonitorR3;
2560 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2561 STAMPROFILE StatMonitorR3FlushPage;
2562 /** Per access size counts indexed by size minus 1, last for larger. */
2563 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2564 /** Missaligned access counts indexed by offset - 1. */
2565 STAMCOUNTER aStatMonitorR3Misaligned[7];
2566 /** Nr of handled PT faults. */
2567 STAMCOUNTER StatMonitorR3FaultPT;
2568 /** Nr of handled PD faults. */
2569 STAMCOUNTER StatMonitorR3FaultPD;
2570 /** Nr of handled PDPT faults. */
2571 STAMCOUNTER StatMonitorR3FaultPDPT;
2572 /** Nr of handled PML4 faults. */
2573 STAMCOUNTER StatMonitorR3FaultPML4;
2574
2575 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2576 STAMCOUNTER StatResetDirtyPages;
2577 /** Times we've called pgmPoolAddDirtyPage. */
2578 STAMCOUNTER StatDirtyPage;
2579 /** Times we've had to flush duplicates for dirty page management. */
2580 STAMCOUNTER StatDirtyPageDupFlush;
2581 /** Times we've had to flush because of overflow. */
2582 STAMCOUNTER StatDirtyPageOverFlowFlush;
2583
2584 /** The high water mark for cModifiedPages. */
2585 uint16_t cModifiedPagesHigh;
2586 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2587
2588 /** The number of cache hits. */
2589 STAMCOUNTER StatCacheHits;
2590 /** The number of cache misses. */
2591 STAMCOUNTER StatCacheMisses;
2592 /** The number of times we've got a conflict of 'kind' in the cache. */
2593 STAMCOUNTER StatCacheKindMismatches;
2594 /** Number of times we've been out of pages. */
2595 STAMCOUNTER StatCacheFreeUpOne;
2596 /** The number of cacheable allocations. */
2597 STAMCOUNTER StatCacheCacheable;
2598 /** The number of uncacheable allocations. */
2599 STAMCOUNTER StatCacheUncacheable;
2600#else
2601 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2602#endif
2603 /** The AVL tree for looking up a page by its HC physical address. */
2604 AVLOHCPHYSTREE HCPhysTree;
2605 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2606 /** Array of pages. (cMaxPages in length)
2607 * The Id is the index into thist array.
2608 */
2609 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2610} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2611AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2612AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2613AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2614#ifdef VBOX_WITH_STATISTICS
2615AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2616#endif
2617AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2618
2619
2620/** @def PGMPOOL_PAGE_2_PTR
2621 * Maps a pool page pool into the current context.
2622 *
2623 * @returns VBox status code.
2624 * @param a_pVM Pointer to the VM.
2625 * @param a_pPage The pool page.
2626 *
2627 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2628 * small page window employeed by that function. Be careful.
2629 * @remark There is no need to assert on the result.
2630 */
2631#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2632# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2633#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2634# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2635DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2636{
2637 AssertPtr(a_pPage);
2638 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2639 return a_pPage->pvPageR3;
2640}
2641#else
2642# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2643#endif
2644
2645
2646/** @def PGMPOOL_PAGE_2_PTR_V2
2647 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2648 *
2649 * @returns VBox status code.
2650 * @param a_pVM Pointer to the VM.
2651 * @param a_pVCpu The current CPU.
2652 * @param a_pPage The pool page.
2653 *
2654 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2655 * small page window employeed by that function. Be careful.
2656 * @remark There is no need to assert on the result.
2657 */
2658#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2659# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2660#else
2661# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2662#endif
2663
2664
2665/** @name Per guest page tracking data.
2666 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2667 * is to use more bits for it and split it up later on. But for now we'll play
2668 * safe and change as little as possible.
2669 *
2670 * The 16-bit word has two parts:
2671 *
2672 * The first 14-bit forms the @a idx field. It is either the index of a page in
2673 * the shadow page pool, or and index into the extent list.
2674 *
2675 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2676 * shadow page pool references to the page. If cRefs equals
2677 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2678 * (misnomer) table and not the shadow page pool.
2679 *
2680 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2681 * the 16-bit word.
2682 *
2683 * @{ */
2684/** The shift count for getting to the cRefs part. */
2685#define PGMPOOL_TD_CREFS_SHIFT 14
2686/** The mask applied after shifting the tracking data down by
2687 * PGMPOOL_TD_CREFS_SHIFT. */
2688#define PGMPOOL_TD_CREFS_MASK 0x3
2689/** The cRefs value used to indicate that the idx is the head of a
2690 * physical cross reference list. */
2691#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2692/** The shift used to get idx. */
2693#define PGMPOOL_TD_IDX_SHIFT 0
2694/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2695#define PGMPOOL_TD_IDX_MASK 0x3fff
2696/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2697 * simply too many mappings of this page. */
2698#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2699
2700/** @def PGMPOOL_TD_MAKE
2701 * Makes a 16-bit tracking data word.
2702 *
2703 * @returns tracking data.
2704 * @param cRefs The @a cRefs field. Must be within bounds!
2705 * @param idx The @a idx field. Must also be within bounds! */
2706#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2707
2708/** @def PGMPOOL_TD_GET_CREFS
2709 * Get the @a cRefs field from a tracking data word.
2710 *
2711 * @returns The @a cRefs field
2712 * @param u16 The tracking data word.
2713 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2714 * non-zero @a u16. */
2715#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2716
2717/** @def PGMPOOL_TD_GET_IDX
2718 * Get the @a idx field from a tracking data word.
2719 *
2720 * @returns The @a idx field
2721 * @param u16 The tracking data word. */
2722#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2723/** @} */
2724
2725
2726
2727/** @name A20 gate macros
2728 * @{ */
2729#define PGM_WITH_A20
2730#ifdef PGM_WITH_A20
2731# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2732# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2733# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2734 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2735# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2736#else
2737# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2738# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2739# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2740# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2741#endif
2742/** @} */
2743
2744
2745/**
2746 * Roots and anchors for trees and list employing self relative offsets as
2747 * pointers.
2748 *
2749 * When using self-relative offsets instead of pointers, the offsets needs to be
2750 * the same in all offsets. Thus the roots and anchors needs to live on the
2751 * hyper heap just like the nodes.
2752 */
2753typedef struct PGMTREES
2754{
2755 /** List of physical access handler types (offset pointers) of type
2756 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2757 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2758 /** Physical access handlers (AVL range+offsetptr tree). */
2759 AVLROGCPHYSTREE PhysHandlers;
2760#ifdef VBOX_WITH_RAW_MODE
2761 /** Virtual access handlers (AVL range + GC ptr tree). */
2762 AVLROGCPTRTREE VirtHandlers;
2763 /** Virtual access handlers (Phys range AVL range + offsetptr tree).
2764 * @remarks Handler of the hypervisor kind are of course not present. */
2765 AVLROGCPHYSTREE PhysToVirtHandlers;
2766 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2767 AVLROGCPTRTREE HyperVirtHandlers;
2768 /** List of virtual access handler types (offset pointers) of type
2769 * PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2770 RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2771#endif
2772} PGMTREES;
2773/** Pointer to PGM trees. */
2774typedef PGMTREES *PPGMTREES;
2775
2776
2777/**
2778 * Page fault guest state for the AMD64 paging mode.
2779 */
2780typedef struct PGMPTWALKCORE
2781{
2782 /** The guest virtual address that is being resolved by the walk
2783 * (input). */
2784 RTGCPTR GCPtr;
2785
2786 /** The guest physical address that is the result of the walk.
2787 * @remarks only valid if fSucceeded is set. */
2788 RTGCPHYS GCPhys;
2789
2790 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2791 bool fSucceeded;
2792 /** The level problem arrised at.
2793 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2794 * level 8. This is 0 on success. */
2795 uint8_t uLevel;
2796 /** Set if the page isn't present. */
2797 bool fNotPresent;
2798 /** Encountered a bad physical address. */
2799 bool fBadPhysAddr;
2800 /** Set if there was reserved bit violations. */
2801 bool fRsvdError;
2802 /** Set if it involves a big page (2/4 MB). */
2803 bool fBigPage;
2804 /** Set if it involves a gigantic page (1 GB). */
2805 bool fGigantPage;
2806 /** The effective X86_PTE_US flag for the address. */
2807 bool fEffectiveUS;
2808 /** The effective X86_PTE_RW flag for the address. */
2809 bool fEffectiveRW;
2810 /** The effective X86_PTE_NX flag for the address. */
2811 bool fEffectiveNX;
2812 bool afPadding1[2];
2813 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2814 * The NX bit is inverted and shifted down 63 places to bit 0. */
2815 uint32_t fEffective;
2816} PGMPTWALKCORE;
2817
2818/** @name PGMPTWALKCORE::fEffective bits.
2819 * @{ */
2820/** Effective execute bit (!NX). */
2821#define PGMPTWALK_EFF_X UINT32_C(1)
2822/** Effective write access bit. */
2823#define PGMPTWALK_EFF_RW X86_PTE_RW
2824/** Effective user-mode access bit. */
2825#define PGMPTWALK_EFF_US X86_PTE_US
2826/** Effective write through cache bit. */
2827#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2828/** Effective cache disabled bit. */
2829#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2830/** Effective accessed bit. */
2831#define PGMPTWALK_EFF_A X86_PTE_A
2832/** The dirty bit of the final entry. */
2833#define PGMPTWALK_EFF_D X86_PTE_D
2834/** The PAT bit of the final entry. */
2835#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2836/** The global bit of the final entry. */
2837#define PGMPTWALK_EFF_G X86_PTE_G
2838/** @} */
2839
2840
2841/**
2842 * Guest page table walk for the AMD64 mode.
2843 */
2844typedef struct PGMPTWALKGSTAMD64
2845{
2846 /** The common core. */
2847 PGMPTWALKCORE Core;
2848
2849 PX86PML4 pPml4;
2850 PX86PML4E pPml4e;
2851 X86PML4E Pml4e;
2852
2853 PX86PDPT pPdpt;
2854 PX86PDPE pPdpe;
2855 X86PDPE Pdpe;
2856
2857 PX86PDPAE pPd;
2858 PX86PDEPAE pPde;
2859 X86PDEPAE Pde;
2860
2861 PX86PTPAE pPt;
2862 PX86PTEPAE pPte;
2863 X86PTEPAE Pte;
2864} PGMPTWALKGSTAMD64;
2865/** Pointer to a AMD64 guest page table walk. */
2866typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2867/** Pointer to a const AMD64 guest page table walk. */
2868typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2869
2870/**
2871 * Guest page table walk for the PAE mode.
2872 */
2873typedef struct PGMPTWALKGSTPAE
2874{
2875 /** The common core. */
2876 PGMPTWALKCORE Core;
2877
2878 PX86PDPT pPdpt;
2879 PX86PDPE pPdpe;
2880 X86PDPE Pdpe;
2881
2882 PX86PDPAE pPd;
2883 PX86PDEPAE pPde;
2884 X86PDEPAE Pde;
2885
2886 PX86PTPAE pPt;
2887 PX86PTEPAE pPte;
2888 X86PTEPAE Pte;
2889} PGMPTWALKGSTPAE;
2890/** Pointer to a PAE guest page table walk. */
2891typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2892/** Pointer to a const AMD64 guest page table walk. */
2893typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2894
2895/**
2896 * Guest page table walk for the 32-bit mode.
2897 */
2898typedef struct PGMPTWALKGST32BIT
2899{
2900 /** The common core. */
2901 PGMPTWALKCORE Core;
2902
2903 PX86PD pPd;
2904 PX86PDE pPde;
2905 X86PDE Pde;
2906
2907 PX86PT pPt;
2908 PX86PTE pPte;
2909 X86PTE Pte;
2910} PGMPTWALKGST32BIT;
2911/** Pointer to a 32-bit guest page table walk. */
2912typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2913/** Pointer to a const 32-bit guest page table walk. */
2914typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2915
2916/**
2917 * Which part of PGMPTWALKGST that is valid.
2918 */
2919typedef enum PGMPTWALKGSTTYPE
2920{
2921 /** Customary invalid 0 value. */
2922 PGMPTWALKGSTTYPE_INVALID = 0,
2923 /** PGMPTWALKGST::u.Amd64 is valid. */
2924 PGMPTWALKGSTTYPE_AMD64,
2925 /** PGMPTWALKGST::u.Pae is valid. */
2926 PGMPTWALKGSTTYPE_PAE,
2927 /** PGMPTWALKGST::u.Legacy is valid. */
2928 PGMPTWALKGSTTYPE_32BIT,
2929 /** Customary 32-bit type hack. */
2930 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2931} PGMPTWALKGSTTYPE;
2932
2933/**
2934 * Combined guest page table walk result.
2935 */
2936typedef struct PGMPTWALKGST
2937{
2938 union
2939 {
2940 /** The page walker core - always valid. */
2941 PGMPTWALKCORE Core;
2942 /** The page walker for AMD64. */
2943 PGMPTWALKGSTAMD64 Amd64;
2944 /** The page walker for PAE (32-bit). */
2945 PGMPTWALKGSTPAE Pae;
2946 /** The page walker for 32-bit paging (called legacy due to C naming
2947 * convension). */
2948 PGMPTWALKGST32BIT Legacy;
2949 } u;
2950 /** Indicates which part of the union is valid. */
2951 PGMPTWALKGSTTYPE enmType;
2952} PGMPTWALKGST;
2953/** Pointer to a combined guest page table walk result. */
2954typedef PGMPTWALKGST *PPGMPTWALKGST;
2955/** Pointer to a read-only combined guest page table walk result. */
2956typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2957
2958
2959/** @name Paging mode macros
2960 * @{
2961 */
2962#ifdef IN_RC
2963# define PGM_CTX(a,b) a##RC##b
2964# define PGM_CTX_STR(a,b) a "GC" b
2965# define PGM_CTX_DECL(type) VMMRCDECL(type)
2966#else
2967# ifdef IN_RING3
2968# define PGM_CTX(a,b) a##R3##b
2969# define PGM_CTX_STR(a,b) a "R3" b
2970# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2971# else
2972# define PGM_CTX(a,b) a##R0##b
2973# define PGM_CTX_STR(a,b) a "R0" b
2974# define PGM_CTX_DECL(type) VMMDECL(type)
2975# endif
2976#endif
2977
2978#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2979#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2980#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2981#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2982#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2983#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2984#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2985#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2986#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2987#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2988#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2989#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2990#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2991#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2992#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2993#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2994
2995#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2996#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2997#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2998#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2999#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
3000#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
3001#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
3002#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
3003#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
3004#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
3005#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
3006#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
3007#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
3008#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
3009#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
3010#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
3011#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
3012#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
3013#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
3014#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
3015#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
3016#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
3017#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
3018#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
3019#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
3020
3021/* Shw_Gst */
3022#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
3023#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
3024#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
3025#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
3026#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
3027#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
3028#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
3029#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
3030#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
3031#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
3032#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
3033#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
3034#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
3035#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
3036#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
3037#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
3038#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
3039#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
3040#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
3041#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
3042#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
3043#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
3044#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
3045#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
3046#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
3047#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
3048#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
3049#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
3050#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
3051#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
3052#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
3053#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
3054#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
3055#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
3056
3057#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
3058#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
3059#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
3060#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
3061#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
3062#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
3063#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
3064#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
3065#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
3066#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
3067#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
3068#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
3069#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
3070#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
3071#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
3072#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
3073#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
3074#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
3075#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
3076#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
3077#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
3078#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
3079#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
3080#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
3081#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
3082#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
3083#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
3084#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
3085
3086#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
3087#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
3088#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
3089#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
3090#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
3091#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
3092#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
3093#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
3094#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
3095#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
3096#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
3097#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
3098#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
3099#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
3100#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
3101#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
3102#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
3103#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
3104#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
3105#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
3106#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
3107#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
3108#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
3109#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
3110#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3111#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3112#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3113#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3114#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3115
3116#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3117/** @} */
3118
3119
3120/**
3121 * Function pointers for guest paging.
3122 */
3123typedef struct PGMMODEDATAGST
3124{
3125 /** The guest mode type. */
3126 uint32_t uType;
3127 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
3128 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
3129 DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
3130 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3131 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3132#ifdef IN_RING3
3133 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3134#endif
3135} PGMMODEDATAGST;
3136
3137/** The length of g_aPgmGuestModeData. */
3138#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
3139# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
3140#else
3141# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3142#endif
3143/** The guest mode data array. */
3144extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
3145
3146
3147/**
3148 * Function pointers for shadow paging.
3149 */
3150typedef struct PGMMODEDATASHW
3151{
3152 /** The shadow mode type. */
3153 uint32_t uType;
3154 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
3155 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
3156 uint64_t fMask, uint32_t fOpFlags);
3157 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
3158 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3159#ifdef IN_RING3
3160 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3161#endif
3162} PGMMODEDATASHW;
3163
3164/** The length of g_aPgmShadowModeData. */
3165#ifndef IN_RC
3166# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
3167#else
3168# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3169#endif
3170/** The shadow mode data array. */
3171extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
3172
3173
3174/**
3175 * Function pointers for guest+shadow paging.
3176 */
3177typedef struct PGMMODEDATABTH
3178{
3179 /** The shadow mode type. */
3180 uint32_t uShwType;
3181 /** The guest mode type. */
3182 uint32_t uGstType;
3183
3184 DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3185 DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
3186 DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3187 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
3188 DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3189 DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPU pVCpu);
3190 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3191#ifndef IN_RING3
3192 DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
3193#endif
3194#ifdef VBOX_STRICT
3195 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
3196#endif
3197} PGMMODEDATABTH;
3198
3199/** The length of g_aPgmBothModeData. */
3200#ifndef IN_RC
3201# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3202#else
3203# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_PAE + 1 - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3204#endif
3205/** The guest+shadow mode data array. */
3206extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
3207
3208
3209#ifdef VBOX_WITH_STATISTICS
3210/**
3211 * PGM statistics.
3212 *
3213 * These lives on the heap when compiled in as they would otherwise waste
3214 * unnecessary space in release builds.
3215 */
3216typedef struct PGMSTATS
3217{
3218 /* R3 only: */
3219 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
3220 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
3221
3222 /* R3+RZ */
3223 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
3224 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
3225 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3226 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3227 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3228 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3229 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3230 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3231 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3232 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3233 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3234 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3235 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3236 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3237 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
3238 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
3239 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
3240 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
3241 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3242 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3243 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3244 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3245 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3246 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3247 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3248 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3249 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3250 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3251/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3252 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3253 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3254/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3255
3256 /* RC only: */
3257 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3258 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3259
3260 STAMCOUNTER StatRZPhysRead;
3261 STAMCOUNTER StatRZPhysReadBytes;
3262 STAMCOUNTER StatRZPhysWrite;
3263 STAMCOUNTER StatRZPhysWriteBytes;
3264 STAMCOUNTER StatR3PhysRead;
3265 STAMCOUNTER StatR3PhysReadBytes;
3266 STAMCOUNTER StatR3PhysWrite;
3267 STAMCOUNTER StatR3PhysWriteBytes;
3268 STAMCOUNTER StatRCPhysRead;
3269 STAMCOUNTER StatRCPhysReadBytes;
3270 STAMCOUNTER StatRCPhysWrite;
3271 STAMCOUNTER StatRCPhysWriteBytes;
3272
3273 STAMCOUNTER StatRZPhysSimpleRead;
3274 STAMCOUNTER StatRZPhysSimpleReadBytes;
3275 STAMCOUNTER StatRZPhysSimpleWrite;
3276 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3277 STAMCOUNTER StatR3PhysSimpleRead;
3278 STAMCOUNTER StatR3PhysSimpleReadBytes;
3279 STAMCOUNTER StatR3PhysSimpleWrite;
3280 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3281 STAMCOUNTER StatRCPhysSimpleRead;
3282 STAMCOUNTER StatRCPhysSimpleReadBytes;
3283 STAMCOUNTER StatRCPhysSimpleWrite;
3284 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3285
3286 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3287 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3288 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3289 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3290 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3291 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3292 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3293
3294 /** Time spent by the host OS for large page allocation. */
3295 STAMPROFILE StatAllocLargePage;
3296 /** Time spent clearing the newly allocated large pages. */
3297 STAMPROFILE StatClearLargePage;
3298 /** The number of times allocating a large pages takes more than the allowed period. */
3299 STAMCOUNTER StatLargePageOverflow;
3300 /** pgmPhysIsValidLargePage profiling - R3 */
3301 STAMPROFILE StatR3IsValidLargePage;
3302 /** pgmPhysIsValidLargePage profiling - RZ*/
3303 STAMPROFILE StatRZIsValidLargePage;
3304
3305 STAMPROFILE StatChunkAging;
3306 STAMPROFILE StatChunkFindCandidate;
3307 STAMPROFILE StatChunkUnmap;
3308 STAMPROFILE StatChunkMap;
3309} PGMSTATS;
3310#endif /* VBOX_WITH_STATISTICS */
3311
3312
3313/**
3314 * Converts a PGM pointer into a VM pointer.
3315 * @returns Pointer to the VM structure the PGM is part of.
3316 * @param pPGM Pointer to PGM instance data.
3317 */
3318#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3319
3320/**
3321 * PGM Data (part of VM)
3322 */
3323typedef struct PGM
3324{
3325 /** Offset to the VM structure. */
3326 int32_t offVM;
3327 /** Offset of the PGMCPU structure relative to VMCPU. */
3328 int32_t offVCpuPGM;
3329
3330 /** @cfgm{/RamPreAlloc, boolean, false}
3331 * Indicates whether the base RAM should all be allocated before starting
3332 * the VM (default), or if it should be allocated when first written to.
3333 */
3334 bool fRamPreAlloc;
3335 /** Indicates whether write monitoring is currently in use.
3336 * This is used to prevent conflicts between live saving and page sharing
3337 * detection. */
3338 bool fPhysWriteMonitoringEngaged;
3339 /** Set if the CPU has less than 52-bit physical address width.
3340 * This is used */
3341 bool fLessThan52PhysicalAddressBits;
3342 /** Set when nested paging is active.
3343 * This is meant to save calls to HMIsNestedPagingActive and let the
3344 * compilers optimize the code better. Whether we use nested paging or
3345 * not is something we find out during VMM initialization and we won't
3346 * change this later on. */
3347 bool fNestedPaging;
3348 /** The host paging mode. (This is what SUPLib reports.) */
3349 SUPPAGINGMODE enmHostMode;
3350 /** We're not in a state which permits writes to guest memory.
3351 * (Only used in strict builds.) */
3352 bool fNoMorePhysWrites;
3353 /** @cfgm{/PageFusionAllowed, boolean, false}
3354 * Whether page fusion is allowed. */
3355 bool fPageFusionAllowed;
3356 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3357 * Whether PCI passthrough is enabled. */
3358 bool fPciPassthrough;
3359 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3360 uint8_t cMmio2Regions;
3361 /** Restore original ROM page content when resetting after loading state.
3362 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3363 * enables the VM to start using an updated ROM without requiring powering
3364 * down the VM, just rebooting or resetting it. */
3365 bool fRestoreRomPagesOnReset;
3366 /** Whether to automatically clear all RAM pages on reset. */
3367 bool fZeroRamPagesOnReset;
3368 /** Alignment padding. */
3369 bool afAlignment3[7];
3370
3371 /** Indicates that PGMR3FinalizeMappings has been called and that further
3372 * PGMR3MapIntermediate calls will be rejected. */
3373 bool fFinalizedMappings;
3374 /** If set no conflict checks are required. */
3375 bool fMappingsFixed;
3376 /** If set if restored as fixed but we were unable to re-fixate at the old
3377 * location because of room or address incompatibilities. */
3378 bool fMappingsFixedRestored;
3379 /** Size of fixed mapping.
3380 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3381 uint32_t cbMappingFixed;
3382 /** Generation ID for the RAM ranges. This member is incremented everytime
3383 * a RAM range is linked or unlinked. */
3384 uint32_t volatile idRamRangesGen;
3385
3386 /** Base address (GC) of fixed mapping.
3387 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3388 RTGCPTR GCPtrMappingFixed;
3389 /** The address of the previous RAM range mapping. */
3390 RTGCPTR GCPtrPrevRamRangeMapping;
3391
3392 /** Physical access handler type for ROM protection. */
3393 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3394 /** Alignment padding. */
3395 uint32_t u32Padding;
3396
3397 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3398 RTGCPHYS GCPhys4MBPSEMask;
3399 /** Mask containing the invalid bits of a guest physical address.
3400 * @remarks this does not stop at bit 52. */
3401 RTGCPHYS GCPhysInvAddrMask;
3402
3403
3404 /** RAM range TLB for R3. */
3405 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3406 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3407 * This is sorted by physical address and contains no overlapping ranges. */
3408 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3409 /** Root of the RAM range search tree for ring-3. */
3410 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3411 /** PGM offset based trees - R3 Ptr. */
3412 R3PTRTYPE(PPGMTREES) pTreesR3;
3413 /** Caching the last physical handler we looked up in R3. */
3414 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3415 /** Shadow Page Pool - R3 Ptr. */
3416 R3PTRTYPE(PPGMPOOL) pPoolR3;
3417#ifndef PGM_WITHOUT_MAPPINGS
3418 /** Linked list of GC mappings - for HC.
3419 * The list is sorted ascending on address. */
3420 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3421#endif
3422 /** Pointer to the list of ROM ranges - for R3.
3423 * This is sorted by physical address and contains no overlapping ranges. */
3424 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3425 /** Pointer to the list of MMIO2 ranges - for R3.
3426 * Registration order. */
3427 R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3428 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3429 R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3430
3431 /** RAM range TLB for R0. */
3432 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3433 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3434 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3435 /** Root of the RAM range search tree for ring-0. */
3436 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3437 /** PGM offset based trees - R0 Ptr. */
3438 R0PTRTYPE(PPGMTREES) pTreesR0;
3439 /** Caching the last physical handler we looked up in R0. */
3440 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3441 /** Shadow Page Pool - R0 Ptr. */
3442 R0PTRTYPE(PPGMPOOL) pPoolR0;
3443#ifndef PGM_WITHOUT_MAPPINGS
3444 /** Linked list of GC mappings - for R0.
3445 * The list is sorted ascending on address. */
3446 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3447 RTR0PTR R0PtrAlignment0;
3448#endif
3449 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3450 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3451 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3452 R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3453
3454 /** RAM range TLB for RC. */
3455 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3456 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3457 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3458 /** Root of the RAM range search tree for raw-mode context. */
3459 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3460 /** PGM offset based trees - RC Ptr. */
3461 RCPTRTYPE(PPGMTREES) pTreesRC;
3462 /** Caching the last physical handler we looked up in RC. */
3463 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3464 /** Shadow Page Pool - RC Ptr. */
3465 RCPTRTYPE(PPGMPOOL) pPoolRC;
3466#ifndef PGM_WITHOUT_MAPPINGS
3467 /** Linked list of GC mappings - for RC.
3468 * The list is sorted ascending on address. */
3469 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3470 RTRCPTR RCPtrAlignment0;
3471#endif
3472 /** RC pointer corresponding to PGM::pRomRangesR3. */
3473 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3474#ifndef PGM_WITHOUT_MAPPINGS
3475 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3476 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3477 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3478 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3479#endif
3480
3481
3482#ifndef PGM_WITHOUT_MAPPINGS
3483 /** Pointer to the 5 page CR3 content mapping.
3484 * The first page is always the CR3 (in some form) while the 4 other pages
3485 * are used for the PDs in PAE mode. */
3486 RTGCPTR GCPtrCR3Mapping;
3487
3488 /** @name Intermediate Context
3489 * @{ */
3490 /** Pointer to the intermediate page directory - Normal. */
3491 R3PTRTYPE(PX86PD) pInterPD;
3492 /** Pointer to the intermediate page tables - Normal.
3493 * There are two page tables, one for the identity mapping and one for
3494 * the host context mapping (of the core code). */
3495 R3PTRTYPE(PX86PT) apInterPTs[2];
3496 /** Pointer to the intermediate page tables - PAE. */
3497 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3498 /** Pointer to the intermediate page directory - PAE. */
3499 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3500 /** Pointer to the intermediate page directory - PAE. */
3501 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3502 /** Pointer to the intermediate page-map level 4 - AMD64. */
3503 R3PTRTYPE(PX86PML4) pInterPaePML4;
3504 /** Pointer to the intermediate page directory - AMD64. */
3505 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3506 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3507 RTHCPHYS HCPhysInterPD;
3508 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3509 RTHCPHYS HCPhysInterPaePDPT;
3510 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3511 RTHCPHYS HCPhysInterPaePML4;
3512 /** @} */
3513#endif
3514
3515#ifndef PGM_WITHOUT_MAPPINGS
3516 /** Base address of the dynamic page mapping area.
3517 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3518 *
3519 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3520 * work out. Some cleaning up of the initialization that would
3521 * remove this memory is yet to be done...
3522 */
3523 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3524 /** The address of the raw-mode context mapping cache. */
3525 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3526 /** The address of the ring-0 mapping cache if we're making use of it. */
3527 RTR0PTR pvR0DynMapUsed;
3528#endif
3529
3530 /** Hack: Number of deprecated page mapping locks taken by the current lock
3531 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3532 uint32_t cDeprecatedPageLocks;
3533 /** Alignment padding. */
3534 uint32_t au32Alignment2[3];
3535
3536
3537 /** PGM critical section.
3538 * This protects the physical & virtual access handlers, ram ranges,
3539 * and the page flag updating (some of it anyway).
3540 */
3541 PDMCRITSECT CritSectX;
3542
3543 /**
3544 * Data associated with managing the ring-3 mappings of the allocation chunks.
3545 */
3546 struct
3547 {
3548 /** The chunk mapping TLB. */
3549 PGMCHUNKR3MAPTLB Tlb;
3550 /** The chunk tree, ordered by chunk id. */
3551#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3552 R3PTRTYPE(PAVLU32NODECORE) pTree;
3553#else
3554 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3555#endif
3556#if HC_ARCH_BITS == 32
3557 uint32_t u32Alignment0;
3558#endif
3559 /** The number of mapped chunks. */
3560 uint32_t c;
3561 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3562 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3563 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3564 uint32_t cMax;
3565 /** The current time. This is incremented whenever a chunk is inserted. */
3566 uint32_t iNow;
3567 /** Alignment padding. */
3568 uint32_t au32Alignment1[3];
3569 } ChunkR3Map;
3570
3571 /** The page mapping TLB for ring-3. */
3572 PGMPAGER3MAPTLB PhysTlbR3;
3573 /** The page mapping TLB for ring-0 (still using ring-3 mappings). */
3574 PGMPAGER3MAPTLB PhysTlbR0;
3575
3576 /** @name The zero page.
3577 * @{ */
3578 /** The host physical address of the zero page. */
3579 RTHCPHYS HCPhysZeroPg;
3580 /** The ring-3 mapping of the zero page. */
3581 RTR3PTR pvZeroPgR3;
3582 /** The ring-0 mapping of the zero page. */
3583 RTR0PTR pvZeroPgR0;
3584 /** The GC mapping of the zero page. */
3585 RTRCPTR pvZeroPgRC;
3586 RTRCPTR RCPtrAlignment3;
3587 /** @}*/
3588
3589 /** @name The Invalid MMIO page.
3590 * This page is filled with 0xfeedface.
3591 * @{ */
3592 /** The host physical address of the invalid MMIO page. */
3593 RTHCPHYS HCPhysMmioPg;
3594 /** The host pysical address of the invalid MMIO page plus all invalid
3595 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3596 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3597 RTHCPHYS HCPhysInvMmioPg;
3598 /** The ring-3 mapping of the invalid MMIO page. */
3599 RTR3PTR pvMmioPgR3;
3600#if HC_ARCH_BITS == 32
3601 RTR3PTR R3PtrAlignment4;
3602#endif
3603 /** @} */
3604
3605
3606 /** The number of handy pages. */
3607 uint32_t cHandyPages;
3608
3609 /** The number of large handy pages. */
3610 uint32_t cLargeHandyPages;
3611
3612 /**
3613 * Array of handy pages.
3614 *
3615 * This array is used in a two way communication between pgmPhysAllocPage
3616 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3617 * an intermediary.
3618 *
3619 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3620 * (The current size of 32 pages, means 128 KB of handy memory.)
3621 */
3622 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3623
3624 /**
3625 * Array of large handy pages. (currently size 1)
3626 *
3627 * This array is used in a two way communication between pgmPhysAllocLargePage
3628 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3629 * an intermediary.
3630 */
3631 GMMPAGEDESC aLargeHandyPage[1];
3632
3633 /**
3634 * Live save data.
3635 */
3636 struct
3637 {
3638 /** Per type statistics. */
3639 struct
3640 {
3641 /** The number of ready pages. */
3642 uint32_t cReadyPages;
3643 /** The number of dirty pages. */
3644 uint32_t cDirtyPages;
3645 /** The number of ready zero pages. */
3646 uint32_t cZeroPages;
3647 /** The number of write monitored pages. */
3648 uint32_t cMonitoredPages;
3649 } Rom,
3650 Mmio2,
3651 Ram;
3652 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3653 uint32_t cIgnoredPages;
3654 /** Indicates that a live save operation is active. */
3655 bool fActive;
3656 /** Padding. */
3657 bool afReserved[2];
3658 /** The next history index. */
3659 uint8_t iDirtyPagesHistory;
3660 /** History of the total amount of dirty pages. */
3661 uint32_t acDirtyPagesHistory[64];
3662 /** Short term dirty page average. */
3663 uint32_t cDirtyPagesShort;
3664 /** Long term dirty page average. */
3665 uint32_t cDirtyPagesLong;
3666 /** The number of saved pages. This is used to get some kind of estimate of the
3667 * link speed so we can decide when we're done. It is reset after the first
3668 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3669 * zero pages. */
3670 uint64_t cSavedPages;
3671 /** The nanosecond timestamp when cSavedPages was 0. */
3672 uint64_t uSaveStartNS;
3673 /** Pages per second (for statistics). */
3674 uint32_t cPagesPerSecond;
3675 uint32_t cAlignment;
3676 } LiveSave;
3677
3678 /** @name Error injection.
3679 * @{ */
3680 /** Inject handy page allocation errors pretending we're completely out of
3681 * memory. */
3682 bool volatile fErrInjHandyPages;
3683 /** Padding. */
3684 bool afReserved[3];
3685 /** @} */
3686
3687 /** @name Release Statistics
3688 * @{ */
3689 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3690 uint32_t cPrivatePages; /**< The number of private pages. */
3691 uint32_t cSharedPages; /**< The number of shared pages. */
3692 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3693 uint32_t cZeroPages; /**< The number of zero backed pages. */
3694 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3695 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3696 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3697 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3698 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3699 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3700 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3701 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3702 uint32_t cLargePages; /**< The number of large pages. */
3703 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3704/* uint32_t aAlignment4[1]; */
3705
3706 /** The number of times we were forced to change the hypervisor region location. */
3707 STAMCOUNTER cRelocations;
3708
3709 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3710 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3711 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3712
3713 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3714 /** @} */
3715
3716#ifdef VBOX_WITH_STATISTICS
3717 /** @name Statistics on the heap.
3718 * @{ */
3719 R3PTRTYPE(PGMSTATS *) pStatsR3;
3720 R0PTRTYPE(PGMSTATS *) pStatsR0;
3721 RCPTRTYPE(PGMSTATS *) pStatsRC;
3722 RTRCPTR RCPtrAlignment;
3723 /** @} */
3724#endif
3725} PGM;
3726#ifndef IN_TSTVMSTRUCTGC /* HACK */
3727# ifndef PGM_WITHOUT_MAPPINGS
3728AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3729# endif
3730AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3731# ifndef PGM_WITHOUT_MAPPINGS
3732AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3733# endif
3734AssertCompileMemberAlignment(PGM, CritSectX, 8);
3735AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3736AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3737AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3738AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3739AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3740AssertCompileMemberAlignment(PGM, cRelocations, 8);
3741#endif /* !IN_TSTVMSTRUCTGC */
3742/** Pointer to the PGM instance data. */
3743typedef PGM *PPGM;
3744
3745
3746
3747typedef struct PGMCPUSTATS
3748{
3749 /* Common */
3750 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3751 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3752
3753 /* R0 only: */
3754 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3755 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3756
3757 /* RZ only: */
3758 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3759 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3760 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3761 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3762 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3763 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3764 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3765 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3766 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3767 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3768 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3769 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3770 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3771 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3772 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3773 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3774 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3775 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3776 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3777 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3778 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3779 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3780 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3781 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3782 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3783 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3784 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3785 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3786 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3787 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3788 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3789 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3790 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3791 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3792 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3793 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3794 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3795 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3796 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3797 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3798 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3799 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3800 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3801 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3802 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3803 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3804 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3805 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3806 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3807 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3808 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3809 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3810 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3811 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3812 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3813 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3814 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3815 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3816 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3817 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3818 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3819 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3820 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3821 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3822 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3823 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3824 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3825 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3826 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3827 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3828 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3829 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3830 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3831 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3832 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3833 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3834 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3835 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3836
3837 /* HC - R3 and (maybe) R0: */
3838
3839 /* RZ & R3: */
3840 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3841 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3842 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3843 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3844 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3845 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3846 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3847 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3848 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3849 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3850 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3851 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3852 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3853 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3854 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3855 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3856 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3857 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3858 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3859 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3860 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3861 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3862 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3863 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3864 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3865 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3866 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3867 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3868 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3869 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3870 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3871 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3872 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3873 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3874 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3875 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3876 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3877 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3878 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3879 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3880 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3881 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3882 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3883 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3884 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3885 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3886 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3887 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3888
3889 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3890 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3891 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3892 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3893 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3894 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3895 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3896 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3897 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3898 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3899 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3900 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3901 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3902 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3903 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3904 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3905 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3906 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3907 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3908 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3909 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3910 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3911 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3912 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3913 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3914 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3915 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3916 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3917 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3918 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3919 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3920 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3921 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3922 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3923 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3924 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3925 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3926 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3927 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3928 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3929 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3930 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3931 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3932 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3933 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3934 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3935 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3936 /** @} */
3937} PGMCPUSTATS;
3938
3939
3940/**
3941 * Converts a PGMCPU pointer into a VM pointer.
3942 * @returns Pointer to the VM structure the PGM is part of.
3943 * @param pPGM Pointer to PGMCPU instance data.
3944 */
3945#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3946
3947/**
3948 * Converts a PGMCPU pointer into a PGM pointer.
3949 * @returns Pointer to the VM structure the PGM is part of.
3950 * @param pPGMCpu Pointer to PGMCPU instance data.
3951 */
3952#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3953
3954/**
3955 * PGMCPU Data (part of VMCPU).
3956 */
3957typedef struct PGMCPU
3958{
3959 /** Offset to the VM structure. */
3960 int32_t offVM;
3961 /** Offset to the VMCPU structure. */
3962 int32_t offVCpu;
3963 /** Offset of the PGM structure relative to VMCPU. */
3964 int32_t offPGM;
3965 uint32_t uPadding0; /**< structure size alignment. */
3966
3967#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3968 /** Automatically tracked physical memory mapping set.
3969 * Ring-0 and strict raw-mode builds. */
3970 PGMMAPSET AutoSet;
3971#endif
3972
3973 /** A20 gate mask.
3974 * Our current approach to A20 emulation is to let REM do it and don't bother
3975 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3976 * But whould need arrise, we'll subject physical addresses to this mask. */
3977 RTGCPHYS GCPhysA20Mask;
3978 /** A20 gate state - boolean! */
3979 bool fA20Enabled;
3980 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3981 bool fNoExecuteEnabled;
3982 /** Unused bits. */
3983 bool afUnused[2];
3984
3985 /** What needs syncing (PGM_SYNC_*).
3986 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3987 * PGMFlushTLB, and PGMR3Load. */
3988 uint32_t fSyncFlags;
3989
3990 /** The shadow paging mode. */
3991 PGMMODE enmShadowMode;
3992 /** The guest paging mode. */
3993 PGMMODE enmGuestMode;
3994 /** Guest mode data table index (PGM_TYPE_XXX). */
3995 uint8_t volatile idxGuestModeData;
3996 /** Shadow mode data table index (PGM_TYPE_XXX). */
3997 uint8_t volatile idxShadowModeData;
3998 /** Both mode data table index (complicated). */
3999 uint8_t volatile idxBothModeData;
4000 /** Alignment padding. */
4001 uint8_t abPadding[5];
4002
4003 /** The current physical address represented in the guest CR3 register. */
4004 RTGCPHYS GCPhysCR3;
4005
4006 /** @name 32-bit Guest Paging.
4007 * @{ */
4008 /** The guest's page directory, R3 pointer. */
4009 R3PTRTYPE(PX86PD) pGst32BitPdR3;
4010#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4011 /** The guest's page directory, R0 pointer. */
4012 R0PTRTYPE(PX86PD) pGst32BitPdR0;
4013#endif
4014 /** The guest's page directory, static RC mapping. */
4015 RCPTRTYPE(PX86PD) pGst32BitPdRC;
4016 /** Mask containing the MBZ bits of a big page PDE. */
4017 uint32_t fGst32BitMbzBigPdeMask;
4018 /** Set if the page size extension (PSE) is enabled. */
4019 bool fGst32BitPageSizeExtension;
4020 /** Alignment padding. */
4021 bool afAlignment2[3];
4022 /** @} */
4023
4024 /** @name PAE Guest Paging.
4025 * @{ */
4026 /** The guest's page directory pointer table, static RC mapping. */
4027 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
4028 /** The guest's page directory pointer table, R3 pointer. */
4029 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
4030#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4031 /** The guest's page directory pointer table, R0 pointer. */
4032 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
4033#endif
4034
4035 /** The guest's page directories, R3 pointers.
4036 * These are individual pointers and don't have to be adjacent.
4037 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4038 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
4039 /** The guest's page directories, R0 pointers.
4040 * Same restrictions as apGstPaePDsR3. */
4041#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4042 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
4043#endif
4044 /** The guest's page directories, static GC mapping.
4045 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
4046 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4047 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
4048 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
4049 * @todo Remove this and use aGstPaePdpeRegs instead? */
4050 RTGCPHYS aGCPhysGstPaePDs[4];
4051 /** The values of the 4 PDPE CPU registers (PAE). */
4052 X86PDPE aGstPaePdpeRegs[4];
4053 /** The physical addresses of the monitored guest page directories (PAE). */
4054 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
4055 /** Mask containing the MBZ PTE bits. */
4056 uint64_t fGstPaeMbzPteMask;
4057 /** Mask containing the MBZ PDE bits. */
4058 uint64_t fGstPaeMbzPdeMask;
4059 /** Mask containing the MBZ big page PDE bits. */
4060 uint64_t fGstPaeMbzBigPdeMask;
4061 /** Mask containing the MBZ PDPE bits. */
4062 uint64_t fGstPaeMbzPdpeMask;
4063 /** @} */
4064
4065 /** @name AMD64 Guest Paging.
4066 * @{ */
4067 /** The guest's page directory pointer table, R3 pointer. */
4068 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
4069#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4070 /** The guest's page directory pointer table, R0 pointer. */
4071 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
4072#else
4073 RTR0PTR alignment6b; /**< alignment equalizer. */
4074#endif
4075 /** Mask containing the MBZ PTE bits. */
4076 uint64_t fGstAmd64MbzPteMask;
4077 /** Mask containing the MBZ PDE bits. */
4078 uint64_t fGstAmd64MbzPdeMask;
4079 /** Mask containing the MBZ big page PDE bits. */
4080 uint64_t fGstAmd64MbzBigPdeMask;
4081 /** Mask containing the MBZ PDPE bits. */
4082 uint64_t fGstAmd64MbzPdpeMask;
4083 /** Mask containing the MBZ big page PDPE bits. */
4084 uint64_t fGstAmd64MbzBigPdpeMask;
4085 /** Mask containing the MBZ PML4E bits. */
4086 uint64_t fGstAmd64MbzPml4eMask;
4087 /** Mask containing the PDPE bits that we shadow. */
4088 uint64_t fGstAmd64ShadowedPdpeMask;
4089 /** Mask containing the PML4E bits that we shadow. */
4090 uint64_t fGstAmd64ShadowedPml4eMask;
4091 /** @} */
4092
4093 /** @name PAE and AMD64 Guest Paging.
4094 * @{ */
4095 /** Mask containing the PTE bits that we shadow. */
4096 uint64_t fGst64ShadowedPteMask;
4097 /** Mask containing the PDE bits that we shadow. */
4098 uint64_t fGst64ShadowedPdeMask;
4099 /** Mask containing the big page PDE bits that we shadow in the PDE. */
4100 uint64_t fGst64ShadowedBigPdeMask;
4101 /** Mask containing the big page PDE bits that we shadow in the PTE. */
4102 uint64_t fGst64ShadowedBigPde4PteMask;
4103 /** @} */
4104
4105 /** Pointer to the page of the current active CR3 - R3 Ptr. */
4106 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
4107 /** Pointer to the page of the current active CR3 - R0 Ptr. */
4108 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
4109 /** Pointer to the page of the current active CR3 - RC Ptr. */
4110 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
4111 /** Explicit alignment. */
4112 RTRCPTR alignment6;
4113 /** @} */
4114
4115 /** For saving stack space, the disassembler state is allocated here instead of
4116 * on the stack. */
4117 DISCPUSTATE DisState;
4118
4119 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
4120 uint64_t cNetwareWp0Hacks;
4121
4122 /** Count the number of pgm pool access handler calls. */
4123 uint64_t cPoolAccessHandler;
4124
4125 /** @name Release Statistics
4126 * @{ */
4127 /** The number of times the guest has switched mode since last reset or statistics reset. */
4128 STAMCOUNTER cGuestModeChanges;
4129 /** The number of times the guest has switched mode since last reset or statistics reset. */
4130 STAMCOUNTER cA20Changes;
4131 /** @} */
4132
4133#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4134 /** @name Statistics
4135 * @{ */
4136 /** RC: Pointer to the statistics. */
4137 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4138 /** RC: Which statistic this \#PF should be attributed to. */
4139 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4140 /** R0: Pointer to the statistics. */
4141 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4142 /** R0: Which statistic this \#PF should be attributed to. */
4143 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4144 /** R3: Pointer to the statistics. */
4145 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4146 /** Alignment padding. */
4147 RTR3PTR pPaddingR3;
4148 /** @} */
4149#endif /* VBOX_WITH_STATISTICS */
4150} PGMCPU;
4151/** Pointer to the per-cpu PGM data. */
4152typedef PGMCPU *PPGMCPU;
4153
4154
4155/** @name PGM::fSyncFlags Flags
4156 * @note Was part of saved state a long time ago.
4157 * @{
4158 */
4159/** Updates the virtual access handler state bit in PGMPAGE. */
4160#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4161/** Always sync CR3. */
4162#define PGM_SYNC_ALWAYS RT_BIT(1)
4163/** Check monitoring on next CR3 (re)load and invalidate page.
4164 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4165#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4166/** Check guest mapping in SyncCR3. */
4167#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4168/** Clear the page pool (a light weight flush). */
4169#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4170#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4171/** @} */
4172
4173
4174RT_C_DECLS_BEGIN
4175
4176#if defined(VBOX_STRICT) && defined(IN_RING3)
4177int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4178# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4179#else
4180int pgmLock(PVM pVM);
4181#endif
4182void pgmUnlock(PVM pVM);
4183/**
4184 * Asserts that the caller owns the PDM lock.
4185 * This is the internal variant of PGMIsLockOwner.
4186 * @param a_pVM Pointer to the VM.
4187 */
4188#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4189/**
4190 * Asserts that the caller owns the PDM lock.
4191 * This is the internal variant of PGMIsLockOwner.
4192 * @param a_pVM Pointer to the VM.
4193 * @param a_pVCpu The current CPU handle.
4194 */
4195#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
4196
4197#ifndef PGM_WITHOUT_MAPPINGS
4198int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4199int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4200int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4201int pgmMapResolveConflicts(PVM pVM);
4202PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4203DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4204#endif /* !PGM_WITHOUT_MAPPINGS */
4205
4206int pgmHandlerPhysicalExCreate(PVM pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4207 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
4208int pgmHandlerPhysicalExDup(PVM pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
4209int pgmHandlerPhysicalExRegister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
4210int pgmHandlerPhysicalExDeregister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
4211int pgmHandlerPhysicalExDestroy(PVM pVM, PPGMPHYSHANDLER pHandler);
4212void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4213bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4214void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4215#ifdef VBOX_WITH_RAW_MODE
4216PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4217DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4218# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
4219void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4220# else
4221# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4222# endif
4223#endif /* VBOX_WITH_RAW_MODE */
4224DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4225int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4226
4227int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4228int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4229int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4230int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4231int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4232void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4233int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4234int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4235int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4236int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4237int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4238int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4239int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4240int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4241int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4242int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4243void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4244PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4245#ifndef IN_RING3
4246DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4247DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4248DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4249#endif
4250int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4251 PGMPAGETYPE enmNewType);
4252void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4253void pgmPhysInvalidatePageMapTLB(PVM pVM);
4254void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4255PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4256PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4257PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4258int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4259int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4260
4261#ifdef IN_RING3
4262void pgmR3PhysRelinkRamRanges(PVM pVM);
4263int pgmR3PhysRamPreAllocate(PVM pVM);
4264int pgmR3PhysRamReset(PVM pVM);
4265int pgmR3PhysRomReset(PVM pVM);
4266int pgmR3PhysRamZeroAll(PVM pVM);
4267int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4268int pgmR3PhysRamTerm(PVM pVM);
4269void pgmR3PhysRomTerm(PVM pVM);
4270void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4271
4272int pgmR3PoolInit(PVM pVM);
4273void pgmR3PoolRelocate(PVM pVM);
4274void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4275void pgmR3PoolReset(PVM pVM);
4276void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4277DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4278void pgmR3PoolWriteProtectPages(PVM pVM);
4279
4280#endif /* IN_RING3 */
4281#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4282int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4283int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4284# ifdef LOG_ENABLED
4285void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4286# else
4287void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4288# endif
4289#endif
4290int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4291 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4292void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4293void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4294int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4295void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4296PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4297PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4298int pgmPoolSyncCR3(PVMCPU pVCpu);
4299bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
4300void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4301int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4302void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4303uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4304void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4305void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4306void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4307PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4308#ifndef IN_RING3
4309DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4310#endif
4311
4312void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4313void pgmPoolResetDirtyPages(PVM pVM);
4314void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4315
4316int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4317int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4318void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4319
4320#ifndef PGM_WITHOUT_MAPPINGS
4321void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4322void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4323int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4324int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4325#endif
4326
4327int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4328int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4329int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4330
4331int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4332int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4333int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4334int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4335int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4336int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4337
4338# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4339FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4340FNDBGCCMD pgmR3CmdShowSharedModules;
4341# endif
4342
4343void pgmLogState(PVM pVM);
4344
4345RT_C_DECLS_END
4346
4347/** @} */
4348
4349#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4350
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