PGMInternal.h@ 56296

Last change on this file since 56296 was 56252, checked in by vboxsync, 9 years ago
updated pci raw config docs; read config.
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1	/* $Id: PGMInternal.h 56252 2015-06-05 10:54:51Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/list-off32.h>
43	#include <iprt/sha.h>
44
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Indicates that there are no guest mappings in the shadow tables.
60	*
61	* Note! In ring-3 the macro is also used to exclude the managment of the
62	* intermediate context page tables. On 32-bit systems we use the intermediate
63	* context to support 64-bit guest execution. Thus, we cannot fully make it
64	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
65	*
66	* In raw-mode context there are by design always guest mappings (the code is
67	* executed from one), while in ring-0 there are none at all. Neither context
68	* manages the page tables for intermediate switcher context, that's all done in
69	* ring-3.
70	*
71	* On 32-bit darwin (hybrid kernel) we do 64-bit guest support differently, so
72	* there we can safely work without mappings if we don't compile in raw-mode.
73	*/
74	#if defined(IN_RING0) \
75	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
76	&& ( HC_ARCH_BITS != 32 \
77	\|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# define PGM_WITHOUT_MAPPINGS
82	#endif
83
84	/**
85	* Check and skip global PDEs for non-global flushes
86	*/
87	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
88
89	/**
90	* Optimization for PAE page tables that are modified often
91	*/
92	//#if 0 /* disabled again while debugging */
93	#ifndef IN_RC
94	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	#endif
96	//#endif
97
98	/**
99	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
100	*/
101	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
102	# define PGM_WITH_LARGE_PAGES
103	#endif
104
105	/**
106	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
107	* VMX_EXIT_EPT_MISCONFIG.
108	*/
109	#if 1 /* testing */
110	# define PGM_WITH_MMIO_OPTIMIZATIONS
111	#endif
112
113	/**
114	* Sync N pages instead of a whole page table
115	*/
116	#define PGM_SYNC_N_PAGES
117
118	/**
119	* Number of pages to sync during a page fault
120	*
121	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
122	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
123	*
124	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
125	* world switch overhead, so let's sync more.
126	*/
127	# ifdef IN_RING0
128	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
129	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
130	* but ~5% fewer faults.
131	*/
132	# define PGM_SYNC_NR_PAGES 32
133	#else
134	# define PGM_SYNC_NR_PAGES 8
135	#endif
136
137	/**
138	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
139	*/
140	#define PGM_MAX_PHYSCACHE_ENTRIES 64
141	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
142
143
144	/** @def PGMPOOL_CFG_MAX_GROW
145	* The maximum number of pages to add to the pool in one go.
146	*/
147	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
148
149	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
150	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
151	*/
152	#ifdef VBOX_STRICT
153	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
154	#endif
155
156	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
157	* Enables the experimental lazy page allocation code. */
158	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
159
160	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161	* Enables real write monitoring of pages, i.e. mapping them read-only and
162	* only making them writable when getting a write access #PF. */
163	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164
165	/** @} */
166
167
168	/** @name PDPT and PML4 flags.
169	* These are placed in the three bits available for system programs in
170	* the PDPT and PML4 entries.
171	* @{ */
172	/** The entry is a permanent one and it's must always be present.
173	* Never free such an entry. */
174	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175	/** Mapping (hypervisor allocated pagetable). */
176	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Mapping (hypervisor allocated pagetable). */
184	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187	/** @} */
188
189	/** @name Page flags.
190	* These are placed in the three bits available for system programs in
191	* the page entries.
192	* @{ */
193	/** Made read-only to facilitate dirty bit tracking. */
194	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197	/** Scanned and approved by CSAM (tm).
198	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
199	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201	#endif
202
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	#define PGM_TYPE_NESTED 6
213	#define PGM_TYPE_EPT 7
214	#define PGM_TYPE_MAX PGM_TYPE_EPT
215	/** @} */
216
217	/** Macro for checking if the guest is using paging.
218	* @param uGstType PGM_TYPE_*
219	* @param uShwType PGM_TYPE_*
220	* @remark ASSUMES certain order of the PGM_TYPE_* values.
221	*/
222	#define PGM_WITH_PAGING(uGstType, uShwType) \
223	( (uGstType) >= PGM_TYPE_32BIT \
224	&& (uShwType) != PGM_TYPE_NESTED \
225	&& (uShwType) != PGM_TYPE_EPT)
226
227	/** Macro for checking if the guest supports the NX bit.
228	* @param uGstType PGM_TYPE_*
229	* @param uShwType PGM_TYPE_*
230	* @remark ASSUMES certain order of the PGM_TYPE_* values.
231	*/
232	#define PGM_WITH_NX(uGstType, uShwType) \
233	( (uGstType) >= PGM_TYPE_PAE \
234	&& (uShwType) != PGM_TYPE_NESTED \
235	&& (uShwType) != PGM_TYPE_EPT)
236
237
238	/** @def PGM_HCPHYS_2_PTR
239	* Maps a HC physical page pool address to a virtual address.
240	*
241	* @returns VBox status code.
242	* @param pVM Pointer to the VM.
243	* @param pVCpu The current CPU.
244	* @param HCPhys The HC physical address to map to a virtual one.
245	* @param ppv Where to store the virtual address. No need to cast
246	* this.
247	*
248	* @remark Use with care as we don't have so much dynamic mapping space in
249	* ring-0 on 32-bit darwin and in RC.
250	* @remark There is no need to assert on the result.
251	*/
252	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
253	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
254	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
255	#else
256	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
257	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
258	#endif
259
260	/** @def PGM_GCPHYS_2_PTR_V2
261	* Maps a GC physical page address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM Pointer to the VM.
265	* @param pVCpu The current CPU.
266	* @param GCPhys The GC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark Use with care as we don't have so much dynamic mapping space in
270	* ring-0 on 32-bit darwin and in RC.
271	* @remark There is no need to assert on the result.
272	*/
273	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
274	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
275	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
276	#else
277	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
278	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
279	#endif
280
281	/** @def PGM_GCPHYS_2_PTR
282	* Maps a GC physical page address to a virtual address.
283	*
284	* @returns VBox status code.
285	* @param pVM Pointer to the VM.
286	* @param GCPhys The GC physical address to map to a virtual one.
287	* @param ppv Where to store the virtual address. No need to cast this.
288	*
289	* @remark Use with care as we don't have so much dynamic mapping space in
290	* ring-0 on 32-bit darwin and in RC.
291	* @remark There is no need to assert on the result.
292	*/
293	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
294
295	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
296	* Maps a GC physical page address to a virtual address.
297	*
298	* @returns VBox status code.
299	* @param pVCpu The current CPU.
300	* @param GCPhys The GC physical address to map to a virtual one.
301	* @param ppv Where to store the virtual address. No need to cast this.
302	*
303	* @remark Use with care as we don't have so much dynamic mapping space in
304	* ring-0 on 32-bit darwin and in RC.
305	* @remark There is no need to assert on the result.
306	*/
307	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
308
309	/** @def PGM_GCPHYS_2_PTR_EX
310	* Maps a unaligned GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVM Pointer to the VM.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark Use with care as we don't have so much dynamic mapping space in
318	* ring-0 on 32-bit darwin and in RC.
319	* @remark There is no need to assert on the result.
320	*/
321	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
324	#else
325	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
327	#endif
328
329	/** @def PGM_DYNMAP_UNUSED_HINT
330	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
331	* is no longer used.
332	*
333	* For best effect only apply this to the page that was mapped most recently.
334	*
335	* @param pVCpu The current CPU.
336	* @param pvPage The pool page.
337	*/
338	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
339	# ifdef LOG_ENABLED
340	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
341	# else
342	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
343	# endif
344	#else
345	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
346	#endif
347
348	/** @def PGM_DYNMAP_UNUSED_HINT_VM
349	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
350	* is no longer used.
351	*
352	* For best effect only apply this to the page that was mapped most recently.
353	*
354	* @param pVM Pointer to the VM.
355	* @param pvPage The pool page.
356	*/
357	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
358
359
360	/** @def PGM_INVL_PG
361	* Invalidates a page.
362	*
363	* @param pVCpu Pointer to the VMCPU.
364	* @param GCVirt The virtual address of the page to invalidate.
365	*/
366	#ifdef IN_RC
367	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
368	#elif defined(IN_RING0)
369	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
370	#else
371	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
372	#endif
373
374	/** @def PGM_INVL_PG_ALL_VCPU
375	* Invalidates a page on all VCPUs
376	*
377	* @param pVM Pointer to the VM.
378	* @param GCVirt The virtual address of the page to invalidate.
379	*/
380	#ifdef IN_RC
381	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
382	#elif defined(IN_RING0)
383	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
384	#else
385	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
386	#endif
387
388	/** @def PGM_INVL_BIG_PG
389	* Invalidates a 4MB page directory entry.
390	*
391	* @param pVCpu Pointer to the VMCPU.
392	* @param GCVirt The virtual address within the page directory to invalidate.
393	*/
394	#ifdef IN_RC
395	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
396	#elif defined(IN_RING0)
397	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
398	#else
399	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
400	#endif
401
402	/** @def PGM_INVL_VCPU_TLBS()
403	* Invalidates the TLBs of the specified VCPU
404	*
405	* @param pVCpu Pointer to the VMCPU.
406	*/
407	#ifdef IN_RC
408	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
409	#elif defined(IN_RING0)
410	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
411	#else
412	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
413	#endif
414
415	/** @def PGM_INVL_ALL_VCPU_TLBS()
416	* Invalidates the TLBs of all VCPUs
417	*
418	* @param pVM Pointer to the VM.
419	*/
420	#ifdef IN_RC
421	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
422	#elif defined(IN_RING0)
423	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
424	#else
425	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
426	#endif
427
428
429	/** @name Safer Shadow PAE PT/PTE
430	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
431	* present.
432	*
433	* @{
434	*/
435	#if 1
436	/**
437	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
438	* invalid entries for present.
439	* @sa X86PTEPAE.
440	*/
441	typedef union PGMSHWPTEPAE
442	{
443	/** Unsigned integer view */
444	X86PGPAEUINT uCareful;
445	/* Not other views. */
446	} PGMSHWPTEPAE;
447
448	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
449	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
450	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
451	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
452	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
453	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
454	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
455	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
456	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
457	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
458	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
459	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
460	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
461	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
462	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
463	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
464
465	/**
466	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
467	* invalid entries for present.
468	* @sa X86PTPAE.
469	*/
470	typedef struct PGMSHWPTPAE
471	{
472	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
473	} PGMSHWPTPAE;
474
475	#else
476	typedef X86PTEPAE PGMSHWPTEPAE;
477	typedef X86PTPAE PGMSHWPTPAE;
478	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
479	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
480	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
481	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
482	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
483	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
484	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
485	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
486	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
487	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
488	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
489	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
491	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
492	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
493	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
494
495	#endif
496
497	/** Pointer to a shadow PAE PTE. */
498	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
499	/** Pointer to a const shadow PAE PTE. */
500	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
501
502	/** Pointer to a shadow PAE page table. */
503	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
504	/** Pointer to a const shadow PAE page table. */
505	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
506	/** @} */
507
508
509	/** Size of the GCPtrConflict array in PGMMAPPING.
510	* @remarks Must be a power of two. */
511	#define PGMMAPPING_CONFLICT_MAX 8
512
513	/**
514	* Structure for tracking GC Mappings.
515	*
516	* This structure is used by linked list in both GC and HC.
517	*/
518	typedef struct PGMMAPPING
519	{
520	/** Pointer to next entry. */
521	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
522	/** Pointer to next entry. */
523	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
524	/** Pointer to next entry. */
525	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
526	/** Indicate whether this entry is finalized. */
527	bool fFinalized;
528	/** Start Virtual address. */
529	RTGCPTR GCPtr;
530	/** Last Virtual address (inclusive). */
531	RTGCPTR GCPtrLast;
532	/** Range size (bytes). */
533	RTGCPTR cb;
534	/** Pointer to relocation callback function. */
535	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
536	/** User argument to the callback. */
537	R3PTRTYPE(void *) pvUser;
538	/** Mapping description / name. For easing debugging. */
539	R3PTRTYPE(const char *) pszDesc;
540	/** Last 8 addresses that caused conflicts. */
541	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
542	/** Number of conflicts for this hypervisor mapping. */
543	uint32_t cConflicts;
544	/** Number of page tables. */
545	uint32_t cPTs;
546
547	/** Array of page table mapping data. Each entry
548	* describes one page table. The array can be longer
549	* than the declared length.
550	*/
551	struct
552	{
553	/** The HC physical address of the page table. */
554	RTHCPHYS HCPhysPT;
555	/** The HC physical address of the first PAE page table. */
556	RTHCPHYS HCPhysPaePT0;
557	/** The HC physical address of the second PAE page table. */
558	RTHCPHYS HCPhysPaePT1;
559	/** The HC virtual address of the 32-bit page table. */
560	R3PTRTYPE(PX86PT) pPTR3;
561	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
562	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
563	/** The RC virtual address of the 32-bit page table. */
564	RCPTRTYPE(PX86PT) pPTRC;
565	/** The RC virtual address of the two PAE page table. */
566	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
567	/** The R0 virtual address of the 32-bit page table. */
568	R0PTRTYPE(PX86PT) pPTR0;
569	/** The R0 virtual address of the two PAE page table. */
570	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
571	} aPTs[1];
572	} PGMMAPPING;
573	/** Pointer to structure for tracking GC Mappings. */
574	typedef struct PGMMAPPING *PPGMMAPPING;
575
576
577	/**
578	* Physical page access handler type registration.
579	*/
580	typedef struct PGMPHYSHANDLERTYPEINT
581	{
582	/** Number of references. */
583	uint32_t volatile cRefs;
584	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
585	uint32_t u32Magic;
586	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
587	RTLISTOFF32NODE ListNode;
588	/** The kind of accesses we're handling. */
589	PGMPHYSHANDLERKIND enmKind;
590	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
591	uint32_t uState;
592	/** Pointer to RC callback function. */
593	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
594	/** Pointer to RC callback function for \#PFs. */
595	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
596	/** Pointer to R3 callback function. */
597	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
598	/** Pointer to R0 callback function. */
599	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
600	/** Pointer to R0 callback function for \#PFs. */
601	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
602	/** Description / Name. For easing debugging. */
603	R3PTRTYPE(const char *) pszDesc;
604	} PGMPHYSHANDLERTYPEINT;
605	/** Pointer to a physical access handler type registration. */
606	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
607	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
609	/** Magic value for the physical handler callbacks. */
610	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
611
612	/**
613	* Converts a handle to a pointer.
614	* @returns PPGMPHYSHANDLERTYPEINT
615	* @param a_pVM Pointer to the cross context VM structure.
616	* @param a_hType Physical access handler type handle.
617	*/
618	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
619
620
621	/**
622	* Physical page access handler structure.
623	*
624	* This is used to keep track of physical address ranges
625	* which are being monitored in some kind of way.
626	*/
627	typedef struct PGMPHYSHANDLER
628	{
629	AVLROGCPHYSNODECORE Core;
630	/** Number of pages to update. */
631	uint32_t cPages;
632	/** Set if we have pages that have been aliased. */
633	uint32_t cAliasedPages;
634	/** Set if we have pages that have temporarily been disabled. */
635	uint32_t cTmpOffPages;
636	/** Registered handler type handle (heap offset). */
637	PGMPHYSHANDLERTYPE hType;
638	/** User argument for RC handlers. */
639	RCPTRTYPE(void *) pvUserRC;
640	#if HC_ARCH_BITS == 64
641	RTRCPTR Padding0; /*< Explicit alignment padding. /
642	#endif
643	/** User argument for R3 handlers. */
644	R3PTRTYPE(void *) pvUserR3;
645	/** User argument for R0 handlers. */
646	R0PTRTYPE(void *) pvUserR0;
647	/** Description / Name. For easing debugging. */
648	R3PTRTYPE(const char *) pszDesc;
649	#ifdef VBOX_WITH_STATISTICS
650	/** Profiling of this handler. */
651	STAMPROFILE Stat;
652	#endif
653	} PGMPHYSHANDLER;
654	/** Pointer to a physical page access handler structure. */
655	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
656
657	/**
658	* Gets the type record for a physical handler (no reference added).
659	* @returns PPGMPHYSHANDLERTYPEINT
660	* @param a_pVM Pointer to the cross context VM structure.
661	* @param a_pPhysHandler Pointer to the physical handler structure
662	* (PGMPHYSHANDLER).
663	*/
664	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
665
666
667	/**
668	* Cache node for the physical addresses covered by a virtual handler.
669	*/
670	typedef struct PGMPHYS2VIRTHANDLER
671	{
672	/** Core node for the tree based on physical ranges. */
673	AVLROGCPHYSNODECORE Core;
674	/** Offset from this struct to the PGMVIRTHANDLER structure. */
675	int32_t offVirtHandler;
676	/** Offset of the next alias relative to this one.
677	* Bit 0 is used for indicating whether we're in the tree.
678	* Bit 1 is used for indicating that we're the head node.
679	*/
680	int32_t offNextAlias;
681	} PGMPHYS2VIRTHANDLER;
682	/** Pointer to a phys to virtual handler structure. */
683	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
684
685	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
686	* node is in the tree. */
687	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
688	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
689	* node is in the head of an alias chain.
690	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
691	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
692	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
693	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
694
695
696	/**
697	* Virtual page access handler type registration.
698	*/
699	typedef struct PGMVIRTANDLERTYPEINT
700	{
701	/** Number of references. */
702	uint32_t volatile cRefs;
703	/** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
704	uint32_t u32Magic;
705	/** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
706	RTLISTOFF32NODE ListNode;
707	/** The kind of accesses we're handling. */
708	PGMVIRTHANDLERKIND enmKind;
709	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
710	uint32_t uState;
711	/** Whether the pvUserRC argument should be automatically relocated or not. */
712	bool fRelocUserRC;
713	bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
714	/** Pointer to RC callback function. */
715	RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
716	/** Pointer to RC callback function for \#PFs. */
717	RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
718	/** Pointer to the R3 callback function for invalidation. */
719	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
720	/** Pointer to R3 callback function. */
721	R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
722	/** Description / Name. For easing debugging. */
723	R3PTRTYPE(const char *) pszDesc;
724	} PGMVIRTHANDLERTYPEINT;
725	/** Pointer to a virtual access handler type registration. */
726	typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
727	/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
728	#define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
729	/** Magic value for the virtual handler callbacks. */
730	#define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
731
732	/**
733	* Converts a handle to a pointer.
734	* @returns PPGMVIRTHANDLERTYPEINT
735	* @param a_pVM Pointer to the cross context VM structure.
736	* @param a_hType Vitual access handler type handle.
737	*/
738	#define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
739
740
741	/**
742	* Virtual page access handler structure.
743	*
744	* This is used to keep track of virtual address ranges
745	* which are being monitored in some kind of way.
746	*/
747	typedef struct PGMVIRTHANDLER
748	{
749	/** Core node for the tree based on virtual ranges. */
750	AVLROGCPTRNODECORE Core;
751	/** Size of the range (in bytes). */
752	uint32_t cb;
753	/** Number of cache pages. */
754	uint32_t cPages;
755	/** Registered handler type handle (heap offset). */
756	PGMVIRTHANDLERTYPE hType;
757	/** User argument for RC handlers. */
758	RCPTRTYPE(void *) pvUserRC;
759	/** User argument for R3 handlers. */
760	R3PTRTYPE(void *) pvUserR3;
761	/** Description / Name. For easing debugging. */
762	R3PTRTYPE(const char *) pszDesc;
763	#ifdef VBOX_WITH_STATISTICS
764	/** Profiling of this handler. */
765	STAMPROFILE Stat;
766	#endif
767	/** Array of cached physical addresses for the monitored ranged. */
768	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
769	} PGMVIRTHANDLER;
770	/** Pointer to a virtual page access handler structure. */
771	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
772
773	/**
774	* Gets the type record for a virtual handler (no reference added).
775	* @returns PPGMVIRTHANDLERTYPEINT
776	* @param a_pVM Pointer to the cross context VM structure.
777	* @param a_pVirtHandler Pointer to the virtual handler structure
778	* (PGMVIRTHANDLER).
779	*/
780	#define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
781
782
783	/** @name Page type predicates.
784	* @{ */
785	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
786	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
787	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
788	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
789	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
790	/** @} */
791
792
793	/**
794	* A Physical Guest Page tracking structure.
795	*
796	* The format of this structure is complicated because we have to fit a lot
797	* of information into as few bits as possible. The format is also subject
798	* to change (there is one coming up soon). Which means that for we'll be
799	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
800	* accesses to the structure.
801	*/
802	typedef union PGMPAGE
803	{
804	/** Structured view. */
805	struct
806	{
807	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
808	uint64_t u2HandlerPhysStateY : 2;
809	/** 3:2 - Paging structure needed to map the page
810	* (PGM_PAGE_PDE_TYPE_). /
811	uint64_t u2PDETypeY : 2;
812	/** 4 - Indicator of dirty page for fault tolerance tracking. */
813	uint64_t fFTDirtyY : 1;
814	/** 5 - Flag indicating that a write monitored page was written to
815	* when set. */
816	uint64_t fWrittenToY : 1;
817	/** 7:6 - Unused. */
818	uint64_t u2Unused0 : 2;
819	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
820	uint64_t u2HandlerVirtStateY : 2;
821	/** 11:10 - Unused. */
822	uint64_t u2Unused1 : 2;
823	/** 12:48 - The host physical frame number (shift left to get the
824	* address). */
825	uint64_t HCPhysFN : 36;
826	/** 50:48 - The page state. */
827	uint64_t uStateY : 3;
828	/** 51:53 - The page type (PGMPAGETYPE). */
829	uint64_t uTypeY : 3;
830	/** 63:54 - PTE index for usage tracking (page pool). */
831	uint64_t u10PteIdx : 10;
832
833	/** The GMM page ID.
834	* @remarks In the current implementation, MMIO2 and pages aliased to
835	* MMIO2 pages will be exploiting this field to calculate the
836	* ring-3 mapping address corresponding to the page.
837	* Later we may consider including MMIO2 management into GMM. */
838	uint32_t idPage;
839	/** Usage tracking (page pool). */
840	uint16_t u16TrackingY;
841	/** The number of read locks on this page. */
842	uint8_t cReadLocksY;
843	/** The number of write locks on this page. */
844	uint8_t cWriteLocksY;
845	} s;
846
847	/** 64-bit integer view. */
848	uint64_t au64[2];
849	/** 16-bit view. */
850	uint32_t au32[4];
851	/** 16-bit view. */
852	uint16_t au16[8];
853	/** 8-bit view. */
854	uint8_t au8[16];
855	} PGMPAGE;
856	AssertCompileSize(PGMPAGE, 16);
857	/** Pointer to a physical guest page. */
858	typedef PGMPAGE *PPGMPAGE;
859	/** Pointer to a const physical guest page. */
860	typedef const PGMPAGE *PCPGMPAGE;
861	/** Pointer to a physical guest page pointer. */
862	typedef PPGMPAGE *PPPGMPAGE;
863
864
865	/**
866	* Clears the page structure.
867	* @param a_pPage Pointer to the physical guest page tracking structure.
868	*/
869	#define PGM_PAGE_CLEAR(a_pPage) \
870	do { \
871	(a_pPage)->au64[0] = 0; \
872	(a_pPage)->au64[1] = 0; \
873	} while (0)
874
875	/**
876	* Initializes the page structure.
877	* @param a_pPage Pointer to the physical guest page tracking structure.
878	*/
879	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
880	do { \
881	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
882	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
883	(a_pPage)->au64[0] = SetHCPhysTmp; \
884	(a_pPage)->au64[1] = 0; \
885	(a_pPage)->s.idPage = (a_idPage); \
886	(a_pPage)->s.uStateY = (a_uState); \
887	(a_pPage)->s.uTypeY = (a_uType); \
888	} while (0)
889
890	/**
891	* Initializes the page structure of a ZERO page.
892	* @param a_pPage Pointer to the physical guest page tracking structure.
893	* @param a_pVM The VM handle (for getting the zero page address).
894	* @param a_uType The page type (PGMPAGETYPE).
895	*/
896	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
897	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
898
899
900	/** @name The Page state, PGMPAGE::uStateY.
901	* @{ */
902	/** The zero page.
903	* This is a per-VM page that's never ever mapped writable. */
904	#define PGM_PAGE_STATE_ZERO 0
905	/** A allocated page.
906	* This is a per-VM page allocated from the page pool (or wherever
907	* we get MMIO2 pages from if the type is MMIO2).
908	*/
909	#define PGM_PAGE_STATE_ALLOCATED 1
910	/** A allocated page that's being monitored for writes.
911	* The shadow page table mappings are read-only. When a write occurs, the
912	* fWrittenTo member is set, the page remapped as read-write and the state
913	* moved back to allocated. */
914	#define PGM_PAGE_STATE_WRITE_MONITORED 2
915	/** The page is shared, aka. copy-on-write.
916	* This is a page that's shared with other VMs. */
917	#define PGM_PAGE_STATE_SHARED 3
918	/** The page is ballooned, so no longer available for this VM. */
919	#define PGM_PAGE_STATE_BALLOONED 4
920	/** @} */
921
922
923	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
924	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
925	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
926	#else
927	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
928	#endif
929
930	/**
931	* Gets the page state.
932	* @returns page state (PGM_PAGE_STATE_*).
933	* @param a_pPage Pointer to the physical guest page tracking structure.
934	*
935	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
936	* builds.
937	*/
938	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
939	#if defined(__GNUC__) && defined(VBOX_STRICT)
940	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
941	#else
942	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
943	#endif
944
945	/**
946	* Sets the page state.
947	* @param a_pVM The VM handle, only used for lock ownership assertions.
948	* @param a_pPage Pointer to the physical guest page tracking structure.
949	* @param a_uState The new page state.
950	*/
951	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
952	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
953
954
955	/**
956	* Gets the host physical address of the guest page.
957	* @returns host physical address (RTHCPHYS).
958	* @param a_pPage Pointer to the physical guest page tracking structure.
959	*
960	* @remarks In strict builds on gcc platforms, this macro will make some ugly
961	* assumption about a valid pVM variable/parameter being in the
962	* current context. It will use this pVM variable to assert that the
963	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
964	* pVM is not around.
965	*/
966	#if 0
967	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
968	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
969	#else
970	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
971	# if defined(__GNUC__) && defined(VBOX_STRICT)
972	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
973	# else
974	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
975	# endif
976	#endif
977
978	/**
979	* Sets the host physical address of the guest page.
980	*
981	* @param a_pVM The VM handle, only used for lock ownership assertions.
982	* @param a_pPage Pointer to the physical guest page tracking structure.
983	* @param a_HCPhys The new host physical address.
984	*/
985	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
986	do { \
987	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
988	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
989	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
990	PGM_PAGE_ASSERT_LOCK(a_pVM); \
991	} while (0)
992
993	/**
994	* Get the Page ID.
995	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
996	* @param a_pPage Pointer to the physical guest page tracking structure.
997	*/
998	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
999
1000	/**
1001	* Sets the Page ID.
1002	* @param a_pVM The VM handle, only used for lock ownership assertions.
1003	* @param a_pPage Pointer to the physical guest page tracking structure.
1004	* @param a_idPage The new page ID.
1005	*/
1006	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1007	do { \
1008	(a_pPage)->s.idPage = (a_idPage); \
1009	PGM_PAGE_ASSERT_LOCK(a_pVM); \
1010	} while (0)
1011
1012	/**
1013	* Get the Chunk ID.
1014	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1015	* @param a_pPage Pointer to the physical guest page tracking structure.
1016	*/
1017	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1018
1019	/**
1020	* Get the index of the page within the allocation chunk.
1021	* @returns The page index.
1022	* @param a_pPage Pointer to the physical guest page tracking structure.
1023	*/
1024	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1025
1026	/**
1027	* Gets the page type.
1028	* @returns The page type.
1029	* @param a_pPage Pointer to the physical guest page tracking structure.
1030	*
1031	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1032	* builds.
1033	*/
1034	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1035	#if defined(__GNUC__) && defined(VBOX_STRICT)
1036	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1037	#else
1038	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1039	#endif
1040
1041	/**
1042	* Sets the page type.
1043	*
1044	* @param a_pVM The VM handle, only used for lock ownership assertions.
1045	* @param a_pPage Pointer to the physical guest page tracking structure.
1046	* @param a_enmType The new page type (PGMPAGETYPE).
1047	*/
1048	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1049	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1050
1051	/**
1052	* Gets the page table index
1053	* @returns The page table index.
1054	* @param a_pPage Pointer to the physical guest page tracking structure.
1055	*/
1056	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1057
1058	/**
1059	* Sets the page table index.
1060	* @param a_pVM The VM handle, only used for lock ownership assertions.
1061	* @param a_pPage Pointer to the physical guest page tracking structure.
1062	* @param a_iPte New page table index.
1063	*/
1064	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1065	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1066
1067	/**
1068	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
1069	* @returns true/false.
1070	* @param a_pPage Pointer to the physical guest page tracking structure.
1071	*/
1072	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1073
1074	/**
1075	* Checks if the page is marked for MMIO, including both aliases.
1076	* @returns true/false.
1077	* @param a_pPage Pointer to the physical guest page tracking structure.
1078	*/
1079	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1080	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1081	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1082	)
1083
1084	/**
1085	* Checks if the page is marked for MMIO, including special aliases.
1086	* @returns true/false.
1087	* @param a_pPage Pointer to the physical guest page tracking structure.
1088	*/
1089	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1090	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1091
1092	/**
1093	* Checks if the page is a special aliased MMIO page.
1094	* @returns true/false.
1095	* @param a_pPage Pointer to the physical guest page tracking structure.
1096	*/
1097	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1098
1099	/**
1100	* Checks if the page is backed by the ZERO page.
1101	* @returns true/false.
1102	* @param a_pPage Pointer to the physical guest page tracking structure.
1103	*/
1104	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1105
1106	/**
1107	* Checks if the page is backed by a SHARED page.
1108	* @returns true/false.
1109	* @param a_pPage Pointer to the physical guest page tracking structure.
1110	*/
1111	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1112
1113	/**
1114	* Checks if the page is ballooned.
1115	* @returns true/false.
1116	* @param a_pPage Pointer to the physical guest page tracking structure.
1117	*/
1118	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1119
1120	/**
1121	* Checks if the page is allocated.
1122	* @returns true/false.
1123	* @param a_pPage Pointer to the physical guest page tracking structure.
1124	*/
1125	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1126
1127	/**
1128	* Marks the page as written to (for GMM change monitoring).
1129	* @param a_pVM The VM handle, only used for lock ownership assertions.
1130	* @param a_pPage Pointer to the physical guest page tracking structure.
1131	*/
1132	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1133	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1134
1135	/**
1136	* Clears the written-to indicator.
1137	* @param a_pVM The VM handle, only used for lock ownership assertions.
1138	* @param a_pPage Pointer to the physical guest page tracking structure.
1139	*/
1140	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1141	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1142
1143	/**
1144	* Checks if the page was marked as written-to.
1145	* @returns true/false.
1146	* @param a_pPage Pointer to the physical guest page tracking structure.
1147	*/
1148	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1149
1150	/**
1151	* Marks the page as dirty for FTM
1152	* @param a_pPage Pointer to the physical guest page tracking structure.
1153	*/
1154	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1155
1156	/**
1157	* Clears the FTM dirty indicator
1158	* @param a_pPage Pointer to the physical guest page tracking structure.
1159	*/
1160	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1161
1162	/**
1163	* Checks if the page was marked as dirty for FTM
1164	* @returns true/false.
1165	* @param a_pPage Pointer to the physical guest page tracking structure.
1166	*/
1167	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1168
1169
1170	/** @name PT usage values (PGMPAGE::u2PDEType).
1171	*
1172	* @{ */
1173	/** Either as a PT or PDE. */
1174	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1175	/** Must use a page table to map the range. */
1176	#define PGM_PAGE_PDE_TYPE_PT 1
1177	/** Can use a page directory entry to map the continuous range. */
1178	#define PGM_PAGE_PDE_TYPE_PDE 2
1179	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1180	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1181	/** @} */
1182
1183	/**
1184	* Set the PDE type of the page
1185	* @param a_pVM The VM handle, only used for lock ownership assertions.
1186	* @param a_pPage Pointer to the physical guest page tracking structure.
1187	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1188	*/
1189	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1190	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1191
1192	/**
1193	* Checks if the page was marked being part of a large page
1194	* @returns true/false.
1195	* @param a_pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1198
1199	/** Enabled optimized access handler tests.
1200	* These optimizations makes ASSUMPTIONS about the state values and the s1
1201	* layout. When enabled, the compiler should normally generate more compact
1202	* code.
1203	*/
1204	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1205
1206	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1207	*
1208	* @remarks The values are assigned in order of priority, so we can calculate
1209	* the correct state for a page with different handlers installed.
1210	* @{ */
1211	/** No handler installed. */
1212	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1213	/** Monitoring is temporarily disabled. */
1214	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1215	/** Write access is monitored. */
1216	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1217	/** All access is monitored. */
1218	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1219	/** @} */
1220
1221	/**
1222	* Gets the physical access handler state of a page.
1223	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1224	* @param a_pPage Pointer to the physical guest page tracking structure.
1225	*/
1226	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1227
1228	/**
1229	* Sets the physical access handler state of a page.
1230	* @param a_pPage Pointer to the physical guest page tracking structure.
1231	* @param a_uState The new state value.
1232	*/
1233	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1234	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1235
1236	/**
1237	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1238	* @returns true/false
1239	* @param a_pPage Pointer to the physical guest page tracking structure.
1240	*/
1241	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1242	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1243
1244	/**
1245	* Checks if the page has any active physical access handlers.
1246	* @returns true/false
1247	* @param a_pPage Pointer to the physical guest page tracking structure.
1248	*/
1249	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1250	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1251
1252
1253	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1254	*
1255	* @remarks The values are assigned in order of priority, so we can calculate
1256	* the correct state for a page with different handlers installed.
1257	* @{ */
1258	/** No handler installed. */
1259	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1260	/* 1 is reserved so the lineup is identical with the physical ones. */
1261	/** Write access is monitored. */
1262	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1263	/** All access is monitored. */
1264	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1265	/** @} */
1266
1267	/**
1268	* Gets the virtual access handler state of a page.
1269	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1270	* @param a_pPage Pointer to the physical guest page tracking structure.
1271	*/
1272	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1273
1274	/**
1275	* Sets the virtual access handler state of a page.
1276	* @param a_pPage Pointer to the physical guest page tracking structure.
1277	* @param a_uState The new state value.
1278	*/
1279	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1280	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1281
1282	/**
1283	* Checks if the page has any virtual access handlers.
1284	* @returns true/false
1285	* @param a_pPage Pointer to the physical guest page tracking structure.
1286	*/
1287	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1288	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1289
1290	/**
1291	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1292	* virtual handlers.
1293	* @returns true/false
1294	* @param a_pPage Pointer to the physical guest page tracking structure.
1295	*/
1296	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1297	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1298
1299
1300	/**
1301	* Checks if the page has any access handlers, including temporarily disabled ones.
1302	* @returns true/false
1303	* @param a_pPage Pointer to the physical guest page tracking structure.
1304	*/
1305	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1306	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1307	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1308	#else
1309	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1310	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1311	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1312	#endif
1313
1314	/**
1315	* Checks if the page has any active access handlers.
1316	* @returns true/false
1317	* @param a_pPage Pointer to the physical guest page tracking structure.
1318	*/
1319	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1320	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1321	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1322	#else
1323	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1324	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1325	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1326	#endif
1327
1328	/**
1329	* Checks if the page has any active access handlers catching all accesses.
1330	* @returns true/false
1331	* @param a_pPage Pointer to the physical guest page tracking structure.
1332	*/
1333	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1334	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1335	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1336	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1337	#else
1338	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1339	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1340	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1341	#endif
1342
1343
1344	/** @def PGM_PAGE_GET_TRACKING
1345	* Gets the packed shadow page pool tracking data associated with a guest page.
1346	* @returns uint16_t containing the data.
1347	* @param a_pPage Pointer to the physical guest page tracking structure.
1348	*/
1349	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1350	#if defined(__GNUC__) && defined(VBOX_STRICT)
1351	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1352	#else
1353	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1354	#endif
1355
1356	/** @def PGM_PAGE_SET_TRACKING
1357	* Sets the packed shadow page pool tracking data associated with a guest page.
1358	* @param a_pVM The VM handle, only used for lock ownership assertions.
1359	* @param a_pPage Pointer to the physical guest page tracking structure.
1360	* @param a_u16TrackingData The tracking data to store.
1361	*/
1362	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1363	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1364
1365	/** @def PGM_PAGE_GET_TD_CREFS
1366	* Gets the @a cRefs tracking data member.
1367	* @returns cRefs.
1368	* @param a_pPage Pointer to the physical guest page tracking structure.
1369	*/
1370	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1371	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1372	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1373	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1374
1375	/** @def PGM_PAGE_GET_TD_IDX
1376	* Gets the @a idx tracking data member.
1377	* @returns idx.
1378	* @param a_pPage Pointer to the physical guest page tracking structure.
1379	*/
1380	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1381	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1382	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1383	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1384
1385
1386	/** Max number of locks on a page. */
1387	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1388
1389	/** Get the read lock count.
1390	* @returns count.
1391	* @param a_pPage Pointer to the physical guest page tracking structure.
1392	*/
1393	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1394
1395	/** Get the write lock count.
1396	* @returns count.
1397	* @param a_pPage Pointer to the physical guest page tracking structure.
1398	*/
1399	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1400
1401	/** Decrement the read lock counter.
1402	* @param a_pPage Pointer to the physical guest page tracking structure.
1403	*/
1404	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1405
1406	/** Decrement the write lock counter.
1407	* @param a_pPage Pointer to the physical guest page tracking structure.
1408	*/
1409	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1410
1411	/** Increment the read lock counter.
1412	* @param a_pPage Pointer to the physical guest page tracking structure.
1413	*/
1414	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1415
1416	/** Increment the write lock counter.
1417	* @param a_pPage Pointer to the physical guest page tracking structure.
1418	*/
1419	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1420
1421
1422	#if 0
1423	/** Enables sanity checking of write monitoring using CRC-32. */
1424	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1425	#endif
1426
1427	/**
1428	* Per page live save tracking data.
1429	*/
1430	typedef struct PGMLIVESAVERAMPAGE
1431	{
1432	/** Number of times it has been dirtied. */
1433	uint32_t cDirtied : 24;
1434	/** Whether it is currently dirty. */
1435	uint32_t fDirty : 1;
1436	/** Ignore the page.
1437	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1438	* deal with these after pausing the VM and DevPCI have said it bit about
1439	* remappings. */
1440	uint32_t fIgnore : 1;
1441	/** Was a ZERO page last time around. */
1442	uint32_t fZero : 1;
1443	/** Was a SHARED page last time around. */
1444	uint32_t fShared : 1;
1445	/** Whether the page is/was write monitored in a previous pass. */
1446	uint32_t fWriteMonitored : 1;
1447	/** Whether the page is/was write monitored earlier in this pass. */
1448	uint32_t fWriteMonitoredJustNow : 1;
1449	/** Bits reserved for future use. */
1450	uint32_t u2Reserved : 2;
1451	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1452	/** CRC-32 for the page. This is for internal consistency checks. */
1453	uint32_t u32Crc;
1454	#endif
1455	} PGMLIVESAVERAMPAGE;
1456	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1457	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1458	#else
1459	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1460	#endif
1461	/** Pointer to the per page live save tracking data. */
1462	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1463
1464	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1465	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1466
1467
1468	/**
1469	* RAM range for GC Phys to HC Phys conversion.
1470	*
1471	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1472	* conversions too, but we'll let MM handle that for now.
1473	*
1474	* This structure is used by linked lists in both GC and HC.
1475	*/
1476	typedef struct PGMRAMRANGE
1477	{
1478	/** Start of the range. Page aligned. */
1479	RTGCPHYS GCPhys;
1480	/** Size of the range. (Page aligned of course). */
1481	RTGCPHYS cb;
1482	/** Pointer to the next RAM range - for R3. */
1483	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1484	/** Pointer to the next RAM range - for R0. */
1485	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1486	/** Pointer to the next RAM range - for RC. */
1487	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1488	/** PGM_RAM_RANGE_FLAGS_* flags. */
1489	uint32_t fFlags;
1490	/** Last address in the range (inclusive). Page aligned (-1). */
1491	RTGCPHYS GCPhysLast;
1492	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1493	R3PTRTYPE(void *) pvR3;
1494	/** Live save per page tracking data. */
1495	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1496	/** The range description. */
1497	R3PTRTYPE(const char *) pszDesc;
1498	/** Pointer to self - R0 pointer. */
1499	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1500	/** Pointer to self - RC pointer. */
1501	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1502
1503	/** Alignment padding. */
1504	RTRCPTR Alignment0;
1505	/** Pointer to the left search three node - ring-3 context. */
1506	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1507	/** Pointer to the right search three node - ring-3 context. */
1508	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1509	/** Pointer to the left search three node - ring-0 context. */
1510	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1511	/** Pointer to the right search three node - ring-0 context. */
1512	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1513	/** Pointer to the left search three node - raw-mode context. */
1514	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1515	/** Pointer to the right search three node - raw-mode context. */
1516	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1517
1518	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1519	#if HC_ARCH_BITS == 32
1520	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1521	#endif
1522	/** Array of physical guest page tracking structures. */
1523	PGMPAGE aPages[1];
1524	} PGMRAMRANGE;
1525	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1526	typedef PGMRAMRANGE *PPGMRAMRANGE;
1527
1528	/** @name PGMRAMRANGE::fFlags
1529	* @{ */
1530	/** The RAM range is floating around as an independent guest mapping. */
1531	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1532	/** Ad hoc RAM range for an ROM mapping. */
1533	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1534	/** Ad hoc RAM range for an MMIO mapping. */
1535	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1536	/** Ad hoc RAM range for an MMIO2 mapping. */
1537	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1538	/** @} */
1539
1540	/** Tests if a RAM range is an ad hoc one or not.
1541	* @returns true/false.
1542	* @param pRam The RAM range.
1543	*/
1544	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1545	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1546
1547	/** The number of entries in the RAM range TLBs (there is one for each
1548	* context). Must be a power of two. */
1549	#define PGM_RAMRANGE_TLB_ENTRIES 8
1550
1551	/**
1552	* Calculates the RAM range TLB index for the physical address.
1553	*
1554	* @returns RAM range TLB index.
1555	* @param GCPhys The guest physical address.
1556	*/
1557	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1558
1559
1560
1561	/**
1562	* Per page tracking structure for ROM image.
1563	*
1564	* A ROM image may have a shadow page, in which case we may have two pages
1565	* backing it. This structure contains the PGMPAGE for both while
1566	* PGMRAMRANGE have a copy of the active one. It is important that these
1567	* aren't out of sync in any regard other than page pool tracking data.
1568	*/
1569	typedef struct PGMROMPAGE
1570	{
1571	/** The page structure for the virgin ROM page. */
1572	PGMPAGE Virgin;
1573	/** The page structure for the shadow RAM page. */
1574	PGMPAGE Shadow;
1575	/** The current protection setting. */
1576	PGMROMPROT enmProt;
1577	/** Live save status information. Makes use of unused alignment space. */
1578	struct
1579	{
1580	/** The previous protection value. */
1581	uint8_t u8Prot;
1582	/** Written to flag set by the handler. */
1583	bool fWrittenTo;
1584	/** Whether the shadow page is dirty or not. */
1585	bool fDirty;
1586	/** Whether it was dirtied in the recently. */
1587	bool fDirtiedRecently;
1588	} LiveSave;
1589	} PGMROMPAGE;
1590	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1591	/** Pointer to a ROM page tracking structure. */
1592	typedef PGMROMPAGE *PPGMROMPAGE;
1593
1594
1595	/**
1596	* A registered ROM image.
1597	*
1598	* This is needed to keep track of ROM image since they generally intrude
1599	* into a PGMRAMRANGE. It also keeps track of additional info like the
1600	* two page sets (read-only virgin and read-write shadow), the current
1601	* state of each page.
1602	*
1603	* Because access handlers cannot easily be executed in a different
1604	* context, the ROM ranges needs to be accessible and in all contexts.
1605	*/
1606	typedef struct PGMROMRANGE
1607	{
1608	/** Pointer to the next range - R3. */
1609	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1610	/** Pointer to the next range - R0. */
1611	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1612	/** Pointer to the next range - RC. */
1613	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1614	/** Pointer alignment */
1615	RTRCPTR RCPtrAlignment;
1616	/** Address of the range. */
1617	RTGCPHYS GCPhys;
1618	/** Address of the last byte in the range. */
1619	RTGCPHYS GCPhysLast;
1620	/** Size of the range. */
1621	RTGCPHYS cb;
1622	/** The flags (PGMPHYS_ROM_FLAGS_). /
1623	uint32_t fFlags;
1624	/** The saved state range ID. */
1625	uint8_t idSavedState;
1626	/** Alignment padding. */
1627	uint8_t au8Alignment[3];
1628	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1629	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1630	/** The size bits pvOriginal points to. */
1631	uint32_t cbOriginal;
1632	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1633	* This is used for strictness checks. */
1634	R3PTRTYPE(const void *) pvOriginal;
1635	/** The ROM description. */
1636	R3PTRTYPE(const char *) pszDesc;
1637	/** The per page tracking structures. */
1638	PGMROMPAGE aPages[1];
1639	} PGMROMRANGE;
1640	/** Pointer to a ROM range. */
1641	typedef PGMROMRANGE *PPGMROMRANGE;
1642
1643
1644	/**
1645	* Live save per page data for an MMIO2 page.
1646	*
1647	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1648	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1649	* CRC-32 for detecting changes as well as special handling of zero pages. This
1650	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1651	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1652	* because of speed (2.5x and 6x slower).)
1653	*
1654	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1655	* save but normally is disabled. Since we can write monitor guest
1656	* accesses on our own, we only need this for host accesses. Shouldn't be
1657	* too difficult for DevVGA, VMMDev might be doable, the planned
1658	* networking fun will be fun since it involves ring-0.
1659	*/
1660	typedef struct PGMLIVESAVEMMIO2PAGE
1661	{
1662	/** Set if the page is considered dirty. */
1663	bool fDirty;
1664	/** The number of scans this page has remained unchanged for.
1665	* Only updated for dirty pages. */
1666	uint8_t cUnchangedScans;
1667	/** Whether this page was zero at the last scan. */
1668	bool fZero;
1669	/** Alignment padding. */
1670	bool fReserved;
1671	/** CRC-32 for the first half of the page.
1672	* This is used together with u32CrcH2 to quickly detect changes in the page
1673	* during the non-final passes. */
1674	uint32_t u32CrcH1;
1675	/** CRC-32 for the second half of the page. */
1676	uint32_t u32CrcH2;
1677	/** SHA-1 for the saved page.
1678	* This is used in the final pass to skip pages without changes. */
1679	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1680	} PGMLIVESAVEMMIO2PAGE;
1681	/** Pointer to a live save status data for an MMIO2 page. */
1682	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1683
1684	/**
1685	* A registered MMIO2 (= Device RAM) range.
1686	*
1687	* There are a few reason why we need to keep track of these
1688	* registrations. One of them is the deregistration & cleanup stuff,
1689	* while another is that the PGMRAMRANGE associated with such a region may
1690	* have to be removed from the ram range list.
1691	*
1692	* Overlapping with a RAM range has to be 100% or none at all. The pages
1693	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1694	* will be raised if a partial overlap or an overlap of ROM pages is
1695	* encountered. On an overlap we will free all the existing RAM pages and
1696	* put in the ram range pages instead.
1697	*/
1698	typedef struct PGMMMIO2RANGE
1699	{
1700	/** The owner of the range. (a device) */
1701	PPDMDEVINSR3 pDevInsR3;
1702	/** Pointer to the ring-3 mapping of the allocation. */
1703	RTR3PTR pvR3;
1704	/** Pointer to the next range - R3. */
1705	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1706	/** Whether it's mapped or not. */
1707	bool fMapped;
1708	/** Whether it's overlapping or not. */
1709	bool fOverlapping;
1710	/** The PCI region number.
1711	* @remarks This ASSUMES that nobody will ever really need to have multiple
1712	* PCI devices with matching MMIO region numbers on a single device. */
1713	uint8_t iRegion;
1714	/** The saved state range ID. */
1715	uint8_t idSavedState;
1716	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1717	uint8_t idMmio2;
1718	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1719	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1720	/** Live save per page tracking data. */
1721	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1722	/** The associated RAM range. */
1723	PGMRAMRANGE RamRange;
1724	} PGMMMIO2RANGE;
1725	/** Pointer to a MMIO2 range. */
1726	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1727
1728	/** @name Intenal MMIO2 constants.
1729	* @{ */
1730	/** The maximum number of MMIO2 ranges. */
1731	#define PGM_MMIO2_MAX_RANGES 8
1732	/** The maximum number of pages in a MMIO2 range. */
1733	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1734	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1735	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1736	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1737	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1738	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1739	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1740	/** @} */
1741
1742
1743
1744	/**
1745	* PGMPhysRead/Write cache entry
1746	*/
1747	typedef struct PGMPHYSCACHEENTRY
1748	{
1749	/** R3 pointer to physical page. */
1750	R3PTRTYPE(uint8_t *) pbR3;
1751	/** GC Physical address for cache entry */
1752	RTGCPHYS GCPhys;
1753	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1754	RTGCPHYS u32Padding0; /*< alignment padding. /
1755	#endif
1756	} PGMPHYSCACHEENTRY;
1757
1758	/**
1759	* PGMPhysRead/Write cache to reduce REM memory access overhead
1760	*/
1761	typedef struct PGMPHYSCACHE
1762	{
1763	/** Bitmap of valid cache entries */
1764	uint64_t aEntries;
1765	/** Cache entries */
1766	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1767	} PGMPHYSCACHE;
1768
1769
1770	/** Pointer to an allocation chunk ring-3 mapping. */
1771	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1772	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1773	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1774
1775	/**
1776	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1777	*
1778	* The primary tree (Core) uses the chunk id as key.
1779	*/
1780	typedef struct PGMCHUNKR3MAP
1781	{
1782	/** The key is the chunk id. */
1783	AVLU32NODECORE Core;
1784	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1785	* selection. */
1786	uint32_t iLastUsed;
1787	/** The current reference count. */
1788	uint32_t volatile cRefs;
1789	/** The current permanent reference count. */
1790	uint32_t volatile cPermRefs;
1791	/** The mapping address. */
1792	void *pv;
1793	} PGMCHUNKR3MAP;
1794
1795	/**
1796	* Allocation chunk ring-3 mapping TLB entry.
1797	*/
1798	typedef struct PGMCHUNKR3MAPTLBE
1799	{
1800	/** The chunk id. */
1801	uint32_t volatile idChunk;
1802	#if HC_ARCH_BITS == 64
1803	uint32_t u32Padding; /*< alignment padding. /
1804	#endif
1805	/** The chunk map. */
1806	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1807	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1808	#else
1809	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1810	#endif
1811	} PGMCHUNKR3MAPTLBE;
1812	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1813	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1814
1815	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1816	* @remark Must be a power of two value. */
1817	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1818
1819	/**
1820	* Allocation chunk ring-3 mapping TLB.
1821	*
1822	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1823	* At first glance this might look kinda odd since AVL trees are
1824	* supposed to give the most optimal lookup times of all trees
1825	* due to their balancing. However, take a tree with 1023 nodes
1826	* in it, that's 10 levels, meaning that most searches has to go
1827	* down 9 levels before they find what they want. This isn't fast
1828	* compared to a TLB hit. There is the factor of cache misses,
1829	* and of course the problem with trees and branch prediction.
1830	* This is why we use TLBs in front of most of the trees.
1831	*
1832	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1833	* difficult when we switch to the new inlined AVL trees (from kStuff).
1834	*/
1835	typedef struct PGMCHUNKR3MAPTLB
1836	{
1837	/** The TLB entries. */
1838	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1839	} PGMCHUNKR3MAPTLB;
1840
1841	/**
1842	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1843	* @returns Chunk TLB index.
1844	* @param idChunk The Chunk ID.
1845	*/
1846	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1847
1848
1849	/**
1850	* Ring-3 guest page mapping TLB entry.
1851	* @remarks used in ring-0 as well at the moment.
1852	*/
1853	typedef struct PGMPAGER3MAPTLBE
1854	{
1855	/** Address of the page. */
1856	RTGCPHYS volatile GCPhys;
1857	/** The guest page. */
1858	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1859	R3PTRTYPE(PPGMPAGE) volatile pPage;
1860	#else
1861	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1862	#endif
1863	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1864	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1865	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1866	#else
1867	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1868	#endif
1869	/** The address */
1870	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1871	R3PTRTYPE(void *) volatile pv;
1872	#else
1873	R3R0PTRTYPE(void *) volatile pv;
1874	#endif
1875	#if HC_ARCH_BITS == 32
1876	uint32_t u32Padding; /*< alignment padding. /
1877	#endif
1878	} PGMPAGER3MAPTLBE;
1879	/** Pointer to an entry in the HC physical TLB. */
1880	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1881
1882
1883	/** The number of entries in the ring-3 guest page mapping TLB.
1884	* @remarks The value must be a power of two. */
1885	#define PGM_PAGER3MAPTLB_ENTRIES 256
1886
1887	/**
1888	* Ring-3 guest page mapping TLB.
1889	* @remarks used in ring-0 as well at the moment.
1890	*/
1891	typedef struct PGMPAGER3MAPTLB
1892	{
1893	/** The TLB entries. */
1894	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1895	} PGMPAGER3MAPTLB;
1896	/** Pointer to the ring-3 guest page mapping TLB. */
1897	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1898
1899	/**
1900	* Calculates the index of the TLB entry for the specified guest page.
1901	* @returns Physical TLB index.
1902	* @param GCPhys The guest physical address.
1903	*/
1904	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1905
1906
1907	/**
1908	* Raw-mode context dynamic mapping cache entry.
1909	*
1910	* Because of raw-mode context being reloctable and all relocations are applied
1911	* in ring-3, this has to be defined here and be RC specific.
1912	*
1913	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1914	*/
1915	typedef struct PGMRCDYNMAPENTRY
1916	{
1917	/** The physical address of the currently mapped page.
1918	* This is duplicate for three reasons: cache locality, cache policy of the PT
1919	* mappings and sanity checks. */
1920	RTHCPHYS HCPhys;
1921	/** Pointer to the page. */
1922	RTRCPTR pvPage;
1923	/** The number of references. */
1924	int32_t volatile cRefs;
1925	/** PTE pointer union. */
1926	struct PGMRCDYNMAPENTRY_PPTE
1927	{
1928	/** PTE pointer, 32-bit legacy version. */
1929	RCPTRTYPE(PX86PTE) pLegacy;
1930	/** PTE pointer, PAE version. */
1931	RCPTRTYPE(PX86PTEPAE) pPae;
1932	} uPte;
1933	} PGMRCDYNMAPENTRY;
1934	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1935	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1936
1937
1938	/**
1939	* Dynamic mapping cache for the raw-mode context.
1940	*
1941	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1942	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1943	* so that we can perform relocations from PGMR3Relocate. This has the
1944	* consequence that we must have separate ring-0 and raw-mode context versions
1945	* of this struct even if they share the basic elements.
1946	*
1947	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1948	*/
1949	typedef struct PGMRCDYNMAP
1950	{
1951	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1952	uint32_t u32Magic;
1953	/** Array for tracking and managing the pages. */
1954	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1955	/** The cache size given as a number of pages. */
1956	uint32_t cPages;
1957	/** The current load.
1958	* This does not include guard pages. */
1959	uint32_t cLoad;
1960	/** The max load ever.
1961	* This is maintained to get trigger adding of more mapping space. */
1962	uint32_t cMaxLoad;
1963	/** The number of guard pages. */
1964	uint32_t cGuardPages;
1965	/** The number of users (protected by hInitLock). */
1966	uint32_t cUsers;
1967	} PGMRCDYNMAP;
1968	/** Pointer to the dynamic cache for the raw-mode context. */
1969	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1970
1971
1972	/**
1973	* Mapping cache usage set entry.
1974	*
1975	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1976	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1977	* cache. If it's extended to include ring-3, well, then something
1978	* will have be changed here...
1979	*/
1980	typedef struct PGMMAPSETENTRY
1981	{
1982	/** Pointer to the page. */
1983	#ifndef IN_RC
1984	RTR0PTR pvPage;
1985	#else
1986	RTRCPTR pvPage;
1987	# if HC_ARCH_BITS == 64
1988	uint32_t u32Alignment2;
1989	# endif
1990	#endif
1991	/** The mapping cache index. */
1992	uint16_t iPage;
1993	/** The number of references.
1994	* The max is UINT16_MAX - 1. */
1995	uint16_t cRefs;
1996	/** The number inlined references.
1997	* The max is UINT16_MAX - 1. */
1998	uint16_t cInlinedRefs;
1999	/** Unreferences. */
2000	uint16_t cUnrefs;
2001
2002	#if HC_ARCH_BITS == 32
2003	uint32_t u32Alignment1;
2004	#endif
2005	/** The physical address for this entry. */
2006	RTHCPHYS HCPhys;
2007	} PGMMAPSETENTRY;
2008	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2009	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2010	/** Pointer to a mapping cache usage set entry. */
2011	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2012
2013	/**
2014	* Mapping cache usage set.
2015	*
2016	* This is used in ring-0 and the raw-mode context to track dynamic mappings
2017	* done during exits / traps. The set is
2018	*/
2019	typedef struct PGMMAPSET
2020	{
2021	/** The number of occupied entries.
2022	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2023	* dynamic mappings. */
2024	uint32_t cEntries;
2025	/** The start of the current subset.
2026	* This is UINT32_MAX if no subset is currently open. */
2027	uint32_t iSubset;
2028	/** The index of the current CPU, only valid if the set is open. */
2029	int32_t iCpu;
2030	uint32_t alignment;
2031	/** The entries. */
2032	PGMMAPSETENTRY aEntries[64];
2033	/** HCPhys -> iEntry fast lookup table.
2034	* Use PGMMAPSET_HASH for hashing.
2035	* The entries may or may not be valid, check against cEntries. */
2036	uint8_t aiHashTable[128];
2037	} PGMMAPSET;
2038	AssertCompileSizeAlignment(PGMMAPSET, 8);
2039	/** Pointer to the mapping cache set. */
2040	typedef PGMMAPSET *PPGMMAPSET;
2041
2042	/** PGMMAPSET::cEntries value for a closed set. */
2043	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2044
2045	/** Hash function for aiHashTable. */
2046	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2047
2048
2049	/** @name Context neutral page mapper TLB.
2050	*
2051	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2052	* code is writting in a kind of context neutral way. Time will show whether
2053	* this actually makes sense or not...
2054	*
2055	* @todo this needs to be reconsidered and dropped/redone since the ring-0
2056	* context ends up using a global mapping cache on some platforms
2057	* (darwin).
2058	*
2059	* @{ */
2060	/** @typedef PPGMPAGEMAPTLB
2061	* The page mapper TLB pointer type for the current context. */
2062	/** @typedef PPGMPAGEMAPTLB
2063	* The page mapper TLB entry pointer type for the current context. */
2064	/** @typedef PPGMPAGEMAPTLB
2065	* The page mapper TLB entry pointer pointer type for the current context. */
2066	/** @def PGM_PAGEMAPTLB_ENTRIES
2067	* The number of TLB entries in the page mapper TLB for the current context. */
2068	/** @def PGM_PAGEMAPTLB_IDX
2069	* Calculate the TLB index for a guest physical address.
2070	* @returns The TLB index.
2071	* @param GCPhys The guest physical address. */
2072	/** @typedef PPGMPAGEMAP
2073	* Pointer to a page mapper unit for current context. */
2074	/** @typedef PPPGMPAGEMAP
2075	* Pointer to a page mapper unit pointer for current context. */
2076	#ifdef IN_RC
2077	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2078	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2079	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2080	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2081	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2082	typedef void * PPGMPAGEMAP;
2083	typedef void ** PPPGMPAGEMAP;
2084	//#elif IN_RING0
2085	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2086	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2087	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2088	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2089	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2090	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2091	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2092	#else
2093	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2094	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2095	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2096	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2097	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2098	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2099	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2100	#endif
2101	/** @} */
2102
2103
2104	/** @name PGM Pool Indexes.
2105	* Aka. the unique shadow page identifier.
2106	* @{ */
2107	/** NIL page pool IDX. */
2108	#define NIL_PGMPOOL_IDX 0
2109	/** The first normal index. There used to be 5 fictive pages up front, now
2110	* there is only the NIL page. */
2111	#define PGMPOOL_IDX_FIRST 1
2112	/** The last valid index. (inclusive, 14 bits) */
2113	#define PGMPOOL_IDX_LAST 0x3fff
2114	/** @} */
2115
2116	/** The NIL index for the parent chain. */
2117	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2118	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2119
2120	/**
2121	* Node in the chain linking a shadowed page to it's parent (user).
2122	*/
2123	#pragma pack(1)
2124	typedef struct PGMPOOLUSER
2125	{
2126	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2127	uint16_t iNext;
2128	/** The user page index. */
2129	uint16_t iUser;
2130	/** Index into the user table. */
2131	uint32_t iUserTable;
2132	} PGMPOOLUSER, *PPGMPOOLUSER;
2133	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2134	#pragma pack()
2135
2136
2137	/** The NIL index for the phys ext chain. */
2138	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2139	/** The NIL pte index for a phys ext chain slot. */
2140	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2141
2142	/**
2143	* Node in the chain of physical cross reference extents.
2144	* @todo Calling this an 'extent' is not quite right, find a better name.
2145	* @todo find out the optimal size of the aidx array
2146	*/
2147	#pragma pack(1)
2148	typedef struct PGMPOOLPHYSEXT
2149	{
2150	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2151	uint16_t iNext;
2152	/** Alignment. */
2153	uint16_t u16Align;
2154	/** The user page index. */
2155	uint16_t aidx[3];
2156	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2157	uint16_t apte[3];
2158	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2159	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2160	#pragma pack()
2161
2162
2163	/**
2164	* The kind of page that's being shadowed.
2165	*/
2166	typedef enum PGMPOOLKIND
2167	{
2168	/** The virtual invalid 0 entry. */
2169	PGMPOOLKIND_INVALID = 0,
2170	/** The entry is free (=unused). */
2171	PGMPOOLKIND_FREE,
2172
2173	/** Shw: 32-bit page table; Gst: no paging. */
2174	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2175	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2176	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2177	/** Shw: 32-bit page table; Gst: 4MB page. */
2178	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2179	/** Shw: PAE page table; Gst: no paging. */
2180	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2181	/** Shw: PAE page table; Gst: 32-bit page table. */
2182	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2183	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2184	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2185	/** Shw: PAE page table; Gst: PAE page table. */
2186	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2187	/** Shw: PAE page table; Gst: 2MB page. */
2188	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2189
2190	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2191	PGMPOOLKIND_32BIT_PD,
2192	/** Shw: 32-bit page directory. Gst: no paging. */
2193	PGMPOOLKIND_32BIT_PD_PHYS,
2194	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2195	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2196	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2197	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2198	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2199	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2200	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2201	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2202	/** Shw: PAE page directory; Gst: PAE page directory. */
2203	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2204	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2205	PGMPOOLKIND_PAE_PD_PHYS,
2206
2207	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2208	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2209	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2210	PGMPOOLKIND_PAE_PDPT,
2211	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2212	PGMPOOLKIND_PAE_PDPT_PHYS,
2213
2214	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2215	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2216	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2217	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2218	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2219	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2220	/** Shw: 64-bit page directory table; Gst: no paging. */
2221	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2222
2223	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2224	PGMPOOLKIND_64BIT_PML4,
2225
2226	/** Shw: EPT page directory pointer table; Gst: no paging. */
2227	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2228	/** Shw: EPT page directory table; Gst: no paging. */
2229	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2230	/** Shw: EPT page table; Gst: no paging. */
2231	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2232
2233	/** Shw: Root Nested paging table. */
2234	PGMPOOLKIND_ROOT_NESTED,
2235
2236	/** The last valid entry. */
2237	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2238	} PGMPOOLKIND;
2239
2240	/**
2241	* The access attributes of the page; only applies to big pages.
2242	*/
2243	typedef enum
2244	{
2245	PGMPOOLACCESS_DONTCARE = 0,
2246	PGMPOOLACCESS_USER_RW,
2247	PGMPOOLACCESS_USER_R,
2248	PGMPOOLACCESS_USER_RW_NX,
2249	PGMPOOLACCESS_USER_R_NX,
2250	PGMPOOLACCESS_SUPERVISOR_RW,
2251	PGMPOOLACCESS_SUPERVISOR_R,
2252	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2253	PGMPOOLACCESS_SUPERVISOR_R_NX
2254	} PGMPOOLACCESS;
2255
2256	/**
2257	* The tracking data for a page in the pool.
2258	*/
2259	typedef struct PGMPOOLPAGE
2260	{
2261	/** AVL node code with the (HC) physical address of this page. */
2262	AVLOHCPHYSNODECORE Core;
2263	/** Pointer to the R3 mapping of the page. */
2264	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2265	R3PTRTYPE(void *) pvPageR3;
2266	#else
2267	R3R0PTRTYPE(void *) pvPageR3;
2268	#endif
2269	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2270	uint32_t Alignment0;
2271	#endif
2272	/** The guest physical address. */
2273	RTGCPHYS GCPhys;
2274	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2275	uint8_t enmKind;
2276	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2277	uint8_t enmAccess;
2278	/** This supplements enmKind and enmAccess */
2279	bool fA20Enabled : 1;
2280
2281	/** Used to indicate that the page is zeroed. */
2282	bool fZeroed : 1;
2283	/** Used to indicate that a PT has non-global entries. */
2284	bool fSeenNonGlobal : 1;
2285	/** Used to indicate that we're monitoring writes to the guest page. */
2286	bool fMonitored : 1;
2287	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2288	* (All pages are in the age list.) */
2289	bool fCached : 1;
2290	/** This is used by the R3 access handlers when invoked by an async thread.
2291	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2292	bool volatile fReusedFlushPending : 1;
2293	/** Used to mark the page as dirty (write monitoring is temporarily
2294	* off). */
2295	bool fDirty : 1;
2296	bool fPadding1 : 1;
2297	bool fPadding2;
2298
2299	/** The index of this page. */
2300	uint16_t idx;
2301	/** The next entry in the list this page currently resides in.
2302	* It's either in the free list or in the GCPhys hash. */
2303	uint16_t iNext;
2304	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2305	uint16_t iUserHead;
2306	/** The number of present entries. */
2307	uint16_t cPresent;
2308	/** The first entry in the table which is present. */
2309	uint16_t iFirstPresent;
2310	/** The number of modifications to the monitored page. */
2311	uint16_t cModifications;
2312	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2313	uint16_t iModifiedNext;
2314	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2315	uint16_t iModifiedPrev;
2316	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2317	uint16_t iMonitoredNext;
2318	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2319	uint16_t iMonitoredPrev;
2320	/** The next page in the age list. */
2321	uint16_t iAgeNext;
2322	/** The previous page in the age list. */
2323	uint16_t iAgePrev;
2324	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2325	uint8_t idxDirtyEntry;
2326
2327	/** @name Access handler statistics to determine whether the guest is
2328	* (re)initializing a page table.
2329	* @{ */
2330	RTGCPTR GCPtrLastAccessHandlerRip;
2331	RTGCPTR GCPtrLastAccessHandlerFault;
2332	uint64_t cLastAccessHandler;
2333	/** @} */
2334	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2335	uint32_t volatile cLocked;
2336	#if GC_ARCH_BITS == 64
2337	uint32_t u32Alignment3;
2338	#endif
2339	# ifdef VBOX_STRICT
2340	RTGCPTR GCPtrDirtyFault;
2341	# endif
2342	} PGMPOOLPAGE;
2343	/** Pointer to a pool page. */
2344	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2345	/** Pointer to a const pool page. */
2346	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2347	/** Pointer to a pool page pointer. */
2348	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2349
2350
2351	/** The hash table size. */
2352	# define PGMPOOL_HASH_SIZE 0x40
2353	/** The hash function. */
2354	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2355
2356
2357	/**
2358	* The shadow page pool instance data.
2359	*
2360	* It's all one big allocation made at init time, except for the
2361	* pages that is. The user nodes follows immediately after the
2362	* page structures.
2363	*/
2364	typedef struct PGMPOOL
2365	{
2366	/** The VM handle - R3 Ptr. */
2367	PVMR3 pVMR3;
2368	/** The VM handle - R0 Ptr. */
2369	PVMR0 pVMR0;
2370	/** The VM handle - RC Ptr. */
2371	PVMRC pVMRC;
2372	/** The max pool size. This includes the special IDs. */
2373	uint16_t cMaxPages;
2374	/** The current pool size. */
2375	uint16_t cCurPages;
2376	/** The head of the free page list. */
2377	uint16_t iFreeHead;
2378	/* Padding. */
2379	uint16_t u16Padding;
2380	/** Head of the chain of free user nodes. */
2381	uint16_t iUserFreeHead;
2382	/** The number of user nodes we've allocated. */
2383	uint16_t cMaxUsers;
2384	/** The number of present page table entries in the entire pool. */
2385	uint32_t cPresent;
2386	/** Pointer to the array of user nodes - RC pointer. */
2387	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2388	/** Pointer to the array of user nodes - R3 pointer. */
2389	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2390	/** Pointer to the array of user nodes - R0 pointer. */
2391	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2392	/** Head of the chain of free phys ext nodes. */
2393	uint16_t iPhysExtFreeHead;
2394	/** The number of user nodes we've allocated. */
2395	uint16_t cMaxPhysExts;
2396	/** Pointer to the array of physical xref extent - RC pointer. */
2397	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2398	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2399	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2400	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2401	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2402	/** Hash table for GCPhys addresses. */
2403	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2404	/** The head of the age list. */
2405	uint16_t iAgeHead;
2406	/** The tail of the age list. */
2407	uint16_t iAgeTail;
2408	/** Set if the cache is enabled. */
2409	bool fCacheEnabled;
2410	/** Alignment padding. */
2411	bool afPadding1[3];
2412	/** Head of the list of modified pages. */
2413	uint16_t iModifiedHead;
2414	/** The current number of modified pages. */
2415	uint16_t cModifiedPages;
2416	/** Physical access handler type registration handle. */
2417	PGMPHYSHANDLERTYPE hAccessHandlerType;
2418	/** Next available slot (in aDirtyPages). */
2419	uint32_t idxFreeDirtyPage;
2420	/** Number of active dirty pages. */
2421	uint32_t cDirtyPages;
2422	/** Array of current dirty pgm pool page indices. */
2423	struct
2424	{
2425	uint16_t uIdx;
2426	uint16_t Alignment[3];
2427	uint64_t aPage[512];
2428	} aDirtyPages[16];
2429	/** The number of pages currently in use. */
2430	uint16_t cUsedPages;
2431	#ifdef VBOX_WITH_STATISTICS
2432	/** The high water mark for cUsedPages. */
2433	uint16_t cUsedPagesHigh;
2434	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2435	/** Profiling pgmPoolAlloc(). */
2436	STAMPROFILEADV StatAlloc;
2437	/** Profiling pgmR3PoolClearDoIt(). */
2438	STAMPROFILE StatClearAll;
2439	/** Profiling pgmR3PoolReset(). */
2440	STAMPROFILE StatR3Reset;
2441	/** Profiling pgmPoolFlushPage(). */
2442	STAMPROFILE StatFlushPage;
2443	/** Profiling pgmPoolFree(). */
2444	STAMPROFILE StatFree;
2445	/** Counting explicit flushes by PGMPoolFlushPage(). */
2446	STAMCOUNTER StatForceFlushPage;
2447	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2448	STAMCOUNTER StatForceFlushDirtyPage;
2449	/** Counting flushes for reused pages. */
2450	STAMCOUNTER StatForceFlushReused;
2451	/** Profiling time spent zeroing pages. */
2452	STAMPROFILE StatZeroPage;
2453	/** Profiling of pgmPoolTrackDeref. */
2454	STAMPROFILE StatTrackDeref;
2455	/** Profiling pgmTrackFlushGCPhysPT. */
2456	STAMPROFILE StatTrackFlushGCPhysPT;
2457	/** Profiling pgmTrackFlushGCPhysPTs. */
2458	STAMPROFILE StatTrackFlushGCPhysPTs;
2459	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2460	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2461	/** Number of times we've been out of user records. */
2462	STAMCOUNTER StatTrackFreeUpOneUser;
2463	/** Nr of flushed entries. */
2464	STAMCOUNTER StatTrackFlushEntry;
2465	/** Nr of updated entries. */
2466	STAMCOUNTER StatTrackFlushEntryKeep;
2467	/** Profiling deref activity related tracking GC physical pages. */
2468	STAMPROFILE StatTrackDerefGCPhys;
2469	/** Number of linear searches for a HCPhys in the ram ranges. */
2470	STAMCOUNTER StatTrackLinearRamSearches;
2471	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2472	STAMCOUNTER StamTrackPhysExtAllocFailures;
2473	/** Profiling the RC/R0 access handler. */
2474	STAMPROFILE StatMonitorRZ;
2475	/** Times we've failed interpreting the instruction. */
2476	STAMCOUNTER StatMonitorRZEmulateInstr;
2477	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2478	STAMPROFILE StatMonitorRZFlushPage;
2479	/* Times we've detected a page table reinit. */
2480	STAMCOUNTER StatMonitorRZFlushReinit;
2481	/** Counting flushes for pages that are modified too often. */
2482	STAMCOUNTER StatMonitorRZFlushModOverflow;
2483	/** Times we've detected fork(). */
2484	STAMCOUNTER StatMonitorRZFork;
2485	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2486	STAMPROFILE StatMonitorRZHandled;
2487	/** Times we've failed interpreting a patch code instruction. */
2488	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2489	/** Times we've failed interpreting a patch code instruction during flushing. */
2490	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2491	/** The number of times we've seen rep prefixes we can't handle. */
2492	STAMCOUNTER StatMonitorRZRepPrefix;
2493	/** Profiling the REP STOSD cases we've handled. */
2494	STAMPROFILE StatMonitorRZRepStosd;
2495	/** Nr of handled PT faults. */
2496	STAMCOUNTER StatMonitorRZFaultPT;
2497	/** Nr of handled PD faults. */
2498	STAMCOUNTER StatMonitorRZFaultPD;
2499	/** Nr of handled PDPT faults. */
2500	STAMCOUNTER StatMonitorRZFaultPDPT;
2501	/** Nr of handled PML4 faults. */
2502	STAMCOUNTER StatMonitorRZFaultPML4;
2503
2504	/** Profiling the R3 access handler. */
2505	STAMPROFILE StatMonitorR3;
2506	/** Times we've failed interpreting the instruction. */
2507	STAMCOUNTER StatMonitorR3EmulateInstr;
2508	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2509	STAMPROFILE StatMonitorR3FlushPage;
2510	/* Times we've detected a page table reinit. */
2511	STAMCOUNTER StatMonitorR3FlushReinit;
2512	/** Counting flushes for pages that are modified too often. */
2513	STAMCOUNTER StatMonitorR3FlushModOverflow;
2514	/** Times we've detected fork(). */
2515	STAMCOUNTER StatMonitorR3Fork;
2516	/** Profiling the R3 access we've handled (except REP STOSD). */
2517	STAMPROFILE StatMonitorR3Handled;
2518	/** The number of times we've seen rep prefixes we can't handle. */
2519	STAMCOUNTER StatMonitorR3RepPrefix;
2520	/** Profiling the REP STOSD cases we've handled. */
2521	STAMPROFILE StatMonitorR3RepStosd;
2522	/** Nr of handled PT faults. */
2523	STAMCOUNTER StatMonitorR3FaultPT;
2524	/** Nr of handled PD faults. */
2525	STAMCOUNTER StatMonitorR3FaultPD;
2526	/** Nr of handled PDPT faults. */
2527	STAMCOUNTER StatMonitorR3FaultPDPT;
2528	/** Nr of handled PML4 faults. */
2529	STAMCOUNTER StatMonitorR3FaultPML4;
2530	/** The number of times we're called in an async thread an need to flush. */
2531	STAMCOUNTER StatMonitorR3Async;
2532	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2533	STAMCOUNTER StatResetDirtyPages;
2534	/** Times we've called pgmPoolAddDirtyPage. */
2535	STAMCOUNTER StatDirtyPage;
2536	/** Times we've had to flush duplicates for dirty page management. */
2537	STAMCOUNTER StatDirtyPageDupFlush;
2538	/** Times we've had to flush because of overflow. */
2539	STAMCOUNTER StatDirtyPageOverFlowFlush;
2540
2541	/** The high water mark for cModifiedPages. */
2542	uint16_t cModifiedPagesHigh;
2543	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2544
2545	/** The number of cache hits. */
2546	STAMCOUNTER StatCacheHits;
2547	/** The number of cache misses. */
2548	STAMCOUNTER StatCacheMisses;
2549	/** The number of times we've got a conflict of 'kind' in the cache. */
2550	STAMCOUNTER StatCacheKindMismatches;
2551	/** Number of times we've been out of pages. */
2552	STAMCOUNTER StatCacheFreeUpOne;
2553	/** The number of cacheable allocations. */
2554	STAMCOUNTER StatCacheCacheable;
2555	/** The number of uncacheable allocations. */
2556	STAMCOUNTER StatCacheUncacheable;
2557	#else
2558	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2559	#endif
2560	/** The AVL tree for looking up a page by its HC physical address. */
2561	AVLOHCPHYSTREE HCPhysTree;
2562	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2563	/** Array of pages. (cMaxPages in length)
2564	* The Id is the index into thist array.
2565	*/
2566	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2567	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2568	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2569	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2570	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2571	#ifdef VBOX_WITH_STATISTICS
2572	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2573	#endif
2574	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2575
2576
2577	/** @def PGMPOOL_PAGE_2_PTR
2578	* Maps a pool page pool into the current context.
2579	*
2580	* @returns VBox status code.
2581	* @param a_pVM Pointer to the VM.
2582	* @param a_pPage The pool page.
2583	*
2584	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2585	* small page window employeed by that function. Be careful.
2586	* @remark There is no need to assert on the result.
2587	*/
2588	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2589	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2590	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2591	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2592	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2593	{
2594	AssertPtr(a_pPage);
2595	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2596	return a_pPage->pvPageR3;
2597	}
2598	#else
2599	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2600	#endif
2601
2602
2603	/** @def PGMPOOL_PAGE_2_PTR_V2
2604	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2605	*
2606	* @returns VBox status code.
2607	* @param a_pVM Pointer to the VM.
2608	* @param a_pVCpu The current CPU.
2609	* @param a_pPage The pool page.
2610	*
2611	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2612	* small page window employeed by that function. Be careful.
2613	* @remark There is no need to assert on the result.
2614	*/
2615	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2616	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2617	#else
2618	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2619	#endif
2620
2621
2622	/** @name Per guest page tracking data.
2623	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2624	* is to use more bits for it and split it up later on. But for now we'll play
2625	* safe and change as little as possible.
2626	*
2627	* The 16-bit word has two parts:
2628	*
2629	* The first 14-bit forms the @a idx field. It is either the index of a page in
2630	* the shadow page pool, or and index into the extent list.
2631	*
2632	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2633	* shadow page pool references to the page. If cRefs equals
2634	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2635	* (misnomer) table and not the shadow page pool.
2636	*
2637	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2638	* the 16-bit word.
2639	*
2640	* @{ */
2641	/** The shift count for getting to the cRefs part. */
2642	#define PGMPOOL_TD_CREFS_SHIFT 14
2643	/** The mask applied after shifting the tracking data down by
2644	* PGMPOOL_TD_CREFS_SHIFT. */
2645	#define PGMPOOL_TD_CREFS_MASK 0x3
2646	/** The cRefs value used to indicate that the idx is the head of a
2647	* physical cross reference list. */
2648	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2649	/** The shift used to get idx. */
2650	#define PGMPOOL_TD_IDX_SHIFT 0
2651	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2652	#define PGMPOOL_TD_IDX_MASK 0x3fff
2653	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2654	* simply too many mappings of this page. */
2655	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2656
2657	/** @def PGMPOOL_TD_MAKE
2658	* Makes a 16-bit tracking data word.
2659	*
2660	* @returns tracking data.
2661	* @param cRefs The @a cRefs field. Must be within bounds!
2662	* @param idx The @a idx field. Must also be within bounds! */
2663	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2664
2665	/** @def PGMPOOL_TD_GET_CREFS
2666	* Get the @a cRefs field from a tracking data word.
2667	*
2668	* @returns The @a cRefs field
2669	* @param u16 The tracking data word.
2670	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2671	* non-zero @a u16. */
2672	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2673
2674	/** @def PGMPOOL_TD_GET_IDX
2675	* Get the @a idx field from a tracking data word.
2676	*
2677	* @returns The @a idx field
2678	* @param u16 The tracking data word. */
2679	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2680	/** @} */
2681
2682
2683
2684	/** @name A20 gate macros
2685	* @{ */
2686	#define PGM_WITH_A20
2687	#ifdef PGM_WITH_A20
2688	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2689	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2690	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2691	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2692	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2693	#else
2694	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2695	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2696	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2697	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2698	#endif
2699	/** @} */
2700
2701
2702	/**
2703	* Roots and anchors for trees and list employing self relative offsets as
2704	* pointers.
2705	*
2706	* When using self-relative offsets instead of pointers, the offsets needs to be
2707	* the same in all offsets. Thus the roots and anchors needs to live on the
2708	* hyper heap just like the nodes.
2709	*/
2710	typedef struct PGMTREES
2711	{
2712	/** Physical access handlers (AVL range+offsetptr tree). */
2713	AVLROGCPHYSTREE PhysHandlers;
2714	/** Virtual access handlers (AVL range + GC ptr tree). */
2715	AVLROGCPTRTREE VirtHandlers;
2716	/** Virtual access handlers (Phys range AVL range + offsetptr tree).
2717	* @remarks Handler of the hypervisor kind are of course not present. */
2718	AVLROGCPHYSTREE PhysToVirtHandlers;
2719	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2720	AVLROGCPTRTREE HyperVirtHandlers;
2721	/** List of physical access handler types (offset pointers) of type
2722	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2723	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2724	/** List of virtual access handler types (offset pointers) of type
2725	* PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2726	RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2727	} PGMTREES;
2728	/** Pointer to PGM trees. */
2729	typedef PGMTREES *PPGMTREES;
2730
2731
2732	/**
2733	* Page fault guest state for the AMD64 paging mode.
2734	*/
2735	typedef struct PGMPTWALKCORE
2736	{
2737	/** The guest virtual address that is being resolved by the walk
2738	* (input). */
2739	RTGCPTR GCPtr;
2740
2741	/** The guest physical address that is the result of the walk.
2742	* @remarks only valid if fSucceeded is set. */
2743	RTGCPHYS GCPhys;
2744
2745	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2746	bool fSucceeded;
2747	/** The level problem arrised at.
2748	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2749	* level 8. This is 0 on success. */
2750	uint8_t uLevel;
2751	/** Set if the page isn't present. */
2752	bool fNotPresent;
2753	/** Encountered a bad physical address. */
2754	bool fBadPhysAddr;
2755	/** Set if there was reserved bit violations. */
2756	bool fRsvdError;
2757	/** Set if it involves a big page (2/4 MB). */
2758	bool fBigPage;
2759	/** Set if it involves a gigantic page (1 GB). */
2760	bool fGigantPage;
2761	/** The effect X86_PTE_US flag for the address. */
2762	bool fEffectiveUS;
2763	/** The effect X86_PTE_RW flag for the address. */
2764	bool fEffectiveRW;
2765	/** The effect X86_PTE_NX flag for the address. */
2766	bool fEffectiveNX;
2767	} PGMPTWALKCORE;
2768
2769
2770	/**
2771	* Guest page table walk for the AMD64 mode.
2772	*/
2773	typedef struct PGMPTWALKGSTAMD64
2774	{
2775	/** The common core. */
2776	PGMPTWALKCORE Core;
2777
2778	PX86PML4 pPml4;
2779	PX86PML4E pPml4e;
2780	X86PML4E Pml4e;
2781
2782	PX86PDPT pPdpt;
2783	PX86PDPE pPdpe;
2784	X86PDPE Pdpe;
2785
2786	PX86PDPAE pPd;
2787	PX86PDEPAE pPde;
2788	X86PDEPAE Pde;
2789
2790	PX86PTPAE pPt;
2791	PX86PTEPAE pPte;
2792	X86PTEPAE Pte;
2793	} PGMPTWALKGSTAMD64;
2794	/** Pointer to a AMD64 guest page table walk. */
2795	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2796	/** Pointer to a const AMD64 guest page table walk. */
2797	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2798
2799	/**
2800	* Guest page table walk for the PAE mode.
2801	*/
2802	typedef struct PGMPTWALKGSTPAE
2803	{
2804	/** The common core. */
2805	PGMPTWALKCORE Core;
2806
2807	PX86PDPT pPdpt;
2808	PX86PDPE pPdpe;
2809	X86PDPE Pdpe;
2810
2811	PX86PDPAE pPd;
2812	PX86PDEPAE pPde;
2813	X86PDEPAE Pde;
2814
2815	PX86PTPAE pPt;
2816	PX86PTEPAE pPte;
2817	X86PTEPAE Pte;
2818	} PGMPTWALKGSTPAE;
2819	/** Pointer to a PAE guest page table walk. */
2820	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2821	/** Pointer to a const AMD64 guest page table walk. */
2822	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2823
2824	/**
2825	* Guest page table walk for the 32-bit mode.
2826	*/
2827	typedef struct PGMPTWALKGST32BIT
2828	{
2829	/** The common core. */
2830	PGMPTWALKCORE Core;
2831
2832	PX86PD pPd;
2833	PX86PDE pPde;
2834	X86PDE Pde;
2835
2836	PX86PT pPt;
2837	PX86PTE pPte;
2838	X86PTE Pte;
2839	} PGMPTWALKGST32BIT;
2840	/** Pointer to a 32-bit guest page table walk. */
2841	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2842	/** Pointer to a const 32-bit guest page table walk. */
2843	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2844
2845	/**
2846	* Which part of PGMPTWALKGST that is valid.
2847	*/
2848	typedef enum PGMPTWALKGSTTYPE
2849	{
2850	/** Customary invalid 0 value. */
2851	PGMPTWALKGSTTYPE_INVALID = 0,
2852	/** PGMPTWALKGST::u.Amd64 is valid. */
2853	PGMPTWALKGSTTYPE_AMD64,
2854	/** PGMPTWALKGST::u.Pae is valid. */
2855	PGMPTWALKGSTTYPE_PAE,
2856	/** PGMPTWALKGST::u.Legacy is valid. */
2857	PGMPTWALKGSTTYPE_32BIT,
2858	/** Customary 32-bit type hack. */
2859	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2860	} PGMPTWALKGSTTYPE;
2861
2862	/**
2863	* Combined guest page table walk result.
2864	*/
2865	typedef struct PGMPTWALKGST
2866	{
2867	union
2868	{
2869	/** The page walker core - always valid. */
2870	PGMPTWALKCORE Core;
2871	/** The page walker for AMD64. */
2872	PGMPTWALKGSTAMD64 Amd64;
2873	/** The page walker for PAE (32-bit). */
2874	PGMPTWALKGSTPAE Pae;
2875	/** The page walker for 32-bit paging (called legacy due to C naming
2876	* convension). */
2877	PGMPTWALKGST32BIT Legacy;
2878	} u;
2879	/** Indicates which part of the union is valid. */
2880	PGMPTWALKGSTTYPE enmType;
2881	} PGMPTWALKGST;
2882	/** Pointer to a combined guest page table walk result. */
2883	typedef PGMPTWALKGST *PPGMPTWALKGST;
2884	/** Pointer to a read-only combined guest page table walk result. */
2885	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2886
2887
2888	/** @name Paging mode macros
2889	* @{
2890	*/
2891	#ifdef IN_RC
2892	# define PGM_CTX(a,b) a##RC##b
2893	# define PGM_CTX_STR(a,b) a "GC" b
2894	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2895	#else
2896	# ifdef IN_RING3
2897	# define PGM_CTX(a,b) a##R3##b
2898	# define PGM_CTX_STR(a,b) a "R3" b
2899	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2900	# else
2901	# define PGM_CTX(a,b) a##R0##b
2902	# define PGM_CTX_STR(a,b) a "R0" b
2903	# define PGM_CTX_DECL(type) VMMDECL(type)
2904	# endif
2905	#endif
2906
2907	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2908	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2909	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2910	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2911	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2912	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2913	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2914	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2915	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2916	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2917	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2918	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2919	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2920	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2921	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2922	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2923	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2924
2925	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2926	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2927	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2928	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2929	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2930	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2931	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2932	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2933	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2934	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2935	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2936	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2937	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2938	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2939	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2940	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2941	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2942
2943	/* Shw_Gst */
2944	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2945	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2946	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2947	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2948	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2949	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2950	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2951	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2952	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2953	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2954	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2955	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2956	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2957	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2958	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2959	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2960	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2961	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2962	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2963
2964	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2965	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2966	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2967	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2968	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2969	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2970	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2971	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2972	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2973	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2974	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2975	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2976	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2977	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2978	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2979	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2980	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2981	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2982	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2983	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2984	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2985	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2986	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2987	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2988	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2989	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2990	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2991	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2992	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2993	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2994	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2995	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2996	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2997	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2998	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2999	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3000	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3001
3002	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3003	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
3004	/** @} */
3005
3006	/**
3007	* Data for each paging mode.
3008	*/
3009	typedef struct PGMMODEDATA
3010	{
3011	/** The guest mode type. */
3012	uint32_t uGstType;
3013	/** The shadow mode type. */
3014	uint32_t uShwType;
3015
3016	/** @name Function pointers for Shadow paging.
3017	* @{
3018	*/
3019	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3020	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3021	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3022	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3023
3024	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3025	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3026
3027	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3028	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3029	/** @} */
3030
3031	/** @name Function pointers for Guest paging.
3032	* @{
3033	*/
3034	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3035	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3036	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3037	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3038	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3039	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3040	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3041	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3042	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3043	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3044	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3045	/** @} */
3046
3047	/** @name Function pointers for Both Shadow and Guest paging.
3048	* @{
3049	*/
3050	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3051	/* no pfnR3BthTrap0eHandler */
3052	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3053	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3054	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3055	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3056	#ifdef VBOX_STRICT
3057	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3058	#endif
3059	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3060	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3061
3062	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3063	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3064	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3065	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3066	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3067	#ifdef VBOX_STRICT
3068	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3069	#endif
3070	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3071	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3072
3073	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3074	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3075	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3076	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3077	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3078	#ifdef VBOX_STRICT
3079	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3080	#endif
3081	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3082	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3083	/** @} */
3084	} PGMMODEDATA, *PPGMMODEDATA;
3085
3086
3087	#ifdef VBOX_WITH_STATISTICS
3088	/**
3089	* PGM statistics.
3090	*
3091	* These lives on the heap when compiled in as they would otherwise waste
3092	* unnecessary space in release builds.
3093	*/
3094	typedef struct PGMSTATS
3095	{
3096	/* R3 only: */
3097	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
3098	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
3099
3100	/* R3+RZ */
3101	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3102	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3103	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3104	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3105	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3106	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3107	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3108	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3109	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3110	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3111	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3112	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3113	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3114	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3115	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
3116	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
3117	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
3118	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
3119	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3120	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3121	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3122	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3123	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3124	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3125	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3126	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3127	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3128	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3129	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3130	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3131	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3132	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3133
3134	/* RC only: */
3135	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3136	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3137
3138	STAMCOUNTER StatRZPhysRead;
3139	STAMCOUNTER StatRZPhysReadBytes;
3140	STAMCOUNTER StatRZPhysWrite;
3141	STAMCOUNTER StatRZPhysWriteBytes;
3142	STAMCOUNTER StatR3PhysRead;
3143	STAMCOUNTER StatR3PhysReadBytes;
3144	STAMCOUNTER StatR3PhysWrite;
3145	STAMCOUNTER StatR3PhysWriteBytes;
3146	STAMCOUNTER StatRCPhysRead;
3147	STAMCOUNTER StatRCPhysReadBytes;
3148	STAMCOUNTER StatRCPhysWrite;
3149	STAMCOUNTER StatRCPhysWriteBytes;
3150
3151	STAMCOUNTER StatRZPhysSimpleRead;
3152	STAMCOUNTER StatRZPhysSimpleReadBytes;
3153	STAMCOUNTER StatRZPhysSimpleWrite;
3154	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3155	STAMCOUNTER StatR3PhysSimpleRead;
3156	STAMCOUNTER StatR3PhysSimpleReadBytes;
3157	STAMCOUNTER StatR3PhysSimpleWrite;
3158	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3159	STAMCOUNTER StatRCPhysSimpleRead;
3160	STAMCOUNTER StatRCPhysSimpleReadBytes;
3161	STAMCOUNTER StatRCPhysSimpleWrite;
3162	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3163
3164	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3165	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3166	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3167	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3168	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3169	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3170	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3171
3172	/** Time spent by the host OS for large page allocation. */
3173	STAMPROFILE StatAllocLargePage;
3174	/** Time spent clearing the newly allocated large pages. */
3175	STAMPROFILE StatClearLargePage;
3176	/** The number of times allocating a large pages takes more than the allowed period. */
3177	STAMCOUNTER StatLargePageOverflow;
3178	/** pgmPhysIsValidLargePage profiling - R3 */
3179	STAMPROFILE StatR3IsValidLargePage;
3180	/** pgmPhysIsValidLargePage profiling - RZ*/
3181	STAMPROFILE StatRZIsValidLargePage;
3182
3183	STAMPROFILE StatChunkAging;
3184	STAMPROFILE StatChunkFindCandidate;
3185	STAMPROFILE StatChunkUnmap;
3186	STAMPROFILE StatChunkMap;
3187	} PGMSTATS;
3188	#endif /* VBOX_WITH_STATISTICS */
3189
3190
3191	/**
3192	* Converts a PGM pointer into a VM pointer.
3193	* @returns Pointer to the VM structure the PGM is part of.
3194	* @param pPGM Pointer to PGM instance data.
3195	*/
3196	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3197
3198	/**
3199	* PGM Data (part of VM)
3200	*/
3201	typedef struct PGM
3202	{
3203	/** Offset to the VM structure. */
3204	int32_t offVM;
3205	/** Offset of the PGMCPU structure relative to VMCPU. */
3206	int32_t offVCpuPGM;
3207
3208	/** @cfgm{/RamPreAlloc, boolean, false}
3209	* Indicates whether the base RAM should all be allocated before starting
3210	* the VM (default), or if it should be allocated when first written to.
3211	*/
3212	bool fRamPreAlloc;
3213	/** Indicates whether write monitoring is currently in use.
3214	* This is used to prevent conflicts between live saving and page sharing
3215	* detection. */
3216	bool fPhysWriteMonitoringEngaged;
3217	/** Set if the CPU has less than 52-bit physical address width.
3218	* This is used */
3219	bool fLessThan52PhysicalAddressBits;
3220	/** Set when nested paging is active.
3221	* This is meant to save calls to HMIsNestedPagingActive and let the
3222	* compilers optimize the code better. Whether we use nested paging or
3223	* not is something we find out during VMM initialization and we won't
3224	* change this later on. */
3225	bool fNestedPaging;
3226	/** The host paging mode. (This is what SUPLib reports.) */
3227	SUPPAGINGMODE enmHostMode;
3228	/** We're not in a state which permits writes to guest memory.
3229	* (Only used in strict builds.) */
3230	bool fNoMorePhysWrites;
3231	/** @cfgm{/PageFusionAllowed, boolean, false}
3232	* Whether page fusion is allowed. */
3233	bool fPageFusionAllowed;
3234	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3235	* Whether PCI passthrough is enabled. */
3236	bool fPciPassthrough;
3237	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3238	uint8_t cMmio2Regions;
3239	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3240	bool afAlignment1[1];
3241
3242	/** Indicates that PGMR3FinalizeMappings has been called and that further
3243	* PGMR3MapIntermediate calls will be rejected. */
3244	bool fFinalizedMappings;
3245	/** If set no conflict checks are required. */
3246	bool fMappingsFixed;
3247	/** If set if restored as fixed but we were unable to re-fixate at the old
3248	* location because of room or address incompatibilities. */
3249	bool fMappingsFixedRestored;
3250	/** Size of fixed mapping.
3251	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3252	uint32_t cbMappingFixed;
3253	/** Generation ID for the RAM ranges. This member is incremented everytime
3254	* a RAM range is linked or unlinked. */
3255	uint32_t volatile idRamRangesGen;
3256
3257	/** Base address (GC) of fixed mapping.
3258	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3259	RTGCPTR GCPtrMappingFixed;
3260	/** The address of the previous RAM range mapping. */
3261	RTGCPTR GCPtrPrevRamRangeMapping;
3262
3263	/** Physical access handler type for ROM protection. */
3264	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3265	/** Alignment padding. */
3266	uint32_t u32Padding;
3267
3268	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3269	RTGCPHYS GCPhys4MBPSEMask;
3270	/** Mask containing the invalid bits of a guest physical address.
3271	* @remarks this does not stop at bit 52. */
3272	RTGCPHYS GCPhysInvAddrMask;
3273
3274
3275	/** RAM range TLB for R3. */
3276	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3277	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3278	* This is sorted by physical address and contains no overlapping ranges. */
3279	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3280	/** Root of the RAM range search tree for ring-3. */
3281	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3282	/** PGM offset based trees - R3 Ptr. */
3283	R3PTRTYPE(PPGMTREES) pTreesR3;
3284	/** Caching the last physical handler we looked up in R3. */
3285	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3286	/** Shadow Page Pool - R3 Ptr. */
3287	R3PTRTYPE(PPGMPOOL) pPoolR3;
3288	/** Linked list of GC mappings - for HC.
3289	* The list is sorted ascending on address. */
3290	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3291	/** Pointer to the list of ROM ranges - for R3.
3292	* This is sorted by physical address and contains no overlapping ranges. */
3293	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3294	/** Pointer to the list of MMIO2 ranges - for R3.
3295	* Registration order. */
3296	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3297	/** Pointer to SHW+GST mode data (function pointers).
3298	* The index into this table is made up from */
3299	R3PTRTYPE(PPGMMODEDATA) paModeData;
3300	RTR3PTR R3PtrAlignment0;
3301	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3302	R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3303
3304	/** RAM range TLB for R0. */
3305	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3306	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3307	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3308	/** Root of the RAM range search tree for ring-0. */
3309	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3310	/** PGM offset based trees - R0 Ptr. */
3311	R0PTRTYPE(PPGMTREES) pTreesR0;
3312	/** Caching the last physical handler we looked up in R0. */
3313	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3314	/** Shadow Page Pool - R0 Ptr. */
3315	R0PTRTYPE(PPGMPOOL) pPoolR0;
3316	/** Linked list of GC mappings - for R0.
3317	* The list is sorted ascending on address. */
3318	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3319	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3320	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3321	RTR0PTR R0PtrAlignment0;
3322	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3323	R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3324
3325	/** RAM range TLB for RC. */
3326	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3327	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3328	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3329	/** Root of the RAM range search tree for raw-mode context. */
3330	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3331	/** PGM offset based trees - RC Ptr. */
3332	RCPTRTYPE(PPGMTREES) pTreesRC;
3333	/** Caching the last physical handler we looked up in RC. */
3334	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3335	/** Shadow Page Pool - RC Ptr. */
3336	RCPTRTYPE(PPGMPOOL) pPoolRC;
3337	/** Linked list of GC mappings - for RC.
3338	* The list is sorted ascending on address. */
3339	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3340	/** RC pointer corresponding to PGM::pRomRangesR3. */
3341	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3342	RTRCPTR RCPtrAlignment0;
3343	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3344	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3345	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3346	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3347
3348
3349	/** Pointer to the 5 page CR3 content mapping.
3350	* The first page is always the CR3 (in some form) while the 4 other pages
3351	* are used of the PDs in PAE mode. */
3352	RTGCPTR GCPtrCR3Mapping;
3353
3354	/** @name Intermediate Context
3355	* @{ */
3356	/** Pointer to the intermediate page directory - Normal. */
3357	R3PTRTYPE(PX86PD) pInterPD;
3358	/** Pointer to the intermediate page tables - Normal.
3359	* There are two page tables, one for the identity mapping and one for
3360	* the host context mapping (of the core code). */
3361	R3PTRTYPE(PX86PT) apInterPTs[2];
3362	/** Pointer to the intermediate page tables - PAE. */
3363	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3364	/** Pointer to the intermediate page directory - PAE. */
3365	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3366	/** Pointer to the intermediate page directory - PAE. */
3367	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3368	/** Pointer to the intermediate page-map level 4 - AMD64. */
3369	R3PTRTYPE(PX86PML4) pInterPaePML4;
3370	/** Pointer to the intermediate page directory - AMD64. */
3371	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3372	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3373	RTHCPHYS HCPhysInterPD;
3374	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3375	RTHCPHYS HCPhysInterPaePDPT;
3376	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3377	RTHCPHYS HCPhysInterPaePML4;
3378	/** @} */
3379
3380	/** Base address of the dynamic page mapping area.
3381	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3382	*
3383	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3384	* work out. Some cleaning up of the initialization that would
3385	* remove this memory is yet to be done...
3386	*/
3387	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3388	/** The address of the raw-mode context mapping cache. */
3389	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3390	/** The address of the ring-0 mapping cache if we're making use of it. */
3391	RTR0PTR pvR0DynMapUsed;
3392
3393	/** Hack: Number of deprecated page mapping locks taken by the current lock
3394	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3395	uint32_t cDeprecatedPageLocks;
3396	#if HC_ARCH_BITS == 64
3397	/** Alignment padding. */
3398	uint32_t u32Alignment2;
3399	#endif
3400
3401
3402	/** PGM critical section.
3403	* This protects the physical & virtual access handlers, ram ranges,
3404	* and the page flag updating (some of it anyway).
3405	*/
3406	PDMCRITSECT CritSectX;
3407
3408	/**
3409	* Data associated with managing the ring-3 mappings of the allocation chunks.
3410	*/
3411	struct
3412	{
3413	/** The chunk tree, ordered by chunk id. */
3414	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3415	R3PTRTYPE(PAVLU32NODECORE) pTree;
3416	#else
3417	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3418	#endif
3419	#if HC_ARCH_BITS == 32
3420	uint32_t u32Alignment0;
3421	#endif
3422	/** The chunk mapping TLB. */
3423	PGMCHUNKR3MAPTLB Tlb;
3424	/** The number of mapped chunks. */
3425	uint32_t c;
3426	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3427	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3428	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3429	uint32_t cMax;
3430	/** The current time. This is incremented whenever a chunk is inserted. */
3431	uint32_t iNow;
3432	/** Alignment padding. */
3433	uint32_t u32Alignment1;
3434	} ChunkR3Map;
3435
3436	/**
3437	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3438	*/
3439	PGMPAGER3MAPTLB PhysTlbHC;
3440
3441	/** @name The zero page.
3442	* @{ */
3443	/** The host physical address of the zero page. */
3444	RTHCPHYS HCPhysZeroPg;
3445	/** The ring-3 mapping of the zero page. */
3446	RTR3PTR pvZeroPgR3;
3447	/** The ring-0 mapping of the zero page. */
3448	RTR0PTR pvZeroPgR0;
3449	/** The GC mapping of the zero page. */
3450	RTRCPTR pvZeroPgRC;
3451	RTRCPTR RCPtrAlignment3;
3452	/** @}*/
3453
3454	/** @name The Invalid MMIO page.
3455	* This page is filled with 0xfeedface.
3456	* @{ */
3457	/** The host physical address of the invalid MMIO page. */
3458	RTHCPHYS HCPhysMmioPg;
3459	/** The host pysical address of the invalid MMIO page plus all invalid
3460	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3461	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3462	RTHCPHYS HCPhysInvMmioPg;
3463	/** The ring-3 mapping of the invalid MMIO page. */
3464	RTR3PTR pvMmioPgR3;
3465	#if HC_ARCH_BITS == 32
3466	RTR3PTR R3PtrAlignment4;
3467	#endif
3468	/** @} */
3469
3470
3471	/** The number of handy pages. */
3472	uint32_t cHandyPages;
3473
3474	/** The number of large handy pages. */
3475	uint32_t cLargeHandyPages;
3476
3477	/**
3478	* Array of handy pages.
3479	*
3480	* This array is used in a two way communication between pgmPhysAllocPage
3481	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3482	* an intermediary.
3483	*
3484	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3485	* (The current size of 32 pages, means 128 KB of handy memory.)
3486	*/
3487	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3488
3489	/**
3490	* Array of large handy pages. (currently size 1)
3491	*
3492	* This array is used in a two way communication between pgmPhysAllocLargePage
3493	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3494	* an intermediary.
3495	*/
3496	GMMPAGEDESC aLargeHandyPage[1];
3497
3498	/**
3499	* Live save data.
3500	*/
3501	struct
3502	{
3503	/** Per type statistics. */
3504	struct
3505	{
3506	/** The number of ready pages. */
3507	uint32_t cReadyPages;
3508	/** The number of dirty pages. */
3509	uint32_t cDirtyPages;
3510	/** The number of ready zero pages. */
3511	uint32_t cZeroPages;
3512	/** The number of write monitored pages. */
3513	uint32_t cMonitoredPages;
3514	} Rom,
3515	Mmio2,
3516	Ram;
3517	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3518	uint32_t cIgnoredPages;
3519	/** Indicates that a live save operation is active. */
3520	bool fActive;
3521	/** Padding. */
3522	bool afReserved[2];
3523	/** The next history index. */
3524	uint8_t iDirtyPagesHistory;
3525	/** History of the total amount of dirty pages. */
3526	uint32_t acDirtyPagesHistory[64];
3527	/** Short term dirty page average. */
3528	uint32_t cDirtyPagesShort;
3529	/** Long term dirty page average. */
3530	uint32_t cDirtyPagesLong;
3531	/** The number of saved pages. This is used to get some kind of estimate of the
3532	* link speed so we can decide when we're done. It is reset after the first
3533	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3534	* zero pages. */
3535	uint64_t cSavedPages;
3536	/** The nanosecond timestamp when cSavedPages was 0. */
3537	uint64_t uSaveStartNS;
3538	/** Pages per second (for statistics). */
3539	uint32_t cPagesPerSecond;
3540	uint32_t cAlignment;
3541	} LiveSave;
3542
3543	/** @name Error injection.
3544	* @{ */
3545	/** Inject handy page allocation errors pretending we're completely out of
3546	* memory. */
3547	bool volatile fErrInjHandyPages;
3548	/** Padding. */
3549	bool afReserved[3];
3550	/** @} */
3551
3552	/** @name Release Statistics
3553	* @{ */
3554	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3555	uint32_t cPrivatePages; /*< The number of private pages. /
3556	uint32_t cSharedPages; /*< The number of shared pages. /
3557	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3558	uint32_t cZeroPages; /*< The number of zero backed pages. /
3559	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3560	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3561	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3562	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3563	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3564	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3565	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3566	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3567	uint32_t cLargePages; /*< The number of large pages. /
3568	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3569	/* uint32_t aAlignment4[1]; */
3570
3571	/** The number of times we were forced to change the hypervisor region location. */
3572	STAMCOUNTER cRelocations;
3573
3574	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3575	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3576	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3577
3578	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3579	/** @} */
3580
3581	#ifdef VBOX_WITH_STATISTICS
3582	/** @name Statistics on the heap.
3583	* @{ */
3584	R3PTRTYPE(PGMSTATS *) pStatsR3;
3585	R0PTRTYPE(PGMSTATS *) pStatsR0;
3586	RCPTRTYPE(PGMSTATS *) pStatsRC;
3587	RTRCPTR RCPtrAlignment;
3588	/** @} */
3589	#endif
3590	} PGM;
3591	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3592	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3593	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3594	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3595	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3596	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3597	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3598	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3599	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3600	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3601	#endif /* !IN_TSTVMSTRUCTGC */
3602	/** Pointer to the PGM instance data. */
3603	typedef PGM *PPGM;
3604
3605
3606
3607	typedef struct PGMCPUSTATS
3608	{
3609	/* Common */
3610	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3611	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3612
3613	/* R0 only: */
3614	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3615	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3616
3617	/* RZ only: */
3618	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3619	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3620	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3621	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3622	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3623	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3624	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3625	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3626	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3627	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3628	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3629	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3630	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3631	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3632	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3633	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3634	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3635	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3636	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3637	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3638	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3639	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3640	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3641	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3642	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3643	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3644	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3645	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3646	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3647	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3648	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3649	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3650	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3651	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3652	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3653	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3654	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3655	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3656	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3657	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3658	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3659	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3660	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3661	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3662	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3663	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3664	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3665	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3666	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3667	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3668	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3669	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3670	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3671	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3672	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3673	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3674	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3675	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3676	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3677	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3678	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3679	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3680	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3681	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3682	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3683	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3684	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3685	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3686	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3687	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3688	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3689	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3690	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3691	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3692	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3693	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3694	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3695	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3696
3697	/* HC - R3 and (maybe) R0: */
3698
3699	/* RZ & R3: */
3700	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3701	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3702	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3703	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3704	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3705	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3706	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3707	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3708	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3709	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3710	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3711	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3712	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3713	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3714	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3715	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3716	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3717	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3718	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3719	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3720	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3721	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3722	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3723	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3724	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3725	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3726	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3727	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3728	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3729	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3730	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3731	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3732	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3733	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3734	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3735	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3736	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3737	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3738	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3739	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3740	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3741	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3742	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3743	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3744	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3745	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3746	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3747
3748	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3749	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3750	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3751	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3752	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3753	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3754	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3755	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3756	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3757	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3758	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3759	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3760	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3761	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3762	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3763	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3764	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3765	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3766	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3767	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3768	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3769	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3770	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3771	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3772	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3773	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3774	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3775	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3776	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3777	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3778	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3779	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3780	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3781	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3782	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3783	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3784	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3785	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3786	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3787	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3788	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3789	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3790	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3791	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3792	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3793	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3794	/** @} */
3795	} PGMCPUSTATS;
3796
3797
3798	/**
3799	* Converts a PGMCPU pointer into a VM pointer.
3800	* @returns Pointer to the VM structure the PGM is part of.
3801	* @param pPGM Pointer to PGMCPU instance data.
3802	*/
3803	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3804
3805	/**
3806	* Converts a PGMCPU pointer into a PGM pointer.
3807	* @returns Pointer to the VM structure the PGM is part of.
3808	* @param pPGM Pointer to PGMCPU instance data.
3809	*/
3810	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3811
3812	/**
3813	* PGMCPU Data (part of VMCPU).
3814	*/
3815	typedef struct PGMCPU
3816	{
3817	/** Offset to the VM structure. */
3818	int32_t offVM;
3819	/** Offset to the VMCPU structure. */
3820	int32_t offVCpu;
3821	/** Offset of the PGM structure relative to VMCPU. */
3822	int32_t offPGM;
3823	uint32_t uPadding0; /*< structure size alignment. /
3824
3825	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3826	/** Automatically tracked physical memory mapping set.
3827	* Ring-0 and strict raw-mode builds. */
3828	PGMMAPSET AutoSet;
3829	#endif
3830
3831	/** A20 gate mask.
3832	* Our current approach to A20 emulation is to let REM do it and don't bother
3833	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3834	* But whould need arrise, we'll subject physical addresses to this mask. */
3835	RTGCPHYS GCPhysA20Mask;
3836	/** A20 gate state - boolean! */
3837	bool fA20Enabled;
3838	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3839	bool fNoExecuteEnabled;
3840	/** Unused bits. */
3841	bool afUnused[2];
3842
3843	/** What needs syncing (PGM_SYNC_*).
3844	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3845	* PGMFlushTLB, and PGMR3Load. */
3846	uint32_t fSyncFlags;
3847
3848	/** The shadow paging mode. */
3849	PGMMODE enmShadowMode;
3850	/** The guest paging mode. */
3851	PGMMODE enmGuestMode;
3852
3853	/** The current physical address representing in the guest CR3 register. */
3854	RTGCPHYS GCPhysCR3;
3855
3856	/** @name 32-bit Guest Paging.
3857	* @{ */
3858	/** The guest's page directory, R3 pointer. */
3859	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3860	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3861	/** The guest's page directory, R0 pointer. */
3862	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3863	#endif
3864	/** The guest's page directory, static RC mapping. */
3865	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3866	/** Mask containing the MBZ bits of a big page PDE. */
3867	uint32_t fGst32BitMbzBigPdeMask;
3868	/** Set if the page size extension (PSE) is enabled. */
3869	bool fGst32BitPageSizeExtension;
3870	/** Alignment padding. */
3871	bool afAlignment2[3];
3872	/** @} */
3873
3874	/** @name PAE Guest Paging.
3875	* @{ */
3876	/** The guest's page directory pointer table, static RC mapping. */
3877	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3878	/** The guest's page directory pointer table, R3 pointer. */
3879	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3880	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3881	/** The guest's page directory pointer table, R0 pointer. */
3882	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3883	#endif
3884
3885	/** The guest's page directories, R3 pointers.
3886	* These are individual pointers and don't have to be adjacent.
3887	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3888	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3889	/** The guest's page directories, R0 pointers.
3890	* Same restrictions as apGstPaePDsR3. */
3891	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3892	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3893	#endif
3894	/** The guest's page directories, static GC mapping.
3895	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3896	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3897	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3898	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3899	* @todo Remove this and use aGstPaePdpeRegs instead? */
3900	RTGCPHYS aGCPhysGstPaePDs[4];
3901	/** The values of the 4 PDPE CPU registers (PAE). */
3902	X86PDPE aGstPaePdpeRegs[4];
3903	/** The physical addresses of the monitored guest page directories (PAE). */
3904	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3905	/** Mask containing the MBZ PTE bits. */
3906	uint64_t fGstPaeMbzPteMask;
3907	/** Mask containing the MBZ PDE bits. */
3908	uint64_t fGstPaeMbzPdeMask;
3909	/** Mask containing the MBZ big page PDE bits. */
3910	uint64_t fGstPaeMbzBigPdeMask;
3911	/** Mask containing the MBZ PDPE bits. */
3912	uint64_t fGstPaeMbzPdpeMask;
3913	/** @} */
3914
3915	/** @name AMD64 Guest Paging.
3916	* @{ */
3917	/** The guest's page directory pointer table, R3 pointer. */
3918	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3919	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3920	/** The guest's page directory pointer table, R0 pointer. */
3921	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3922	#else
3923	RTR0PTR alignment6b; /*< alignment equalizer. /
3924	#endif
3925	/** Mask containing the MBZ PTE bits. */
3926	uint64_t fGstAmd64MbzPteMask;
3927	/** Mask containing the MBZ PDE bits. */
3928	uint64_t fGstAmd64MbzPdeMask;
3929	/** Mask containing the MBZ big page PDE bits. */
3930	uint64_t fGstAmd64MbzBigPdeMask;
3931	/** Mask containing the MBZ PDPE bits. */
3932	uint64_t fGstAmd64MbzPdpeMask;
3933	/** Mask containing the MBZ big page PDPE bits. */
3934	uint64_t fGstAmd64MbzBigPdpeMask;
3935	/** Mask containing the MBZ PML4E bits. */
3936	uint64_t fGstAmd64MbzPml4eMask;
3937	/** Mask containing the PDPE bits that we shadow. */
3938	uint64_t fGstAmd64ShadowedPdpeMask;
3939	/** Mask containing the PML4E bits that we shadow. */
3940	uint64_t fGstAmd64ShadowedPml4eMask;
3941	/** @} */
3942
3943	/** @name PAE and AMD64 Guest Paging.
3944	* @{ */
3945	/** Mask containing the PTE bits that we shadow. */
3946	uint64_t fGst64ShadowedPteMask;
3947	/** Mask containing the PDE bits that we shadow. */
3948	uint64_t fGst64ShadowedPdeMask;
3949	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3950	uint64_t fGst64ShadowedBigPdeMask;
3951	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3952	uint64_t fGst64ShadowedBigPde4PteMask;
3953	/** @} */
3954
3955	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3956	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3957	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3958	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3959	/** Pointer to the page of the current active CR3 - RC Ptr. */
3960	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3961	# if HC_ARCH_BITS == 64
3962	RTRCPTR alignment6; /*< structure size alignment. /
3963	# endif
3964	/** @} */
3965
3966	/** @name Function pointers for Shadow paging.
3967	* @{
3968	*/
3969	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3970	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3971	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3972	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3973
3974	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3975	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3976
3977	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3978	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3979
3980	/** @} */
3981
3982	/** @name Function pointers for Guest paging.
3983	* @{
3984	*/
3985	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3986	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3987	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3988	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3989	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3990	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3991	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3992	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3993	#if HC_ARCH_BITS == 64
3994	RTRCPTR alignment3; /*< structure size alignment. /
3995	#endif
3996
3997	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3998	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3999	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4000	/** @} */
4001
4002	/** @name Function pointers for Both Shadow and Guest paging.
4003	* @{
4004	*/
4005	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4006	/* no pfnR3BthTrap0eHandler */
4007	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4008	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4009	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4010	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4011	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4012	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4013	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
4014
4015	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4016	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4017	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4018	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4019	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4020	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4021	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4022	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
4023
4024	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4025	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4026	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4027	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4028	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4029	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4030	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4031	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
4032	#if 0
4033	RTRCPTR alignment2; /*< structure size alignment. /
4034	#endif
4035	/** @} */
4036
4037	/** For saving stack space, the disassembler state is allocated here instead of
4038	* on the stack. */
4039	DISCPUSTATE DisState;
4040
4041	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
4042	uint64_t cNetwareWp0Hacks;
4043
4044	/** Count the number of pgm pool access handler calls. */
4045	uint64_t cPoolAccessHandler;
4046
4047	/** @name Release Statistics
4048	* @{ */
4049	/** The number of times the guest has switched mode since last reset or statistics reset. */
4050	STAMCOUNTER cGuestModeChanges;
4051	/** The number of times the guest has switched mode since last reset or statistics reset. */
4052	STAMCOUNTER cA20Changes;
4053	/** @} */
4054
4055	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4056	/** @name Statistics
4057	* @{ */
4058	/** RC: Pointer to the statistics. */
4059	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4060	/** RC: Which statistic this \#PF should be attributed to. */
4061	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4062	/** R0: Pointer to the statistics. */
4063	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4064	/** R0: Which statistic this \#PF should be attributed to. */
4065	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4066	/** R3: Pointer to the statistics. */
4067	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4068	/** Alignment padding. */
4069	RTR3PTR pPaddingR3;
4070	/** @} */
4071	#endif /* VBOX_WITH_STATISTICS */
4072	} PGMCPU;
4073	/** Pointer to the per-cpu PGM data. */
4074	typedef PGMCPU *PPGMCPU;
4075
4076
4077	/** @name PGM::fSyncFlags Flags
4078	* @{
4079	*/
4080	/** Updates the virtual access handler state bit in PGMPAGE. */
4081	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4082	/** Always sync CR3. */
4083	#define PGM_SYNC_ALWAYS RT_BIT(1)
4084	/** Check monitoring on next CR3 (re)load and invalidate page.
4085	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4086	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4087	/** Check guest mapping in SyncCR3. */
4088	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4089	/** Clear the page pool (a light weight flush). */
4090	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4091	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4092	/** @} */
4093
4094
4095	RT_C_DECLS_BEGIN
4096
4097	#if defined(VBOX_STRICT) && defined(IN_RING3)
4098	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4099	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4100	#else
4101	int pgmLock(PVM pVM);
4102	#endif
4103	void pgmUnlock(PVM pVM);
4104	/**
4105	* Asserts that the caller owns the PDM lock.
4106	* This is the internal variant of PGMIsLockOwner.
4107	* @param a_pVM Pointer to the VM.
4108	*/
4109	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4110	/**
4111	* Asserts that the caller owns the PDM lock.
4112	* This is the internal variant of PGMIsLockOwner.
4113	* @param a_pVM Pointer to the VM.
4114	* @param a_pVCpu The current CPU handle.
4115	*/
4116	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4117
4118	#ifndef PGM_WITHOUT_MAPPINGS
4119	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4120	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4121	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4122	int pgmMapResolveConflicts(PVM pVM);
4123	#endif /* !PGM_WITHOUT_MAPPINGS */
4124	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4125	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4126
4127	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4128	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4129	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4130	PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4131	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4132	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4133	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4134	#else
4135	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4136	#endif
4137	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4138	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4139
4140	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4141	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4142	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4143	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4144	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4145	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4146	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4147	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4148	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4149	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4150	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4151	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4152	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4153	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4154	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4155	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4156	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4157	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4158	#ifndef IN_RING3
4159	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4160	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4161	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4162	#endif
4163	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4164	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4165	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4166	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4167	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4168	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4169	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4170	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4171	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4172
4173	#ifdef IN_RING3
4174	void pgmR3PhysRelinkRamRanges(PVM pVM);
4175	int pgmR3PhysRamPreAllocate(PVM pVM);
4176	int pgmR3PhysRamReset(PVM pVM);
4177	int pgmR3PhysRomReset(PVM pVM);
4178	int pgmR3PhysRamZeroAll(PVM pVM);
4179	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4180	int pgmR3PhysRamTerm(PVM pVM);
4181	void pgmR3PhysRomTerm(PVM pVM);
4182	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4183
4184	int pgmR3PoolInit(PVM pVM);
4185	void pgmR3PoolRelocate(PVM pVM);
4186	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4187	void pgmR3PoolReset(PVM pVM);
4188	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4189	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4190	void pgmR3PoolWriteProtectPages(PVM pVM);
4191
4192	#endif /* IN_RING3 */
4193	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4194	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4195	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4196	# ifdef LOG_ENABLED
4197	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4198	# else
4199	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4200	# endif
4201	#endif
4202	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4203	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4204	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4205	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4206	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4207	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4208	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4209	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4210	int pgmPoolSyncCR3(PVMCPU pVCpu);
4211	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4212	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4213	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4214	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4215	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4216	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4217	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4218	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4219	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4220	#ifndef IN_RING3
4221	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPoolAccessPfHandler;
4222	#endif
4223
4224	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4225	void pgmPoolResetDirtyPages(PVM pVM);
4226	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4227
4228	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4229	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4230	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4231
4232	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4233	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4234	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4235	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4236
4237	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4238	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4239	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4240
4241	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4242	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4243	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4244	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4245	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4246
4247	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4248	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4249	FNDBGCCMD pgmR3CmdShowSharedModules;
4250	# endif
4251
4252	RT_C_DECLS_END
4253
4254	/** @} */
4255
4256	#endif
4257

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 56296

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