PGMInternal.h@ 49141

Last change on this file since 49141 was 47786, checked in by vboxsync, 11 years ago
PGM: Added a new page type for the VT-x APIC access page MMIO alias instead of abusing the MMIO2 aliasing. There are important differences, we can safely access the MMIO2 page when aliased and save time doing so, while the alias created by IOMMMIOMapMMIOHCPage must not be accessed outside the VT-x execution AFAIK.
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File size: 187.6 KB

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1	/* $Id: PGMInternal.h 47786 2013-08-16 08:59:32Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/sha.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Indicates that there are no guest mappings in the shadow tables.
59	*
60	* Note! In ring-3 the macro is also used to exclude the managment of the
61	* intermediate context page tables. On 32-bit systems we use the intermediate
62	* context to support 64-bit guest execution. Thus, we cannot fully make it
63	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
64	*
65	* In raw-mode context there are by design always guest mappings (the code is
66	* executed from one), while in ring-0 there are none at all. Neither context
67	* manages the page tables for intermediate switcher context, that's all done in
68	* ring-3.
69	*
70	* On 32-bit darwin (hybrid kernel) we do 64-bit guest support differently, so
71	* there we can safely work without mappings if we don't compile in raw-mode.
72	*/
73	#if defined(IN_RING0) \
74	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
75	&& ( HC_ARCH_BITS != 32 \
76	\|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \
77	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
78	) \
79	)
80	# define PGM_WITHOUT_MAPPINGS
81	#endif
82
83	/**
84	* Check and skip global PDEs for non-global flushes
85	*/
86	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
87
88	/**
89	* Optimization for PAE page tables that are modified often
90	*/
91	//#if 0 /* disabled again while debugging */
92	#ifndef IN_RC
93	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
94	#endif
95	//#endif
96
97	/**
98	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
99	*/
100	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
101	# define PGM_WITH_LARGE_PAGES
102	#endif
103
104	/**
105	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
106	* VMX_EXIT_EPT_MISCONFIG.
107	*/
108	#if 1 /* testing */
109	# define PGM_WITH_MMIO_OPTIMIZATIONS
110	#endif
111
112	/**
113	* Sync N pages instead of a whole page table
114	*/
115	#define PGM_SYNC_N_PAGES
116
117	/**
118	* Number of pages to sync during a page fault
119	*
120	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
121	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
122	*
123	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
124	* world switch overhead, so let's sync more.
125	*/
126	# ifdef IN_RING0
127	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
128	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
129	* but ~5% fewer faults.
130	*/
131	# define PGM_SYNC_NR_PAGES 32
132	#else
133	# define PGM_SYNC_NR_PAGES 8
134	#endif
135
136	/**
137	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
138	*/
139	#define PGM_MAX_PHYSCACHE_ENTRIES 64
140	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
141
142
143	/** @def PGMPOOL_CFG_MAX_GROW
144	* The maximum number of pages to add to the pool in one go.
145	*/
146	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
147
148	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
149	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
150	*/
151	#ifdef VBOX_STRICT
152	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
153	#endif
154
155	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
156	* Enables the experimental lazy page allocation code. */
157	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
158
159	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
160	* Enables real write monitoring of pages, i.e. mapping them read-only and
161	* only making them writable when getting a write access #PF. */
162	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
163
164	/** @} */
165
166
167	/** @name PDPT and PML4 flags.
168	* These are placed in the three bits available for system programs in
169	* the PDPT and PML4 entries.
170	* @{ */
171	/** The entry is a permanent one and it's must always be present.
172	* Never free such an entry. */
173	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
174	/** Mapping (hypervisor allocated pagetable). */
175	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
176	/** @} */
177
178	/** @name Page directory flags.
179	* These are placed in the three bits available for system programs in
180	* the page directory entries.
181	* @{ */
182	/** Mapping (hypervisor allocated pagetable). */
183	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
184	/** Made read-only to facilitate dirty bit tracking. */
185	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
186	/** @} */
187
188	/** @name Page flags.
189	* These are placed in the three bits available for system programs in
190	* the page entries.
191	* @{ */
192	/** Made read-only to facilitate dirty bit tracking. */
193	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
194
195	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
196	/** Scanned and approved by CSAM (tm).
197	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
198	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
199	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
200	#endif
201
202	/** @} */
203
204	/** @name Defines used to indicate the shadow and guest paging in the templates.
205	* @{ */
206	#define PGM_TYPE_REAL 1
207	#define PGM_TYPE_PROT 2
208	#define PGM_TYPE_32BIT 3
209	#define PGM_TYPE_PAE 4
210	#define PGM_TYPE_AMD64 5
211	#define PGM_TYPE_NESTED 6
212	#define PGM_TYPE_EPT 7
213	#define PGM_TYPE_MAX PGM_TYPE_EPT
214	/** @} */
215
216	/** Macro for checking if the guest is using paging.
217	* @param uGstType PGM_TYPE_*
218	* @param uShwType PGM_TYPE_*
219	* @remark ASSUMES certain order of the PGM_TYPE_* values.
220	*/
221	#define PGM_WITH_PAGING(uGstType, uShwType) \
222	( (uGstType) >= PGM_TYPE_32BIT \
223	&& (uShwType) != PGM_TYPE_NESTED \
224	&& (uShwType) != PGM_TYPE_EPT)
225
226	/** Macro for checking if the guest supports the NX bit.
227	* @param uGstType PGM_TYPE_*
228	* @param uShwType PGM_TYPE_*
229	* @remark ASSUMES certain order of the PGM_TYPE_* values.
230	*/
231	#define PGM_WITH_NX(uGstType, uShwType) \
232	( (uGstType) >= PGM_TYPE_PAE \
233	&& (uShwType) != PGM_TYPE_NESTED \
234	&& (uShwType) != PGM_TYPE_EPT)
235
236
237	/** @def PGM_HCPHYS_2_PTR
238	* Maps a HC physical page pool address to a virtual address.
239	*
240	* @returns VBox status code.
241	* @param pVM Pointer to the VM.
242	* @param pVCpu The current CPU.
243	* @param HCPhys The HC physical address to map to a virtual one.
244	* @param ppv Where to store the virtual address. No need to cast
245	* this.
246	*
247	* @remark Use with care as we don't have so much dynamic mapping space in
248	* ring-0 on 32-bit darwin and in RC.
249	* @remark There is no need to assert on the result.
250	*/
251	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
252	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
253	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
254	#else
255	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
256	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
257	#endif
258
259	/** @def PGM_GCPHYS_2_PTR_V2
260	* Maps a GC physical page address to a virtual address.
261	*
262	* @returns VBox status code.
263	* @param pVM Pointer to the VM.
264	* @param pVCpu The current CPU.
265	* @param GCPhys The GC physical address to map to a virtual one.
266	* @param ppv Where to store the virtual address. No need to cast this.
267	*
268	* @remark Use with care as we don't have so much dynamic mapping space in
269	* ring-0 on 32-bit darwin and in RC.
270	* @remark There is no need to assert on the result.
271	*/
272	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
273	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
274	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
275	#else
276	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
277	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
278	#endif
279
280	/** @def PGM_GCPHYS_2_PTR
281	* Maps a GC physical page address to a virtual address.
282	*
283	* @returns VBox status code.
284	* @param pVM Pointer to the VM.
285	* @param GCPhys The GC physical address to map to a virtual one.
286	* @param ppv Where to store the virtual address. No need to cast this.
287	*
288	* @remark Use with care as we don't have so much dynamic mapping space in
289	* ring-0 on 32-bit darwin and in RC.
290	* @remark There is no need to assert on the result.
291	*/
292	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
293
294	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
295	* Maps a GC physical page address to a virtual address.
296	*
297	* @returns VBox status code.
298	* @param pVCpu The current CPU.
299	* @param GCPhys The GC physical address to map to a virtual one.
300	* @param ppv Where to store the virtual address. No need to cast this.
301	*
302	* @remark Use with care as we don't have so much dynamic mapping space in
303	* ring-0 on 32-bit darwin and in RC.
304	* @remark There is no need to assert on the result.
305	*/
306	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
307
308	/** @def PGM_GCPHYS_2_PTR_EX
309	* Maps a unaligned GC physical page address to a virtual address.
310	*
311	* @returns VBox status code.
312	* @param pVM Pointer to the VM.
313	* @param GCPhys The GC physical address to map to a virtual one.
314	* @param ppv Where to store the virtual address. No need to cast this.
315	*
316	* @remark Use with care as we don't have so much dynamic mapping space in
317	* ring-0 on 32-bit darwin and in RC.
318	* @remark There is no need to assert on the result.
319	*/
320	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
321	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
322	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
323	#else
324	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
325	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
326	#endif
327
328	/** @def PGM_DYNMAP_UNUSED_HINT
329	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
330	* is no longer used.
331	*
332	* For best effect only apply this to the page that was mapped most recently.
333	*
334	* @param pVCpu The current CPU.
335	* @param pvPage The pool page.
336	*/
337	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
338	# ifdef LOG_ENABLED
339	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
340	# else
341	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
342	# endif
343	#else
344	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
345	#endif
346
347	/** @def PGM_DYNMAP_UNUSED_HINT_VM
348	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
349	* is no longer used.
350	*
351	* For best effect only apply this to the page that was mapped most recently.
352	*
353	* @param pVM Pointer to the VM.
354	* @param pvPage The pool page.
355	*/
356	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
357
358
359	/** @def PGM_INVL_PG
360	* Invalidates a page.
361	*
362	* @param pVCpu Pointer to the VMCPU.
363	* @param GCVirt The virtual address of the page to invalidate.
364	*/
365	#ifdef IN_RC
366	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
367	#elif defined(IN_RING0)
368	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
369	#else
370	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
371	#endif
372
373	/** @def PGM_INVL_PG_ALL_VCPU
374	* Invalidates a page on all VCPUs
375	*
376	* @param pVM Pointer to the VM.
377	* @param GCVirt The virtual address of the page to invalidate.
378	*/
379	#ifdef IN_RC
380	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
381	#elif defined(IN_RING0)
382	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
383	#else
384	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
385	#endif
386
387	/** @def PGM_INVL_BIG_PG
388	* Invalidates a 4MB page directory entry.
389	*
390	* @param pVCpu Pointer to the VMCPU.
391	* @param GCVirt The virtual address within the page directory to invalidate.
392	*/
393	#ifdef IN_RC
394	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
395	#elif defined(IN_RING0)
396	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
397	#else
398	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
399	#endif
400
401	/** @def PGM_INVL_VCPU_TLBS()
402	* Invalidates the TLBs of the specified VCPU
403	*
404	* @param pVCpu Pointer to the VMCPU.
405	*/
406	#ifdef IN_RC
407	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
408	#elif defined(IN_RING0)
409	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
410	#else
411	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
412	#endif
413
414	/** @def PGM_INVL_ALL_VCPU_TLBS()
415	* Invalidates the TLBs of all VCPUs
416	*
417	* @param pVM Pointer to the VM.
418	*/
419	#ifdef IN_RC
420	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
421	#elif defined(IN_RING0)
422	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
423	#else
424	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
425	#endif
426
427
428	/** @name Safer Shadow PAE PT/PTE
429	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
430	* present.
431	*
432	* @{
433	*/
434	#if 1
435	/**
436	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
437	* invalid entries for present.
438	* @sa X86PTEPAE.
439	*/
440	typedef union PGMSHWPTEPAE
441	{
442	/** Unsigned integer view */
443	X86PGPAEUINT uCareful;
444	/* Not other views. */
445	} PGMSHWPTEPAE;
446
447	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
448	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
449	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
450	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
451	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
452	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
453	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
454	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
455	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
456	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
457	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
458	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
459	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
460	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
461	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
462	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
463
464	/**
465	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
466	* invalid entries for present.
467	* @sa X86PTPAE.
468	*/
469	typedef struct PGMSHWPTPAE
470	{
471	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
472	} PGMSHWPTPAE;
473
474	#else
475	typedef X86PTEPAE PGMSHWPTEPAE;
476	typedef X86PTPAE PGMSHWPTPAE;
477	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
478	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
479	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
480	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
481	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
482	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
483	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
484	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
485	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
486	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
487	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
488	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
489	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
491	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
492	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
493
494	#endif
495
496	/** Pointer to a shadow PAE PTE. */
497	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
498	/** Pointer to a const shadow PAE PTE. */
499	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
500
501	/** Pointer to a shadow PAE page table. */
502	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
503	/** Pointer to a const shadow PAE page table. */
504	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
505	/** @} */
506
507
508	/** Size of the GCPtrConflict array in PGMMAPPING.
509	* @remarks Must be a power of two. */
510	#define PGMMAPPING_CONFLICT_MAX 8
511
512	/**
513	* Structure for tracking GC Mappings.
514	*
515	* This structure is used by linked list in both GC and HC.
516	*/
517	typedef struct PGMMAPPING
518	{
519	/** Pointer to next entry. */
520	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
521	/** Pointer to next entry. */
522	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
523	/** Pointer to next entry. */
524	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
525	/** Indicate whether this entry is finalized. */
526	bool fFinalized;
527	/** Start Virtual address. */
528	RTGCPTR GCPtr;
529	/** Last Virtual address (inclusive). */
530	RTGCPTR GCPtrLast;
531	/** Range size (bytes). */
532	RTGCPTR cb;
533	/** Pointer to relocation callback function. */
534	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
535	/** User argument to the callback. */
536	R3PTRTYPE(void *) pvUser;
537	/** Mapping description / name. For easing debugging. */
538	R3PTRTYPE(const char *) pszDesc;
539	/** Last 8 addresses that caused conflicts. */
540	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
541	/** Number of conflicts for this hypervisor mapping. */
542	uint32_t cConflicts;
543	/** Number of page tables. */
544	uint32_t cPTs;
545
546	/** Array of page table mapping data. Each entry
547	* describes one page table. The array can be longer
548	* than the declared length.
549	*/
550	struct
551	{
552	/** The HC physical address of the page table. */
553	RTHCPHYS HCPhysPT;
554	/** The HC physical address of the first PAE page table. */
555	RTHCPHYS HCPhysPaePT0;
556	/** The HC physical address of the second PAE page table. */
557	RTHCPHYS HCPhysPaePT1;
558	/** The HC virtual address of the 32-bit page table. */
559	R3PTRTYPE(PX86PT) pPTR3;
560	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
561	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
562	/** The RC virtual address of the 32-bit page table. */
563	RCPTRTYPE(PX86PT) pPTRC;
564	/** The RC virtual address of the two PAE page table. */
565	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
566	/** The R0 virtual address of the 32-bit page table. */
567	R0PTRTYPE(PX86PT) pPTR0;
568	/** The R0 virtual address of the two PAE page table. */
569	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
570	} aPTs[1];
571	} PGMMAPPING;
572	/** Pointer to structure for tracking GC Mappings. */
573	typedef struct PGMMAPPING *PPGMMAPPING;
574
575
576	/**
577	* Physical page access handler structure.
578	*
579	* This is used to keep track of physical address ranges
580	* which are being monitored in some kind of way.
581	*/
582	typedef struct PGMPHYSHANDLER
583	{
584	AVLROGCPHYSNODECORE Core;
585	/** Access type. */
586	PGMPHYSHANDLERTYPE enmType;
587	/** Number of pages to update. */
588	uint32_t cPages;
589	/** Set if we have pages that have been aliased. */
590	uint32_t cAliasedPages;
591	/** Set if we have pages that have temporarily been disabled. */
592	uint32_t cTmpOffPages;
593	/** Pointer to R3 callback function. */
594	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
595	/** User argument for R3 handlers. */
596	R3PTRTYPE(void *) pvUserR3;
597	/** Pointer to R0 callback function. */
598	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
599	/** User argument for R0 handlers. */
600	R0PTRTYPE(void *) pvUserR0;
601	/** Pointer to RC callback function. */
602	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
603	/** User argument for RC handlers. */
604	RCPTRTYPE(void *) pvUserRC;
605	/** Description / Name. For easing debugging. */
606	R3PTRTYPE(const char *) pszDesc;
607	#ifdef VBOX_WITH_STATISTICS
608	/** Profiling of this handler. */
609	STAMPROFILE Stat;
610	#endif
611	} PGMPHYSHANDLER;
612	/** Pointer to a physical page access handler structure. */
613	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
614
615
616	/**
617	* Cache node for the physical addresses covered by a virtual handler.
618	*/
619	typedef struct PGMPHYS2VIRTHANDLER
620	{
621	/** Core node for the tree based on physical ranges. */
622	AVLROGCPHYSNODECORE Core;
623	/** Offset from this struct to the PGMVIRTHANDLER structure. */
624	int32_t offVirtHandler;
625	/** Offset of the next alias relative to this one.
626	* Bit 0 is used for indicating whether we're in the tree.
627	* Bit 1 is used for indicating that we're the head node.
628	*/
629	int32_t offNextAlias;
630	} PGMPHYS2VIRTHANDLER;
631	/** Pointer to a phys to virtual handler structure. */
632	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
633
634	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
635	* node is in the tree. */
636	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
637	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
638	* node is in the head of an alias chain.
639	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
640	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
641	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
642	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
643
644
645	/**
646	* Virtual page access handler structure.
647	*
648	* This is used to keep track of virtual address ranges
649	* which are being monitored in some kind of way.
650	*/
651	typedef struct PGMVIRTHANDLER
652	{
653	/** Core node for the tree based on virtual ranges. */
654	AVLROGCPTRNODECORE Core;
655	/** Size of the range (in bytes). */
656	RTGCPTR cb;
657	/** Number of cache pages. */
658	uint32_t cPages;
659	/** Access type. */
660	PGMVIRTHANDLERTYPE enmType;
661	/** Pointer to the RC callback function. */
662	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
663	#if HC_ARCH_BITS == 64
664	RTRCPTR padding;
665	#endif
666	/** Pointer to the R3 callback function for invalidation. */
667	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
668	/** Pointer to the R3 callback function. */
669	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
670	/** Description / Name. For easing debugging. */
671	R3PTRTYPE(const char *) pszDesc;
672	#ifdef VBOX_WITH_STATISTICS
673	/** Profiling of this handler. */
674	STAMPROFILE Stat;
675	#endif
676	/** Array of cached physical addresses for the monitored ranged. */
677	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
678	} PGMVIRTHANDLER;
679	/** Pointer to a virtual page access handler structure. */
680	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
681
682
683	/** @name Page type predicates.
684	* @{ */
685	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
686	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
687	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
688	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
689	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
690	/** @} */
691
692
693	/**
694	* A Physical Guest Page tracking structure.
695	*
696	* The format of this structure is complicated because we have to fit a lot
697	* of information into as few bits as possible. The format is also subject
698	* to change (there is one coming up soon). Which means that for we'll be
699	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
700	* accesses to the structure.
701	*/
702	typedef union PGMPAGE
703	{
704	/** Structured view. */
705	struct
706	{
707	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
708	uint64_t u2HandlerPhysStateY : 2;
709	/** 3:2 - Paging structure needed to map the page
710	* (PGM_PAGE_PDE_TYPE_). /
711	uint64_t u2PDETypeY : 2;
712	/** 4 - Indicator of dirty page for fault tolerance tracking. */
713	uint64_t fFTDirtyY : 1;
714	/** 5 - Flag indicating that a write monitored page was written to
715	* when set. */
716	uint64_t fWrittenToY : 1;
717	/** 7:6 - Unused. */
718	uint64_t u2Unused0 : 2;
719	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
720	uint64_t u2HandlerVirtStateY : 2;
721	/** 11:10 - Unused. */
722	uint64_t u2Unused1 : 2;
723	/** 12:48 - The host physical frame number (shift left to get the
724	* address). */
725	uint64_t HCPhysFN : 36;
726	/** 50:48 - The page state. */
727	uint64_t uStateY : 3;
728	/** 51:53 - The page type (PGMPAGETYPE). */
729	uint64_t uTypeY : 3;
730	/** 63:54 - PTE index for usage tracking (page pool). */
731	uint64_t u10PteIdx : 10;
732
733	/** The GMM page ID.
734	* @remarks In the current implementation, MMIO2 and pages aliased to
735	* MMIO2 pages will be exploiting this field to calculate the
736	* ring-3 mapping address corresponding to the page.
737	* Later we may consider including MMIO2 management into GMM. */
738	uint32_t idPage;
739	/** Usage tracking (page pool). */
740	uint16_t u16TrackingY;
741	/** The number of read locks on this page. */
742	uint8_t cReadLocksY;
743	/** The number of write locks on this page. */
744	uint8_t cWriteLocksY;
745	} s;
746
747	/** 64-bit integer view. */
748	uint64_t au64[2];
749	/** 16-bit view. */
750	uint32_t au32[4];
751	/** 16-bit view. */
752	uint16_t au16[8];
753	/** 8-bit view. */
754	uint8_t au8[16];
755	} PGMPAGE;
756	AssertCompileSize(PGMPAGE, 16);
757	/** Pointer to a physical guest page. */
758	typedef PGMPAGE *PPGMPAGE;
759	/** Pointer to a const physical guest page. */
760	typedef const PGMPAGE *PCPGMPAGE;
761	/** Pointer to a physical guest page pointer. */
762	typedef PPGMPAGE *PPPGMPAGE;
763
764
765	/**
766	* Clears the page structure.
767	* @param a_pPage Pointer to the physical guest page tracking structure.
768	*/
769	#define PGM_PAGE_CLEAR(a_pPage) \
770	do { \
771	(a_pPage)->au64[0] = 0; \
772	(a_pPage)->au64[1] = 0; \
773	} while (0)
774
775	/**
776	* Initializes the page structure.
777	* @param a_pPage Pointer to the physical guest page tracking structure.
778	*/
779	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
780	do { \
781	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
782	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
783	(a_pPage)->au64[0] = SetHCPhysTmp; \
784	(a_pPage)->au64[1] = 0; \
785	(a_pPage)->s.idPage = (a_idPage); \
786	(a_pPage)->s.uStateY = (a_uState); \
787	(a_pPage)->s.uTypeY = (a_uType); \
788	} while (0)
789
790	/**
791	* Initializes the page structure of a ZERO page.
792	* @param a_pPage Pointer to the physical guest page tracking structure.
793	* @param a_pVM The VM handle (for getting the zero page address).
794	* @param a_uType The page type (PGMPAGETYPE).
795	*/
796	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
797	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
798
799
800	/** @name The Page state, PGMPAGE::uStateY.
801	* @{ */
802	/** The zero page.
803	* This is a per-VM page that's never ever mapped writable. */
804	#define PGM_PAGE_STATE_ZERO 0
805	/** A allocated page.
806	* This is a per-VM page allocated from the page pool (or wherever
807	* we get MMIO2 pages from if the type is MMIO2).
808	*/
809	#define PGM_PAGE_STATE_ALLOCATED 1
810	/** A allocated page that's being monitored for writes.
811	* The shadow page table mappings are read-only. When a write occurs, the
812	* fWrittenTo member is set, the page remapped as read-write and the state
813	* moved back to allocated. */
814	#define PGM_PAGE_STATE_WRITE_MONITORED 2
815	/** The page is shared, aka. copy-on-write.
816	* This is a page that's shared with other VMs. */
817	#define PGM_PAGE_STATE_SHARED 3
818	/** The page is ballooned, so no longer available for this VM. */
819	#define PGM_PAGE_STATE_BALLOONED 4
820	/** @} */
821
822
823	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
824	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
825	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
826	#else
827	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
828	#endif
829
830	/**
831	* Gets the page state.
832	* @returns page state (PGM_PAGE_STATE_*).
833	* @param a_pPage Pointer to the physical guest page tracking structure.
834	*
835	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
836	* builds.
837	*/
838	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
839	#if defined(__GNUC__) && defined(VBOX_STRICT)
840	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
841	#else
842	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
843	#endif
844
845	/**
846	* Sets the page state.
847	* @param a_pVM The VM handle, only used for lock ownership assertions.
848	* @param a_pPage Pointer to the physical guest page tracking structure.
849	* @param a_uState The new page state.
850	*/
851	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
852	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
853
854
855	/**
856	* Gets the host physical address of the guest page.
857	* @returns host physical address (RTHCPHYS).
858	* @param a_pPage Pointer to the physical guest page tracking structure.
859	*
860	* @remarks In strict builds on gcc platforms, this macro will make some ugly
861	* assumption about a valid pVM variable/parameter being in the
862	* current context. It will use this pVM variable to assert that the
863	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
864	* pVM is not around.
865	*/
866	#if 0
867	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
868	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
869	#else
870	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
871	# if defined(__GNUC__) && defined(VBOX_STRICT)
872	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
873	# else
874	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
875	# endif
876	#endif
877
878	/**
879	* Sets the host physical address of the guest page.
880	*
881	* @param a_pVM The VM handle, only used for lock ownership assertions.
882	* @param a_pPage Pointer to the physical guest page tracking structure.
883	* @param a_HCPhys The new host physical address.
884	*/
885	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
886	do { \
887	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
888	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
889	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
890	PGM_PAGE_ASSERT_LOCK(a_pVM); \
891	} while (0)
892
893	/**
894	* Get the Page ID.
895	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
896	* @param a_pPage Pointer to the physical guest page tracking structure.
897	*/
898	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
899
900	/**
901	* Sets the Page ID.
902	* @param a_pVM The VM handle, only used for lock ownership assertions.
903	* @param a_pPage Pointer to the physical guest page tracking structure.
904	* @param a_idPage The new page ID.
905	*/
906	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
907	do { \
908	(a_pPage)->s.idPage = (a_idPage); \
909	PGM_PAGE_ASSERT_LOCK(a_pVM); \
910	} while (0)
911
912	/**
913	* Get the Chunk ID.
914	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
915	* @param a_pPage Pointer to the physical guest page tracking structure.
916	*/
917	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
918
919	/**
920	* Get the index of the page within the allocation chunk.
921	* @returns The page index.
922	* @param a_pPage Pointer to the physical guest page tracking structure.
923	*/
924	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
925
926	/**
927	* Gets the page type.
928	* @returns The page type.
929	* @param a_pPage Pointer to the physical guest page tracking structure.
930	*
931	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
932	* builds.
933	*/
934	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
935	#if defined(__GNUC__) && defined(VBOX_STRICT)
936	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
937	#else
938	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
939	#endif
940
941	/**
942	* Sets the page type.
943	*
944	* @param a_pVM The VM handle, only used for lock ownership assertions.
945	* @param a_pPage Pointer to the physical guest page tracking structure.
946	* @param a_enmType The new page type (PGMPAGETYPE).
947	*/
948	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
949	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
950
951	/**
952	* Gets the page table index
953	* @returns The page table index.
954	* @param a_pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
957
958	/**
959	* Sets the page table index.
960	* @param a_pVM The VM handle, only used for lock ownership assertions.
961	* @param a_pPage Pointer to the physical guest page tracking structure.
962	* @param a_iPte New page table index.
963	*/
964	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
965	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
966
967	/**
968	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
969	* @returns true/false.
970	* @param a_pPage Pointer to the physical guest page tracking structure.
971	*/
972	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
973
974	/**
975	* Checks if the page is marked for MMIO, including both aliases.
976	* @returns true/false.
977	* @param a_pPage Pointer to the physical guest page tracking structure.
978	*/
979	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
980	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
981	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
982	)
983
984	/**
985	* Checks if the page is marked for MMIO, including special aliases.
986	* @returns true/false.
987	* @param a_pPage Pointer to the physical guest page tracking structure.
988	*/
989	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
990	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
991
992	/**
993	* Checks if the page is a special aliased MMIO page.
994	* @returns true/false.
995	* @param a_pPage Pointer to the physical guest page tracking structure.
996	*/
997	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
998
999	/**
1000	* Checks if the page is backed by the ZERO page.
1001	* @returns true/false.
1002	* @param a_pPage Pointer to the physical guest page tracking structure.
1003	*/
1004	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1005
1006	/**
1007	* Checks if the page is backed by a SHARED page.
1008	* @returns true/false.
1009	* @param a_pPage Pointer to the physical guest page tracking structure.
1010	*/
1011	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1012
1013	/**
1014	* Checks if the page is ballooned.
1015	* @returns true/false.
1016	* @param a_pPage Pointer to the physical guest page tracking structure.
1017	*/
1018	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1019
1020	/**
1021	* Checks if the page is allocated.
1022	* @returns true/false.
1023	* @param a_pPage Pointer to the physical guest page tracking structure.
1024	*/
1025	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1026
1027	/**
1028	* Marks the page as written to (for GMM change monitoring).
1029	* @param a_pVM The VM handle, only used for lock ownership assertions.
1030	* @param a_pPage Pointer to the physical guest page tracking structure.
1031	*/
1032	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1033	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1034
1035	/**
1036	* Clears the written-to indicator.
1037	* @param a_pVM The VM handle, only used for lock ownership assertions.
1038	* @param a_pPage Pointer to the physical guest page tracking structure.
1039	*/
1040	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1041	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1042
1043	/**
1044	* Checks if the page was marked as written-to.
1045	* @returns true/false.
1046	* @param a_pPage Pointer to the physical guest page tracking structure.
1047	*/
1048	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1049
1050	/**
1051	* Marks the page as dirty for FTM
1052	* @param a_pPage Pointer to the physical guest page tracking structure.
1053	*/
1054	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1055
1056	/**
1057	* Clears the FTM dirty indicator
1058	* @param a_pPage Pointer to the physical guest page tracking structure.
1059	*/
1060	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1061
1062	/**
1063	* Checks if the page was marked as dirty for FTM
1064	* @returns true/false.
1065	* @param a_pPage Pointer to the physical guest page tracking structure.
1066	*/
1067	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1068
1069
1070	/** @name PT usage values (PGMPAGE::u2PDEType).
1071	*
1072	* @{ */
1073	/** Either as a PT or PDE. */
1074	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1075	/** Must use a page table to map the range. */
1076	#define PGM_PAGE_PDE_TYPE_PT 1
1077	/** Can use a page directory entry to map the continuous range. */
1078	#define PGM_PAGE_PDE_TYPE_PDE 2
1079	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1080	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1081	/** @} */
1082
1083	/**
1084	* Set the PDE type of the page
1085	* @param a_pVM The VM handle, only used for lock ownership assertions.
1086	* @param a_pPage Pointer to the physical guest page tracking structure.
1087	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1088	*/
1089	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1090	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1091
1092	/**
1093	* Checks if the page was marked being part of a large page
1094	* @returns true/false.
1095	* @param a_pPage Pointer to the physical guest page tracking structure.
1096	*/
1097	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1098
1099	/** Enabled optimized access handler tests.
1100	* These optimizations makes ASSUMPTIONS about the state values and the s1
1101	* layout. When enabled, the compiler should normally generate more compact
1102	* code.
1103	*/
1104	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1105
1106	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1107	*
1108	* @remarks The values are assigned in order of priority, so we can calculate
1109	* the correct state for a page with different handlers installed.
1110	* @{ */
1111	/** No handler installed. */
1112	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1113	/** Monitoring is temporarily disabled. */
1114	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1115	/** Write access is monitored. */
1116	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1117	/** All access is monitored. */
1118	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1119	/** @} */
1120
1121	/**
1122	* Gets the physical access handler state of a page.
1123	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1124	* @param a_pPage Pointer to the physical guest page tracking structure.
1125	*/
1126	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1127
1128	/**
1129	* Sets the physical access handler state of a page.
1130	* @param a_pPage Pointer to the physical guest page tracking structure.
1131	* @param a_uState The new state value.
1132	*/
1133	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1134	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1135
1136	/**
1137	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1138	* @returns true/false
1139	* @param a_pPage Pointer to the physical guest page tracking structure.
1140	*/
1141	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1142	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1143
1144	/**
1145	* Checks if the page has any active physical access handlers.
1146	* @returns true/false
1147	* @param a_pPage Pointer to the physical guest page tracking structure.
1148	*/
1149	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1150	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1151
1152
1153	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1154	*
1155	* @remarks The values are assigned in order of priority, so we can calculate
1156	* the correct state for a page with different handlers installed.
1157	* @{ */
1158	/** No handler installed. */
1159	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1160	/* 1 is reserved so the lineup is identical with the physical ones. */
1161	/** Write access is monitored. */
1162	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1163	/** All access is monitored. */
1164	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1165	/** @} */
1166
1167	/**
1168	* Gets the virtual access handler state of a page.
1169	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1170	* @param a_pPage Pointer to the physical guest page tracking structure.
1171	*/
1172	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1173
1174	/**
1175	* Sets the virtual access handler state of a page.
1176	* @param a_pPage Pointer to the physical guest page tracking structure.
1177	* @param a_uState The new state value.
1178	*/
1179	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1180	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1181
1182	/**
1183	* Checks if the page has any virtual access handlers.
1184	* @returns true/false
1185	* @param a_pPage Pointer to the physical guest page tracking structure.
1186	*/
1187	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1188	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1189
1190	/**
1191	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1192	* virtual handlers.
1193	* @returns true/false
1194	* @param a_pPage Pointer to the physical guest page tracking structure.
1195	*/
1196	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1197	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1198
1199
1200	/**
1201	* Checks if the page has any access handlers, including temporarily disabled ones.
1202	* @returns true/false
1203	* @param a_pPage Pointer to the physical guest page tracking structure.
1204	*/
1205	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1206	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1207	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1208	#else
1209	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1210	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1211	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1212	#endif
1213
1214	/**
1215	* Checks if the page has any active access handlers.
1216	* @returns true/false
1217	* @param a_pPage Pointer to the physical guest page tracking structure.
1218	*/
1219	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1220	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1221	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1222	#else
1223	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1224	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1225	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1226	#endif
1227
1228	/**
1229	* Checks if the page has any active access handlers catching all accesses.
1230	* @returns true/false
1231	* @param a_pPage Pointer to the physical guest page tracking structure.
1232	*/
1233	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1234	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1235	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1236	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1237	#else
1238	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1239	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1240	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1241	#endif
1242
1243
1244	/** @def PGM_PAGE_GET_TRACKING
1245	* Gets the packed shadow page pool tracking data associated with a guest page.
1246	* @returns uint16_t containing the data.
1247	* @param a_pPage Pointer to the physical guest page tracking structure.
1248	*/
1249	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1250	#if defined(__GNUC__) && defined(VBOX_STRICT)
1251	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1252	#else
1253	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1254	#endif
1255
1256	/** @def PGM_PAGE_SET_TRACKING
1257	* Sets the packed shadow page pool tracking data associated with a guest page.
1258	* @param a_pVM The VM handle, only used for lock ownership assertions.
1259	* @param a_pPage Pointer to the physical guest page tracking structure.
1260	* @param a_u16TrackingData The tracking data to store.
1261	*/
1262	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1263	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1264
1265	/** @def PGM_PAGE_GET_TD_CREFS
1266	* Gets the @a cRefs tracking data member.
1267	* @returns cRefs.
1268	* @param a_pPage Pointer to the physical guest page tracking structure.
1269	*/
1270	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1271	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1272	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1273	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1274
1275	/** @def PGM_PAGE_GET_TD_IDX
1276	* Gets the @a idx tracking data member.
1277	* @returns idx.
1278	* @param a_pPage Pointer to the physical guest page tracking structure.
1279	*/
1280	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1281	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1282	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1283	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1284
1285
1286	/** Max number of locks on a page. */
1287	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1288
1289	/** Get the read lock count.
1290	* @returns count.
1291	* @param a_pPage Pointer to the physical guest page tracking structure.
1292	*/
1293	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1294
1295	/** Get the write lock count.
1296	* @returns count.
1297	* @param a_pPage Pointer to the physical guest page tracking structure.
1298	*/
1299	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1300
1301	/** Decrement the read lock counter.
1302	* @param a_pPage Pointer to the physical guest page tracking structure.
1303	*/
1304	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1305
1306	/** Decrement the write lock counter.
1307	* @param a_pPage Pointer to the physical guest page tracking structure.
1308	*/
1309	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1310
1311	/** Increment the read lock counter.
1312	* @param a_pPage Pointer to the physical guest page tracking structure.
1313	*/
1314	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1315
1316	/** Increment the write lock counter.
1317	* @param a_pPage Pointer to the physical guest page tracking structure.
1318	*/
1319	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1320
1321
1322	#if 0
1323	/** Enables sanity checking of write monitoring using CRC-32. */
1324	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1325	#endif
1326
1327	/**
1328	* Per page live save tracking data.
1329	*/
1330	typedef struct PGMLIVESAVERAMPAGE
1331	{
1332	/** Number of times it has been dirtied. */
1333	uint32_t cDirtied : 24;
1334	/** Whether it is currently dirty. */
1335	uint32_t fDirty : 1;
1336	/** Ignore the page.
1337	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1338	* deal with these after pausing the VM and DevPCI have said it bit about
1339	* remappings. */
1340	uint32_t fIgnore : 1;
1341	/** Was a ZERO page last time around. */
1342	uint32_t fZero : 1;
1343	/** Was a SHARED page last time around. */
1344	uint32_t fShared : 1;
1345	/** Whether the page is/was write monitored in a previous pass. */
1346	uint32_t fWriteMonitored : 1;
1347	/** Whether the page is/was write monitored earlier in this pass. */
1348	uint32_t fWriteMonitoredJustNow : 1;
1349	/** Bits reserved for future use. */
1350	uint32_t u2Reserved : 2;
1351	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1352	/** CRC-32 for the page. This is for internal consistency checks. */
1353	uint32_t u32Crc;
1354	#endif
1355	} PGMLIVESAVERAMPAGE;
1356	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1357	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1358	#else
1359	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1360	#endif
1361	/** Pointer to the per page live save tracking data. */
1362	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1363
1364	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1365	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1366
1367
1368	/**
1369	* RAM range for GC Phys to HC Phys conversion.
1370	*
1371	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1372	* conversions too, but we'll let MM handle that for now.
1373	*
1374	* This structure is used by linked lists in both GC and HC.
1375	*/
1376	typedef struct PGMRAMRANGE
1377	{
1378	/** Start of the range. Page aligned. */
1379	RTGCPHYS GCPhys;
1380	/** Size of the range. (Page aligned of course). */
1381	RTGCPHYS cb;
1382	/** Pointer to the next RAM range - for R3. */
1383	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1384	/** Pointer to the next RAM range - for R0. */
1385	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1386	/** Pointer to the next RAM range - for RC. */
1387	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1388	/** PGM_RAM_RANGE_FLAGS_* flags. */
1389	uint32_t fFlags;
1390	/** Last address in the range (inclusive). Page aligned (-1). */
1391	RTGCPHYS GCPhysLast;
1392	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1393	R3PTRTYPE(void *) pvR3;
1394	/** Live save per page tracking data. */
1395	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1396	/** The range description. */
1397	R3PTRTYPE(const char *) pszDesc;
1398	/** Pointer to self - R0 pointer. */
1399	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1400	/** Pointer to self - RC pointer. */
1401	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1402
1403	/** Alignment padding. */
1404	RTRCPTR Alignment0;
1405	/** Pointer to the left search three node - ring-3 context. */
1406	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1407	/** Pointer to the right search three node - ring-3 context. */
1408	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1409	/** Pointer to the left search three node - ring-0 context. */
1410	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1411	/** Pointer to the right search three node - ring-0 context. */
1412	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1413	/** Pointer to the left search three node - raw-mode context. */
1414	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1415	/** Pointer to the right search three node - raw-mode context. */
1416	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1417
1418	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1419	#if HC_ARCH_BITS == 32
1420	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1421	#endif
1422	/** Array of physical guest page tracking structures. */
1423	PGMPAGE aPages[1];
1424	} PGMRAMRANGE;
1425	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1426	typedef PGMRAMRANGE *PPGMRAMRANGE;
1427
1428	/** @name PGMRAMRANGE::fFlags
1429	* @{ */
1430	/** The RAM range is floating around as an independent guest mapping. */
1431	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1432	/** Ad hoc RAM range for an ROM mapping. */
1433	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1434	/** Ad hoc RAM range for an MMIO mapping. */
1435	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1436	/** Ad hoc RAM range for an MMIO2 mapping. */
1437	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1438	/** @} */
1439
1440	/** Tests if a RAM range is an ad hoc one or not.
1441	* @returns true/false.
1442	* @param pRam The RAM range.
1443	*/
1444	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1445	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1446
1447	/** The number of entries in the RAM range TLBs (there is one for each
1448	* context). Must be a power of two. */
1449	#define PGM_RAMRANGE_TLB_ENTRIES 8
1450
1451	/**
1452	* Calculates the RAM range TLB index for the physical address.
1453	*
1454	* @returns RAM range TLB index.
1455	* @param GCPhys The guest physical address.
1456	*/
1457	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1458
1459
1460
1461	/**
1462	* Per page tracking structure for ROM image.
1463	*
1464	* A ROM image may have a shadow page, in which case we may have two pages
1465	* backing it. This structure contains the PGMPAGE for both while
1466	* PGMRAMRANGE have a copy of the active one. It is important that these
1467	* aren't out of sync in any regard other than page pool tracking data.
1468	*/
1469	typedef struct PGMROMPAGE
1470	{
1471	/** The page structure for the virgin ROM page. */
1472	PGMPAGE Virgin;
1473	/** The page structure for the shadow RAM page. */
1474	PGMPAGE Shadow;
1475	/** The current protection setting. */
1476	PGMROMPROT enmProt;
1477	/** Live save status information. Makes use of unused alignment space. */
1478	struct
1479	{
1480	/** The previous protection value. */
1481	uint8_t u8Prot;
1482	/** Written to flag set by the handler. */
1483	bool fWrittenTo;
1484	/** Whether the shadow page is dirty or not. */
1485	bool fDirty;
1486	/** Whether it was dirtied in the recently. */
1487	bool fDirtiedRecently;
1488	} LiveSave;
1489	} PGMROMPAGE;
1490	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1491	/** Pointer to a ROM page tracking structure. */
1492	typedef PGMROMPAGE *PPGMROMPAGE;
1493
1494
1495	/**
1496	* A registered ROM image.
1497	*
1498	* This is needed to keep track of ROM image since they generally intrude
1499	* into a PGMRAMRANGE. It also keeps track of additional info like the
1500	* two page sets (read-only virgin and read-write shadow), the current
1501	* state of each page.
1502	*
1503	* Because access handlers cannot easily be executed in a different
1504	* context, the ROM ranges needs to be accessible and in all contexts.
1505	*/
1506	typedef struct PGMROMRANGE
1507	{
1508	/** Pointer to the next range - R3. */
1509	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1510	/** Pointer to the next range - R0. */
1511	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1512	/** Pointer to the next range - RC. */
1513	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1514	/** Pointer alignment */
1515	RTRCPTR RCPtrAlignment;
1516	/** Address of the range. */
1517	RTGCPHYS GCPhys;
1518	/** Address of the last byte in the range. */
1519	RTGCPHYS GCPhysLast;
1520	/** Size of the range. */
1521	RTGCPHYS cb;
1522	/** The flags (PGMPHYS_ROM_FLAGS_). /
1523	uint32_t fFlags;
1524	/** The saved state range ID. */
1525	uint8_t idSavedState;
1526	/** Alignment padding. */
1527	uint8_t au8Alignment[3];
1528	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1529	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1530	/** The size bits pvOriginal points to. */
1531	uint32_t cbOriginal;
1532	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1533	* This is used for strictness checks. */
1534	R3PTRTYPE(const void *) pvOriginal;
1535	/** The ROM description. */
1536	R3PTRTYPE(const char *) pszDesc;
1537	/** The per page tracking structures. */
1538	PGMROMPAGE aPages[1];
1539	} PGMROMRANGE;
1540	/** Pointer to a ROM range. */
1541	typedef PGMROMRANGE *PPGMROMRANGE;
1542
1543
1544	/**
1545	* Live save per page data for an MMIO2 page.
1546	*
1547	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1548	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1549	* CRC-32 for detecting changes as well as special handling of zero pages. This
1550	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1551	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1552	* because of speed (2.5x and 6x slower).)
1553	*
1554	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1555	* save but normally is disabled. Since we can write monitor guest
1556	* accesses on our own, we only need this for host accesses. Shouldn't be
1557	* too difficult for DevVGA, VMMDev might be doable, the planned
1558	* networking fun will be fun since it involves ring-0.
1559	*/
1560	typedef struct PGMLIVESAVEMMIO2PAGE
1561	{
1562	/** Set if the page is considered dirty. */
1563	bool fDirty;
1564	/** The number of scans this page has remained unchanged for.
1565	* Only updated for dirty pages. */
1566	uint8_t cUnchangedScans;
1567	/** Whether this page was zero at the last scan. */
1568	bool fZero;
1569	/** Alignment padding. */
1570	bool fReserved;
1571	/** CRC-32 for the first half of the page.
1572	* This is used together with u32CrcH2 to quickly detect changes in the page
1573	* during the non-final passes. */
1574	uint32_t u32CrcH1;
1575	/** CRC-32 for the second half of the page. */
1576	uint32_t u32CrcH2;
1577	/** SHA-1 for the saved page.
1578	* This is used in the final pass to skip pages without changes. */
1579	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1580	} PGMLIVESAVEMMIO2PAGE;
1581	/** Pointer to a live save status data for an MMIO2 page. */
1582	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1583
1584	/**
1585	* A registered MMIO2 (= Device RAM) range.
1586	*
1587	* There are a few reason why we need to keep track of these
1588	* registrations. One of them is the deregistration & cleanup stuff,
1589	* while another is that the PGMRAMRANGE associated with such a region may
1590	* have to be removed from the ram range list.
1591	*
1592	* Overlapping with a RAM range has to be 100% or none at all. The pages
1593	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1594	* will be raised if a partial overlap or an overlap of ROM pages is
1595	* encountered. On an overlap we will free all the existing RAM pages and
1596	* put in the ram range pages instead.
1597	*/
1598	typedef struct PGMMMIO2RANGE
1599	{
1600	/** The owner of the range. (a device) */
1601	PPDMDEVINSR3 pDevInsR3;
1602	/** Pointer to the ring-3 mapping of the allocation. */
1603	RTR3PTR pvR3;
1604	/** Pointer to the next range - R3. */
1605	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1606	/** Whether it's mapped or not. */
1607	bool fMapped;
1608	/** Whether it's overlapping or not. */
1609	bool fOverlapping;
1610	/** The PCI region number.
1611	* @remarks This ASSUMES that nobody will ever really need to have multiple
1612	* PCI devices with matching MMIO region numbers on a single device. */
1613	uint8_t iRegion;
1614	/** The saved state range ID. */
1615	uint8_t idSavedState;
1616	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1617	uint8_t idMmio2;
1618	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1619	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1620	/** Live save per page tracking data. */
1621	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1622	/** The associated RAM range. */
1623	PGMRAMRANGE RamRange;
1624	} PGMMMIO2RANGE;
1625	/** Pointer to a MMIO2 range. */
1626	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1627
1628	/** @name Intenal MMIO2 constants.
1629	* @{ */
1630	/** The maximum number of MMIO2 ranges. */
1631	#define PGM_MMIO2_MAX_RANGES 8
1632	/** The maximum number of pages in a MMIO2 range. */
1633	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1634	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1635	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1636	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1637	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1638	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1639	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1640	/** @} */
1641
1642
1643
1644	/**
1645	* PGMPhysRead/Write cache entry
1646	*/
1647	typedef struct PGMPHYSCACHEENTRY
1648	{
1649	/** R3 pointer to physical page. */
1650	R3PTRTYPE(uint8_t *) pbR3;
1651	/** GC Physical address for cache entry */
1652	RTGCPHYS GCPhys;
1653	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1654	RTGCPHYS u32Padding0; /*< alignment padding. /
1655	#endif
1656	} PGMPHYSCACHEENTRY;
1657
1658	/**
1659	* PGMPhysRead/Write cache to reduce REM memory access overhead
1660	*/
1661	typedef struct PGMPHYSCACHE
1662	{
1663	/** Bitmap of valid cache entries */
1664	uint64_t aEntries;
1665	/** Cache entries */
1666	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1667	} PGMPHYSCACHE;
1668
1669
1670	/** Pointer to an allocation chunk ring-3 mapping. */
1671	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1672	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1673	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1674
1675	/**
1676	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1677	*
1678	* The primary tree (Core) uses the chunk id as key.
1679	*/
1680	typedef struct PGMCHUNKR3MAP
1681	{
1682	/** The key is the chunk id. */
1683	AVLU32NODECORE Core;
1684	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1685	* selection. */
1686	uint32_t iLastUsed;
1687	/** The current reference count. */
1688	uint32_t volatile cRefs;
1689	/** The current permanent reference count. */
1690	uint32_t volatile cPermRefs;
1691	/** The mapping address. */
1692	void *pv;
1693	} PGMCHUNKR3MAP;
1694
1695	/**
1696	* Allocation chunk ring-3 mapping TLB entry.
1697	*/
1698	typedef struct PGMCHUNKR3MAPTLBE
1699	{
1700	/** The chunk id. */
1701	uint32_t volatile idChunk;
1702	#if HC_ARCH_BITS == 64
1703	uint32_t u32Padding; /*< alignment padding. /
1704	#endif
1705	/** The chunk map. */
1706	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1707	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1708	#else
1709	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1710	#endif
1711	} PGMCHUNKR3MAPTLBE;
1712	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1713	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1714
1715	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1716	* @remark Must be a power of two value. */
1717	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1718
1719	/**
1720	* Allocation chunk ring-3 mapping TLB.
1721	*
1722	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1723	* At first glance this might look kinda odd since AVL trees are
1724	* supposed to give the most optimal lookup times of all trees
1725	* due to their balancing. However, take a tree with 1023 nodes
1726	* in it, that's 10 levels, meaning that most searches has to go
1727	* down 9 levels before they find what they want. This isn't fast
1728	* compared to a TLB hit. There is the factor of cache misses,
1729	* and of course the problem with trees and branch prediction.
1730	* This is why we use TLBs in front of most of the trees.
1731	*
1732	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1733	* difficult when we switch to the new inlined AVL trees (from kStuff).
1734	*/
1735	typedef struct PGMCHUNKR3MAPTLB
1736	{
1737	/** The TLB entries. */
1738	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1739	} PGMCHUNKR3MAPTLB;
1740
1741	/**
1742	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1743	* @returns Chunk TLB index.
1744	* @param idChunk The Chunk ID.
1745	*/
1746	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1747
1748
1749	/**
1750	* Ring-3 guest page mapping TLB entry.
1751	* @remarks used in ring-0 as well at the moment.
1752	*/
1753	typedef struct PGMPAGER3MAPTLBE
1754	{
1755	/** Address of the page. */
1756	RTGCPHYS volatile GCPhys;
1757	/** The guest page. */
1758	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1759	R3PTRTYPE(PPGMPAGE) volatile pPage;
1760	#else
1761	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1762	#endif
1763	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1764	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1765	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1766	#else
1767	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1768	#endif
1769	/** The address */
1770	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1771	R3PTRTYPE(void *) volatile pv;
1772	#else
1773	R3R0PTRTYPE(void *) volatile pv;
1774	#endif
1775	#if HC_ARCH_BITS == 32
1776	uint32_t u32Padding; /*< alignment padding. /
1777	#endif
1778	} PGMPAGER3MAPTLBE;
1779	/** Pointer to an entry in the HC physical TLB. */
1780	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1781
1782
1783	/** The number of entries in the ring-3 guest page mapping TLB.
1784	* @remarks The value must be a power of two. */
1785	#define PGM_PAGER3MAPTLB_ENTRIES 256
1786
1787	/**
1788	* Ring-3 guest page mapping TLB.
1789	* @remarks used in ring-0 as well at the moment.
1790	*/
1791	typedef struct PGMPAGER3MAPTLB
1792	{
1793	/** The TLB entries. */
1794	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1795	} PGMPAGER3MAPTLB;
1796	/** Pointer to the ring-3 guest page mapping TLB. */
1797	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1798
1799	/**
1800	* Calculates the index of the TLB entry for the specified guest page.
1801	* @returns Physical TLB index.
1802	* @param GCPhys The guest physical address.
1803	*/
1804	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1805
1806
1807	/**
1808	* Raw-mode context dynamic mapping cache entry.
1809	*
1810	* Because of raw-mode context being reloctable and all relocations are applied
1811	* in ring-3, this has to be defined here and be RC specific.
1812	*
1813	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1814	*/
1815	typedef struct PGMRCDYNMAPENTRY
1816	{
1817	/** The physical address of the currently mapped page.
1818	* This is duplicate for three reasons: cache locality, cache policy of the PT
1819	* mappings and sanity checks. */
1820	RTHCPHYS HCPhys;
1821	/** Pointer to the page. */
1822	RTRCPTR pvPage;
1823	/** The number of references. */
1824	int32_t volatile cRefs;
1825	/** PTE pointer union. */
1826	struct PGMRCDYNMAPENTRY_PPTE
1827	{
1828	/** PTE pointer, 32-bit legacy version. */
1829	RCPTRTYPE(PX86PTE) pLegacy;
1830	/** PTE pointer, PAE version. */
1831	RCPTRTYPE(PX86PTEPAE) pPae;
1832	} uPte;
1833	} PGMRCDYNMAPENTRY;
1834	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1835	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1836
1837
1838	/**
1839	* Dynamic mapping cache for the raw-mode context.
1840	*
1841	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1842	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1843	* so that we can perform relocations from PGMR3Relocate. This has the
1844	* consequence that we must have separate ring-0 and raw-mode context versions
1845	* of this struct even if they share the basic elements.
1846	*
1847	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1848	*/
1849	typedef struct PGMRCDYNMAP
1850	{
1851	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1852	uint32_t u32Magic;
1853	/** Array for tracking and managing the pages. */
1854	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1855	/** The cache size given as a number of pages. */
1856	uint32_t cPages;
1857	/** The current load.
1858	* This does not include guard pages. */
1859	uint32_t cLoad;
1860	/** The max load ever.
1861	* This is maintained to get trigger adding of more mapping space. */
1862	uint32_t cMaxLoad;
1863	/** The number of guard pages. */
1864	uint32_t cGuardPages;
1865	/** The number of users (protected by hInitLock). */
1866	uint32_t cUsers;
1867	} PGMRCDYNMAP;
1868	/** Pointer to the dynamic cache for the raw-mode context. */
1869	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1870
1871
1872	/**
1873	* Mapping cache usage set entry.
1874	*
1875	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1876	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1877	* cache. If it's extended to include ring-3, well, then something
1878	* will have be changed here...
1879	*/
1880	typedef struct PGMMAPSETENTRY
1881	{
1882	/** Pointer to the page. */
1883	#ifndef IN_RC
1884	RTR0PTR pvPage;
1885	#else
1886	RTRCPTR pvPage;
1887	# if HC_ARCH_BITS == 64
1888	uint32_t u32Alignment2;
1889	# endif
1890	#endif
1891	/** The mapping cache index. */
1892	uint16_t iPage;
1893	/** The number of references.
1894	* The max is UINT16_MAX - 1. */
1895	uint16_t cRefs;
1896	/** The number inlined references.
1897	* The max is UINT16_MAX - 1. */
1898	uint16_t cInlinedRefs;
1899	/** Unreferences. */
1900	uint16_t cUnrefs;
1901
1902	#if HC_ARCH_BITS == 32
1903	uint32_t u32Alignment1;
1904	#endif
1905	/** The physical address for this entry. */
1906	RTHCPHYS HCPhys;
1907	} PGMMAPSETENTRY;
1908	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1909	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1910	/** Pointer to a mapping cache usage set entry. */
1911	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1912
1913	/**
1914	* Mapping cache usage set.
1915	*
1916	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1917	* done during exits / traps. The set is
1918	*/
1919	typedef struct PGMMAPSET
1920	{
1921	/** The number of occupied entries.
1922	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1923	* dynamic mappings. */
1924	uint32_t cEntries;
1925	/** The start of the current subset.
1926	* This is UINT32_MAX if no subset is currently open. */
1927	uint32_t iSubset;
1928	/** The index of the current CPU, only valid if the set is open. */
1929	int32_t iCpu;
1930	uint32_t alignment;
1931	/** The entries. */
1932	PGMMAPSETENTRY aEntries[64];
1933	/** HCPhys -> iEntry fast lookup table.
1934	* Use PGMMAPSET_HASH for hashing.
1935	* The entries may or may not be valid, check against cEntries. */
1936	uint8_t aiHashTable[128];
1937	} PGMMAPSET;
1938	AssertCompileSizeAlignment(PGMMAPSET, 8);
1939	/** Pointer to the mapping cache set. */
1940	typedef PGMMAPSET *PPGMMAPSET;
1941
1942	/** PGMMAPSET::cEntries value for a closed set. */
1943	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1944
1945	/** Hash function for aiHashTable. */
1946	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1947
1948
1949	/** @name Context neutral page mapper TLB.
1950	*
1951	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1952	* code is writting in a kind of context neutral way. Time will show whether
1953	* this actually makes sense or not...
1954	*
1955	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1956	* context ends up using a global mapping cache on some platforms
1957	* (darwin).
1958	*
1959	* @{ */
1960	/** @typedef PPGMPAGEMAPTLB
1961	* The page mapper TLB pointer type for the current context. */
1962	/** @typedef PPGMPAGEMAPTLB
1963	* The page mapper TLB entry pointer type for the current context. */
1964	/** @typedef PPGMPAGEMAPTLB
1965	* The page mapper TLB entry pointer pointer type for the current context. */
1966	/** @def PGM_PAGEMAPTLB_ENTRIES
1967	* The number of TLB entries in the page mapper TLB for the current context. */
1968	/** @def PGM_PAGEMAPTLB_IDX
1969	* Calculate the TLB index for a guest physical address.
1970	* @returns The TLB index.
1971	* @param GCPhys The guest physical address. */
1972	/** @typedef PPGMPAGEMAP
1973	* Pointer to a page mapper unit for current context. */
1974	/** @typedef PPPGMPAGEMAP
1975	* Pointer to a page mapper unit pointer for current context. */
1976	#ifdef IN_RC
1977	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1978	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1979	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1980	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1981	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1982	typedef void * PPGMPAGEMAP;
1983	typedef void ** PPPGMPAGEMAP;
1984	//#elif IN_RING0
1985	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1986	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1987	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1988	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1989	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1990	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1991	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1992	#else
1993	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1994	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1995	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1996	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1997	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1998	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1999	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2000	#endif
2001	/** @} */
2002
2003
2004	/** @name PGM Pool Indexes.
2005	* Aka. the unique shadow page identifier.
2006	* @{ */
2007	/** NIL page pool IDX. */
2008	#define NIL_PGMPOOL_IDX 0
2009	/** The first normal index. There used to be 5 fictive pages up front, now
2010	* there is only the NIL page. */
2011	#define PGMPOOL_IDX_FIRST 1
2012	/** The last valid index. (inclusive, 14 bits) */
2013	#define PGMPOOL_IDX_LAST 0x3fff
2014	/** @} */
2015
2016	/** The NIL index for the parent chain. */
2017	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2018	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2019
2020	/**
2021	* Node in the chain linking a shadowed page to it's parent (user).
2022	*/
2023	#pragma pack(1)
2024	typedef struct PGMPOOLUSER
2025	{
2026	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2027	uint16_t iNext;
2028	/** The user page index. */
2029	uint16_t iUser;
2030	/** Index into the user table. */
2031	uint32_t iUserTable;
2032	} PGMPOOLUSER, *PPGMPOOLUSER;
2033	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2034	#pragma pack()
2035
2036
2037	/** The NIL index for the phys ext chain. */
2038	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2039	/** The NIL pte index for a phys ext chain slot. */
2040	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2041
2042	/**
2043	* Node in the chain of physical cross reference extents.
2044	* @todo Calling this an 'extent' is not quite right, find a better name.
2045	* @todo find out the optimal size of the aidx array
2046	*/
2047	#pragma pack(1)
2048	typedef struct PGMPOOLPHYSEXT
2049	{
2050	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2051	uint16_t iNext;
2052	/** Alignment. */
2053	uint16_t u16Align;
2054	/** The user page index. */
2055	uint16_t aidx[3];
2056	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2057	uint16_t apte[3];
2058	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2059	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2060	#pragma pack()
2061
2062
2063	/**
2064	* The kind of page that's being shadowed.
2065	*/
2066	typedef enum PGMPOOLKIND
2067	{
2068	/** The virtual invalid 0 entry. */
2069	PGMPOOLKIND_INVALID = 0,
2070	/** The entry is free (=unused). */
2071	PGMPOOLKIND_FREE,
2072
2073	/** Shw: 32-bit page table; Gst: no paging */
2074	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2075	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2076	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2077	/** Shw: 32-bit page table; Gst: 4MB page. */
2078	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2079	/** Shw: PAE page table; Gst: no paging */
2080	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2081	/** Shw: PAE page table; Gst: 32-bit page table. */
2082	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2083	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2084	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2085	/** Shw: PAE page table; Gst: PAE page table. */
2086	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2087	/** Shw: PAE page table; Gst: 2MB page. */
2088	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2089
2090	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2091	PGMPOOLKIND_32BIT_PD,
2092	/** Shw: 32-bit page directory. Gst: no paging. */
2093	PGMPOOLKIND_32BIT_PD_PHYS,
2094	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2095	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2096	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2097	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2098	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2099	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2100	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2101	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2102	/** Shw: PAE page directory; Gst: PAE page directory. */
2103	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2104	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2105	PGMPOOLKIND_PAE_PD_PHYS,
2106
2107	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2108	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2109	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2110	PGMPOOLKIND_PAE_PDPT,
2111	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2112	PGMPOOLKIND_PAE_PDPT_PHYS,
2113
2114	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2115	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2116	/** Shw: 64-bit page directory pointer table; Gst: no paging */
2117	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2118	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2119	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2120	/** Shw: 64-bit page directory table; Gst: no paging */
2121	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2122
2123	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2124	PGMPOOLKIND_64BIT_PML4,
2125
2126	/** Shw: EPT page directory pointer table; Gst: no paging */
2127	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2128	/** Shw: EPT page directory table; Gst: no paging */
2129	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2130	/** Shw: EPT page table; Gst: no paging */
2131	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2132
2133	/** Shw: Root Nested paging table. */
2134	PGMPOOLKIND_ROOT_NESTED,
2135
2136	/** The last valid entry. */
2137	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2138	} PGMPOOLKIND;
2139
2140	/**
2141	* The access attributes of the page; only applies to big pages.
2142	*/
2143	typedef enum
2144	{
2145	PGMPOOLACCESS_DONTCARE = 0,
2146	PGMPOOLACCESS_USER_RW,
2147	PGMPOOLACCESS_USER_R,
2148	PGMPOOLACCESS_USER_RW_NX,
2149	PGMPOOLACCESS_USER_R_NX,
2150	PGMPOOLACCESS_SUPERVISOR_RW,
2151	PGMPOOLACCESS_SUPERVISOR_R,
2152	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2153	PGMPOOLACCESS_SUPERVISOR_R_NX
2154	} PGMPOOLACCESS;
2155
2156	/**
2157	* The tracking data for a page in the pool.
2158	*/
2159	typedef struct PGMPOOLPAGE
2160	{
2161	/** AVL node code with the (HC) physical address of this page. */
2162	AVLOHCPHYSNODECORE Core;
2163	/** Pointer to the R3 mapping of the page. */
2164	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2165	R3PTRTYPE(void *) pvPageR3;
2166	#else
2167	R3R0PTRTYPE(void *) pvPageR3;
2168	#endif
2169	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2170	uint32_t Alignment0;
2171	#endif
2172	/** The guest physical address. */
2173	RTGCPHYS GCPhys;
2174	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2175	uint8_t enmKind;
2176	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2177	uint8_t enmAccess;
2178	/** This supplements enmKind and enmAccess */
2179	bool fA20Enabled : 1;
2180
2181	/** Used to indicate that the page is zeroed. */
2182	bool fZeroed : 1;
2183	/** Used to indicate that a PT has non-global entries. */
2184	bool fSeenNonGlobal : 1;
2185	/** Used to indicate that we're monitoring writes to the guest page. */
2186	bool fMonitored : 1;
2187	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2188	* (All pages are in the age list.) */
2189	bool fCached : 1;
2190	/** This is used by the R3 access handlers when invoked by an async thread.
2191	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2192	bool volatile fReusedFlushPending : 1;
2193	/** Used to mark the page as dirty (write monitoring is temporarily
2194	* off). */
2195	bool fDirty : 1;
2196	bool fPadding1 : 1;
2197	bool fPadding2;
2198
2199	/** The index of this page. */
2200	uint16_t idx;
2201	/** The next entry in the list this page currently resides in.
2202	* It's either in the free list or in the GCPhys hash. */
2203	uint16_t iNext;
2204	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2205	uint16_t iUserHead;
2206	/** The number of present entries. */
2207	uint16_t cPresent;
2208	/** The first entry in the table which is present. */
2209	uint16_t iFirstPresent;
2210	/** The number of modifications to the monitored page. */
2211	uint16_t cModifications;
2212	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2213	uint16_t iModifiedNext;
2214	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2215	uint16_t iModifiedPrev;
2216	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2217	uint16_t iMonitoredNext;
2218	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2219	uint16_t iMonitoredPrev;
2220	/** The next page in the age list. */
2221	uint16_t iAgeNext;
2222	/** The previous page in the age list. */
2223	uint16_t iAgePrev;
2224	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2225	uint8_t idxDirtyEntry;
2226
2227	/** @name Access handler statistics to determine whether the guest is
2228	* (re)initializing a page table.
2229	* @{ */
2230	RTGCPTR GCPtrLastAccessHandlerRip;
2231	RTGCPTR GCPtrLastAccessHandlerFault;
2232	uint64_t cLastAccessHandler;
2233	/** @} */
2234	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2235	uint32_t volatile cLocked;
2236	#if GC_ARCH_BITS == 64
2237	uint32_t u32Alignment3;
2238	#endif
2239	# ifdef VBOX_STRICT
2240	RTGCPTR GCPtrDirtyFault;
2241	# endif
2242	} PGMPOOLPAGE;
2243	/** Pointer to a pool page. */
2244	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2245	/** Pointer to a const pool page. */
2246	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2247	/** Pointer to a pool page pointer. */
2248	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2249
2250
2251	/** The hash table size. */
2252	# define PGMPOOL_HASH_SIZE 0x40
2253	/** The hash function. */
2254	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2255
2256
2257	/**
2258	* The shadow page pool instance data.
2259	*
2260	* It's all one big allocation made at init time, except for the
2261	* pages that is. The user nodes follows immediately after the
2262	* page structures.
2263	*/
2264	typedef struct PGMPOOL
2265	{
2266	/** The VM handle - R3 Ptr. */
2267	PVMR3 pVMR3;
2268	/** The VM handle - R0 Ptr. */
2269	PVMR0 pVMR0;
2270	/** The VM handle - RC Ptr. */
2271	PVMRC pVMRC;
2272	/** The max pool size. This includes the special IDs. */
2273	uint16_t cMaxPages;
2274	/** The current pool size. */
2275	uint16_t cCurPages;
2276	/** The head of the free page list. */
2277	uint16_t iFreeHead;
2278	/* Padding. */
2279	uint16_t u16Padding;
2280	/** Head of the chain of free user nodes. */
2281	uint16_t iUserFreeHead;
2282	/** The number of user nodes we've allocated. */
2283	uint16_t cMaxUsers;
2284	/** The number of present page table entries in the entire pool. */
2285	uint32_t cPresent;
2286	/** Pointer to the array of user nodes - RC pointer. */
2287	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2288	/** Pointer to the array of user nodes - R3 pointer. */
2289	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2290	/** Pointer to the array of user nodes - R0 pointer. */
2291	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2292	/** Head of the chain of free phys ext nodes. */
2293	uint16_t iPhysExtFreeHead;
2294	/** The number of user nodes we've allocated. */
2295	uint16_t cMaxPhysExts;
2296	/** Pointer to the array of physical xref extent - RC pointer. */
2297	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2298	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2299	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2300	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2301	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2302	/** Hash table for GCPhys addresses. */
2303	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2304	/** The head of the age list. */
2305	uint16_t iAgeHead;
2306	/** The tail of the age list. */
2307	uint16_t iAgeTail;
2308	/** Set if the cache is enabled. */
2309	bool fCacheEnabled;
2310	/** Alignment padding. */
2311	bool afPadding1[3];
2312	/** Head of the list of modified pages. */
2313	uint16_t iModifiedHead;
2314	/** The current number of modified pages. */
2315	uint16_t cModifiedPages;
2316	/** Access handler, RC. */
2317	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2318	/** Access handler, R0. */
2319	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2320	/** Access handler, R3. */
2321	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2322	/** The access handler description (R3 ptr). */
2323	R3PTRTYPE(const char *) pszAccessHandler;
2324	# if HC_ARCH_BITS == 32
2325	/** Alignment padding. */
2326	uint32_t u32Padding2;
2327	# endif
2328	/** Next available slot (in aDirtyPages). */
2329	uint32_t idxFreeDirtyPage;
2330	/** Number of active dirty pages. */
2331	uint32_t cDirtyPages;
2332	/** Array of current dirty pgm pool page indices. */
2333	struct
2334	{
2335	uint16_t uIdx;
2336	uint16_t Alignment[3];
2337	uint64_t aPage[512];
2338	} aDirtyPages[16];
2339	/** The number of pages currently in use. */
2340	uint16_t cUsedPages;
2341	#ifdef VBOX_WITH_STATISTICS
2342	/** The high water mark for cUsedPages. */
2343	uint16_t cUsedPagesHigh;
2344	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2345	/** Profiling pgmPoolAlloc(). */
2346	STAMPROFILEADV StatAlloc;
2347	/** Profiling pgmR3PoolClearDoIt(). */
2348	STAMPROFILE StatClearAll;
2349	/** Profiling pgmR3PoolReset(). */
2350	STAMPROFILE StatR3Reset;
2351	/** Profiling pgmPoolFlushPage(). */
2352	STAMPROFILE StatFlushPage;
2353	/** Profiling pgmPoolFree(). */
2354	STAMPROFILE StatFree;
2355	/** Counting explicit flushes by PGMPoolFlushPage(). */
2356	STAMCOUNTER StatForceFlushPage;
2357	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2358	STAMCOUNTER StatForceFlushDirtyPage;
2359	/** Counting flushes for reused pages. */
2360	STAMCOUNTER StatForceFlushReused;
2361	/** Profiling time spent zeroing pages. */
2362	STAMPROFILE StatZeroPage;
2363	/** Profiling of pgmPoolTrackDeref. */
2364	STAMPROFILE StatTrackDeref;
2365	/** Profiling pgmTrackFlushGCPhysPT. */
2366	STAMPROFILE StatTrackFlushGCPhysPT;
2367	/** Profiling pgmTrackFlushGCPhysPTs. */
2368	STAMPROFILE StatTrackFlushGCPhysPTs;
2369	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2370	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2371	/** Number of times we've been out of user records. */
2372	STAMCOUNTER StatTrackFreeUpOneUser;
2373	/** Nr of flushed entries. */
2374	STAMCOUNTER StatTrackFlushEntry;
2375	/** Nr of updated entries. */
2376	STAMCOUNTER StatTrackFlushEntryKeep;
2377	/** Profiling deref activity related tracking GC physical pages. */
2378	STAMPROFILE StatTrackDerefGCPhys;
2379	/** Number of linear searches for a HCPhys in the ram ranges. */
2380	STAMCOUNTER StatTrackLinearRamSearches;
2381	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2382	STAMCOUNTER StamTrackPhysExtAllocFailures;
2383	/** Profiling the RC/R0 access handler. */
2384	STAMPROFILE StatMonitorRZ;
2385	/** Times we've failed interpreting the instruction. */
2386	STAMCOUNTER StatMonitorRZEmulateInstr;
2387	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2388	STAMPROFILE StatMonitorRZFlushPage;
2389	/* Times we've detected a page table reinit. */
2390	STAMCOUNTER StatMonitorRZFlushReinit;
2391	/** Counting flushes for pages that are modified too often. */
2392	STAMCOUNTER StatMonitorRZFlushModOverflow;
2393	/** Times we've detected fork(). */
2394	STAMCOUNTER StatMonitorRZFork;
2395	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2396	STAMPROFILE StatMonitorRZHandled;
2397	/** Times we've failed interpreting a patch code instruction. */
2398	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2399	/** Times we've failed interpreting a patch code instruction during flushing. */
2400	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2401	/** The number of times we've seen rep prefixes we can't handle. */
2402	STAMCOUNTER StatMonitorRZRepPrefix;
2403	/** Profiling the REP STOSD cases we've handled. */
2404	STAMPROFILE StatMonitorRZRepStosd;
2405	/** Nr of handled PT faults. */
2406	STAMCOUNTER StatMonitorRZFaultPT;
2407	/** Nr of handled PD faults. */
2408	STAMCOUNTER StatMonitorRZFaultPD;
2409	/** Nr of handled PDPT faults. */
2410	STAMCOUNTER StatMonitorRZFaultPDPT;
2411	/** Nr of handled PML4 faults. */
2412	STAMCOUNTER StatMonitorRZFaultPML4;
2413
2414	/** Profiling the R3 access handler. */
2415	STAMPROFILE StatMonitorR3;
2416	/** Times we've failed interpreting the instruction. */
2417	STAMCOUNTER StatMonitorR3EmulateInstr;
2418	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2419	STAMPROFILE StatMonitorR3FlushPage;
2420	/* Times we've detected a page table reinit. */
2421	STAMCOUNTER StatMonitorR3FlushReinit;
2422	/** Counting flushes for pages that are modified too often. */
2423	STAMCOUNTER StatMonitorR3FlushModOverflow;
2424	/** Times we've detected fork(). */
2425	STAMCOUNTER StatMonitorR3Fork;
2426	/** Profiling the R3 access we've handled (except REP STOSD). */
2427	STAMPROFILE StatMonitorR3Handled;
2428	/** The number of times we've seen rep prefixes we can't handle. */
2429	STAMCOUNTER StatMonitorR3RepPrefix;
2430	/** Profiling the REP STOSD cases we've handled. */
2431	STAMPROFILE StatMonitorR3RepStosd;
2432	/** Nr of handled PT faults. */
2433	STAMCOUNTER StatMonitorR3FaultPT;
2434	/** Nr of handled PD faults. */
2435	STAMCOUNTER StatMonitorR3FaultPD;
2436	/** Nr of handled PDPT faults. */
2437	STAMCOUNTER StatMonitorR3FaultPDPT;
2438	/** Nr of handled PML4 faults. */
2439	STAMCOUNTER StatMonitorR3FaultPML4;
2440	/** The number of times we're called in an async thread an need to flush. */
2441	STAMCOUNTER StatMonitorR3Async;
2442	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2443	STAMCOUNTER StatResetDirtyPages;
2444	/** Times we've called pgmPoolAddDirtyPage. */
2445	STAMCOUNTER StatDirtyPage;
2446	/** Times we've had to flush duplicates for dirty page management. */
2447	STAMCOUNTER StatDirtyPageDupFlush;
2448	/** Times we've had to flush because of overflow. */
2449	STAMCOUNTER StatDirtyPageOverFlowFlush;
2450
2451	/** The high water mark for cModifiedPages. */
2452	uint16_t cModifiedPagesHigh;
2453	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2454
2455	/** The number of cache hits. */
2456	STAMCOUNTER StatCacheHits;
2457	/** The number of cache misses. */
2458	STAMCOUNTER StatCacheMisses;
2459	/** The number of times we've got a conflict of 'kind' in the cache. */
2460	STAMCOUNTER StatCacheKindMismatches;
2461	/** Number of times we've been out of pages. */
2462	STAMCOUNTER StatCacheFreeUpOne;
2463	/** The number of cacheable allocations. */
2464	STAMCOUNTER StatCacheCacheable;
2465	/** The number of uncacheable allocations. */
2466	STAMCOUNTER StatCacheUncacheable;
2467	#else
2468	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2469	#endif
2470	/** The AVL tree for looking up a page by its HC physical address. */
2471	AVLOHCPHYSTREE HCPhysTree;
2472	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2473	/** Array of pages. (cMaxPages in length)
2474	* The Id is the index into thist array.
2475	*/
2476	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2477	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2478	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2479	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2480	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2481	#ifdef VBOX_WITH_STATISTICS
2482	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2483	#endif
2484	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2485
2486
2487	/** @def PGMPOOL_PAGE_2_PTR
2488	* Maps a pool page pool into the current context.
2489	*
2490	* @returns VBox status code.
2491	* @param a_pVM Pointer to the VM.
2492	* @param a_pPage The pool page.
2493	*
2494	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2495	* small page window employeed by that function. Be careful.
2496	* @remark There is no need to assert on the result.
2497	*/
2498	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2499	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2500	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2501	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2502	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2503	{
2504	AssertPtr(a_pPage);
2505	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2506	return a_pPage->pvPageR3;
2507	}
2508	#else
2509	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2510	#endif
2511
2512
2513	/** @def PGMPOOL_PAGE_2_PTR_V2
2514	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2515	*
2516	* @returns VBox status code.
2517	* @param a_pVM Pointer to the VM.
2518	* @param a_pVCpu The current CPU.
2519	* @param a_pPage The pool page.
2520	*
2521	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2522	* small page window employeed by that function. Be careful.
2523	* @remark There is no need to assert on the result.
2524	*/
2525	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2526	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2527	#else
2528	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2529	#endif
2530
2531
2532	/** @name Per guest page tracking data.
2533	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2534	* is to use more bits for it and split it up later on. But for now we'll play
2535	* safe and change as little as possible.
2536	*
2537	* The 16-bit word has two parts:
2538	*
2539	* The first 14-bit forms the @a idx field. It is either the index of a page in
2540	* the shadow page pool, or and index into the extent list.
2541	*
2542	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2543	* shadow page pool references to the page. If cRefs equals
2544	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2545	* (misnomer) table and not the shadow page pool.
2546	*
2547	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2548	* the 16-bit word.
2549	*
2550	* @{ */
2551	/** The shift count for getting to the cRefs part. */
2552	#define PGMPOOL_TD_CREFS_SHIFT 14
2553	/** The mask applied after shifting the tracking data down by
2554	* PGMPOOL_TD_CREFS_SHIFT. */
2555	#define PGMPOOL_TD_CREFS_MASK 0x3
2556	/** The cRefs value used to indicate that the idx is the head of a
2557	* physical cross reference list. */
2558	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2559	/** The shift used to get idx. */
2560	#define PGMPOOL_TD_IDX_SHIFT 0
2561	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2562	#define PGMPOOL_TD_IDX_MASK 0x3fff
2563	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2564	* simply too many mappings of this page. */
2565	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2566
2567	/** @def PGMPOOL_TD_MAKE
2568	* Makes a 16-bit tracking data word.
2569	*
2570	* @returns tracking data.
2571	* @param cRefs The @a cRefs field. Must be within bounds!
2572	* @param idx The @a idx field. Must also be within bounds! */
2573	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2574
2575	/** @def PGMPOOL_TD_GET_CREFS
2576	* Get the @a cRefs field from a tracking data word.
2577	*
2578	* @returns The @a cRefs field
2579	* @param u16 The tracking data word.
2580	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2581	* non-zero @a u16. */
2582	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2583
2584	/** @def PGMPOOL_TD_GET_IDX
2585	* Get the @a idx field from a tracking data word.
2586	*
2587	* @returns The @a idx field
2588	* @param u16 The tracking data word. */
2589	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2590	/** @} */
2591
2592
2593
2594	/** @name A20 gate macros
2595	* @{ */
2596	#define PGM_WITH_A20
2597	#ifdef PGM_WITH_A20
2598	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2599	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2600	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2601	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2602	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2603	#else
2604	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2605	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2606	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2607	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2608	#endif
2609	/** @} */
2610
2611
2612	/**
2613	* Trees are using self relative offsets as pointers.
2614	* So, all its data, including the root pointer, must be in the heap for HC and GC
2615	* to have the same layout.
2616	*/
2617	typedef struct PGMTREES
2618	{
2619	/** Physical access handlers (AVL range+offsetptr tree). */
2620	AVLROGCPHYSTREE PhysHandlers;
2621	/** Virtual access handlers (AVL range + GC ptr tree). */
2622	AVLROGCPTRTREE VirtHandlers;
2623	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2624	AVLROGCPHYSTREE PhysToVirtHandlers;
2625	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2626	AVLROGCPTRTREE HyperVirtHandlers;
2627	} PGMTREES;
2628	/** Pointer to PGM trees. */
2629	typedef PGMTREES *PPGMTREES;
2630
2631
2632	/**
2633	* Page fault guest state for the AMD64 paging mode.
2634	*/
2635	typedef struct PGMPTWALKCORE
2636	{
2637	/** The guest virtual address that is being resolved by the walk
2638	* (input). */
2639	RTGCPTR GCPtr;
2640
2641	/** The guest physical address that is the result of the walk.
2642	* @remarks only valid if fSucceeded is set. */
2643	RTGCPHYS GCPhys;
2644
2645	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2646	bool fSucceeded;
2647	/** The level problem arrised at.
2648	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2649	* level 8. This is 0 on success. */
2650	uint8_t uLevel;
2651	/** Set if the page isn't present. */
2652	bool fNotPresent;
2653	/** Encountered a bad physical address. */
2654	bool fBadPhysAddr;
2655	/** Set if there was reserved bit violations. */
2656	bool fRsvdError;
2657	/** Set if it involves a big page (2/4 MB). */
2658	bool fBigPage;
2659	/** Set if it involves a gigantic page (1 GB). */
2660	bool fGigantPage;
2661	/** The effect X86_PTE_US flag for the address. */
2662	bool fEffectiveUS;
2663	/** The effect X86_PTE_RW flag for the address. */
2664	bool fEffectiveRW;
2665	/** The effect X86_PTE_NX flag for the address. */
2666	bool fEffectiveNX;
2667	} PGMPTWALKCORE;
2668
2669
2670	/**
2671	* Guest page table walk for the AMD64 mode.
2672	*/
2673	typedef struct PGMPTWALKGSTAMD64
2674	{
2675	/** The common core. */
2676	PGMPTWALKCORE Core;
2677
2678	PX86PML4 pPml4;
2679	PX86PML4E pPml4e;
2680	X86PML4E Pml4e;
2681
2682	PX86PDPT pPdpt;
2683	PX86PDPE pPdpe;
2684	X86PDPE Pdpe;
2685
2686	PX86PDPAE pPd;
2687	PX86PDEPAE pPde;
2688	X86PDEPAE Pde;
2689
2690	PX86PTPAE pPt;
2691	PX86PTEPAE pPte;
2692	X86PTEPAE Pte;
2693	} PGMPTWALKGSTAMD64;
2694	/** Pointer to a AMD64 guest page table walk. */
2695	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2696	/** Pointer to a const AMD64 guest page table walk. */
2697	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2698
2699	/**
2700	* Guest page table walk for the PAE mode.
2701	*/
2702	typedef struct PGMPTWALKGSTPAE
2703	{
2704	/** The common core. */
2705	PGMPTWALKCORE Core;
2706
2707	PX86PDPT pPdpt;
2708	PX86PDPE pPdpe;
2709	X86PDPE Pdpe;
2710
2711	PX86PDPAE pPd;
2712	PX86PDEPAE pPde;
2713	X86PDEPAE Pde;
2714
2715	PX86PTPAE pPt;
2716	PX86PTEPAE pPte;
2717	X86PTEPAE Pte;
2718	} PGMPTWALKGSTPAE;
2719	/** Pointer to a PAE guest page table walk. */
2720	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2721	/** Pointer to a const AMD64 guest page table walk. */
2722	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2723
2724	/**
2725	* Guest page table walk for the 32-bit mode.
2726	*/
2727	typedef struct PGMPTWALKGST32BIT
2728	{
2729	/** The common core. */
2730	PGMPTWALKCORE Core;
2731
2732	PX86PD pPd;
2733	PX86PDE pPde;
2734	X86PDE Pde;
2735
2736	PX86PT pPt;
2737	PX86PTE pPte;
2738	X86PTE Pte;
2739	} PGMPTWALKGST32BIT;
2740	/** Pointer to a 32-bit guest page table walk. */
2741	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2742	/** Pointer to a const 32-bit guest page table walk. */
2743	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2744
2745	/**
2746	* Which part of PGMPTWALKGST that is valid.
2747	*/
2748	typedef enum PGMPTWALKGSTTYPE
2749	{
2750	/** Customary invalid 0 value. */
2751	PGMPTWALKGSTTYPE_INVALID = 0,
2752	/** PGMPTWALKGST::u.Amd64 is valid. */
2753	PGMPTWALKGSTTYPE_AMD64,
2754	/** PGMPTWALKGST::u.Pae is valid. */
2755	PGMPTWALKGSTTYPE_PAE,
2756	/** PGMPTWALKGST::u.Legacy is valid. */
2757	PGMPTWALKGSTTYPE_32BIT,
2758	/** Customary 32-bit type hack. */
2759	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2760	} PGMPTWALKGSTTYPE;
2761
2762	/**
2763	* Combined guest page table walk result.
2764	*/
2765	typedef struct PGMPTWALKGST
2766	{
2767	union
2768	{
2769	/** The page walker core - always valid. */
2770	PGMPTWALKCORE Core;
2771	/** The page walker for AMD64. */
2772	PGMPTWALKGSTAMD64 Amd64;
2773	/** The page walker for PAE (32-bit). */
2774	PGMPTWALKGSTPAE Pae;
2775	/** The page walker for 32-bit paging (called legacy due to C naming
2776	* convension). */
2777	PGMPTWALKGST32BIT Legacy;
2778	} u;
2779	/** Indicates which part of the union is valid. */
2780	PGMPTWALKGSTTYPE enmType;
2781	} PGMPTWALKGST;
2782	/** Pointer to a combined guest page table walk result. */
2783	typedef PGMPTWALKGST *PPGMPTWALKGST;
2784	/** Pointer to a read-only combined guest page table walk result. */
2785	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2786
2787
2788	/** @name Paging mode macros
2789	* @{
2790	*/
2791	#ifdef IN_RC
2792	# define PGM_CTX(a,b) a##RC##b
2793	# define PGM_CTX_STR(a,b) a "GC" b
2794	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2795	#else
2796	# ifdef IN_RING3
2797	# define PGM_CTX(a,b) a##R3##b
2798	# define PGM_CTX_STR(a,b) a "R3" b
2799	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2800	# else
2801	# define PGM_CTX(a,b) a##R0##b
2802	# define PGM_CTX_STR(a,b) a "R0" b
2803	# define PGM_CTX_DECL(type) VMMDECL(type)
2804	# endif
2805	#endif
2806
2807	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2808	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2809	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2810	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2811	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2812	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2813	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2814	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2815	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2816	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2817	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2818	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2819	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2820	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2821	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2822	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2823	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2824
2825	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2826	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2827	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2828	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2829	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2830	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2831	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2832	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2833	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2834	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2835	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2836	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2837	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2838	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2839	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2840	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2841	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2842
2843	/* Shw_Gst */
2844	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2845	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2846	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2847	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2848	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2849	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2850	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2851	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2852	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2853	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2854	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2855	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2856	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2857	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2858	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2859	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2860	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2861	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2862	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2863
2864	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2865	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2866	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2867	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2868	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2869	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2870	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2871	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2872	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2873	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2874	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2875	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2876	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2877	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2878	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2879	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2880	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2881	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2882	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2883	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2884	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2885	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2886	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2887	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2888	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2889	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2890	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2891	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2892	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2893	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2894	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2895	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2896	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2897	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2898	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2899	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2900	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2901
2902	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2903	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2904	/** @} */
2905
2906	/**
2907	* Data for each paging mode.
2908	*/
2909	typedef struct PGMMODEDATA
2910	{
2911	/** The guest mode type. */
2912	uint32_t uGstType;
2913	/** The shadow mode type. */
2914	uint32_t uShwType;
2915
2916	/** @name Function pointers for Shadow paging.
2917	* @{
2918	*/
2919	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2920	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2921	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2922	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2923
2924	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2925	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2926
2927	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2928	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2929	/** @} */
2930
2931	/** @name Function pointers for Guest paging.
2932	* @{
2933	*/
2934	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2935	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2936	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2937	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2938	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2939	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2940	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2941	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2942	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2943	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2944	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2945	/** @} */
2946
2947	/** @name Function pointers for Both Shadow and Guest paging.
2948	* @{
2949	*/
2950	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2951	/* no pfnR3BthTrap0eHandler */
2952	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2953	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2954	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2955	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2956	#ifdef VBOX_STRICT
2957	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2958	#endif
2959	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2960	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2961
2962	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2963	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2964	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2965	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2966	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2967	#ifdef VBOX_STRICT
2968	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2969	#endif
2970	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2971	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2972
2973	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2974	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2975	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2976	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2977	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2978	#ifdef VBOX_STRICT
2979	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2980	#endif
2981	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2982	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2983	/** @} */
2984	} PGMMODEDATA, *PPGMMODEDATA;
2985
2986
2987	#ifdef VBOX_WITH_STATISTICS
2988	/**
2989	* PGM statistics.
2990	*
2991	* These lives on the heap when compiled in as they would otherwise waste
2992	* unnecessary space in release builds.
2993	*/
2994	typedef struct PGMSTATS
2995	{
2996	/* R3 only: */
2997	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2998	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2999
3000	/* R3+RZ */
3001	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3002	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3003	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3004	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3005	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3006	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3007	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3008	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3009	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3010	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3011	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3012	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3013	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3014	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3015	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
3016	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
3017	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
3018	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
3019	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3020	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3021	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3022	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3023	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3024	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3025	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3026	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3027	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3028	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3029	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3030	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3031	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3032	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3033
3034	/* RC only: */
3035	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3036	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3037
3038	STAMCOUNTER StatRZPhysRead;
3039	STAMCOUNTER StatRZPhysReadBytes;
3040	STAMCOUNTER StatRZPhysWrite;
3041	STAMCOUNTER StatRZPhysWriteBytes;
3042	STAMCOUNTER StatR3PhysRead;
3043	STAMCOUNTER StatR3PhysReadBytes;
3044	STAMCOUNTER StatR3PhysWrite;
3045	STAMCOUNTER StatR3PhysWriteBytes;
3046	STAMCOUNTER StatRCPhysRead;
3047	STAMCOUNTER StatRCPhysReadBytes;
3048	STAMCOUNTER StatRCPhysWrite;
3049	STAMCOUNTER StatRCPhysWriteBytes;
3050
3051	STAMCOUNTER StatRZPhysSimpleRead;
3052	STAMCOUNTER StatRZPhysSimpleReadBytes;
3053	STAMCOUNTER StatRZPhysSimpleWrite;
3054	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3055	STAMCOUNTER StatR3PhysSimpleRead;
3056	STAMCOUNTER StatR3PhysSimpleReadBytes;
3057	STAMCOUNTER StatR3PhysSimpleWrite;
3058	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3059	STAMCOUNTER StatRCPhysSimpleRead;
3060	STAMCOUNTER StatRCPhysSimpleReadBytes;
3061	STAMCOUNTER StatRCPhysSimpleWrite;
3062	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3063
3064	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3065	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3066	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3067	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3068	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3069	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3070	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3071
3072	/** Time spent by the host OS for large page allocation. */
3073	STAMPROFILE StatAllocLargePage;
3074	/** Time spent clearing the newly allocated large pages. */
3075	STAMPROFILE StatClearLargePage;
3076	/** The number of times allocating a large pages takes more than the allowed period. */
3077	STAMCOUNTER StatLargePageOverflow;
3078	/** pgmPhysIsValidLargePage profiling - R3 */
3079	STAMPROFILE StatR3IsValidLargePage;
3080	/** pgmPhysIsValidLargePage profiling - RZ*/
3081	STAMPROFILE StatRZIsValidLargePage;
3082
3083	STAMPROFILE StatChunkAging;
3084	STAMPROFILE StatChunkFindCandidate;
3085	STAMPROFILE StatChunkUnmap;
3086	STAMPROFILE StatChunkMap;
3087	} PGMSTATS;
3088	#endif /* VBOX_WITH_STATISTICS */
3089
3090
3091	/**
3092	* Converts a PGM pointer into a VM pointer.
3093	* @returns Pointer to the VM structure the PGM is part of.
3094	* @param pPGM Pointer to PGM instance data.
3095	*/
3096	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3097
3098	/**
3099	* PGM Data (part of VM)
3100	*/
3101	typedef struct PGM
3102	{
3103	/** Offset to the VM structure. */
3104	int32_t offVM;
3105	/** Offset of the PGMCPU structure relative to VMCPU. */
3106	int32_t offVCpuPGM;
3107
3108	/** @cfgm{RamPreAlloc, boolean, false}
3109	* Indicates whether the base RAM should all be allocated before starting
3110	* the VM (default), or if it should be allocated when first written to.
3111	*/
3112	bool fRamPreAlloc;
3113	/** Indicates whether write monitoring is currently in use.
3114	* This is used to prevent conflicts between live saving and page sharing
3115	* detection. */
3116	bool fPhysWriteMonitoringEngaged;
3117	/** Set if the CPU has less than 52-bit physical address width.
3118	* This is used */
3119	bool fLessThan52PhysicalAddressBits;
3120	/** Set when nested paging is active.
3121	* This is meant to save calls to HMIsNestedPagingActive and let the
3122	* compilers optimize the code better. Whether we use nested paging or
3123	* not is something we find out during VMM initialization and we won't
3124	* change this later on. */
3125	bool fNestedPaging;
3126	/** The host paging mode. (This is what SUPLib reports.) */
3127	SUPPAGINGMODE enmHostMode;
3128	/** We're not in a state which permits writes to guest memory.
3129	* (Only used in strict builds.) */
3130	bool fNoMorePhysWrites;
3131	/** Set if PCI passthrough is enabled. */
3132	bool fPciPassthrough;
3133	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3134	uint8_t cMmio2Regions;
3135	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3136	bool afAlignment1[2];
3137
3138	/** Indicates that PGMR3FinalizeMappings has been called and that further
3139	* PGMR3MapIntermediate calls will be rejected. */
3140	bool fFinalizedMappings;
3141	/** If set no conflict checks are required. */
3142	bool fMappingsFixed;
3143	/** If set if restored as fixed but we were unable to re-fixate at the old
3144	* location because of room or address incompatibilities. */
3145	bool fMappingsFixedRestored;
3146	/** Size of fixed mapping.
3147	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3148	uint32_t cbMappingFixed;
3149	/** Generation ID for the RAM ranges. This member is incremented everytime
3150	* a RAM range is linked or unlinked. */
3151	uint32_t volatile idRamRangesGen;
3152
3153	/** Base address (GC) of fixed mapping.
3154	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3155	RTGCPTR GCPtrMappingFixed;
3156	/** The address of the previous RAM range mapping. */
3157	RTGCPTR GCPtrPrevRamRangeMapping;
3158
3159	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3160	RTGCPHYS GCPhys4MBPSEMask;
3161	/** Mask containing the invalid bits of a guest physical address.
3162	* @remarks this does not stop at bit 52. */
3163	RTGCPHYS GCPhysInvAddrMask;
3164
3165
3166	/** RAM range TLB for R3. */
3167	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3168	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3169	* This is sorted by physical address and contains no overlapping ranges. */
3170	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3171	/** Root of the RAM range search tree for ring-3. */
3172	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3173	/** PGM offset based trees - R3 Ptr. */
3174	R3PTRTYPE(PPGMTREES) pTreesR3;
3175	/** Caching the last physical handler we looked up in R3. */
3176	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3177	/** Shadow Page Pool - R3 Ptr. */
3178	R3PTRTYPE(PPGMPOOL) pPoolR3;
3179	/** Linked list of GC mappings - for HC.
3180	* The list is sorted ascending on address. */
3181	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3182	/** Pointer to the list of ROM ranges - for R3.
3183	* This is sorted by physical address and contains no overlapping ranges. */
3184	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3185	/** Pointer to the list of MMIO2 ranges - for R3.
3186	* Registration order. */
3187	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3188	/** Pointer to SHW+GST mode data (function pointers).
3189	* The index into this table is made up from */
3190	R3PTRTYPE(PPGMMODEDATA) paModeData;
3191	RTR3PTR R3PtrAlignment0;
3192	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3193	R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3194
3195	/** RAM range TLB for R0. */
3196	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3197	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3198	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3199	/** Root of the RAM range search tree for ring-0. */
3200	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3201	/** PGM offset based trees - R0 Ptr. */
3202	R0PTRTYPE(PPGMTREES) pTreesR0;
3203	/** Caching the last physical handler we looked up in R0. */
3204	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3205	/** Shadow Page Pool - R0 Ptr. */
3206	R0PTRTYPE(PPGMPOOL) pPoolR0;
3207	/** Linked list of GC mappings - for R0.
3208	* The list is sorted ascending on address. */
3209	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3210	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3211	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3212	RTR0PTR R0PtrAlignment0;
3213	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3214	R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3215
3216	/** RAM range TLB for RC. */
3217	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3218	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3219	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3220	/** Root of the RAM range search tree for raw-mode context. */
3221	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3222	/** PGM offset based trees - RC Ptr. */
3223	RCPTRTYPE(PPGMTREES) pTreesRC;
3224	/** Caching the last physical handler we looked up in RC. */
3225	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3226	/** Shadow Page Pool - RC Ptr. */
3227	RCPTRTYPE(PPGMPOOL) pPoolRC;
3228	/** Linked list of GC mappings - for RC.
3229	* The list is sorted ascending on address. */
3230	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3231	/** RC pointer corresponding to PGM::pRomRangesR3. */
3232	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3233	RTRCPTR RCPtrAlignment0;
3234	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3235	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3236	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3237	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3238
3239
3240	/** Pointer to the 5 page CR3 content mapping.
3241	* The first page is always the CR3 (in some form) while the 4 other pages
3242	* are used of the PDs in PAE mode. */
3243	RTGCPTR GCPtrCR3Mapping;
3244
3245	/** @name Intermediate Context
3246	* @{ */
3247	/** Pointer to the intermediate page directory - Normal. */
3248	R3PTRTYPE(PX86PD) pInterPD;
3249	/** Pointer to the intermediate page tables - Normal.
3250	* There are two page tables, one for the identity mapping and one for
3251	* the host context mapping (of the core code). */
3252	R3PTRTYPE(PX86PT) apInterPTs[2];
3253	/** Pointer to the intermediate page tables - PAE. */
3254	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3255	/** Pointer to the intermediate page directory - PAE. */
3256	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3257	/** Pointer to the intermediate page directory - PAE. */
3258	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3259	/** Pointer to the intermediate page-map level 4 - AMD64. */
3260	R3PTRTYPE(PX86PML4) pInterPaePML4;
3261	/** Pointer to the intermediate page directory - AMD64. */
3262	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3263	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3264	RTHCPHYS HCPhysInterPD;
3265	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3266	RTHCPHYS HCPhysInterPaePDPT;
3267	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3268	RTHCPHYS HCPhysInterPaePML4;
3269	/** @} */
3270
3271	/** Base address of the dynamic page mapping area.
3272	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3273	*
3274	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3275	* work out. Some cleaning up of the initialization that would
3276	* remove this memory is yet to be done...
3277	*/
3278	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3279	/** The address of the raw-mode context mapping cache. */
3280	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3281	/** The address of the ring-0 mapping cache if we're making use of it. */
3282	RTR0PTR pvR0DynMapUsed;
3283
3284	/** Hack: Number of deprecated page mapping locks taken by the current lock
3285	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3286	uint32_t cDeprecatedPageLocks;
3287	#if HC_ARCH_BITS == 64
3288	/** Alignment padding. */
3289	uint32_t u32Alignment2;
3290	#endif
3291
3292
3293	/** PGM critical section.
3294	* This protects the physical & virtual access handlers, ram ranges,
3295	* and the page flag updating (some of it anyway).
3296	*/
3297	PDMCRITSECT CritSectX;
3298
3299	/**
3300	* Data associated with managing the ring-3 mappings of the allocation chunks.
3301	*/
3302	struct
3303	{
3304	/** The chunk tree, ordered by chunk id. */
3305	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3306	R3PTRTYPE(PAVLU32NODECORE) pTree;
3307	#else
3308	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3309	#endif
3310	#if HC_ARCH_BITS == 32
3311	uint32_t u32Alignment0;
3312	#endif
3313	/** The chunk mapping TLB. */
3314	PGMCHUNKR3MAPTLB Tlb;
3315	/** The number of mapped chunks. */
3316	uint32_t c;
3317	/** The maximum number of mapped chunks.
3318	* @cfgm PGM/MaxRing3Chunks */
3319	uint32_t cMax;
3320	/** The current time. This is incremented whenever a chunk is inserted. */
3321	uint32_t iNow;
3322	/** Alignment padding. */
3323	uint32_t u32Alignment1;
3324	} ChunkR3Map;
3325
3326	/**
3327	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3328	*/
3329	PGMPAGER3MAPTLB PhysTlbHC;
3330
3331	/** @name The zero page.
3332	* @{ */
3333	/** The host physical address of the zero page. */
3334	RTHCPHYS HCPhysZeroPg;
3335	/** The ring-3 mapping of the zero page. */
3336	RTR3PTR pvZeroPgR3;
3337	/** The ring-0 mapping of the zero page. */
3338	RTR0PTR pvZeroPgR0;
3339	/** The GC mapping of the zero page. */
3340	RTRCPTR pvZeroPgRC;
3341	RTRCPTR RCPtrAlignment3;
3342	/** @}*/
3343
3344	/** @name The Invalid MMIO page.
3345	* This page is filled with 0xfeedface.
3346	* @{ */
3347	/** The host physical address of the invalid MMIO page. */
3348	RTHCPHYS HCPhysMmioPg;
3349	/** The host pysical address of the invalid MMIO page plus all invalid
3350	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3351	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3352	RTHCPHYS HCPhysInvMmioPg;
3353	/** The ring-3 mapping of the invalid MMIO page. */
3354	RTR3PTR pvMmioPgR3;
3355	#if HC_ARCH_BITS == 32
3356	RTR3PTR R3PtrAlignment4;
3357	#endif
3358	/** @} */
3359
3360
3361	/** The number of handy pages. */
3362	uint32_t cHandyPages;
3363
3364	/** The number of large handy pages. */
3365	uint32_t cLargeHandyPages;
3366
3367	/**
3368	* Array of handy pages.
3369	*
3370	* This array is used in a two way communication between pgmPhysAllocPage
3371	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3372	* an intermediary.
3373	*
3374	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3375	* (The current size of 32 pages, means 128 KB of handy memory.)
3376	*/
3377	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3378
3379	/**
3380	* Array of large handy pages. (currently size 1)
3381	*
3382	* This array is used in a two way communication between pgmPhysAllocLargePage
3383	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3384	* an intermediary.
3385	*/
3386	GMMPAGEDESC aLargeHandyPage[1];
3387
3388	/**
3389	* Live save data.
3390	*/
3391	struct
3392	{
3393	/** Per type statistics. */
3394	struct
3395	{
3396	/** The number of ready pages. */
3397	uint32_t cReadyPages;
3398	/** The number of dirty pages. */
3399	uint32_t cDirtyPages;
3400	/** The number of ready zero pages. */
3401	uint32_t cZeroPages;
3402	/** The number of write monitored pages. */
3403	uint32_t cMonitoredPages;
3404	} Rom,
3405	Mmio2,
3406	Ram;
3407	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3408	uint32_t cIgnoredPages;
3409	/** Indicates that a live save operation is active. */
3410	bool fActive;
3411	/** Padding. */
3412	bool afReserved[2];
3413	/** The next history index. */
3414	uint8_t iDirtyPagesHistory;
3415	/** History of the total amount of dirty pages. */
3416	uint32_t acDirtyPagesHistory[64];
3417	/** Short term dirty page average. */
3418	uint32_t cDirtyPagesShort;
3419	/** Long term dirty page average. */
3420	uint32_t cDirtyPagesLong;
3421	/** The number of saved pages. This is used to get some kind of estimate of the
3422	* link speed so we can decide when we're done. It is reset after the first
3423	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3424	* zero pages. */
3425	uint64_t cSavedPages;
3426	/** The nanosecond timestamp when cSavedPages was 0. */
3427	uint64_t uSaveStartNS;
3428	/** Pages per second (for statistics). */
3429	uint32_t cPagesPerSecond;
3430	uint32_t cAlignment;
3431	} LiveSave;
3432
3433	/** @name Error injection.
3434	* @{ */
3435	/** Inject handy page allocation errors pretending we're completely out of
3436	* memory. */
3437	bool volatile fErrInjHandyPages;
3438	/** Padding. */
3439	bool afReserved[3];
3440	/** @} */
3441
3442	/** @name Release Statistics
3443	* @{ */
3444	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3445	uint32_t cPrivatePages; /*< The number of private pages. /
3446	uint32_t cSharedPages; /*< The number of shared pages. /
3447	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3448	uint32_t cZeroPages; /*< The number of zero backed pages. /
3449	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3450	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3451	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3452	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3453	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3454	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3455	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3456	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3457	uint32_t cLargePages; /*< The number of large pages. /
3458	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3459	/* uint32_t aAlignment4[1]; */
3460
3461	/** The number of times we were forced to change the hypervisor region location. */
3462	STAMCOUNTER cRelocations;
3463
3464	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3465	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3466	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3467
3468	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3469	/** @} */
3470
3471	#ifdef VBOX_WITH_STATISTICS
3472	/** @name Statistics on the heap.
3473	* @{ */
3474	R3PTRTYPE(PGMSTATS *) pStatsR3;
3475	R0PTRTYPE(PGMSTATS *) pStatsR0;
3476	RCPTRTYPE(PGMSTATS *) pStatsRC;
3477	RTRCPTR RCPtrAlignment;
3478	/** @} */
3479	#endif
3480	} PGM;
3481	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3482	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3483	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3484	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3485	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3486	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3487	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3488	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3489	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3490	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3491	#endif /* !IN_TSTVMSTRUCTGC */
3492	/** Pointer to the PGM instance data. */
3493	typedef PGM *PPGM;
3494
3495
3496
3497	typedef struct PGMCPUSTATS
3498	{
3499	/* Common */
3500	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3501	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3502
3503	/* R0 only: */
3504	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3505	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3506
3507	/* RZ only: */
3508	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3509	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3510	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3511	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3512	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3513	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3514	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3515	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3516	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3517	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3518	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3519	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3520	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3521	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3522	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3523	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3524	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3525	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3526	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3527	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3528	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3529	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3530	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3531	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3532	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3533	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3534	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3535	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3536	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3537	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3538	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3539	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3540	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3541	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3542	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3543	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3544	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3545	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3546	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3547	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3548	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3549	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3550	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3551	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3552	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3553	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3554	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3555	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3556	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3557	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3558	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3559	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3560	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3561	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3562	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3563	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3564	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3565	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3566	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3567	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3568	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3569	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3570	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3571	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3572	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3573	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3574	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3575	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3576	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3577	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3578	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3579	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3580	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3581	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3582	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3583	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3584	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3585	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3586
3587	/* HC - R3 and (maybe) R0: */
3588
3589	/* RZ & R3: */
3590	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3591	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3592	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3593	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3594	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3595	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3596	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3597	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3598	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3599	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3600	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3601	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3602	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3603	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3604	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3605	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3606	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3607	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3608	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3609	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3610	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3611	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3612	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3613	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3614	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3615	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3616	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3617	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3618	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3619	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3620	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3621	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3622	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3623	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3624	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3625	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3626	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3627	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3628	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3629	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3630	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3631	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3632	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3633	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3634	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3635	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3636	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3637
3638	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3639	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3640	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3641	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3642	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3643	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3644	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3645	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3646	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3647	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3648	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3649	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3650	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3651	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3652	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3653	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3654	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3655	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3656	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3657	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3658	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3659	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3660	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3661	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3662	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3663	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3664	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3665	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3666	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3667	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3668	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3669	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3670	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3671	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3672	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3673	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3674	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3675	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3676	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3677	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3678	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3679	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3680	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3681	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3682	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3683	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3684	/** @} */
3685	} PGMCPUSTATS;
3686
3687
3688	/**
3689	* Converts a PGMCPU pointer into a VM pointer.
3690	* @returns Pointer to the VM structure the PGM is part of.
3691	* @param pPGM Pointer to PGMCPU instance data.
3692	*/
3693	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3694
3695	/**
3696	* Converts a PGMCPU pointer into a PGM pointer.
3697	* @returns Pointer to the VM structure the PGM is part of.
3698	* @param pPGM Pointer to PGMCPU instance data.
3699	*/
3700	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3701
3702	/**
3703	* PGMCPU Data (part of VMCPU).
3704	*/
3705	typedef struct PGMCPU
3706	{
3707	/** Offset to the VM structure. */
3708	int32_t offVM;
3709	/** Offset to the VMCPU structure. */
3710	int32_t offVCpu;
3711	/** Offset of the PGM structure relative to VMCPU. */
3712	int32_t offPGM;
3713	uint32_t uPadding0; /*< structure size alignment. /
3714
3715	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3716	/** Automatically tracked physical memory mapping set.
3717	* Ring-0 and strict raw-mode builds. */
3718	PGMMAPSET AutoSet;
3719	#endif
3720
3721	/** A20 gate mask.
3722	* Our current approach to A20 emulation is to let REM do it and don't bother
3723	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3724	* But whould need arrise, we'll subject physical addresses to this mask. */
3725	RTGCPHYS GCPhysA20Mask;
3726	/** A20 gate state - boolean! */
3727	bool fA20Enabled;
3728	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3729	bool fNoExecuteEnabled;
3730	/** Unused bits. */
3731	bool afUnused[2];
3732
3733	/** What needs syncing (PGM_SYNC_*).
3734	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3735	* PGMFlushTLB, and PGMR3Load. */
3736	uint32_t fSyncFlags;
3737
3738	/** The shadow paging mode. */
3739	PGMMODE enmShadowMode;
3740	/** The guest paging mode. */
3741	PGMMODE enmGuestMode;
3742
3743	/** The current physical address representing in the guest CR3 register. */
3744	RTGCPHYS GCPhysCR3;
3745
3746	/** @name 32-bit Guest Paging.
3747	* @{ */
3748	/** The guest's page directory, R3 pointer. */
3749	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3750	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3751	/** The guest's page directory, R0 pointer. */
3752	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3753	#endif
3754	/** The guest's page directory, static RC mapping. */
3755	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3756	/** Mask containing the MBZ bits of a big page PDE. */
3757	uint32_t fGst32BitMbzBigPdeMask;
3758	/** Set if the page size extension (PSE) is enabled. */
3759	bool fGst32BitPageSizeExtension;
3760	/** Alignment padding. */
3761	bool afAlignment2[3];
3762	/** @} */
3763
3764	/** @name PAE Guest Paging.
3765	* @{ */
3766	/** The guest's page directory pointer table, static RC mapping. */
3767	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3768	/** The guest's page directory pointer table, R3 pointer. */
3769	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3770	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3771	/** The guest's page directory pointer table, R0 pointer. */
3772	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3773	#endif
3774
3775	/** The guest's page directories, R3 pointers.
3776	* These are individual pointers and don't have to be adjacent.
3777	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3778	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3779	/** The guest's page directories, R0 pointers.
3780	* Same restrictions as apGstPaePDsR3. */
3781	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3782	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3783	#endif
3784	/** The guest's page directories, static GC mapping.
3785	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3786	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3787	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3788	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3789	* @todo Remove this and use aGstPaePdpeRegs instead? */
3790	RTGCPHYS aGCPhysGstPaePDs[4];
3791	/** The values of the 4 PDPE CPU registers (PAE). */
3792	X86PDPE aGstPaePdpeRegs[4];
3793	/** The physical addresses of the monitored guest page directories (PAE). */
3794	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3795	/** Mask containing the MBZ PTE bits. */
3796	uint64_t fGstPaeMbzPteMask;
3797	/** Mask containing the MBZ PDE bits. */
3798	uint64_t fGstPaeMbzPdeMask;
3799	/** Mask containing the MBZ big page PDE bits. */
3800	uint64_t fGstPaeMbzBigPdeMask;
3801	/** Mask containing the MBZ PDPE bits. */
3802	uint64_t fGstPaeMbzPdpeMask;
3803	/** @} */
3804
3805	/** @name AMD64 Guest Paging.
3806	* @{ */
3807	/** The guest's page directory pointer table, R3 pointer. */
3808	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3809	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3810	/** The guest's page directory pointer table, R0 pointer. */
3811	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3812	#else
3813	RTR0PTR alignment6b; /*< alignment equalizer. /
3814	#endif
3815	/** Mask containing the MBZ PTE bits. */
3816	uint64_t fGstAmd64MbzPteMask;
3817	/** Mask containing the MBZ PDE bits. */
3818	uint64_t fGstAmd64MbzPdeMask;
3819	/** Mask containing the MBZ big page PDE bits. */
3820	uint64_t fGstAmd64MbzBigPdeMask;
3821	/** Mask containing the MBZ PDPE bits. */
3822	uint64_t fGstAmd64MbzPdpeMask;
3823	/** Mask containing the MBZ big page PDPE bits. */
3824	uint64_t fGstAmd64MbzBigPdpeMask;
3825	/** Mask containing the MBZ PML4E bits. */
3826	uint64_t fGstAmd64MbzPml4eMask;
3827	/** Mask containing the PDPE bits that we shadow. */
3828	uint64_t fGstAmd64ShadowedPdpeMask;
3829	/** Mask containing the PML4E bits that we shadow. */
3830	uint64_t fGstAmd64ShadowedPml4eMask;
3831	/** @} */
3832
3833	/** @name PAE and AMD64 Guest Paging.
3834	* @{ */
3835	/** Mask containing the PTE bits that we shadow. */
3836	uint64_t fGst64ShadowedPteMask;
3837	/** Mask containing the PDE bits that we shadow. */
3838	uint64_t fGst64ShadowedPdeMask;
3839	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3840	uint64_t fGst64ShadowedBigPdeMask;
3841	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3842	uint64_t fGst64ShadowedBigPde4PteMask;
3843	/** @} */
3844
3845	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3846	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3847	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3848	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3849	/** Pointer to the page of the current active CR3 - RC Ptr. */
3850	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3851	# if HC_ARCH_BITS == 64
3852	RTRCPTR alignment6; /*< structure size alignment. /
3853	# endif
3854	/** @} */
3855
3856	/** @name Function pointers for Shadow paging.
3857	* @{
3858	*/
3859	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3860	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3861	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3862	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3863
3864	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3865	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3866
3867	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3868	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3869
3870	/** @} */
3871
3872	/** @name Function pointers for Guest paging.
3873	* @{
3874	*/
3875	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3876	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3877	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3878	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3879	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3880	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3881	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3882	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3883	#if HC_ARCH_BITS == 64
3884	RTRCPTR alignment3; /*< structure size alignment. /
3885	#endif
3886
3887	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3888	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3889	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3890	/** @} */
3891
3892	/** @name Function pointers for Both Shadow and Guest paging.
3893	* @{
3894	*/
3895	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3896	/* no pfnR3BthTrap0eHandler */
3897	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3898	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3899	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3900	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3901	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3902	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3903	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3904
3905	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3906	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3907	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3908	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3909	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3910	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3911	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3912	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3913
3914	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3915	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3916	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3917	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3918	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3919	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3920	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3921	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3922	#if 0
3923	RTRCPTR alignment2; /*< structure size alignment. /
3924	#endif
3925	/** @} */
3926
3927	/** For saving stack space, the disassembler state is allocated here instead of
3928	* on the stack. */
3929	DISCPUSTATE DisState;
3930
3931	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3932	uint64_t cNetwareWp0Hacks;
3933
3934	/** Count the number of pgm pool access handler calls. */
3935	uint64_t cPoolAccessHandler;
3936
3937	/** @name Release Statistics
3938	* @{ */
3939	/** The number of times the guest has switched mode since last reset or statistics reset. */
3940	STAMCOUNTER cGuestModeChanges;
3941	/** The number of times the guest has switched mode since last reset or statistics reset. */
3942	STAMCOUNTER cA20Changes;
3943	/** @} */
3944
3945	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3946	/** @name Statistics
3947	* @{ */
3948	/** RC: Pointer to the statistics. */
3949	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3950	/** RC: Which statistic this \#PF should be attributed to. */
3951	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3952	/** R0: Pointer to the statistics. */
3953	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3954	/** R0: Which statistic this \#PF should be attributed to. */
3955	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3956	/** R3: Pointer to the statistics. */
3957	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3958	/** Alignment padding. */
3959	RTR3PTR pPaddingR3;
3960	/** @} */
3961	#endif /* VBOX_WITH_STATISTICS */
3962	} PGMCPU;
3963	/** Pointer to the per-cpu PGM data. */
3964	typedef PGMCPU *PPGMCPU;
3965
3966
3967	/** @name PGM::fSyncFlags Flags
3968	* @{
3969	*/
3970	/** Updates the virtual access handler state bit in PGMPAGE. */
3971	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3972	/** Always sync CR3. */
3973	#define PGM_SYNC_ALWAYS RT_BIT(1)
3974	/** Check monitoring on next CR3 (re)load and invalidate page.
3975	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3976	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3977	/** Check guest mapping in SyncCR3. */
3978	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3979	/** Clear the page pool (a light weight flush). */
3980	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3981	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3982	/** @} */
3983
3984
3985	RT_C_DECLS_BEGIN
3986
3987	#if defined(VBOX_STRICT) && defined(IN_RING3)
3988	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
3989	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
3990	#else
3991	int pgmLock(PVM pVM);
3992	#endif
3993	void pgmUnlock(PVM pVM);
3994	/**
3995	* Asserts that the caller owns the PDM lock.
3996	* This is the internal variant of PGMIsLockOwner.
3997	* @param a_pVM Pointer to the VM.
3998	*/
3999	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4000	/**
4001	* Asserts that the caller owns the PDM lock.
4002	* This is the internal variant of PGMIsLockOwner.
4003	* @param a_pVM Pointer to the VM.
4004	* @param a_pVCpu The current CPU handle.
4005	*/
4006	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4007
4008	#ifndef PGM_WITHOUT_MAPPINGS
4009	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4010	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4011	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4012	int pgmMapResolveConflicts(PVM pVM);
4013	#endif /* !PGM_WITHOUT_MAPPINGS */
4014	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4015	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4016
4017	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4018	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4019	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4020	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
4021	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4022	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4023	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4024	#else
4025	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4026	#endif
4027	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4028	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4029
4030	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4031	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4032	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4033	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4034	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4035	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4036	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4037	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4038	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4039	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4040	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4041	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4042	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4043	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4044	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4045	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4046	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4047	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
4048	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
4049	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4050	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4051	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4052	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4053	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4054	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4055	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4056	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4057	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4058
4059	#ifdef IN_RING3
4060	void pgmR3PhysRelinkRamRanges(PVM pVM);
4061	int pgmR3PhysRamPreAllocate(PVM pVM);
4062	int pgmR3PhysRamReset(PVM pVM);
4063	int pgmR3PhysRomReset(PVM pVM);
4064	int pgmR3PhysRamZeroAll(PVM pVM);
4065	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4066	int pgmR3PhysRamTerm(PVM pVM);
4067	void pgmR3PhysRomTerm(PVM pVM);
4068	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4069
4070	int pgmR3PoolInit(PVM pVM);
4071	void pgmR3PoolRelocate(PVM pVM);
4072	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4073	void pgmR3PoolReset(PVM pVM);
4074	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4075	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4076	void pgmR3PoolWriteProtectPages(PVM pVM);
4077
4078	#endif /* IN_RING3 */
4079	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4080	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4081	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4082	# ifdef LOG_ENABLED
4083	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4084	# else
4085	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4086	# endif
4087	#endif
4088	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4089	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4090	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4091	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4092	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4093	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4094	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4095	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4096	int pgmPoolSyncCR3(PVMCPU pVCpu);
4097	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4098	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4099	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4100	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4101	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4102	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4103	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
4104	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4105	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4106
4107	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4108	void pgmPoolResetDirtyPages(PVM pVM);
4109	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4110
4111	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4112	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4113	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4114
4115	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4116	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4117	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4118	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4119
4120	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4121	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4122	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4123
4124	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4125	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4126	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4127	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4128	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4129
4130	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4131	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4132	FNDBGCCMD pgmR3CmdShowSharedModules;
4133	# endif
4134
4135	RT_C_DECLS_END
4136
4137	/** @} */
4138
4139	#endif
4140

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 49141

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