VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 38707

Last change on this file since 38707 was 38707, checked in by vboxsync, 13 years ago

VMM/VT-x: Fix for PAE guests running on 32-bit hosts or 64-bit hosts where VBoxInternal/PGM/MaxRing3Chunks is used.
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1/* $Id: PGMInternal.h 38707 2011-09-09 14:10:18Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hwaccm.h>
36#include <VBox/vmm/hwacc_vmx.h>
37#include "internal/pgm.h"
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pvPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pvPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one coming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef union PGMPAGE
692{
693 /** Structured view. */
694 struct
695 {
696 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
697 uint64_t u2HandlerPhysStateY : 2;
698 /** 3:2 - Paging structure needed to map the page
699 * (PGM_PAGE_PDE_TYPE_*). */
700 uint64_t u2PDETypeY : 2;
701 /** 4 - Indicator of dirty page for fault tolerance tracking. */
702 uint64_t fFTDirtyY : 1;
703 /** 5 - Flag indicating that a write monitored page was written to
704 * when set. */
705 uint64_t fWrittenToY : 1;
706 /** 7:6 - Unused. */
707 uint64_t u2Unused0 : 2;
708 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
709 uint64_t u2HandlerVirtStateY : 2;
710 /** 11:10 - Unused. */
711 uint64_t u2Unused1 : 2;
712 /** 12:48 - The host physical frame number (shift left to get the
713 * address). */
714 uint64_t HCPhysFN : 36;
715 /** 50:48 - The page state. */
716 uint64_t uStateY : 3;
717 /** 51:53 - The page type (PGMPAGETYPE). */
718 uint64_t uTypeY : 3;
719 /** 63:54 - PTE index for usage tracking (page pool). */
720 uint64_t u10PteIdx : 10;
721
722 /** The GMM page ID. */
723 uint32_t idPage;
724 /** Usage tracking (page pool). */
725 uint16_t u16TrackingY;
726 /** The number of read locks on this page. */
727 uint8_t cReadLocksY;
728 /** The number of write locks on this page. */
729 uint8_t cWriteLocksY;
730 } s;
731
732 /** 64-bit integer view. */
733 uint64_t au64[2];
734 /** 16-bit view. */
735 uint32_t au32[4];
736 /** 16-bit view. */
737 uint16_t au16[8];
738 /** 8-bit view. */
739 uint8_t au8[16];
740} PGMPAGE;
741AssertCompileSize(PGMPAGE, 16);
742/** Pointer to a physical guest page. */
743typedef PGMPAGE *PPGMPAGE;
744/** Pointer to a const physical guest page. */
745typedef const PGMPAGE *PCPGMPAGE;
746/** Pointer to a physical guest page pointer. */
747typedef PPGMPAGE *PPPGMPAGE;
748
749
750/**
751 * Clears the page structure.
752 * @param a_pPage Pointer to the physical guest page tracking structure.
753 */
754#define PGM_PAGE_CLEAR(a_pPage) \
755 do { \
756 (a_pPage)->au64[0] = 0; \
757 (a_pPage)->au64[1] = 0; \
758 } while (0)
759
760/**
761 * Initializes the page structure.
762 * @param a_pPage Pointer to the physical guest page tracking structure.
763 */
764#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
765 do { \
766 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
767 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
768 (a_pPage)->au64[0] = SetHCPhysTmp; \
769 (a_pPage)->au64[1] = 0; \
770 (a_pPage)->s.idPage = (a_idPage); \
771 (a_pPage)->s.uStateY = (a_uState); \
772 (a_pPage)->s.uTypeY = (a_uType); \
773 } while (0)
774
775/**
776 * Initializes the page structure of a ZERO page.
777 * @param a_pPage Pointer to the physical guest page tracking structure.
778 * @param a_pVM The VM handle (for getting the zero page address).
779 * @param a_uType The page type (PGMPAGETYPE).
780 */
781#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
782 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
783
784
785/** @name The Page state, PGMPAGE::uStateY.
786 * @{ */
787/** The zero page.
788 * This is a per-VM page that's never ever mapped writable. */
789#define PGM_PAGE_STATE_ZERO 0
790/** A allocated page.
791 * This is a per-VM page allocated from the page pool (or wherever
792 * we get MMIO2 pages from if the type is MMIO2).
793 */
794#define PGM_PAGE_STATE_ALLOCATED 1
795/** A allocated page that's being monitored for writes.
796 * The shadow page table mappings are read-only. When a write occurs, the
797 * fWrittenTo member is set, the page remapped as read-write and the state
798 * moved back to allocated. */
799#define PGM_PAGE_STATE_WRITE_MONITORED 2
800/** The page is shared, aka. copy-on-write.
801 * This is a page that's shared with other VMs. */
802#define PGM_PAGE_STATE_SHARED 3
803/** The page is ballooned, so no longer available for this VM. */
804#define PGM_PAGE_STATE_BALLOONED 4
805/** @} */
806
807
808/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
809#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
810# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
811#else
812# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
813#endif
814
815/**
816 * Gets the page state.
817 * @returns page state (PGM_PAGE_STATE_*).
818 * @param a_pPage Pointer to the physical guest page tracking structure.
819 *
820 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
821 * builds.
822 */
823#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
824#if defined(__GNUC__) && defined(VBOX_STRICT)
825# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
826#else
827# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
828#endif
829
830/**
831 * Sets the page state.
832 * @param a_pVM The VM handle, only used for lock ownership assertions.
833 * @param a_pPage Pointer to the physical guest page tracking structure.
834 * @param a_uState The new page state.
835 */
836#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
837 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
838
839
840/**
841 * Gets the host physical address of the guest page.
842 * @returns host physical address (RTHCPHYS).
843 * @param a_pPage Pointer to the physical guest page tracking structure.
844 *
845 * @remarks In strict builds on gcc platforms, this macro will make some ugly
846 * assumption about a valid pVM variable/parameter being in the
847 * current context. It will use this pVM variable to assert that the
848 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
849 * pVM is not around.
850 */
851#if 0
852# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
853# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
854#else
855# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
856# if defined(__GNUC__) && defined(VBOX_STRICT)
857# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
858# else
859# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
860# endif
861#endif
862
863/**
864 * Sets the host physical address of the guest page.
865 *
866 * @param a_pVM The VM handle, only used for lock ownership assertions.
867 * @param a_pPage Pointer to the physical guest page tracking structure.
868 * @param a_HCPhys The new host physical address.
869 */
870#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
871 do { \
872 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
873 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
874 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
875 PGM_PAGE_ASSERT_LOCK(a_pVM); \
876 } while (0)
877
878/**
879 * Get the Page ID.
880 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
881 * @param a_pPage Pointer to the physical guest page tracking structure.
882 */
883#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
884
885/**
886 * Sets the Page ID.
887 * @param a_pVM The VM handle, only used for lock ownership assertions.
888 * @param a_pPage Pointer to the physical guest page tracking structure.
889 * @param a_idPage The new page ID.
890 */
891#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
892 do { \
893 (a_pPage)->s.idPage = (a_idPage); \
894 PGM_PAGE_ASSERT_LOCK(a_pVM); \
895 } while (0)
896
897/**
898 * Get the Chunk ID.
899 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
900 * @param a_pPage Pointer to the physical guest page tracking structure.
901 */
902#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
903
904/**
905 * Get the index of the page within the allocation chunk.
906 * @returns The page index.
907 * @param a_pPage Pointer to the physical guest page tracking structure.
908 */
909#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
910
911/**
912 * Gets the page type.
913 * @returns The page type.
914 * @param a_pPage Pointer to the physical guest page tracking structure.
915 *
916 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
917 * builds.
918 */
919#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
920#if defined(__GNUC__) && defined(VBOX_STRICT)
921# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
922#else
923# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
924#endif
925
926/**
927 * Sets the page type.
928 *
929 * @param a_pVM The VM handle, only used for lock ownership assertions.
930 * @param a_pPage Pointer to the physical guest page tracking structure.
931 * @param a_enmType The new page type (PGMPAGETYPE).
932 */
933#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
934 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
935
936/**
937 * Gets the page table index
938 * @returns The page table index.
939 * @param a_pPage Pointer to the physical guest page tracking structure.
940 */
941#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
942
943/**
944 * Sets the page table index.
945 * @param a_pVM The VM handle, only used for lock ownership assertions.
946 * @param a_pPage Pointer to the physical guest page tracking structure.
947 * @param a_iPte New page table index.
948 */
949#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
950 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
951
952/**
953 * Checks if the page is marked for MMIO.
954 * @returns true/false.
955 * @param a_pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
958
959/**
960 * Checks if the page is backed by the ZERO page.
961 * @returns true/false.
962 * @param a_pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
965
966/**
967 * Checks if the page is backed by a SHARED page.
968 * @returns true/false.
969 * @param a_pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
972
973/**
974 * Checks if the page is ballooned.
975 * @returns true/false.
976 * @param a_pPage Pointer to the physical guest page tracking structure.
977 */
978#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
979
980/**
981 * Checks if the page is allocated.
982 * @returns true/false.
983 * @param a_pPage Pointer to the physical guest page tracking structure.
984 */
985#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
986
987/**
988 * Marks the page as written to (for GMM change monitoring).
989 * @param a_pVM The VM handle, only used for lock ownership assertions.
990 * @param a_pPage Pointer to the physical guest page tracking structure.
991 */
992#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
993 do { (a_pPage)->au8[1] |= UINT8_C(0x80); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0) /// FIXME FIXME
994
995/**
996 * Clears the written-to indicator.
997 * @param a_pVM The VM handle, only used for lock ownership assertions.
998 * @param a_pPage Pointer to the physical guest page tracking structure.
999 */
1000#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1001 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1002
1003/**
1004 * Checks if the page was marked as written-to.
1005 * @returns true/false.
1006 * @param a_pPage Pointer to the physical guest page tracking structure.
1007 */
1008#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1009
1010/**
1011 * Marks the page as dirty for FTM
1012 * @param a_pPage Pointer to the physical guest page tracking structure.
1013 */
1014#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1015
1016/**
1017 * Clears the FTM dirty indicator
1018 * @param a_pPage Pointer to the physical guest page tracking structure.
1019 */
1020#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1021
1022/**
1023 * Checks if the page was marked as dirty for FTM
1024 * @returns true/false.
1025 * @param a_pPage Pointer to the physical guest page tracking structure.
1026 */
1027#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1028
1029
1030/** @name PT usage values (PGMPAGE::u2PDEType).
1031 *
1032 * @{ */
1033/** Either as a PT or PDE. */
1034#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1035/** Must use a page table to map the range. */
1036#define PGM_PAGE_PDE_TYPE_PT 1
1037/** Can use a page directory entry to map the continuous range. */
1038#define PGM_PAGE_PDE_TYPE_PDE 2
1039/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1040#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1041/** @} */
1042
1043/**
1044 * Set the PDE type of the page
1045 * @param a_pVM The VM handle, only used for lock ownership assertions.
1046 * @param a_pPage Pointer to the physical guest page tracking structure.
1047 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1048 */
1049#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1050 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1051
1052/**
1053 * Checks if the page was marked being part of a large page
1054 * @returns true/false.
1055 * @param a_pPage Pointer to the physical guest page tracking structure.
1056 */
1057#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1058
1059/** Enabled optimized access handler tests.
1060 * These optimizations makes ASSUMPTIONS about the state values and the s1
1061 * layout. When enabled, the compiler should normally generate more compact
1062 * code.
1063 */
1064#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1065
1066/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1067 *
1068 * @remarks The values are assigned in order of priority, so we can calculate
1069 * the correct state for a page with different handlers installed.
1070 * @{ */
1071/** No handler installed. */
1072#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1073/** Monitoring is temporarily disabled. */
1074#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1075/** Write access is monitored. */
1076#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1077/** All access is monitored. */
1078#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1079/** @} */
1080
1081/**
1082 * Gets the physical access handler state of a page.
1083 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1084 * @param a_pPage Pointer to the physical guest page tracking structure.
1085 */
1086#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1087
1088/**
1089 * Sets the physical access handler state of a page.
1090 * @param a_pPage Pointer to the physical guest page tracking structure.
1091 * @param a_uState The new state value.
1092 */
1093#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1094 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1095
1096/**
1097 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1098 * @returns true/false
1099 * @param a_pPage Pointer to the physical guest page tracking structure.
1100 */
1101#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1102 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1103
1104/**
1105 * Checks if the page has any active physical access handlers.
1106 * @returns true/false
1107 * @param a_pPage Pointer to the physical guest page tracking structure.
1108 */
1109#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1110 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1111
1112
1113/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1114 *
1115 * @remarks The values are assigned in order of priority, so we can calculate
1116 * the correct state for a page with different handlers installed.
1117 * @{ */
1118/** No handler installed. */
1119#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1120/* 1 is reserved so the lineup is identical with the physical ones. */
1121/** Write access is monitored. */
1122#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1123/** All access is monitored. */
1124#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1125/** @} */
1126
1127/**
1128 * Gets the virtual access handler state of a page.
1129 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1130 * @param a_pPage Pointer to the physical guest page tracking structure.
1131 */
1132#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1133
1134/**
1135 * Sets the virtual access handler state of a page.
1136 * @param a_pPage Pointer to the physical guest page tracking structure.
1137 * @param a_uState The new state value.
1138 */
1139#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1140 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1141
1142/**
1143 * Checks if the page has any virtual access handlers.
1144 * @returns true/false
1145 * @param a_pPage Pointer to the physical guest page tracking structure.
1146 */
1147#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1148 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1149
1150/**
1151 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1152 * virtual handlers.
1153 * @returns true/false
1154 * @param a_pPage Pointer to the physical guest page tracking structure.
1155 */
1156#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1157 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1158
1159
1160/**
1161 * Checks if the page has any access handlers, including temporarily disabled ones.
1162 * @returns true/false
1163 * @param a_pPage Pointer to the physical guest page tracking structure.
1164 */
1165#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1166# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1167 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1168#else
1169# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1170 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1171 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1172#endif
1173
1174/**
1175 * Checks if the page has any active access handlers.
1176 * @returns true/false
1177 * @param a_pPage Pointer to the physical guest page tracking structure.
1178 */
1179#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1180# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1181 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1182#else
1183# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1184 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1185 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1186#endif
1187
1188/**
1189 * Checks if the page has any active access handlers catching all accesses.
1190 * @returns true/false
1191 * @param a_pPage Pointer to the physical guest page tracking structure.
1192 */
1193#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1194# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1195 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1196 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1197#else
1198# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1199 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1200 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1201#endif
1202
1203
1204/** @def PGM_PAGE_GET_TRACKING
1205 * Gets the packed shadow page pool tracking data associated with a guest page.
1206 * @returns uint16_t containing the data.
1207 * @param a_pPage Pointer to the physical guest page tracking structure.
1208 */
1209#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1210#if defined(__GNUC__) && defined(VBOX_STRICT)
1211# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1212#else
1213# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1214#endif
1215
1216/** @def PGM_PAGE_SET_TRACKING
1217 * Sets the packed shadow page pool tracking data associated with a guest page.
1218 * @param a_pVM The VM handle, only used for lock ownership assertions.
1219 * @param a_pPage Pointer to the physical guest page tracking structure.
1220 * @param a_u16TrackingData The tracking data to store.
1221 */
1222#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1223 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1224
1225/** @def PGM_PAGE_GET_TD_CREFS
1226 * Gets the @a cRefs tracking data member.
1227 * @returns cRefs.
1228 * @param a_pPage Pointer to the physical guest page tracking structure.
1229 */
1230#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1231 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1232#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1233 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1234
1235/** @def PGM_PAGE_GET_TD_IDX
1236 * Gets the @a idx tracking data member.
1237 * @returns idx.
1238 * @param a_pPage Pointer to the physical guest page tracking structure.
1239 */
1240#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1241 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1242#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1243 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1244
1245
1246/** Max number of locks on a page. */
1247#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1248
1249/** Get the read lock count.
1250 * @returns count.
1251 * @param a_pPage Pointer to the physical guest page tracking structure.
1252 */
1253#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1254
1255/** Get the write lock count.
1256 * @returns count.
1257 * @param a_pPage Pointer to the physical guest page tracking structure.
1258 */
1259#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1260
1261/** Decrement the read lock counter.
1262 * @param a_pPage Pointer to the physical guest page tracking structure.
1263 */
1264#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1265
1266/** Decrement the write lock counter.
1267 * @param a_pPage Pointer to the physical guest page tracking structure.
1268 */
1269#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1270
1271/** Increment the read lock counter.
1272 * @param a_pPage Pointer to the physical guest page tracking structure.
1273 */
1274#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1275
1276/** Increment the write lock counter.
1277 * @param a_pPage Pointer to the physical guest page tracking structure.
1278 */
1279#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1280
1281
1282#if 0
1283/** Enables sanity checking of write monitoring using CRC-32. */
1284# define PGMLIVESAVERAMPAGE_WITH_CRC32
1285#endif
1286
1287/**
1288 * Per page live save tracking data.
1289 */
1290typedef struct PGMLIVESAVERAMPAGE
1291{
1292 /** Number of times it has been dirtied. */
1293 uint32_t cDirtied : 24;
1294 /** Whether it is currently dirty. */
1295 uint32_t fDirty : 1;
1296 /** Ignore the page.
1297 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1298 * deal with these after pausing the VM and DevPCI have said it bit about
1299 * remappings. */
1300 uint32_t fIgnore : 1;
1301 /** Was a ZERO page last time around. */
1302 uint32_t fZero : 1;
1303 /** Was a SHARED page last time around. */
1304 uint32_t fShared : 1;
1305 /** Whether the page is/was write monitored in a previous pass. */
1306 uint32_t fWriteMonitored : 1;
1307 /** Whether the page is/was write monitored earlier in this pass. */
1308 uint32_t fWriteMonitoredJustNow : 1;
1309 /** Bits reserved for future use. */
1310 uint32_t u2Reserved : 2;
1311#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1312 /** CRC-32 for the page. This is for internal consistency checks. */
1313 uint32_t u32Crc;
1314#endif
1315} PGMLIVESAVERAMPAGE;
1316#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1317AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1318#else
1319AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1320#endif
1321/** Pointer to the per page live save tracking data. */
1322typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1323
1324/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1325#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1326
1327
1328/**
1329 * RAM range for GC Phys to HC Phys conversion.
1330 *
1331 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1332 * conversions too, but we'll let MM handle that for now.
1333 *
1334 * This structure is used by linked lists in both GC and HC.
1335 */
1336typedef struct PGMRAMRANGE
1337{
1338 /** Start of the range. Page aligned. */
1339 RTGCPHYS GCPhys;
1340 /** Size of the range. (Page aligned of course). */
1341 RTGCPHYS cb;
1342 /** Pointer to the next RAM range - for R3. */
1343 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1344 /** Pointer to the next RAM range - for R0. */
1345 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1346 /** Pointer to the next RAM range - for RC. */
1347 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1348 /** PGM_RAM_RANGE_FLAGS_* flags. */
1349 uint32_t fFlags;
1350 /** Last address in the range (inclusive). Page aligned (-1). */
1351 RTGCPHYS GCPhysLast;
1352 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1353 R3PTRTYPE(void *) pvR3;
1354 /** Live save per page tracking data. */
1355 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1356 /** The range description. */
1357 R3PTRTYPE(const char *) pszDesc;
1358 /** Pointer to self - R0 pointer. */
1359 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1360 /** Pointer to self - RC pointer. */
1361 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1362
1363 /** Alignment padding. */
1364 RTRCPTR Alignment0;
1365 /** Pointer to the left search three node - ring-3 context. */
1366 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1367 /** Pointer to the right search three node - ring-3 context. */
1368 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1369 /** Pointer to the left search three node - ring-0 context. */
1370 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1371 /** Pointer to the right search three node - ring-0 context. */
1372 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1373 /** Pointer to the left search three node - raw-mode context. */
1374 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1375 /** Pointer to the right search three node - raw-mode context. */
1376 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1377
1378 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1379#if HC_ARCH_BITS == 32
1380 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1381#endif
1382 /** Array of physical guest page tracking structures. */
1383 PGMPAGE aPages[1];
1384} PGMRAMRANGE;
1385/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1386typedef PGMRAMRANGE *PPGMRAMRANGE;
1387
1388/** @name PGMRAMRANGE::fFlags
1389 * @{ */
1390/** The RAM range is floating around as an independent guest mapping. */
1391#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1392/** Ad hoc RAM range for an ROM mapping. */
1393#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1394/** Ad hoc RAM range for an MMIO mapping. */
1395#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1396/** Ad hoc RAM range for an MMIO2 mapping. */
1397#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1398/** @} */
1399
1400/** Tests if a RAM range is an ad hoc one or not.
1401 * @returns true/false.
1402 * @param pRam The RAM range.
1403 */
1404#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1405 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1406
1407/** The number of entries in the RAM range TLBs (there is one for each
1408 * context). Must be a power of two. */
1409#define PGM_RAMRANGE_TLB_ENTRIES 8
1410
1411/**
1412 * Calculates the RAM range TLB index for the physical address.
1413 *
1414 * @returns RAM range TLB index.
1415 * @param GCPhys The guest physical address.
1416 */
1417#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1418
1419
1420
1421/**
1422 * Per page tracking structure for ROM image.
1423 *
1424 * A ROM image may have a shadow page, in which case we may have two pages
1425 * backing it. This structure contains the PGMPAGE for both while
1426 * PGMRAMRANGE have a copy of the active one. It is important that these
1427 * aren't out of sync in any regard other than page pool tracking data.
1428 */
1429typedef struct PGMROMPAGE
1430{
1431 /** The page structure for the virgin ROM page. */
1432 PGMPAGE Virgin;
1433 /** The page structure for the shadow RAM page. */
1434 PGMPAGE Shadow;
1435 /** The current protection setting. */
1436 PGMROMPROT enmProt;
1437 /** Live save status information. Makes use of unused alignment space. */
1438 struct
1439 {
1440 /** The previous protection value. */
1441 uint8_t u8Prot;
1442 /** Written to flag set by the handler. */
1443 bool fWrittenTo;
1444 /** Whether the shadow page is dirty or not. */
1445 bool fDirty;
1446 /** Whether it was dirtied in the recently. */
1447 bool fDirtiedRecently;
1448 } LiveSave;
1449} PGMROMPAGE;
1450AssertCompileSizeAlignment(PGMROMPAGE, 8);
1451/** Pointer to a ROM page tracking structure. */
1452typedef PGMROMPAGE *PPGMROMPAGE;
1453
1454
1455/**
1456 * A registered ROM image.
1457 *
1458 * This is needed to keep track of ROM image since they generally intrude
1459 * into a PGMRAMRANGE. It also keeps track of additional info like the
1460 * two page sets (read-only virgin and read-write shadow), the current
1461 * state of each page.
1462 *
1463 * Because access handlers cannot easily be executed in a different
1464 * context, the ROM ranges needs to be accessible and in all contexts.
1465 */
1466typedef struct PGMROMRANGE
1467{
1468 /** Pointer to the next range - R3. */
1469 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1470 /** Pointer to the next range - R0. */
1471 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1472 /** Pointer to the next range - RC. */
1473 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1474 /** Pointer alignment */
1475 RTRCPTR RCPtrAlignment;
1476 /** Address of the range. */
1477 RTGCPHYS GCPhys;
1478 /** Address of the last byte in the range. */
1479 RTGCPHYS GCPhysLast;
1480 /** Size of the range. */
1481 RTGCPHYS cb;
1482 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1483 uint32_t fFlags;
1484 /** The saved state range ID. */
1485 uint8_t idSavedState;
1486 /** Alignment padding. */
1487 uint8_t au8Alignment[3];
1488 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1489 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1490 /** The size bits pvOriginal points to. */
1491 uint32_t cbOriginal;
1492 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1493 * This is used for strictness checks. */
1494 R3PTRTYPE(const void *) pvOriginal;
1495 /** The ROM description. */
1496 R3PTRTYPE(const char *) pszDesc;
1497 /** The per page tracking structures. */
1498 PGMROMPAGE aPages[1];
1499} PGMROMRANGE;
1500/** Pointer to a ROM range. */
1501typedef PGMROMRANGE *PPGMROMRANGE;
1502
1503
1504/**
1505 * Live save per page data for an MMIO2 page.
1506 *
1507 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1508 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1509 * CRC-32 for detecting changes as well as special handling of zero pages. This
1510 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1511 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1512 * because of speed (2.5x and 6x slower).)
1513 *
1514 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1515 * save but normally is disabled. Since we can write monitor guest
1516 * accesses on our own, we only need this for host accesses. Shouldn't be
1517 * too difficult for DevVGA, VMMDev might be doable, the planned
1518 * networking fun will be fun since it involves ring-0.
1519 */
1520typedef struct PGMLIVESAVEMMIO2PAGE
1521{
1522 /** Set if the page is considered dirty. */
1523 bool fDirty;
1524 /** The number of scans this page has remained unchanged for.
1525 * Only updated for dirty pages. */
1526 uint8_t cUnchangedScans;
1527 /** Whether this page was zero at the last scan. */
1528 bool fZero;
1529 /** Alignment padding. */
1530 bool fReserved;
1531 /** CRC-32 for the first half of the page.
1532 * This is used together with u32CrcH2 to quickly detect changes in the page
1533 * during the non-final passes. */
1534 uint32_t u32CrcH1;
1535 /** CRC-32 for the second half of the page. */
1536 uint32_t u32CrcH2;
1537 /** SHA-1 for the saved page.
1538 * This is used in the final pass to skip pages without changes. */
1539 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1540} PGMLIVESAVEMMIO2PAGE;
1541/** Pointer to a live save status data for an MMIO2 page. */
1542typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1543
1544/**
1545 * A registered MMIO2 (= Device RAM) range.
1546 *
1547 * There are a few reason why we need to keep track of these
1548 * registrations. One of them is the deregistration & cleanup stuff,
1549 * while another is that the PGMRAMRANGE associated with such a region may
1550 * have to be removed from the ram range list.
1551 *
1552 * Overlapping with a RAM range has to be 100% or none at all. The pages
1553 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1554 * will be raised if a partial overlap or an overlap of ROM pages is
1555 * encountered. On an overlap we will free all the existing RAM pages and
1556 * put in the ram range pages instead.
1557 */
1558typedef struct PGMMMIO2RANGE
1559{
1560 /** The owner of the range. (a device) */
1561 PPDMDEVINSR3 pDevInsR3;
1562 /** Pointer to the ring-3 mapping of the allocation. */
1563 RTR3PTR pvR3;
1564 /** Pointer to the next range - R3. */
1565 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1566 /** Whether it's mapped or not. */
1567 bool fMapped;
1568 /** Whether it's overlapping or not. */
1569 bool fOverlapping;
1570 /** The PCI region number.
1571 * @remarks This ASSUMES that nobody will ever really need to have multiple
1572 * PCI devices with matching MMIO region numbers on a single device. */
1573 uint8_t iRegion;
1574 /** The saved state range ID. */
1575 uint8_t idSavedState;
1576 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1577 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1578 /** Live save per page tracking data. */
1579 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1580 /** The associated RAM range. */
1581 PGMRAMRANGE RamRange;
1582} PGMMMIO2RANGE;
1583/** Pointer to a MMIO2 range. */
1584typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1585
1586
1587
1588
1589/**
1590 * PGMPhysRead/Write cache entry
1591 */
1592typedef struct PGMPHYSCACHEENTRY
1593{
1594 /** R3 pointer to physical page. */
1595 R3PTRTYPE(uint8_t *) pbR3;
1596 /** GC Physical address for cache entry */
1597 RTGCPHYS GCPhys;
1598#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1599 RTGCPHYS u32Padding0; /**< alignment padding. */
1600#endif
1601} PGMPHYSCACHEENTRY;
1602
1603/**
1604 * PGMPhysRead/Write cache to reduce REM memory access overhead
1605 */
1606typedef struct PGMPHYSCACHE
1607{
1608 /** Bitmap of valid cache entries */
1609 uint64_t aEntries;
1610 /** Cache entries */
1611 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1612} PGMPHYSCACHE;
1613
1614
1615/** Pointer to an allocation chunk ring-3 mapping. */
1616typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1617/** Pointer to an allocation chunk ring-3 mapping pointer. */
1618typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1619
1620/**
1621 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1622 *
1623 * The primary tree (Core) uses the chunk id as key.
1624 */
1625typedef struct PGMCHUNKR3MAP
1626{
1627 /** The key is the chunk id. */
1628 AVLU32NODECORE Core;
1629 /** The current age thingy. */
1630 uint32_t iAge;
1631 /** The current reference count. */
1632 uint32_t volatile cRefs;
1633 /** The current permanent reference count. */
1634 uint32_t volatile cPermRefs;
1635 /** The mapping address. */
1636 void *pv;
1637} PGMCHUNKR3MAP;
1638
1639/**
1640 * Allocation chunk ring-3 mapping TLB entry.
1641 */
1642typedef struct PGMCHUNKR3MAPTLBE
1643{
1644 /** The chunk id. */
1645 uint32_t volatile idChunk;
1646#if HC_ARCH_BITS == 64
1647 uint32_t u32Padding; /**< alignment padding. */
1648#endif
1649 /** The chunk map. */
1650#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1651 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1652#else
1653 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1654#endif
1655} PGMCHUNKR3MAPTLBE;
1656/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1657typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1658
1659/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1660 * @remark Must be a power of two value. */
1661#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1662
1663/**
1664 * Allocation chunk ring-3 mapping TLB.
1665 *
1666 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1667 * At first glance this might look kinda odd since AVL trees are
1668 * supposed to give the most optimal lookup times of all trees
1669 * due to their balancing. However, take a tree with 1023 nodes
1670 * in it, that's 10 levels, meaning that most searches has to go
1671 * down 9 levels before they find what they want. This isn't fast
1672 * compared to a TLB hit. There is the factor of cache misses,
1673 * and of course the problem with trees and branch prediction.
1674 * This is why we use TLBs in front of most of the trees.
1675 *
1676 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1677 * difficult when we switch to the new inlined AVL trees (from kStuff).
1678 */
1679typedef struct PGMCHUNKR3MAPTLB
1680{
1681 /** The TLB entries. */
1682 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1683} PGMCHUNKR3MAPTLB;
1684
1685/**
1686 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1687 * @returns Chunk TLB index.
1688 * @param idChunk The Chunk ID.
1689 */
1690#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1691
1692
1693/**
1694 * Ring-3 guest page mapping TLB entry.
1695 * @remarks used in ring-0 as well at the moment.
1696 */
1697typedef struct PGMPAGER3MAPTLBE
1698{
1699 /** Address of the page. */
1700 RTGCPHYS volatile GCPhys;
1701 /** The guest page. */
1702#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1703 R3PTRTYPE(PPGMPAGE) volatile pPage;
1704#else
1705 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1706#endif
1707 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1708#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1709 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1710#else
1711 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1712#endif
1713 /** The address */
1714#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1715 R3PTRTYPE(void *) volatile pv;
1716#else
1717 R3R0PTRTYPE(void *) volatile pv;
1718#endif
1719#if HC_ARCH_BITS == 32
1720 uint32_t u32Padding; /**< alignment padding. */
1721#endif
1722} PGMPAGER3MAPTLBE;
1723/** Pointer to an entry in the HC physical TLB. */
1724typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1725
1726
1727/** The number of entries in the ring-3 guest page mapping TLB.
1728 * @remarks The value must be a power of two. */
1729#define PGM_PAGER3MAPTLB_ENTRIES 256
1730
1731/**
1732 * Ring-3 guest page mapping TLB.
1733 * @remarks used in ring-0 as well at the moment.
1734 */
1735typedef struct PGMPAGER3MAPTLB
1736{
1737 /** The TLB entries. */
1738 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1739} PGMPAGER3MAPTLB;
1740/** Pointer to the ring-3 guest page mapping TLB. */
1741typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1742
1743/**
1744 * Calculates the index of the TLB entry for the specified guest page.
1745 * @returns Physical TLB index.
1746 * @param GCPhys The guest physical address.
1747 */
1748#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1749
1750
1751/**
1752 * Raw-mode context dynamic mapping cache entry.
1753 *
1754 * Because of raw-mode context being reloctable and all relocations are applied
1755 * in ring-3, this has to be defined here and be RC specific.
1756 *
1757 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1758 */
1759typedef struct PGMRCDYNMAPENTRY
1760{
1761 /** The physical address of the currently mapped page.
1762 * This is duplicate for three reasons: cache locality, cache policy of the PT
1763 * mappings and sanity checks. */
1764 RTHCPHYS HCPhys;
1765 /** Pointer to the page. */
1766 RTRCPTR pvPage;
1767 /** The number of references. */
1768 int32_t volatile cRefs;
1769 /** PTE pointer union. */
1770 struct PGMRCDYNMAPENTRY_PPTE
1771 {
1772 /** PTE pointer, 32-bit legacy version. */
1773 RCPTRTYPE(PX86PTE) pLegacy;
1774 /** PTE pointer, PAE version. */
1775 RCPTRTYPE(PX86PTEPAE) pPae;
1776 } uPte;
1777} PGMRCDYNMAPENTRY;
1778/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1779typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1780
1781
1782/**
1783 * Dynamic mapping cache for the raw-mode context.
1784 *
1785 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1786 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1787 * so that we can perform relocations from PGMR3Relocate. This has the
1788 * consequence that we must have separate ring-0 and raw-mode context versions
1789 * of this struct even if they share the basic elements.
1790 *
1791 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1792 */
1793typedef struct PGMRCDYNMAP
1794{
1795 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1796 uint32_t u32Magic;
1797 /** Array for tracking and managing the pages. */
1798 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1799 /** The cache size given as a number of pages. */
1800 uint32_t cPages;
1801 /** The current load.
1802 * This does not include guard pages. */
1803 uint32_t cLoad;
1804 /** The max load ever.
1805 * This is maintained to get trigger adding of more mapping space. */
1806 uint32_t cMaxLoad;
1807 /** The number of guard pages. */
1808 uint32_t cGuardPages;
1809 /** The number of users (protected by hInitLock). */
1810 uint32_t cUsers;
1811} PGMRCDYNMAP;
1812/** Pointer to the dynamic cache for the raw-mode context. */
1813typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1814
1815
1816/**
1817 * Mapping cache usage set entry.
1818 *
1819 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1820 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1821 * cache. If it's extended to include ring-3, well, then something
1822 * will have be changed here...
1823 */
1824typedef struct PGMMAPSETENTRY
1825{
1826 /** Pointer to the page. */
1827#ifndef IN_RC
1828 RTR0PTR pvPage;
1829#else
1830 RTRCPTR pvPage;
1831# if HC_ARCH_BITS == 64
1832 uint32_t u32Alignment2;
1833# endif
1834#endif
1835 /** The mapping cache index. */
1836 uint16_t iPage;
1837 /** The number of references.
1838 * The max is UINT16_MAX - 1. */
1839 uint16_t cRefs;
1840 /** The number inlined references.
1841 * The max is UINT16_MAX - 1. */
1842 uint16_t cInlinedRefs;
1843 /** Unreferences. */
1844 uint16_t cUnrefs;
1845
1846#if HC_ARCH_BITS == 32
1847 uint32_t u32Alignment1;
1848#endif
1849 /** The physical address for this entry. */
1850 RTHCPHYS HCPhys;
1851} PGMMAPSETENTRY;
1852AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1853AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1854/** Pointer to a mapping cache usage set entry. */
1855typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1856
1857/**
1858 * Mapping cache usage set.
1859 *
1860 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1861 * done during exits / traps. The set is
1862 */
1863typedef struct PGMMAPSET
1864{
1865 /** The number of occupied entries.
1866 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1867 * dynamic mappings. */
1868 uint32_t cEntries;
1869 /** The start of the current subset.
1870 * This is UINT32_MAX if no subset is currently open. */
1871 uint32_t iSubset;
1872 /** The index of the current CPU, only valid if the set is open. */
1873 int32_t iCpu;
1874 uint32_t alignment;
1875 /** The entries. */
1876 PGMMAPSETENTRY aEntries[64];
1877 /** HCPhys -> iEntry fast lookup table.
1878 * Use PGMMAPSET_HASH for hashing.
1879 * The entries may or may not be valid, check against cEntries. */
1880 uint8_t aiHashTable[128];
1881} PGMMAPSET;
1882AssertCompileSizeAlignment(PGMMAPSET, 8);
1883/** Pointer to the mapping cache set. */
1884typedef PGMMAPSET *PPGMMAPSET;
1885
1886/** PGMMAPSET::cEntries value for a closed set. */
1887#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1888
1889/** Hash function for aiHashTable. */
1890#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1891
1892
1893/** @name Context neutral page mapper TLB.
1894 *
1895 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1896 * code is writting in a kind of context neutral way. Time will show whether
1897 * this actually makes sense or not...
1898 *
1899 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1900 * context ends up using a global mapping cache on some platforms
1901 * (darwin).
1902 *
1903 * @{ */
1904/** @typedef PPGMPAGEMAPTLB
1905 * The page mapper TLB pointer type for the current context. */
1906/** @typedef PPGMPAGEMAPTLB
1907 * The page mapper TLB entry pointer type for the current context. */
1908/** @typedef PPGMPAGEMAPTLB
1909 * The page mapper TLB entry pointer pointer type for the current context. */
1910/** @def PGM_PAGEMAPTLB_ENTRIES
1911 * The number of TLB entries in the page mapper TLB for the current context. */
1912/** @def PGM_PAGEMAPTLB_IDX
1913 * Calculate the TLB index for a guest physical address.
1914 * @returns The TLB index.
1915 * @param GCPhys The guest physical address. */
1916/** @typedef PPGMPAGEMAP
1917 * Pointer to a page mapper unit for current context. */
1918/** @typedef PPPGMPAGEMAP
1919 * Pointer to a page mapper unit pointer for current context. */
1920#ifdef IN_RC
1921// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1922// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1923// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1924# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1925# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1926 typedef void * PPGMPAGEMAP;
1927 typedef void ** PPPGMPAGEMAP;
1928//#elif IN_RING0
1929// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1930// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1931// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1932//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1933//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1934// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1935// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1936#else
1937 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1938 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1939 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1940# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1941# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1942 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1943 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1944#endif
1945/** @} */
1946
1947
1948/** @name PGM Pool Indexes.
1949 * Aka. the unique shadow page identifier.
1950 * @{ */
1951/** NIL page pool IDX. */
1952#define NIL_PGMPOOL_IDX 0
1953/** The first normal index. */
1954#define PGMPOOL_IDX_FIRST_SPECIAL 1
1955/** Page directory (32-bit root). */
1956#define PGMPOOL_IDX_PD 1
1957/** Page Directory Pointer Table (PAE root). */
1958#define PGMPOOL_IDX_PDPT 2
1959/** AMD64 CR3 level index.*/
1960#define PGMPOOL_IDX_AMD64_CR3 3
1961/** Nested paging root.*/
1962#define PGMPOOL_IDX_NESTED_ROOT 4
1963/** The first normal index. */
1964#define PGMPOOL_IDX_FIRST 5
1965/** The last valid index. (inclusive, 14 bits) */
1966#define PGMPOOL_IDX_LAST 0x3fff
1967/** @} */
1968
1969/** The NIL index for the parent chain. */
1970#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1971#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1972
1973/**
1974 * Node in the chain linking a shadowed page to it's parent (user).
1975 */
1976#pragma pack(1)
1977typedef struct PGMPOOLUSER
1978{
1979 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1980 uint16_t iNext;
1981 /** The user page index. */
1982 uint16_t iUser;
1983 /** Index into the user table. */
1984 uint32_t iUserTable;
1985} PGMPOOLUSER, *PPGMPOOLUSER;
1986typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1987#pragma pack()
1988
1989
1990/** The NIL index for the phys ext chain. */
1991#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1992/** The NIL pte index for a phys ext chain slot. */
1993#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1994
1995/**
1996 * Node in the chain of physical cross reference extents.
1997 * @todo Calling this an 'extent' is not quite right, find a better name.
1998 * @todo find out the optimal size of the aidx array
1999 */
2000#pragma pack(1)
2001typedef struct PGMPOOLPHYSEXT
2002{
2003 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2004 uint16_t iNext;
2005 /** Alignment. */
2006 uint16_t u16Align;
2007 /** The user page index. */
2008 uint16_t aidx[3];
2009 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2010 uint16_t apte[3];
2011} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2012typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2013#pragma pack()
2014
2015
2016/**
2017 * The kind of page that's being shadowed.
2018 */
2019typedef enum PGMPOOLKIND
2020{
2021 /** The virtual invalid 0 entry. */
2022 PGMPOOLKIND_INVALID = 0,
2023 /** The entry is free (=unused). */
2024 PGMPOOLKIND_FREE,
2025
2026 /** Shw: 32-bit page table; Gst: no paging */
2027 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2028 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2029 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2030 /** Shw: 32-bit page table; Gst: 4MB page. */
2031 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2032 /** Shw: PAE page table; Gst: no paging */
2033 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2034 /** Shw: PAE page table; Gst: 32-bit page table. */
2035 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2036 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2037 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2038 /** Shw: PAE page table; Gst: PAE page table. */
2039 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2040 /** Shw: PAE page table; Gst: 2MB page. */
2041 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2042
2043 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2044 PGMPOOLKIND_32BIT_PD,
2045 /** Shw: 32-bit page directory. Gst: no paging. */
2046 PGMPOOLKIND_32BIT_PD_PHYS,
2047 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2048 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2049 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2050 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2051 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2052 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2053 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2054 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2055 /** Shw: PAE page directory; Gst: PAE page directory. */
2056 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2057 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2058 PGMPOOLKIND_PAE_PD_PHYS,
2059
2060 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2061 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2062 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2063 PGMPOOLKIND_PAE_PDPT,
2064 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2065 PGMPOOLKIND_PAE_PDPT_PHYS,
2066
2067 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2068 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2069 /** Shw: 64-bit page directory pointer table; Gst: no paging */
2070 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2071 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2072 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2073 /** Shw: 64-bit page directory table; Gst: no paging */
2074 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2075
2076 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2077 PGMPOOLKIND_64BIT_PML4,
2078
2079 /** Shw: EPT page directory pointer table; Gst: no paging */
2080 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2081 /** Shw: EPT page directory table; Gst: no paging */
2082 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2083 /** Shw: EPT page table; Gst: no paging */
2084 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2085
2086 /** Shw: Root Nested paging table. */
2087 PGMPOOLKIND_ROOT_NESTED,
2088
2089 /** The last valid entry. */
2090 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2091} PGMPOOLKIND;
2092
2093/**
2094 * The access attributes of the page; only applies to big pages.
2095 */
2096typedef enum
2097{
2098 PGMPOOLACCESS_DONTCARE = 0,
2099 PGMPOOLACCESS_USER_RW,
2100 PGMPOOLACCESS_USER_R,
2101 PGMPOOLACCESS_USER_RW_NX,
2102 PGMPOOLACCESS_USER_R_NX,
2103 PGMPOOLACCESS_SUPERVISOR_RW,
2104 PGMPOOLACCESS_SUPERVISOR_R,
2105 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2106 PGMPOOLACCESS_SUPERVISOR_R_NX
2107} PGMPOOLACCESS;
2108
2109/**
2110 * The tracking data for a page in the pool.
2111 */
2112typedef struct PGMPOOLPAGE
2113{
2114 /** AVL node code with the (R3) physical address of this page. */
2115 AVLOHCPHYSNODECORE Core;
2116 /** Pointer to the R3 mapping of the page. */
2117#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2118 R3PTRTYPE(void *) pvPageR3;
2119#else
2120 R3R0PTRTYPE(void *) pvPageR3;
2121#endif
2122 /** The guest physical address. */
2123#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2124 uint32_t Alignment0;
2125#endif
2126 RTGCPHYS GCPhys;
2127
2128 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2129 RTGCPTR pvLastAccessHandlerRip;
2130 RTGCPTR pvLastAccessHandlerFault;
2131 uint64_t cLastAccessHandlerCount;
2132
2133 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2134 uint8_t enmKind;
2135 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2136 uint8_t enmAccess;
2137 /** The index of this page. */
2138 uint16_t idx;
2139 /** The next entry in the list this page currently resides in.
2140 * It's either in the free list or in the GCPhys hash. */
2141 uint16_t iNext;
2142 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2143 uint16_t iUserHead;
2144 /** The number of present entries. */
2145 uint16_t cPresent;
2146 /** The first entry in the table which is present. */
2147 uint16_t iFirstPresent;
2148 /** The number of modifications to the monitored page. */
2149 uint16_t cModifications;
2150 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2151 uint16_t iModifiedNext;
2152 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2153 uint16_t iModifiedPrev;
2154 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2155 uint16_t iMonitoredNext;
2156 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2157 uint16_t iMonitoredPrev;
2158 /** The next page in the age list. */
2159 uint16_t iAgeNext;
2160 /** The previous page in the age list. */
2161 uint16_t iAgePrev;
2162 /** Used to indicate that the page is zeroed. */
2163 bool fZeroed;
2164 /** Used to indicate that a PT has non-global entries. */
2165 bool fSeenNonGlobal;
2166 /** Used to indicate that we're monitoring writes to the guest page. */
2167 bool fMonitored;
2168 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2169 * (All pages are in the age list.) */
2170 bool fCached;
2171 /** This is used by the R3 access handlers when invoked by an async thread.
2172 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2173 bool volatile fReusedFlushPending;
2174 /** Used to mark the page as dirty (write monitoring is temporarily
2175 * off). */
2176 bool fDirty;
2177
2178 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2179 uint32_t cLocked;
2180 uint32_t idxDirty;
2181 RTGCPTR pvDirtyFault;
2182} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2183/** Pointer to a const pool page. */
2184typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2185
2186
2187/** The hash table size. */
2188# define PGMPOOL_HASH_SIZE 0x40
2189/** The hash function. */
2190# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2191
2192
2193/**
2194 * The shadow page pool instance data.
2195 *
2196 * It's all one big allocation made at init time, except for the
2197 * pages that is. The user nodes follows immediately after the
2198 * page structures.
2199 */
2200typedef struct PGMPOOL
2201{
2202 /** The VM handle - R3 Ptr. */
2203 PVMR3 pVMR3;
2204 /** The VM handle - R0 Ptr. */
2205 PVMR0 pVMR0;
2206 /** The VM handle - RC Ptr. */
2207 PVMRC pVMRC;
2208 /** The max pool size. This includes the special IDs. */
2209 uint16_t cMaxPages;
2210 /** The current pool size. */
2211 uint16_t cCurPages;
2212 /** The head of the free page list. */
2213 uint16_t iFreeHead;
2214 /* Padding. */
2215 uint16_t u16Padding;
2216 /** Head of the chain of free user nodes. */
2217 uint16_t iUserFreeHead;
2218 /** The number of user nodes we've allocated. */
2219 uint16_t cMaxUsers;
2220 /** The number of present page table entries in the entire pool. */
2221 uint32_t cPresent;
2222 /** Pointer to the array of user nodes - RC pointer. */
2223 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2224 /** Pointer to the array of user nodes - R3 pointer. */
2225 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2226 /** Pointer to the array of user nodes - R0 pointer. */
2227 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2228 /** Head of the chain of free phys ext nodes. */
2229 uint16_t iPhysExtFreeHead;
2230 /** The number of user nodes we've allocated. */
2231 uint16_t cMaxPhysExts;
2232 /** Pointer to the array of physical xref extent - RC pointer. */
2233 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2234 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2235 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2236 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2237 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2238 /** Hash table for GCPhys addresses. */
2239 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2240 /** The head of the age list. */
2241 uint16_t iAgeHead;
2242 /** The tail of the age list. */
2243 uint16_t iAgeTail;
2244 /** Set if the cache is enabled. */
2245 bool fCacheEnabled;
2246 /** Alignment padding. */
2247 bool afPadding1[3];
2248 /** Head of the list of modified pages. */
2249 uint16_t iModifiedHead;
2250 /** The current number of modified pages. */
2251 uint16_t cModifiedPages;
2252 /** Access handler, RC. */
2253 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2254 /** Access handler, R0. */
2255 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2256 /** Access handler, R3. */
2257 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2258 /** The access handler description (R3 ptr). */
2259 R3PTRTYPE(const char *) pszAccessHandler;
2260# if HC_ARCH_BITS == 32
2261 /** Alignment padding. */
2262 uint32_t u32Padding2;
2263# endif
2264 /* Next available slot. */
2265 uint32_t idxFreeDirtyPage;
2266 /* Number of active dirty pages. */
2267 uint32_t cDirtyPages;
2268 /* Array of current dirty pgm pool page indices. */
2269 struct
2270 {
2271 uint16_t uIdx;
2272 uint16_t Alignment[3];
2273 uint64_t aPage[512];
2274 } aDirtyPages[16];
2275 /** The number of pages currently in use. */
2276 uint16_t cUsedPages;
2277#ifdef VBOX_WITH_STATISTICS
2278 /** The high water mark for cUsedPages. */
2279 uint16_t cUsedPagesHigh;
2280 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2281 /** Profiling pgmPoolAlloc(). */
2282 STAMPROFILEADV StatAlloc;
2283 /** Profiling pgmR3PoolClearDoIt(). */
2284 STAMPROFILE StatClearAll;
2285 /** Profiling pgmR3PoolReset(). */
2286 STAMPROFILE StatR3Reset;
2287 /** Profiling pgmPoolFlushPage(). */
2288 STAMPROFILE StatFlushPage;
2289 /** Profiling pgmPoolFree(). */
2290 STAMPROFILE StatFree;
2291 /** Counting explicit flushes by PGMPoolFlushPage(). */
2292 STAMCOUNTER StatForceFlushPage;
2293 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2294 STAMCOUNTER StatForceFlushDirtyPage;
2295 /** Counting flushes for reused pages. */
2296 STAMCOUNTER StatForceFlushReused;
2297 /** Profiling time spent zeroing pages. */
2298 STAMPROFILE StatZeroPage;
2299 /** Profiling of pgmPoolTrackDeref. */
2300 STAMPROFILE StatTrackDeref;
2301 /** Profiling pgmTrackFlushGCPhysPT. */
2302 STAMPROFILE StatTrackFlushGCPhysPT;
2303 /** Profiling pgmTrackFlushGCPhysPTs. */
2304 STAMPROFILE StatTrackFlushGCPhysPTs;
2305 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2306 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2307 /** Number of times we've been out of user records. */
2308 STAMCOUNTER StatTrackFreeUpOneUser;
2309 /** Nr of flushed entries. */
2310 STAMCOUNTER StatTrackFlushEntry;
2311 /** Nr of updated entries. */
2312 STAMCOUNTER StatTrackFlushEntryKeep;
2313 /** Profiling deref activity related tracking GC physical pages. */
2314 STAMPROFILE StatTrackDerefGCPhys;
2315 /** Number of linear searches for a HCPhys in the ram ranges. */
2316 STAMCOUNTER StatTrackLinearRamSearches;
2317 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2318 STAMCOUNTER StamTrackPhysExtAllocFailures;
2319 /** Profiling the RC/R0 access handler. */
2320 STAMPROFILE StatMonitorRZ;
2321 /** Times we've failed interpreting the instruction. */
2322 STAMCOUNTER StatMonitorRZEmulateInstr;
2323 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2324 STAMPROFILE StatMonitorRZFlushPage;
2325 /* Times we've detected a page table reinit. */
2326 STAMCOUNTER StatMonitorRZFlushReinit;
2327 /** Counting flushes for pages that are modified too often. */
2328 STAMCOUNTER StatMonitorRZFlushModOverflow;
2329 /** Times we've detected fork(). */
2330 STAMCOUNTER StatMonitorRZFork;
2331 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2332 STAMPROFILE StatMonitorRZHandled;
2333 /** Times we've failed interpreting a patch code instruction. */
2334 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2335 /** Times we've failed interpreting a patch code instruction during flushing. */
2336 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2337 /** The number of times we've seen rep prefixes we can't handle. */
2338 STAMCOUNTER StatMonitorRZRepPrefix;
2339 /** Profiling the REP STOSD cases we've handled. */
2340 STAMPROFILE StatMonitorRZRepStosd;
2341 /** Nr of handled PT faults. */
2342 STAMCOUNTER StatMonitorRZFaultPT;
2343 /** Nr of handled PD faults. */
2344 STAMCOUNTER StatMonitorRZFaultPD;
2345 /** Nr of handled PDPT faults. */
2346 STAMCOUNTER StatMonitorRZFaultPDPT;
2347 /** Nr of handled PML4 faults. */
2348 STAMCOUNTER StatMonitorRZFaultPML4;
2349
2350 /** Profiling the R3 access handler. */
2351 STAMPROFILE StatMonitorR3;
2352 /** Times we've failed interpreting the instruction. */
2353 STAMCOUNTER StatMonitorR3EmulateInstr;
2354 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2355 STAMPROFILE StatMonitorR3FlushPage;
2356 /* Times we've detected a page table reinit. */
2357 STAMCOUNTER StatMonitorR3FlushReinit;
2358 /** Counting flushes for pages that are modified too often. */
2359 STAMCOUNTER StatMonitorR3FlushModOverflow;
2360 /** Times we've detected fork(). */
2361 STAMCOUNTER StatMonitorR3Fork;
2362 /** Profiling the R3 access we've handled (except REP STOSD). */
2363 STAMPROFILE StatMonitorR3Handled;
2364 /** The number of times we've seen rep prefixes we can't handle. */
2365 STAMCOUNTER StatMonitorR3RepPrefix;
2366 /** Profiling the REP STOSD cases we've handled. */
2367 STAMPROFILE StatMonitorR3RepStosd;
2368 /** Nr of handled PT faults. */
2369 STAMCOUNTER StatMonitorR3FaultPT;
2370 /** Nr of handled PD faults. */
2371 STAMCOUNTER StatMonitorR3FaultPD;
2372 /** Nr of handled PDPT faults. */
2373 STAMCOUNTER StatMonitorR3FaultPDPT;
2374 /** Nr of handled PML4 faults. */
2375 STAMCOUNTER StatMonitorR3FaultPML4;
2376 /** The number of times we're called in an async thread an need to flush. */
2377 STAMCOUNTER StatMonitorR3Async;
2378 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2379 STAMCOUNTER StatResetDirtyPages;
2380 /** Times we've called pgmPoolAddDirtyPage. */
2381 STAMCOUNTER StatDirtyPage;
2382 /** Times we've had to flush duplicates for dirty page management. */
2383 STAMCOUNTER StatDirtyPageDupFlush;
2384 /** Times we've had to flush because of overflow. */
2385 STAMCOUNTER StatDirtyPageOverFlowFlush;
2386
2387 /** The high water mark for cModifiedPages. */
2388 uint16_t cModifiedPagesHigh;
2389 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2390
2391 /** The number of cache hits. */
2392 STAMCOUNTER StatCacheHits;
2393 /** The number of cache misses. */
2394 STAMCOUNTER StatCacheMisses;
2395 /** The number of times we've got a conflict of 'kind' in the cache. */
2396 STAMCOUNTER StatCacheKindMismatches;
2397 /** Number of times we've been out of pages. */
2398 STAMCOUNTER StatCacheFreeUpOne;
2399 /** The number of cacheable allocations. */
2400 STAMCOUNTER StatCacheCacheable;
2401 /** The number of uncacheable allocations. */
2402 STAMCOUNTER StatCacheUncacheable;
2403#else
2404 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2405#endif
2406 /** The AVL tree for looking up a page by its HC physical address. */
2407 AVLOHCPHYSTREE HCPhysTree;
2408 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2409 /** Array of pages. (cMaxPages in length)
2410 * The Id is the index into thist array.
2411 */
2412 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2413} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2414AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2415AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2416AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2417#ifdef VBOX_WITH_STATISTICS
2418AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2419#endif
2420AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2421
2422
2423/** @def PGMPOOL_PAGE_2_PTR
2424 * Maps a pool page pool into the current context.
2425 *
2426 * @returns VBox status code.
2427 * @param a_pVM The VM handle.
2428 * @param a_pPage The pool page.
2429 *
2430 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2431 * small page window employeed by that function. Be careful.
2432 * @remark There is no need to assert on the result.
2433 */
2434#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2435# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2436#elif defined(VBOX_STRICT)
2437# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage)
2438DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage)
2439{
2440 Assert(a_pPage && a_pPage->pvPageR3);
2441 return a_pPage->pvPageR3;
2442}
2443#else
2444# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2445#endif
2446
2447
2448/** @def PGMPOOL_PAGE_2_PTR_V2
2449 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2450 *
2451 * @returns VBox status code.
2452 * @param a_pVM The VM handle.
2453 * @param a_pVCpu The current CPU.
2454 * @param a_pPage The pool page.
2455 *
2456 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2457 * small page window employeed by that function. Be careful.
2458 * @remark There is no need to assert on the result.
2459 */
2460#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2461# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2462#else
2463# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2464#endif
2465
2466
2467/** @name Per guest page tracking data.
2468 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2469 * is to use more bits for it and split it up later on. But for now we'll play
2470 * safe and change as little as possible.
2471 *
2472 * The 16-bit word has two parts:
2473 *
2474 * The first 14-bit forms the @a idx field. It is either the index of a page in
2475 * the shadow page pool, or and index into the extent list.
2476 *
2477 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2478 * shadow page pool references to the page. If cRefs equals
2479 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2480 * (misnomer) table and not the shadow page pool.
2481 *
2482 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2483 * the 16-bit word.
2484 *
2485 * @{ */
2486/** The shift count for getting to the cRefs part. */
2487#define PGMPOOL_TD_CREFS_SHIFT 14
2488/** The mask applied after shifting the tracking data down by
2489 * PGMPOOL_TD_CREFS_SHIFT. */
2490#define PGMPOOL_TD_CREFS_MASK 0x3
2491/** The cRefs value used to indicate that the idx is the head of a
2492 * physical cross reference list. */
2493#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2494/** The shift used to get idx. */
2495#define PGMPOOL_TD_IDX_SHIFT 0
2496/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2497#define PGMPOOL_TD_IDX_MASK 0x3fff
2498/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2499 * simply too many mappings of this page. */
2500#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2501
2502/** @def PGMPOOL_TD_MAKE
2503 * Makes a 16-bit tracking data word.
2504 *
2505 * @returns tracking data.
2506 * @param cRefs The @a cRefs field. Must be within bounds!
2507 * @param idx The @a idx field. Must also be within bounds! */
2508#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2509
2510/** @def PGMPOOL_TD_GET_CREFS
2511 * Get the @a cRefs field from a tracking data word.
2512 *
2513 * @returns The @a cRefs field
2514 * @param u16 The tracking data word.
2515 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2516 * non-zero @a u16. */
2517#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2518
2519/** @def PGMPOOL_TD_GET_IDX
2520 * Get the @a idx field from a tracking data word.
2521 *
2522 * @returns The @a idx field
2523 * @param u16 The tracking data word. */
2524#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2525/** @} */
2526
2527
2528/**
2529 * Trees are using self relative offsets as pointers.
2530 * So, all its data, including the root pointer, must be in the heap for HC and GC
2531 * to have the same layout.
2532 */
2533typedef struct PGMTREES
2534{
2535 /** Physical access handlers (AVL range+offsetptr tree). */
2536 AVLROGCPHYSTREE PhysHandlers;
2537 /** Virtual access handlers (AVL range + GC ptr tree). */
2538 AVLROGCPTRTREE VirtHandlers;
2539 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2540 AVLROGCPHYSTREE PhysToVirtHandlers;
2541 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2542 AVLROGCPTRTREE HyperVirtHandlers;
2543} PGMTREES;
2544/** Pointer to PGM trees. */
2545typedef PGMTREES *PPGMTREES;
2546
2547
2548/**
2549 * Page fault guest state for the AMD64 paging mode.
2550 */
2551typedef struct PGMPTWALKCORE
2552{
2553 /** The guest virtual address that is being resolved by the walk
2554 * (input). */
2555 RTGCPTR GCPtr;
2556
2557 /** The guest physical address that is the result of the walk.
2558 * @remarks only valid if fSucceeded is set. */
2559 RTGCPHYS GCPhys;
2560
2561 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2562 bool fSucceeded;
2563 /** The level problem arrised at.
2564 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2565 * level 8. This is 0 on success. */
2566 uint8_t uLevel;
2567 /** Set if the page isn't present. */
2568 bool fNotPresent;
2569 /** Encountered a bad physical address. */
2570 bool fBadPhysAddr;
2571 /** Set if there was reserved bit violations. */
2572 bool fRsvdError;
2573 /** Set if it involves a big page (2/4 MB). */
2574 bool fBigPage;
2575 /** Set if it involves a gigantic page (1 GB). */
2576 bool fGigantPage;
2577 /** The effect X86_PTE_US flag for the address. */
2578 bool fEffectiveUS;
2579 /** The effect X86_PTE_RW flag for the address. */
2580 bool fEffectiveRW;
2581 /** The effect X86_PTE_NX flag for the address. */
2582 bool fEffectiveNX;
2583} PGMPTWALKCORE;
2584
2585
2586/**
2587 * Guest page table walk for the AMD64 mode.
2588 */
2589typedef struct PGMPTWALKGSTAMD64
2590{
2591 /** The common core. */
2592 PGMPTWALKCORE Core;
2593
2594 PX86PML4 pPml4;
2595 PX86PML4E pPml4e;
2596 X86PML4E Pml4e;
2597
2598 PX86PDPT pPdpt;
2599 PX86PDPE pPdpe;
2600 X86PDPE Pdpe;
2601
2602 PX86PDPAE pPd;
2603 PX86PDEPAE pPde;
2604 X86PDEPAE Pde;
2605
2606 PX86PTPAE pPt;
2607 PX86PTEPAE pPte;
2608 X86PTEPAE Pte;
2609} PGMPTWALKGSTAMD64;
2610/** Pointer to a AMD64 guest page table walk. */
2611typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2612/** Pointer to a const AMD64 guest page table walk. */
2613typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2614
2615/**
2616 * Guest page table walk for the PAE mode.
2617 */
2618typedef struct PGMPTWALKGSTPAE
2619{
2620 /** The common core. */
2621 PGMPTWALKCORE Core;
2622
2623 PX86PDPT pPdpt;
2624 PX86PDPE pPdpe;
2625 X86PDPE Pdpe;
2626
2627 PX86PDPAE pPd;
2628 PX86PDEPAE pPde;
2629 X86PDEPAE Pde;
2630
2631 PX86PTPAE pPt;
2632 PX86PTEPAE pPte;
2633 X86PTEPAE Pte;
2634} PGMPTWALKGSTPAE;
2635/** Pointer to a PAE guest page table walk. */
2636typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2637/** Pointer to a const AMD64 guest page table walk. */
2638typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2639
2640/**
2641 * Guest page table walk for the 32-bit mode.
2642 */
2643typedef struct PGMPTWALKGST32BIT
2644{
2645 /** The common core. */
2646 PGMPTWALKCORE Core;
2647
2648 PX86PD pPd;
2649 PX86PDE pPde;
2650 X86PDE Pde;
2651
2652 PX86PT pPt;
2653 PX86PTE pPte;
2654 X86PTE Pte;
2655} PGMPTWALKGST32BIT;
2656/** Pointer to a 32-bit guest page table walk. */
2657typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2658/** Pointer to a const 32-bit guest page table walk. */
2659typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2660
2661
2662/** @name Paging mode macros
2663 * @{
2664 */
2665#ifdef IN_RC
2666# define PGM_CTX(a,b) a##RC##b
2667# define PGM_CTX_STR(a,b) a "GC" b
2668# define PGM_CTX_DECL(type) VMMRCDECL(type)
2669#else
2670# ifdef IN_RING3
2671# define PGM_CTX(a,b) a##R3##b
2672# define PGM_CTX_STR(a,b) a "R3" b
2673# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2674# else
2675# define PGM_CTX(a,b) a##R0##b
2676# define PGM_CTX_STR(a,b) a "R0" b
2677# define PGM_CTX_DECL(type) VMMDECL(type)
2678# endif
2679#endif
2680
2681#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2682#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2683#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2684#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2685#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2686#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2687#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2688#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2689#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2690#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2691#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2692#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2693#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2694#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2695#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2696#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2697#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2698
2699#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2700#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2701#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2702#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2703#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2704#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2705#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2706#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2707#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2708#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2709#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2710#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2711#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2712#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2713#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2714#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2715#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2716
2717/* Shw_Gst */
2718#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2719#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2720#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2721#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2722#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2723#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2724#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2725#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2726#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2727#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2728#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2729#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2730#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2731#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2732#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2733#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2734#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2735#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2736#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2737
2738#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2739#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2740#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2741#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2742#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2743#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2744#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2745#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2746#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2747#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2748#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2749#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2750#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2751#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2752#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2753#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2754#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2755#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2756#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2757#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2758#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2759#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2760#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2761#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2762#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2763#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2764#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2765#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2766#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2767#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2768#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2769#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2770#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2771#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2772#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2773#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2774#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2775
2776#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2777#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2778/** @} */
2779
2780/**
2781 * Data for each paging mode.
2782 */
2783typedef struct PGMMODEDATA
2784{
2785 /** The guest mode type. */
2786 uint32_t uGstType;
2787 /** The shadow mode type. */
2788 uint32_t uShwType;
2789
2790 /** @name Function pointers for Shadow paging.
2791 * @{
2792 */
2793 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2794 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2795 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2796 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2797
2798 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2799 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2800
2801 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2802 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2803 /** @} */
2804
2805 /** @name Function pointers for Guest paging.
2806 * @{
2807 */
2808 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2809 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2810 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2811 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2812 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2813 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2814 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2815 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2816 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2817 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2818 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2819 /** @} */
2820
2821 /** @name Function pointers for Both Shadow and Guest paging.
2822 * @{
2823 */
2824 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2825 /* no pfnR3BthTrap0eHandler */
2826 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2827 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2828 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2829 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2830#ifdef VBOX_STRICT
2831 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2832#endif
2833 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2834 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2835
2836 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2837 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2838 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2839 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2840 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2841#ifdef VBOX_STRICT
2842 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2843#endif
2844 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2845 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2846
2847 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2848 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2849 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2850 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2851 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2852#ifdef VBOX_STRICT
2853 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2854#endif
2855 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2856 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2857 /** @} */
2858} PGMMODEDATA, *PPGMMODEDATA;
2859
2860
2861#ifdef VBOX_WITH_STATISTICS
2862/**
2863 * PGM statistics.
2864 *
2865 * These lives on the heap when compiled in as they would otherwise waste
2866 * unnecessary space in release builds.
2867 */
2868typedef struct PGMSTATS
2869{
2870 /* R3 only: */
2871 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2872 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2873
2874 /* R3+RZ */
2875 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2876 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2877 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2878 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2879 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2880 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2881 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2882 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2883 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2884 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2885 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2886 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2887 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2888 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2889 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2890 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2891 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2892 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2893 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2894 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2895 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2896 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2897 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2898 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2899 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2900 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2901 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2902 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2903/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2904 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2905 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2906/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2907
2908 /* RC only: */
2909 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2910 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2911
2912 STAMCOUNTER StatRZPhysRead;
2913 STAMCOUNTER StatRZPhysReadBytes;
2914 STAMCOUNTER StatRZPhysWrite;
2915 STAMCOUNTER StatRZPhysWriteBytes;
2916 STAMCOUNTER StatR3PhysRead;
2917 STAMCOUNTER StatR3PhysReadBytes;
2918 STAMCOUNTER StatR3PhysWrite;
2919 STAMCOUNTER StatR3PhysWriteBytes;
2920 STAMCOUNTER StatRCPhysRead;
2921 STAMCOUNTER StatRCPhysReadBytes;
2922 STAMCOUNTER StatRCPhysWrite;
2923 STAMCOUNTER StatRCPhysWriteBytes;
2924
2925 STAMCOUNTER StatRZPhysSimpleRead;
2926 STAMCOUNTER StatRZPhysSimpleReadBytes;
2927 STAMCOUNTER StatRZPhysSimpleWrite;
2928 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2929 STAMCOUNTER StatR3PhysSimpleRead;
2930 STAMCOUNTER StatR3PhysSimpleReadBytes;
2931 STAMCOUNTER StatR3PhysSimpleWrite;
2932 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2933 STAMCOUNTER StatRCPhysSimpleRead;
2934 STAMCOUNTER StatRCPhysSimpleReadBytes;
2935 STAMCOUNTER StatRCPhysSimpleWrite;
2936 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2937
2938 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2939 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2940 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2941 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2942 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2943 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2944 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2945
2946 /** Time spent by the host OS for large page allocation. */
2947 STAMPROFILE StatAllocLargePage;
2948 /** Time spent clearing the newly allocated large pages. */
2949 STAMPROFILE StatClearLargePage;
2950 /** The number of times allocating a large pages takes more than the allowed period. */
2951 STAMCOUNTER StatLargePageOverflow;
2952 /** pgmPhysIsValidLargePage profiling - R3 */
2953 STAMPROFILE StatR3IsValidLargePage;
2954 /** pgmPhysIsValidLargePage profiling - RZ*/
2955 STAMPROFILE StatRZIsValidLargePage;
2956
2957 STAMPROFILE StatChunkAging;
2958 STAMPROFILE StatChunkFindCandidate;
2959 STAMPROFILE StatChunkUnmap;
2960 STAMPROFILE StatChunkMap;
2961} PGMSTATS;
2962#endif /* VBOX_WITH_STATISTICS */
2963
2964
2965/**
2966 * Converts a PGM pointer into a VM pointer.
2967 * @returns Pointer to the VM structure the PGM is part of.
2968 * @param pPGM Pointer to PGM instance data.
2969 */
2970#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2971
2972/**
2973 * PGM Data (part of VM)
2974 */
2975typedef struct PGM
2976{
2977 /** Offset to the VM structure. */
2978 int32_t offVM;
2979 /** Offset of the PGMCPU structure relative to VMCPU. */
2980 int32_t offVCpuPGM;
2981
2982 /** @cfgm{RamPreAlloc, boolean, false}
2983 * Indicates whether the base RAM should all be allocated before starting
2984 * the VM (default), or if it should be allocated when first written to.
2985 */
2986 bool fRamPreAlloc;
2987 /** Indicates whether write monitoring is currently in use.
2988 * This is used to prevent conflicts between live saving and page sharing
2989 * detection. */
2990 bool fPhysWriteMonitoringEngaged;
2991 /** Set if the CPU has less than 52-bit physical address width.
2992 * This is used */
2993 bool fLessThan52PhysicalAddressBits;
2994 /** Set when nested paging is active.
2995 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2996 * compilers optimize the code better. Whether we use nested paging or
2997 * not is something we find out during VMM initialization and we won't
2998 * change this later on. */
2999 bool fNestedPaging;
3000 /** The host paging mode. (This is what SUPLib reports.) */
3001 SUPPAGINGMODE enmHostMode;
3002 /** We're not in a state which permits writes to guest memory.
3003 * (Only used in strict builds.) */
3004 bool fNoMorePhysWrites;
3005 /** Set if PCI passthrough is enabled. */
3006 bool fPciPassthrough;
3007 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3008 bool afAlignment1[2];
3009
3010 /** Indicates that PGMR3FinalizeMappings has been called and that further
3011 * PGMR3MapIntermediate calls will be rejected. */
3012 bool fFinalizedMappings;
3013 /** If set no conflict checks are required. */
3014 bool fMappingsFixed;
3015 /** If set if restored as fixed but we were unable to re-fixate at the old
3016 * location because of room or address incompatibilities. */
3017 bool fMappingsFixedRestored;
3018 /** If set, then no mappings are put into the shadow page table.
3019 * Use pgmMapAreMappingsEnabled() instead of direct access. */
3020 bool fMappingsDisabled;
3021 /** Size of fixed mapping.
3022 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3023 uint32_t cbMappingFixed;
3024 /** Generation ID for the RAM ranges. This member is incremented everytime
3025 * a RAM range is linked or unlinked. */
3026 uint32_t volatile idRamRangesGen;
3027
3028 /** Base address (GC) of fixed mapping.
3029 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3030 RTGCPTR GCPtrMappingFixed;
3031 /** The address of the previous RAM range mapping. */
3032 RTGCPTR GCPtrPrevRamRangeMapping;
3033
3034 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3035 RTGCPHYS GCPhys4MBPSEMask;
3036 /** Mask containing the invalid bits of a guest physical address.
3037 * @remarks this does not stop at bit 52. */
3038 RTGCPHYS GCPhysInvAddrMask;
3039
3040
3041 /** RAM range TLB for R3. */
3042 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3043 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3044 * This is sorted by physical address and contains no overlapping ranges. */
3045 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3046 /** Root of the RAM range search tree for ring-3. */
3047 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3048 /** PGM offset based trees - R3 Ptr. */
3049 R3PTRTYPE(PPGMTREES) pTreesR3;
3050 /** Caching the last physical handler we looked up in R3. */
3051 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3052 /** Shadow Page Pool - R3 Ptr. */
3053 R3PTRTYPE(PPGMPOOL) pPoolR3;
3054 /** Linked list of GC mappings - for HC.
3055 * The list is sorted ascending on address. */
3056 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3057 /** Pointer to the list of ROM ranges - for R3.
3058 * This is sorted by physical address and contains no overlapping ranges. */
3059 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3060 /** Pointer to the list of MMIO2 ranges - for R3.
3061 * Registration order. */
3062 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3063 /** Pointer to SHW+GST mode data (function pointers).
3064 * The index into this table is made up from */
3065 R3PTRTYPE(PPGMMODEDATA) paModeData;
3066 RTR3PTR R3PtrAlignment0;
3067
3068 /** RAM range TLB for R0. */
3069 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3070 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3071 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3072 /** Root of the RAM range search tree for ring-0. */
3073 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3074 /** PGM offset based trees - R0 Ptr. */
3075 R0PTRTYPE(PPGMTREES) pTreesR0;
3076 /** Caching the last physical handler we looked up in R0. */
3077 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3078 /** Shadow Page Pool - R0 Ptr. */
3079 R0PTRTYPE(PPGMPOOL) pPoolR0;
3080 /** Linked list of GC mappings - for R0.
3081 * The list is sorted ascending on address. */
3082 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3083 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3084 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3085 RTR0PTR R0PtrAlignment0;
3086
3087
3088 /** RAM range TLB for RC. */
3089 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3090 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3091 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3092 /** Root of the RAM range search tree for raw-mode context. */
3093 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3094 /** PGM offset based trees - RC Ptr. */
3095 RCPTRTYPE(PPGMTREES) pTreesRC;
3096 /** Caching the last physical handler we looked up in RC. */
3097 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3098 /** Shadow Page Pool - RC Ptr. */
3099 RCPTRTYPE(PPGMPOOL) pPoolRC;
3100 /** Linked list of GC mappings - for RC.
3101 * The list is sorted ascending on address. */
3102 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3103 /** RC pointer corresponding to PGM::pRomRangesR3. */
3104 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3105 RTRCPTR RCPtrAlignment0;
3106 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3107 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3108 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3109 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3110
3111
3112 /** Pointer to the 5 page CR3 content mapping.
3113 * The first page is always the CR3 (in some form) while the 4 other pages
3114 * are used of the PDs in PAE mode. */
3115 RTGCPTR GCPtrCR3Mapping;
3116
3117 /** @name Intermediate Context
3118 * @{ */
3119 /** Pointer to the intermediate page directory - Normal. */
3120 R3PTRTYPE(PX86PD) pInterPD;
3121 /** Pointer to the intermediate page tables - Normal.
3122 * There are two page tables, one for the identity mapping and one for
3123 * the host context mapping (of the core code). */
3124 R3PTRTYPE(PX86PT) apInterPTs[2];
3125 /** Pointer to the intermediate page tables - PAE. */
3126 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3127 /** Pointer to the intermediate page directory - PAE. */
3128 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3129 /** Pointer to the intermediate page directory - PAE. */
3130 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3131 /** Pointer to the intermediate page-map level 4 - AMD64. */
3132 R3PTRTYPE(PX86PML4) pInterPaePML4;
3133 /** Pointer to the intermediate page directory - AMD64. */
3134 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3135 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3136 RTHCPHYS HCPhysInterPD;
3137 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3138 RTHCPHYS HCPhysInterPaePDPT;
3139 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3140 RTHCPHYS HCPhysInterPaePML4;
3141 /** @} */
3142
3143 /** Base address of the dynamic page mapping area.
3144 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3145 *
3146 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3147 * work out. Some cleaning up of the initialization that would
3148 * remove this memory is yet to be done...
3149 */
3150 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3151 /** The address of the raw-mode context mapping cache. */
3152 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3153 /** The address of the ring-0 mapping cache if we're making use of it. */
3154 RTR0PTR pvR0DynMapUsed;
3155#if HC_ARCH_BITS == 32
3156 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3157 uint32_t u32Alignment2;
3158#endif
3159
3160 /** PGM critical section.
3161 * This protects the physical & virtual access handlers, ram ranges,
3162 * and the page flag updating (some of it anyway).
3163 */
3164 PDMCRITSECT CritSect;
3165
3166 /**
3167 * Data associated with managing the ring-3 mappings of the allocation chunks.
3168 */
3169 struct
3170 {
3171 /** The chunk tree, ordered by chunk id. */
3172#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3173 R3PTRTYPE(PAVLU32NODECORE) pTree;
3174#else
3175 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3176#endif
3177#if HC_ARCH_BITS == 32
3178 uint32_t u32Alignment;
3179#endif
3180 /** The chunk mapping TLB. */
3181 PGMCHUNKR3MAPTLB Tlb;
3182 /** The number of mapped chunks. */
3183 uint32_t c;
3184 /** The maximum number of mapped chunks.
3185 * @cfgm PGM/MaxRing3Chunks */
3186 uint32_t cMax;
3187 /** The current time. */
3188 uint32_t iNow;
3189 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3190 uint32_t AgeingCountdown;
3191 } ChunkR3Map;
3192
3193 /**
3194 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3195 */
3196 PGMPAGER3MAPTLB PhysTlbHC;
3197
3198 /** @name The zero page.
3199 * @{ */
3200 /** The host physical address of the zero page. */
3201 RTHCPHYS HCPhysZeroPg;
3202 /** The ring-3 mapping of the zero page. */
3203 RTR3PTR pvZeroPgR3;
3204 /** The ring-0 mapping of the zero page. */
3205 RTR0PTR pvZeroPgR0;
3206 /** The GC mapping of the zero page. */
3207 RTRCPTR pvZeroPgRC;
3208 RTRCPTR RCPtrAlignment3;
3209 /** @}*/
3210
3211 /** @name The Invalid MMIO page.
3212 * This page is filled with 0xfeedface.
3213 * @{ */
3214 /** The host physical address of the invalid MMIO page. */
3215 RTHCPHYS HCPhysMmioPg;
3216 /** The host pysical address of the invalid MMIO page plus all invalid
3217 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3218 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3219 RTHCPHYS HCPhysInvMmioPg;
3220 /** The ring-3 mapping of the invalid MMIO page. */
3221 RTR3PTR pvMmioPgR3;
3222#if HC_ARCH_BITS == 32
3223 RTR3PTR R3PtrAlignment4;
3224#endif
3225 /** @} */
3226
3227
3228 /** The number of handy pages. */
3229 uint32_t cHandyPages;
3230
3231 /** The number of large handy pages. */
3232 uint32_t cLargeHandyPages;
3233
3234 /**
3235 * Array of handy pages.
3236 *
3237 * This array is used in a two way communication between pgmPhysAllocPage
3238 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3239 * an intermediary.
3240 *
3241 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3242 * (The current size of 32 pages, means 128 KB of handy memory.)
3243 */
3244 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3245
3246 /**
3247 * Array of large handy pages. (currently size 1)
3248 *
3249 * This array is used in a two way communication between pgmPhysAllocLargePage
3250 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3251 * an intermediary.
3252 */
3253 GMMPAGEDESC aLargeHandyPage[1];
3254
3255 /**
3256 * Live save data.
3257 */
3258 struct
3259 {
3260 /** Per type statistics. */
3261 struct
3262 {
3263 /** The number of ready pages. */
3264 uint32_t cReadyPages;
3265 /** The number of dirty pages. */
3266 uint32_t cDirtyPages;
3267 /** The number of ready zero pages. */
3268 uint32_t cZeroPages;
3269 /** The number of write monitored pages. */
3270 uint32_t cMonitoredPages;
3271 } Rom,
3272 Mmio2,
3273 Ram;
3274 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3275 uint32_t cIgnoredPages;
3276 /** Indicates that a live save operation is active. */
3277 bool fActive;
3278 /** Padding. */
3279 bool afReserved[2];
3280 /** The next history index. */
3281 uint8_t iDirtyPagesHistory;
3282 /** History of the total amount of dirty pages. */
3283 uint32_t acDirtyPagesHistory[64];
3284 /** Short term dirty page average. */
3285 uint32_t cDirtyPagesShort;
3286 /** Long term dirty page average. */
3287 uint32_t cDirtyPagesLong;
3288 /** The number of saved pages. This is used to get some kind of estimate of the
3289 * link speed so we can decide when we're done. It is reset after the first
3290 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3291 * zero pages. */
3292 uint64_t cSavedPages;
3293 /** The nanosecond timestamp when cSavedPages was 0. */
3294 uint64_t uSaveStartNS;
3295 /** Pages per second (for statistics). */
3296 uint32_t cPagesPerSecond;
3297 uint32_t cAlignment;
3298 } LiveSave;
3299
3300 /** @name Error injection.
3301 * @{ */
3302 /** Inject handy page allocation errors pretending we're completely out of
3303 * memory. */
3304 bool volatile fErrInjHandyPages;
3305 /** Padding. */
3306 bool afReserved[3];
3307 /** @} */
3308
3309 /** @name Release Statistics
3310 * @{ */
3311 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3312 uint32_t cPrivatePages; /**< The number of private pages. */
3313 uint32_t cSharedPages; /**< The number of shared pages. */
3314 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3315 uint32_t cZeroPages; /**< The number of zero backed pages. */
3316 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3317 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3318 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3319 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3320 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3321 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3322 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3323 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3324 uint32_t cLargePages; /**< The number of large pages. */
3325 uint32_t cLargePagesDisabled;/**< The number of disabled large pages. */
3326/* uint32_t aAlignment4[1]; */
3327
3328 /** The number of times we were forced to change the hypervisor region location. */
3329 STAMCOUNTER cRelocations;
3330
3331 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3332 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3333 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3334 /** @} */
3335
3336#ifdef VBOX_WITH_STATISTICS
3337 /** @name Statistics on the heap.
3338 * @{ */
3339 R3PTRTYPE(PGMSTATS *) pStatsR3;
3340 R0PTRTYPE(PGMSTATS *) pStatsR0;
3341 RCPTRTYPE(PGMSTATS *) pStatsRC;
3342 RTRCPTR RCPtrAlignment;
3343 /** @} */
3344#endif
3345} PGM;
3346#ifndef IN_TSTVMSTRUCTGC /* HACK */
3347AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3348AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3349AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3350AssertCompileMemberAlignment(PGM, CritSect, 8);
3351AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3352AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3353AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3354AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3355AssertCompileMemberAlignment(PGM, cRelocations, 8);
3356#endif /* !IN_TSTVMSTRUCTGC */
3357/** Pointer to the PGM instance data. */
3358typedef PGM *PPGM;
3359
3360
3361
3362typedef struct PGMCPUSTATS
3363{
3364 /* Common */
3365 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3366 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3367
3368 /* R0 only: */
3369 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3370 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3371
3372 /* RZ only: */
3373 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3374 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3375 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3376 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3377 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3378 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3379 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3380 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3381 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3382 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3383 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3384 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3385 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3386 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3387 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3388 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3389 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3390 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3391 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3392 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3393 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3394 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3395 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3396 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3397 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3398 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3399 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3400 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3401 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3402 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3403 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3404 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3405 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3406 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3407 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3408 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3409 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3410 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3411 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3412 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3413 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3414 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3415 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3416 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3417 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3418 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3419 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3420 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3421 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3422 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3423 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3424 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3425 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3426 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3427 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3428 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3429 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3430 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3431 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3432 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3433 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3434 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3435 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3436 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3437 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3438 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3439 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3440 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3441 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3442 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3443 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3444 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3445 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3446 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3447 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3448 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3449
3450 /* HC - R3 and (maybe) R0: */
3451
3452 /* RZ & R3: */
3453 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3454 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3455 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3456 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3457 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3458 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3459 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3460 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3461 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3462 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3463 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3464 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3465 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3466 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3467 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3468 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3469 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3470 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3471 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3472 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3473 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3474 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3475 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3476 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3477 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3478 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3479 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3480 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3481 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3482 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3483 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3484 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3485 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3486 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3487 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3488 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3489 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3490 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3491 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3492 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3493 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3494 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3495 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3496 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3497 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3498 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3499 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3500
3501 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3502 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3503 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3504 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3505 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3506 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3507 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3508 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3509 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3510 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3511 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3512 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3513 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3514 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3515 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3516 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3517 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3518 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3519 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3520 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3521 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3522 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3523 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3524 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3525 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3526 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3527 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3528 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3529 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3530 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3531 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3532 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3533 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3534 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3535 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3536 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3537 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3538 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3539 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3540 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3541 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3542 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3543 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3544 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3545 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3546 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3547 /** @} */
3548} PGMCPUSTATS;
3549
3550
3551/**
3552 * Converts a PGMCPU pointer into a VM pointer.
3553 * @returns Pointer to the VM structure the PGM is part of.
3554 * @param pPGM Pointer to PGMCPU instance data.
3555 */
3556#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3557
3558/**
3559 * Converts a PGMCPU pointer into a PGM pointer.
3560 * @returns Pointer to the VM structure the PGM is part of.
3561 * @param pPGM Pointer to PGMCPU instance data.
3562 */
3563#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3564
3565/**
3566 * PGMCPU Data (part of VMCPU).
3567 */
3568typedef struct PGMCPU
3569{
3570 /** Offset to the VM structure. */
3571 int32_t offVM;
3572 /** Offset to the VMCPU structure. */
3573 int32_t offVCpu;
3574 /** Offset of the PGM structure relative to VMCPU. */
3575 int32_t offPGM;
3576 uint32_t uPadding0; /**< structure size alignment. */
3577
3578#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3579 /** Automatically tracked physical memory mapping set.
3580 * Ring-0 and strict raw-mode builds. */
3581 PGMMAPSET AutoSet;
3582#endif
3583
3584 /** A20 gate mask.
3585 * Our current approach to A20 emulation is to let REM do it and don't bother
3586 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3587 * But whould need arrise, we'll subject physical addresses to this mask. */
3588 RTGCPHYS GCPhysA20Mask;
3589 /** A20 gate state - boolean! */
3590 bool fA20Enabled;
3591 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3592 bool fNoExecuteEnabled;
3593 /** Unused bits. */
3594 bool afUnused[2];
3595
3596 /** What needs syncing (PGM_SYNC_*).
3597 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3598 * PGMFlushTLB, and PGMR3Load. */
3599 RTUINT fSyncFlags;
3600
3601 /** The shadow paging mode. */
3602 PGMMODE enmShadowMode;
3603 /** The guest paging mode. */
3604 PGMMODE enmGuestMode;
3605
3606 /** The current physical address representing in the guest CR3 register. */
3607 RTGCPHYS GCPhysCR3;
3608
3609 /** @name 32-bit Guest Paging.
3610 * @{ */
3611 /** The guest's page directory, R3 pointer. */
3612 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3613#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3614 /** The guest's page directory, R0 pointer. */
3615 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3616#endif
3617 /** The guest's page directory, static RC mapping. */
3618 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3619 /** Mask containing the MBZ bits of a big page PDE. */
3620 uint32_t fGst32BitMbzBigPdeMask;
3621 /** Set if the page size extension (PSE) is enabled. */
3622 bool fGst32BitPageSizeExtension;
3623 /** Alignment padding. */
3624 bool afAlignment2[3];
3625 /** @} */
3626
3627 /** @name PAE Guest Paging.
3628 * @{ */
3629 /** The guest's page directory pointer table, static RC mapping. */
3630 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3631 /** The guest's page directory pointer table, R3 pointer. */
3632 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3633#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3634 /** The guest's page directory pointer table, R0 pointer. */
3635 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3636#endif
3637
3638 /** The guest's page directories, R3 pointers.
3639 * These are individual pointers and don't have to be adjacent.
3640 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3641 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3642 /** The guest's page directories, R0 pointers.
3643 * Same restrictions as apGstPaePDsR3. */
3644#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3645 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3646#endif
3647 /** The guest's page directories, static GC mapping.
3648 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3649 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3650 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3651 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3652 * @todo Remove this and use aGstPaePdpeRegs instead? */
3653 RTGCPHYS aGCPhysGstPaePDs[4];
3654 /** The values of the 4 PDPE CPU registers (PAE). */
3655 X86PDPE aGstPaePdpeRegs[4];
3656 /** The physical addresses of the monitored guest page directories (PAE). */
3657 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3658 /** Mask containing the MBZ PTE bits. */
3659 uint64_t fGstPaeMbzPteMask;
3660 /** Mask containing the MBZ PDE bits. */
3661 uint64_t fGstPaeMbzPdeMask;
3662 /** Mask containing the MBZ big page PDE bits. */
3663 uint64_t fGstPaeMbzBigPdeMask;
3664 /** Mask containing the MBZ PDPE bits. */
3665 uint64_t fGstPaeMbzPdpeMask;
3666 /** @} */
3667
3668 /** @name AMD64 Guest Paging.
3669 * @{ */
3670 /** The guest's page directory pointer table, R3 pointer. */
3671 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3672#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3673 /** The guest's page directory pointer table, R0 pointer. */
3674 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3675#else
3676 RTR0PTR alignment6b; /**< alignment equalizer. */
3677#endif
3678 /** Mask containing the MBZ PTE bits. */
3679 uint64_t fGstAmd64MbzPteMask;
3680 /** Mask containing the MBZ PDE bits. */
3681 uint64_t fGstAmd64MbzPdeMask;
3682 /** Mask containing the MBZ big page PDE bits. */
3683 uint64_t fGstAmd64MbzBigPdeMask;
3684 /** Mask containing the MBZ PDPE bits. */
3685 uint64_t fGstAmd64MbzPdpeMask;
3686 /** Mask containing the MBZ big page PDPE bits. */
3687 uint64_t fGstAmd64MbzBigPdpeMask;
3688 /** Mask containing the MBZ PML4E bits. */
3689 uint64_t fGstAmd64MbzPml4eMask;
3690 /** Mask containing the PDPE bits that we shadow. */
3691 uint64_t fGstAmd64ShadowedPdpeMask;
3692 /** Mask containing the PML4E bits that we shadow. */
3693 uint64_t fGstAmd64ShadowedPml4eMask;
3694 /** @} */
3695
3696 /** @name PAE and AMD64 Guest Paging.
3697 * @{ */
3698 /** Mask containing the PTE bits that we shadow. */
3699 uint64_t fGst64ShadowedPteMask;
3700 /** Mask containing the PDE bits that we shadow. */
3701 uint64_t fGst64ShadowedPdeMask;
3702 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3703 uint64_t fGst64ShadowedBigPdeMask;
3704 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3705 uint64_t fGst64ShadowedBigPde4PteMask;
3706 /** @} */
3707
3708 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3709 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3710 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3711 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3712 /** Pointer to the page of the current active CR3 - RC Ptr. */
3713 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3714 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3715 uint32_t iShwUser;
3716 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3717 uint32_t iShwUserTable;
3718# if HC_ARCH_BITS == 64
3719 RTRCPTR alignment6; /**< structure size alignment. */
3720# endif
3721 /** @} */
3722
3723 /** @name Function pointers for Shadow paging.
3724 * @{
3725 */
3726 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3727 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3728 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3729 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3730
3731 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3732 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3733
3734 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3735 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3736
3737 /** @} */
3738
3739 /** @name Function pointers for Guest paging.
3740 * @{
3741 */
3742 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3743 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3744 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3745 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3746 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3747 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3748 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3749 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3750#if HC_ARCH_BITS == 64
3751 RTRCPTR alignment3; /**< structure size alignment. */
3752#endif
3753
3754 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3755 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3756 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3757 /** @} */
3758
3759 /** @name Function pointers for Both Shadow and Guest paging.
3760 * @{
3761 */
3762 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3763 /* no pfnR3BthTrap0eHandler */
3764 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3765 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3766 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3767 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3768 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3769 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3770 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3771
3772 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3773 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3774 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3775 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3776 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3777 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3778 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3779 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3780
3781 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3782 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3783 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3784 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3785 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3786 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3787 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3788 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3789#if 0
3790 RTRCPTR alignment2; /**< structure size alignment. */
3791#endif
3792 /** @} */
3793
3794 /** For saving stack space, the disassembler state is allocated here instead of
3795 * on the stack.
3796 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3797 union
3798 {
3799 /** The disassembler scratch space. */
3800 DISCPUSTATE DisState;
3801 /** Padding. */
3802 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3803 };
3804
3805 /** Count the number of pgm pool access handler calls. */
3806 uint64_t cPoolAccessHandler;
3807
3808 /** @name Release Statistics
3809 * @{ */
3810 /** The number of times the guest has switched mode since last reset or statistics reset. */
3811 STAMCOUNTER cGuestModeChanges;
3812 /** @} */
3813
3814#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3815 /** @name Statistics
3816 * @{ */
3817 /** RC: Pointer to the statistics. */
3818 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3819 /** RC: Which statistic this \#PF should be attributed to. */
3820 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3821 /** R0: Pointer to the statistics. */
3822 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3823 /** R0: Which statistic this \#PF should be attributed to. */
3824 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3825 /** R3: Pointer to the statistics. */
3826 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3827 /** Alignment padding. */
3828 RTR3PTR pPaddingR3;
3829 /** @} */
3830#endif /* VBOX_WITH_STATISTICS */
3831} PGMCPU;
3832/** Pointer to the per-cpu PGM data. */
3833typedef PGMCPU *PPGMCPU;
3834
3835
3836/** @name PGM::fSyncFlags Flags
3837 * @{
3838 */
3839/** Updates the virtual access handler state bit in PGMPAGE. */
3840#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3841/** Always sync CR3. */
3842#define PGM_SYNC_ALWAYS RT_BIT(1)
3843/** Check monitoring on next CR3 (re)load and invalidate page.
3844 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3845#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3846/** Check guest mapping in SyncCR3. */
3847#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3848/** Clear the page pool (a light weight flush). */
3849#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3850#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3851/** @} */
3852
3853
3854RT_C_DECLS_BEGIN
3855
3856int pgmLock(PVM pVM);
3857void pgmUnlock(PVM pVM);
3858/**
3859 * Asserts that the caller owns the PDM lock.
3860 * This is the internal variant of PGMIsLockOwner.
3861 * @param a_pVM The VM handle.
3862 */
3863#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSect))
3864
3865int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3866int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3867int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3868PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3869int pgmMapResolveConflicts(PVM pVM);
3870DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3871
3872void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3873bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3874void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3875int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3876DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3877#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3878void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3879#else
3880# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3881#endif
3882DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3883int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3884
3885int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3886int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3887int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3888int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
3889int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3890void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3891int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3892int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3893int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3894int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3895int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3896int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3897int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3898VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3899VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3900int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3901void pgmPhysInvalidRamRangeTlbs(PVM pVM);
3902void pgmPhysInvalidatePageMapTLB(PVM pVM);
3903void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
3904PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3905PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3906PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3907int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3908int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3909
3910#ifdef IN_RING3
3911void pgmR3PhysRelinkRamRanges(PVM pVM);
3912int pgmR3PhysRamPreAllocate(PVM pVM);
3913int pgmR3PhysRamReset(PVM pVM);
3914int pgmR3PhysRomReset(PVM pVM);
3915int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3916int pgmR3PhysRamTerm(PVM pVM);
3917void pgmR3PhysRomTerm(PVM pVM);
3918
3919int pgmR3PoolInit(PVM pVM);
3920void pgmR3PoolRelocate(PVM pVM);
3921void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3922void pgmR3PoolReset(PVM pVM);
3923void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3924DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3925void pgmR3PoolWriteProtectPages(PVM pVM);
3926
3927#endif /* IN_RING3 */
3928#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3929int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3930int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3931# ifdef LOG_ENABLED
3932void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3933# else
3934void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3935# endif
3936#endif
3937int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3938 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3939
3940DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3941 PPPGMPOOLPAGE ppPage)
3942{
3943 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3944}
3945
3946void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3947void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3948int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3949void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3950PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3951PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3952int pgmPoolSyncCR3(PVMCPU pVCpu);
3953bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3954void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3955int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3956void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3957uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3958void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3959void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3960int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3961void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3962
3963void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3964void pgmPoolResetDirtyPages(PVM pVM);
3965void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3966
3967int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3968int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3969
3970void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3971void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3972int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3973int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3974
3975int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3976int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3977
3978int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3979int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3980int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3981int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3982
3983# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3984DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3985DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3986# endif
3987
3988RT_C_DECLS_END
3989
3990/** @} */
3991
3992#endif
3993
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