PGMInternal.h@ 107171

Last change on this file since 107171 was 107171, checked in by vboxsync, 8 weeks ago
VMM/PGM: Introducing VBOX_WITH_ONLY_PGM_NEM_MODE to disable lots unused code on *.arm64 and darwin. jiraref:VBP-1466
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1	/* $Id: PGMInternal.h 107171 2024-11-28 10:38:10Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	#ifndef VBOX_VMM_TARGET_ARMV8
79	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/** Maximum number of RAM ranges.
118	* @note This can be increased to 4096 (at least when targeting x86). */
119	#define PGM_MAX_RAM_RANGES 3072
120
121	/** Maximum pages per RAM range.
122	*
123	* The PGMRAMRANGE structures for the high memory can get very big. There
124	* used to be some limitations on SUPR3PageAllocEx allocation sizes, so
125	* traditionally we limited this to 16MB chunks. These days we do ~64 MB
126	* chunks each covering 16GB of guest RAM, making sure each range is a
127	* multiple of 1GB to enable eager hosts to use 1GB pages for NEM mode.
128	*
129	* See also pgmPhysMmio2CalcChunkCount.
130	*/
131	#define PGM_MAX_PAGES_PER_RAM_RANGE _4M
132	#if defined(X86_PD_PAE_SHIFT) && defined(AssertCompile)
133	AssertCompile(RT_ALIGN_32(PGM_MAX_PAGES_PER_RAM_RANGE, X86_PD_PAE_SHIFT - X86_PAGE_SHIFT)); /* NEM large page requirement: 1GB pages. */
134	#endif
135
136	/** The maximum number of MMIO2 ranges. */
137	#define PGM_MAX_MMIO2_RANGES 32
138	/** The maximum number of pages in a MMIO2 PCI region.
139	*
140	* The memory for a MMIO2 PCI region is a single chunk of host virtual memory,
141	* but may be handled internally by PGM as a set of multiple MMIO2/RAM ranges,
142	* since PGM_MAX_PAGES_PER_RAM_RANGE is currently lower than this value (4 GiB
143	* vs 16 GiB).
144	*/
145	#define PGM_MAX_PAGES_PER_MMIO2_REGION _16M
146
147	/** Maximum number of ROM ranges. */
148	#define PGM_MAX_ROM_RANGES 16
149	/** The maximum pages per ROM range.
150	* Currently 512K pages, or 2GB with 4K pages. */
151	#define PGM_MAX_PAGES_PER_ROM_RANGE _512K
152	AssertCompile(PGM_MAX_PAGES_PER_ROM_RANGE <= PGM_MAX_PAGES_PER_RAM_RANGE);
153
154	/**
155	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
156	*/
157	#define PGM_MAX_PHYSCACHE_ENTRIES 64
158	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
159
160
161	/** @def PGMPOOL_CFG_MAX_GROW
162	* The maximum number of pages to add to the pool in one go.
163	*/
164	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
165
166	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
167	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
168	*/
169	#ifdef VBOX_STRICT
170	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
171	#endif
172
173	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
174	* Enables the experimental lazy page allocation code.
175	* @todo Problems with zero page tracking, see \@bugref{10509}. */
176	#if defined(DOXYGEN_RUNNING)
177	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
178	#endif
179
180	/** @def PGM_WITH_PAGE_ZEROING_DETECTION
181	* Enables the code for detecting guest zeroing page in the ZERO state and
182	* tries to avoid allocating them in response.
183	* This kind of relies upon VBOX_WITH_NEW_LAZY_PAGE_ALLOC to work atm. */
184	#if defined(DOXYGEN_RUNNING)
185	# define PGM_WITH_PAGE_ZEROING_DETECTION
186	#endif
187
188	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
189	* Enables real write monitoring of pages, i.e. mapping them read-only and
190	* only making them writable when getting a write access \#PF. */
191	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
192
193	/** @def VBOX_WITH_PGM_NEM_MODE
194	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
195	* details. */
196	#ifdef DOXYGEN_RUNNING
197	# define VBOX_WITH_PGM_NEM_MODE
198	#endif
199
200	/** @} */
201
202	#if defined(VBOX_WITH_PAGE_SHARING) && defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
203	# error "Misconfig! VBOX_WITH_ONLY_PGM_NEM_MODE implies no VBOX_WITH_PAGE_SHARING. Fix VBox/param.h."
204	#endif
205
206	/** @name PDPT and PML4 flags.
207	* These are placed in the three bits available for system programs in
208	* the PDPT and PML4 entries.
209	* @{ */
210	/** The entry is a permanent one and it's must always be present.
211	* Never free such an entry. */
212	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
213	/** PGM specific bits in PML4 entries. */
214	#define PGM_PML4_FLAGS 0
215	/** PGM specific bits in PDPT entries. */
216	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
217	/** @} */
218
219	/** @name Page directory flags.
220	* These are placed in the three bits available for system programs in
221	* the page directory entries.
222	* @{ */
223	/** Indicates the original entry was a big page.
224	* @remarks This is currently only used for statistics and can be recycled. */
225	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
226	/** Made read-only to facilitate dirty bit tracking. */
227	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
228	/** @} */
229
230	/** @name Page flags.
231	* These are placed in the three bits available for system programs in
232	* the page entries.
233	* @{ */
234	/** Made read-only to facilitate dirty bit tracking. */
235	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
236	/** @} */
237
238	/** @name Defines used to indicate the shadow and guest paging in the templates.
239	* @{ */
240	#define PGM_TYPE_REAL 1
241	#define PGM_TYPE_PROT 2
242	#define PGM_TYPE_32BIT 3
243	#define PGM_TYPE_PAE 4
244	#define PGM_TYPE_AMD64 5
245	#define PGM_TYPE_NESTED_32BIT 6
246	#define PGM_TYPE_NESTED_PAE 7
247	#define PGM_TYPE_NESTED_AMD64 8
248	#define PGM_TYPE_EPT 9
249	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
250	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
251	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
252	/** @} */
253
254	/** @name Defines used to indicate the second-level
255	* address translation (SLAT) modes in the templates.
256	* @{ */
257	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
258	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
259	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
260	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
261	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
262	/** @} */
263
264	/** Macro for checking if the guest is using paging.
265	* @param uGstType PGM_TYPE_*
266	* @param uShwType PGM_TYPE_*
267	* @remark ASSUMES certain order of the PGM_TYPE_* values.
268	*/
269	#define PGM_WITH_PAGING(uGstType, uShwType) \
270	( (uGstType) >= PGM_TYPE_32BIT \
271	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
272
273	/** Macro for checking if the guest supports the NX bit.
274	* @param uGstType PGM_TYPE_*
275	* @param uShwType PGM_TYPE_*
276	* @remark ASSUMES certain order of the PGM_TYPE_* values.
277	*/
278	#define PGM_WITH_NX(uGstType, uShwType) \
279	( (uGstType) >= PGM_TYPE_PAE \
280	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
281
282	/** Macro for checking for nested.
283	* @param uType PGM_TYPE_*
284	*/
285	#define PGM_TYPE_IS_NESTED(uType) \
286	( (uType) == PGM_TYPE_NESTED_32BIT \
287	\|\| (uType) == PGM_TYPE_NESTED_PAE \
288	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
289
290	/** Macro for checking for nested or EPT.
291	* @param uType PGM_TYPE_*
292	*/
293	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
294	( (uType) == PGM_TYPE_NESTED_32BIT \
295	\|\| (uType) == PGM_TYPE_NESTED_PAE \
296	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
297	\|\| (uType) == PGM_TYPE_EPT)
298
299
300
301	/** @def PGM_HCPHYS_2_PTR
302	* Maps a HC physical page pool address to a virtual address.
303	*
304	* @returns VBox status code.
305	* @param pVM The cross context VM structure.
306	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
307	* @param HCPhys The HC physical address to map to a virtual one.
308	* @param ppv Where to store the virtual address. No need to cast
309	* this.
310	*
311	* @remark There is no need to assert on the result.
312	*/
313	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
314
315	/** @def PGM_GCPHYS_2_PTR_V2
316	* Maps a GC physical page address to a virtual address.
317	*
318	* @returns VBox status code.
319	* @param pVM The cross context VM structure.
320	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
321	* @param GCPhys The GC physical address to map to a virtual one.
322	* @param ppv Where to store the virtual address. No need to cast this.
323	*
324	* @remark Use with care as we don't have so much dynamic mapping space in
325	* ring-0 on 32-bit darwin and in RC.
326	* @remark There is no need to assert on the result.
327	*/
328	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
329	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
330
331	/** @def PGM_GCPHYS_2_PTR
332	* Maps a GC physical page address to a virtual address.
333	*
334	* @returns VBox status code.
335	* @param pVM The cross context VM structure.
336	* @param GCPhys The GC physical address to map to a virtual one.
337	* @param ppv Where to store the virtual address. No need to cast this.
338	*
339	* @remark Use with care as we don't have so much dynamic mapping space in
340	* ring-0 on 32-bit darwin and in RC.
341	* @remark There is no need to assert on the result.
342	*/
343	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
344
345	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
346	* Maps a GC physical page address to a virtual address.
347	*
348	* @returns VBox status code.
349	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
350	* @param GCPhys The GC physical address to map to a virtual one.
351	* @param ppv Where to store the virtual address. No need to cast this.
352	*
353	* @remark Use with care as we don't have so much dynamic mapping space in
354	* ring-0 on 32-bit darwin and in RC.
355	* @remark There is no need to assert on the result.
356	*/
357	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
358
359	/** @def PGM_GCPHYS_2_PTR_EX
360	* Maps a unaligned GC physical page address to a virtual address.
361	*
362	* @returns VBox status code.
363	* @param pVM The cross context VM structure.
364	* @param GCPhys The GC physical address to map to a virtual one.
365	* @param ppv Where to store the virtual address. No need to cast this.
366	*
367	* @remark Use with care as we don't have so much dynamic mapping space in
368	* ring-0 on 32-bit darwin and in RC.
369	* @remark There is no need to assert on the result.
370	*/
371	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
372	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
373
374	/** @def PGM_DYNMAP_UNUSED_HINT
375	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
376	* is no longer used.
377	*
378	* For best effect only apply this to the page that was mapped most recently.
379	*
380	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
381	* @param pvPage The pool page.
382	*/
383	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
384
385	/** @def PGM_DYNMAP_UNUSED_HINT_VM
386	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
387	* is no longer used.
388	*
389	* For best effect only apply this to the page that was mapped most recently.
390	*
391	* @param pVM The cross context VM structure.
392	* @param pvPage The pool page.
393	*/
394	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
395
396
397	/** @def PGM_INVL_PG
398	* Invalidates a page.
399	*
400	* @param pVCpu The cross context virtual CPU structure.
401	* @param GCVirt The virtual address of the page to invalidate.
402	*/
403	#ifdef IN_RING0
404	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
405	#elif defined(IN_RING3)
406	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
407	#else
408	# error "Not IN_RING0 or IN_RING3!"
409	#endif
410
411	/** @def PGM_INVL_PG_ALL_VCPU
412	* Invalidates a page on all VCPUs
413	*
414	* @param pVM The cross context VM structure.
415	* @param GCVirt The virtual address of the page to invalidate.
416	*/
417	#if defined(VBOX_VMM_TARGET_ARMV8)
418	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) do { } while(0)
419	#else
420	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
421	#endif
422
423	/** @def PGM_INVL_BIG_PG
424	* Invalidates a 4MB page directory entry.
425	*
426	* @param pVCpu The cross context virtual CPU structure.
427	* @param GCVirt The virtual address within the page directory to invalidate.
428	*/
429	#if defined(VBOX_VMM_TARGET_ARMV8)
430	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) do { } while(0)
431	#else
432	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
433	#endif
434
435	/** @def PGM_INVL_VCPU_TLBS()
436	* Invalidates the TLBs of the specified VCPU
437	*
438	* @param pVCpu The cross context virtual CPU structure.
439	*/
440	#if defined(VBOX_VMM_TARGET_ARMV8)
441	# define PGM_INVL_VCPU_TLBS(pVCpu) do { } while(0)
442	#else
443	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
444	#endif
445
446	/** @def PGM_INVL_ALL_VCPU_TLBS()
447	* Invalidates the TLBs of all VCPUs
448	*
449	* @param pVM The cross context VM structure.
450	*/
451	#if defined(VBOX_VMM_TARGET_ARMV8)
452	# define PGM_INVL_ALL_VCPU_TLBS(pVM) do { } while(0)
453	#else
454	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
455	#endif
456
457
458	/** @name Safer Shadow PAE PT/PTE
459	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
460	* present.
461	*
462	* @{
463	*/
464	#if 1
465	/**
466	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
467	* invalid entries for present.
468	* @sa X86PTEPAE.
469	*/
470	typedef union PGMSHWPTEPAE
471	{
472	/** Unsigned integer view */
473	X86PGPAEUINT uCareful;
474	/* Not other views. */
475	} PGMSHWPTEPAE;
476
477	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
478	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
479	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
480	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
481	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
482	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
483	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
484	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
485	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
486	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
487	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
488	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
489	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
491	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
492	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
493
494	/**
495	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
496	* invalid entries for present.
497	* @sa X86PTPAE.
498	*/
499	typedef struct PGMSHWPTPAE
500	{
501	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
502	} PGMSHWPTPAE;
503
504	#else
505	typedef X86PTEPAE PGMSHWPTEPAE;
506	typedef X86PTPAE PGMSHWPTPAE;
507	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
508	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
509	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
510	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
511	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
512	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
513	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
514	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
515	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
516	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
517	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
518	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
519	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
520	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
521	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
522	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
523
524	#endif
525
526	/** Pointer to a shadow PAE PTE. */
527	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
528	/** Pointer to a const shadow PAE PTE. */
529	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
530
531	/** Pointer to a shadow PAE page table. */
532	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
533	/** Pointer to a const shadow PAE page table. */
534	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
535	/** @} */
536
537
538	/** The physical access handler type handle count (power of two). */
539	#define PGMPHYSHANDLERTYPE_COUNT 0x20
540	/** Mask for getting the array index from an access handler type handle.
541	* The other handle bits are random and non-zero to avoid mixups due to zero
542	* initialized fields. */
543	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
544
545	/**
546	* Physical page access handler type registration, ring-0 part.
547	*/
548	typedef struct PGMPHYSHANDLERTYPEINTR0
549	{
550	/** The handle value for verfication. */
551	PGMPHYSHANDLERTYPE hType;
552	/** The kind of accesses we're handling. */
553	PGMPHYSHANDLERKIND enmKind;
554	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
555	uint8_t uState;
556	/** Whether to keep the PGM lock when calling the handler.
557	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
558	bool fKeepPgmLock;
559	/** Set if this is registered by a device instance and uUser should be
560	* translated from a device instance ID to a pointer.
561	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
562	bool fRing0DevInsIdx;
563	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
564	bool fNotInHm : 1;
565	/** Pointer to the ring-0 callback function. */
566	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
567	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
568	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
569	/** Description / Name. For easing debugging. */
570	R0PTRTYPE(const char *) pszDesc;
571	} PGMPHYSHANDLERTYPEINTR0;
572	/** Pointer to a physical access handler type registration. */
573	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
574
575	/**
576	* Physical page access handler type registration, shared/ring-3 part.
577	*/
578	typedef struct PGMPHYSHANDLERTYPEINTR3
579	{
580	/** The handle value for verfication. */
581	PGMPHYSHANDLERTYPE hType;
582	/** The kind of accesses we're handling. */
583	PGMPHYSHANDLERKIND enmKind;
584	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
585	uint8_t uState;
586	/** Whether to keep the PGM lock when calling the handler.
587	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
588	bool fKeepPgmLock;
589	/** Set if this is registered by a device instance and uUser should be
590	* translated from a device instance ID to a pointer.
591	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
592	bool fRing0DevInsIdx;
593	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
594	bool fRing0Enabled : 1;
595	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
596	bool fNotInHm : 1;
597	/** Pointer to the ring-3 callback function. */
598	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
599	/** Description / Name. For easing debugging. */
600	R3PTRTYPE(const char *) pszDesc;
601	} PGMPHYSHANDLERTYPEINTR3;
602	/** Pointer to a physical access handler type registration. */
603	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
604
605	/** Pointer to a physical access handler type record for the current context. */
606	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
607	/** Pointer to a const physical access handler type record for the current context. */
608	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
609	/** Dummy physical access handler type record. */
610	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
611
612
613	/**
614	* Physical page access handler structure.
615	*
616	* This is used to keep track of physical address ranges
617	* which are being monitored in some kind of way.
618	*/
619	typedef struct PGMPHYSHANDLER
620	{
621	/** @name Tree stuff.
622	* @{ */
623	/** First address. */
624	RTGCPHYS Key;
625	/** Last address. */
626	RTGCPHYS KeyLast;
627	uint32_t idxLeft;
628	uint32_t idxRight;
629	uint8_t cHeight;
630	/** @} */
631	uint8_t abPadding[3];
632	/** Number of pages to update. */
633	uint32_t cPages;
634	/** Set if we have pages that have been aliased. */
635	uint32_t cAliasedPages;
636	/** Set if we have pages that have temporarily been disabled. */
637	uint32_t cTmpOffPages;
638	/** Registered handler type handle.
639	* @note Marked volatile to prevent re-reading after validation. */
640	PGMPHYSHANDLERTYPE volatile hType;
641	/** User argument for the handlers. */
642	uint64_t uUser;
643	/** Description / Name. For easing debugging. */
644	R3PTRTYPE(const char *) pszDesc;
645	/** Profiling of this handler.
646	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
647	STAMPROFILE Stat;
648	} PGMPHYSHANDLER;
649	AssertCompileSize(PGMPHYSHANDLER, 12*8);
650	/** Pointer to a physical page access handler structure. */
651	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
652
653	/**
654	* Gets the type record for a physical handler (no reference added).
655	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
656	* @param a_pVM The cross context VM structure.
657	* @param a_pPhysHandler Pointer to the physical handler structure
658	* (PGMPHYSHANDLER).
659	*/
660	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
661	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
662
663	/**
664	* Gets the type record for a physical handler, never returns NULL.
665	*
666	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
667	* @param a_pVM The cross context VM structure.
668	* @param a_pPhysHandler Pointer to the physical handler structure
669	* (PGMPHYSHANDLER).
670	*/
671	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
672	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
673
674	/** Physical access handler allocator. */
675	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
676
677	/** Physical access handler tree. */
678	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
679	/** Pointer to a physical access handler tree. */
680	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
681
682
683	/**
684	* A Physical Guest Page tracking structure.
685	*
686	* The format of this structure is complicated because we have to fit a lot
687	* of information into as few bits as possible. The format is also subject
688	* to change (there is one coming up soon). Which means that for we'll be
689	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
690	* accesses to the structure.
691	*/
692	typedef union PGMPAGE
693	{
694	/** 64-bit integer view. */
695	uint64_t au64[2];
696	/** 16-bit view. */
697	uint32_t au32[4];
698	/** 16-bit view. */
699	uint16_t au16[8];
700	/** 8-bit view. */
701	uint8_t au8[16];
702
703	/** Structured view. */
704	struct
705	{
706	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
707	uint64_t u2HandlerPhysStateY : 2;
708	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
709	uint64_t fHandlerPhysNotInHm : 1;
710	/** 3 - Flag indicating that a write monitored page was written to when set. */
711	uint64_t fWrittenToY : 1;
712	/** 4 - Set when the page is write monitored because it's an IEM TB code
713	* page. Save recompiled code the need to verify opcode bytes.
714	*
715	* IEM fetches this flag as part of the TLB queries. The flag is cleared when
716	* the page is made writable and IEM is informed and will invalidate its
717	* physical TLB layer.
718	*
719	* @note Can possibly be set on ROM pages that are not in the monitored state. */
720	uint64_t fCodePageY : 1;
721	/** 7:5 - Unused. */
722	uint64_t u2Unused0 : 3;
723	/** 9:8 - Paging structure needed to map the page
724	* (PGM_PAGE_PDE_TYPE_). /
725	uint64_t u2PDETypeY : 2;
726	/** 11:10 - NEM state bits. */
727	uint64_t u2NemStateY : 2;
728	/** 12:48 - The host physical frame number (shift left to get the
729	* address). */
730	uint64_t HCPhysFN : 36;
731	/** 50:48 - The page state. */
732	uint64_t uStateY : 3;
733	/** 51:53 - The page type (PGMPAGETYPE). */
734	uint64_t uTypeY : 3;
735	/** 63:54 - PTE index for usage tracking (page pool). */
736	uint64_t u10PteIdx : 10;
737
738	/** The GMM page ID.
739	* @remarks In the current implementation, MMIO2 and pages aliased to
740	* MMIO2 pages will be exploiting this field to calculate the
741	* ring-3 mapping address corresponding to the page.
742	* Later we may consider including MMIO2 management into GMM. */
743	uint32_t idPage;
744	/** Usage tracking (page pool). */
745	uint16_t u16TrackingY;
746	/** The number of read locks on this page. */
747	uint8_t cReadLocksY;
748	/** The number of write locks on this page. */
749	uint8_t cWriteLocksY;
750	} s;
751	} PGMPAGE;
752	AssertCompileSize(PGMPAGE, 16);
753	/** Pointer to a physical guest page. */
754	typedef PGMPAGE *PPGMPAGE;
755	/** Pointer to a const physical guest page. */
756	typedef const PGMPAGE *PCPGMPAGE;
757	/** Pointer to a physical guest page pointer. */
758	typedef PPGMPAGE *PPPGMPAGE;
759
760
761	/**
762	* Clears the page structure.
763	* @param a_pPage Pointer to the physical guest page tracking structure.
764	*/
765	#define PGM_PAGE_CLEAR(a_pPage) \
766	do { \
767	(a_pPage)->au64[0] = 0; \
768	(a_pPage)->au64[1] = 0; \
769	} while (0)
770
771	/**
772	* Initializes the page structure.
773	* @param a_pPage Pointer to the physical guest page tracking structure.
774	* @param a_HCPhys The host physical address of the page.
775	* @param a_idPage The (GMM) page ID of the page.
776	* @param a_uType The page type (PGMPAGETYPE).
777	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
778	*/
779	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
780	# define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
781	do { \
782	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
783	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
784	(a_pPage)->au64[0] = SetHCPhysTmp; \
785	(a_pPage)->au64[1] = 0; \
786	(a_pPage)->s.idPage = (a_idPage); \
787	(a_pPage)->s.uStateY = (a_uState); \
788	(a_pPage)->s.uTypeY = (a_uType); \
789	} while (0)
790	#else
791	# define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
792	do { \
793	(a_pPage)->au64[0] = 0; \
794	(a_pPage)->au64[1] = 0; \
795	(a_pPage)->s.idPage = (a_idPage); \
796	(a_pPage)->s.uStateY = (a_uState); \
797	(a_pPage)->s.uTypeY = (a_uType); \
798	} while (0)
799	#endif
800
801	/**
802	* Initializes the page structure of a ZERO page.
803	* @param a_pPage Pointer to the physical guest page tracking structure.
804	* @param a_pVM The VM handle (for getting the zero page address).
805	* @param a_uType The page type (PGMPAGETYPE).
806	*/
807	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
808	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
809
810
811	/** @name The Page state, PGMPAGE::uStateY.
812	* @{ */
813	/** The zero page.
814	* This is a per-VM page that's never ever mapped writable. */
815	#define PGM_PAGE_STATE_ZERO 0U
816	/** A allocated page.
817	* This is a per-VM page allocated from the page pool (or wherever
818	* we get MMIO2 pages from if the type is MMIO2).
819	*/
820	#define PGM_PAGE_STATE_ALLOCATED 1U
821	/** A allocated page that's being monitored for writes.
822	* The shadow page table mappings are read-only. When a write occurs, the
823	* fWrittenTo member is set, the page remapped as read-write and the state
824	* moved back to allocated. */
825	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
826	/** The page is shared, aka. copy-on-write.
827	* This is a page that's shared with other VMs. */
828	#define PGM_PAGE_STATE_SHARED 3U
829	/** The page is ballooned, so no longer available for this VM. */
830	#define PGM_PAGE_STATE_BALLOONED 4U
831	/** @} */
832
833
834	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
835	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
836	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
837	#else
838	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
839	#endif
840
841	/**
842	* Gets the page state.
843	* @returns page state (PGM_PAGE_STATE_*).
844	* @param a_pPage Pointer to the physical guest page tracking structure.
845	*
846	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
847	* builds.
848	*/
849	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
850	#if defined(__GNUC__) && defined(VBOX_STRICT)
851	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
852	#else
853	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
854	#endif
855
856	/**
857	* Sets the page state.
858	* @param a_pVM The VM handle, only used for lock ownership assertions.
859	* @param a_pPage Pointer to the physical guest page tracking structure.
860	* @param a_uState The new page state.
861	*/
862	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
863	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
864
865
866	/**
867	* Gets the host physical address of the guest page.
868	* @returns host physical address (RTHCPHYS).
869	* @param a_pPage Pointer to the physical guest page tracking structure.
870	*
871	* @remarks In strict builds on gcc platforms, this macro will make some ugly
872	* assumption about a valid pVM variable/parameter being in the
873	* current context. It will use this pVM variable to assert that the
874	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
875	* pVM is not around.
876	*/
877	#if 0
878	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
879	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
880	#else
881	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
882	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
883	# else
884	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( 0 )
885	# endif
886	# if defined(__GNUC__) && defined(VBOX_STRICT)
887	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
888	# else
889	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
890	# endif
891	#endif
892
893	/**
894	* Sets the host physical address of the guest page.
895	*
896	* @param a_pVM The VM handle, only used for lock ownership assertions.
897	* @param a_pPage Pointer to the physical guest page tracking structure.
898	* @param a_HCPhys The new host physical address.
899	*/
900	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
901	# define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
902	do { \
903	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
904	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
905	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
906	PGM_PAGE_ASSERT_LOCK(a_pVM); \
907	} while (0)
908	#else
909	# define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
910	do { \
911	(a_pPage)->s.HCPhysFN = 0; \
912	PGM_PAGE_ASSERT_LOCK(a_pVM); \
913	} while (0)
914	#endif
915
916	/**
917	* Get the Page ID.
918	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
919	* @param a_pPage Pointer to the physical guest page tracking structure.
920	*/
921	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
922
923	/**
924	* Sets the Page ID.
925	* @param a_pVM The VM handle, only used for lock ownership assertions.
926	* @param a_pPage Pointer to the physical guest page tracking structure.
927	* @param a_idPage The new page ID.
928	*/
929	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
930	do { \
931	(a_pPage)->s.idPage = (a_idPage); \
932	PGM_PAGE_ASSERT_LOCK(a_pVM); \
933	} while (0)
934
935	/**
936	* Get the Chunk ID.
937	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
938	* @param a_pPage Pointer to the physical guest page tracking structure.
939	*/
940	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
941
942	/**
943	* Get the index of the page within the allocation chunk.
944	* @returns The page index.
945	* @param a_pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
948
949	/**
950	* Gets the page type.
951	* @returns The page type.
952	* @param a_pPage Pointer to the physical guest page tracking structure.
953	*
954	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
955	* builds.
956	*/
957	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
958	#if defined(__GNUC__) && defined(VBOX_STRICT)
959	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
960	#else
961	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
962	#endif
963
964	/**
965	* Sets the page type.
966	*
967	* @param a_pVM The VM handle, only used for lock ownership assertions.
968	* @param a_pPage Pointer to the physical guest page tracking structure.
969	* @param a_enmType The new page type (PGMPAGETYPE).
970	*/
971	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
972	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
973
974	/**
975	* Gets the page table index
976	* @returns The page table index.
977	* @param a_pPage Pointer to the physical guest page tracking structure.
978	*/
979	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
980
981	/**
982	* Sets the page table index.
983	* @param a_pVM The VM handle, only used for lock ownership assertions.
984	* @param a_pPage Pointer to the physical guest page tracking structure.
985	* @param a_iPte New page table index.
986	*/
987	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
988	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
989
990	/**
991	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
992	* @returns true/false.
993	* @param a_pPage Pointer to the physical guest page tracking structure.
994	*/
995	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
996
997	/**
998	* Checks if the page is marked for MMIO, including both aliases.
999	* @returns true/false.
1000	* @param a_pPage Pointer to the physical guest page tracking structure.
1001	*/
1002	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1003	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1004	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1005	)
1006
1007	/**
1008	* Checks if the page is marked for MMIO, including special aliases.
1009	* @returns true/false.
1010	* @param a_pPage Pointer to the physical guest page tracking structure.
1011	*/
1012	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1013	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1014
1015	/**
1016	* Checks if the page is a special aliased MMIO page.
1017	* @returns true/false.
1018	* @param a_pPage Pointer to the physical guest page tracking structure.
1019	*/
1020	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1021
1022	/**
1023	* Checks if the page is backed by the ZERO page.
1024	* @returns true/false.
1025	* @param a_pPage Pointer to the physical guest page tracking structure.
1026	*/
1027	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1028
1029	/**
1030	* Checks if the page is backed by a SHARED page.
1031	* @returns true/false.
1032	* @param a_pPage Pointer to the physical guest page tracking structure.
1033	*/
1034	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1035
1036	/**
1037	* Checks if the page is ballooned.
1038	* @returns true/false.
1039	* @param a_pPage Pointer to the physical guest page tracking structure.
1040	*/
1041	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1042
1043	/**
1044	* Checks if the page is allocated.
1045	* @returns true/false.
1046	* @param a_pPage Pointer to the physical guest page tracking structure.
1047	*/
1048	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1049
1050
1051	/**
1052	* Marks the page as written to (for GMM change monitoring).
1053	* @param a_pVM The VM handle, only used for lock ownership assertions.
1054	* @param a_pPage Pointer to the physical guest page tracking structure.
1055	*/
1056	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1057	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1058
1059	/**
1060	* Clears the written-to indicator.
1061	* @param a_pVM The VM handle, only used for lock ownership assertions.
1062	* @param a_pPage Pointer to the physical guest page tracking structure.
1063	*/
1064	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1065	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1066
1067	/**
1068	* Checks if the page was marked as written-to.
1069	* @returns true/false.
1070	* @param a_pPage Pointer to the physical guest page tracking structure.
1071	*/
1072	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1073
1074
1075	/**
1076	* Marks the page as an IEM code page (being write monitored or a ROM page).
1077	* @param a_pVM The VM handle, only used for lock ownership assertions.
1078	* @param a_pPage Pointer to the physical guest page tracking structure.
1079	*/
1080	#define PGM_PAGE_SET_CODE_PAGE(a_pVM, a_pPage) \
1081	do { (a_pPage)->s.fCodePageY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1082
1083	/**
1084	* Clears the code page indicator.
1085	* @param a_pVM The VM handle, only used for lock ownership assertions.
1086	* @param a_pPage Pointer to the physical guest page tracking structure.
1087	*/
1088	#define PGM_PAGE_CLEAR_CODE_PAGE(a_pVM, a_pPage) \
1089	do { (a_pPage)->s.fCodePageY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1090
1091	/**
1092	* Checks if the page is an IEM code page (implies write monitored or ROM page).
1093	* @returns true/false.
1094	* @param a_pPage Pointer to the physical guest page tracking structure.
1095	*/
1096	#define PGM_PAGE_IS_CODE_PAGE(a_pPage) ( (a_pPage)->s.fCodePageY )
1097
1098
1099	/** @name PT usage values (PGMPAGE::u2PDEType).
1100	*
1101	* @{ */
1102	/** Either as a PT or PDE. */
1103	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1104	/** Must use a page table to map the range. */
1105	#define PGM_PAGE_PDE_TYPE_PT 1
1106	/** Can use a page directory entry to map the continuous range. */
1107	#define PGM_PAGE_PDE_TYPE_PDE 2
1108	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1109	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1110	/** @} */
1111
1112	/**
1113	* Set the PDE type of the page
1114	* @param a_pVM The VM handle, only used for lock ownership assertions.
1115	* @param a_pPage Pointer to the physical guest page tracking structure.
1116	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1117	*/
1118	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1119	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1120
1121	/**
1122	* Checks if the page was marked being part of a large page
1123	* @returns true/false.
1124	* @param a_pPage Pointer to the physical guest page tracking structure.
1125	*/
1126	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1127
1128	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1129	*
1130	* @remarks The values are assigned in order of priority, so we can calculate
1131	* the correct state for a page with different handlers installed.
1132	* @{ */
1133	/** No handler installed. */
1134	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1135	/** Monitoring is temporarily disabled. */
1136	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1137	/** Write access is monitored. */
1138	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1139	/** All access is monitored. */
1140	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1141	/** @} */
1142
1143	/**
1144	* Gets the physical access handler state of a page.
1145	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1146	* @param a_pPage Pointer to the physical guest page tracking structure.
1147	*/
1148	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1149
1150	/**
1151	* Sets the physical access handler state of a page.
1152	* @param a_pPage Pointer to the physical guest page tracking structure.
1153	* @param a_uState The new state value.
1154	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1155	*/
1156	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1157	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1158
1159	/**
1160	* Sets the physical access handler state of a page.
1161	* @param a_pPage Pointer to the physical guest page tracking structure.
1162	* @param a_uState The new state value.
1163	*/
1164	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1165	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1166
1167	/**
1168	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1169	* @returns true/false
1170	* @param a_pPage Pointer to the physical guest page tracking structure.
1171	*/
1172	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1173	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1174
1175	/**
1176	* Checks if the page has any active physical access handlers.
1177	* @returns true/false
1178	* @param a_pPage Pointer to the physical guest page tracking structure.
1179	*/
1180	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1181	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1182
1183	/**
1184	* Checks if the page has any access handlers, including temporarily disabled ones.
1185	* @returns true/false
1186	* @param a_pPage Pointer to the physical guest page tracking structure.
1187	*/
1188	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1189	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1190
1191	/**
1192	* Checks if the page has any active access handlers.
1193	* @returns true/false
1194	* @param a_pPage Pointer to the physical guest page tracking structure.
1195	*/
1196	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1197	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1198
1199	/**
1200	* Checks if the page has any active access handlers catching all accesses.
1201	* @returns true/false
1202	* @param a_pPage Pointer to the physical guest page tracking structure.
1203	*/
1204	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1205	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1206
1207	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1208	* Checks if the physical handlers of the page should be ignored in shadow page
1209	* tables and such.
1210	* @returns true/false
1211	* @param a_pPage Pointer to the physical guest page tracking structure.
1212	*/
1213	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1214
1215	/** @def PGM_PAGE_GET_TRACKING
1216	* Gets the packed shadow page pool tracking data associated with a guest page.
1217	* @returns uint16_t containing the data.
1218	* @param a_pPage Pointer to the physical guest page tracking structure.
1219	*/
1220	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1221	#if defined(__GNUC__) && defined(VBOX_STRICT)
1222	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1223	#else
1224	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1225	#endif
1226
1227	/** @def PGM_PAGE_SET_TRACKING
1228	* Sets the packed shadow page pool tracking data associated with a guest page.
1229	* @param a_pVM The VM handle, only used for lock ownership assertions.
1230	* @param a_pPage Pointer to the physical guest page tracking structure.
1231	* @param a_u16TrackingData The tracking data to store.
1232	*/
1233	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1234	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1235
1236	/** @def PGM_PAGE_GET_TD_CREFS
1237	* Gets the @a cRefs tracking data member.
1238	* @returns cRefs.
1239	* @param a_pPage Pointer to the physical guest page tracking structure.
1240	*/
1241	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1242	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1243	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1244	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1245
1246	/** @def PGM_PAGE_GET_TD_IDX
1247	* Gets the @a idx tracking data member.
1248	* @returns idx.
1249	* @param a_pPage Pointer to the physical guest page tracking structure.
1250	*/
1251	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1252	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1253	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1254	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1255
1256
1257	/** Max number of locks on a page. */
1258	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1259
1260	/** Get the read lock count.
1261	* @returns count.
1262	* @param a_pPage Pointer to the physical guest page tracking structure.
1263	*/
1264	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1265
1266	/** Get the write lock count.
1267	* @returns count.
1268	* @param a_pPage Pointer to the physical guest page tracking structure.
1269	*/
1270	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1271
1272	/** Decrement the read lock counter.
1273	* @param a_pPage Pointer to the physical guest page tracking structure.
1274	*/
1275	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1276
1277	/** Decrement the write lock counter.
1278	* @param a_pPage Pointer to the physical guest page tracking structure.
1279	*/
1280	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1281
1282	/** Increment the read lock counter.
1283	* @param a_pPage Pointer to the physical guest page tracking structure.
1284	*/
1285	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1286
1287	/** Increment the write lock counter.
1288	* @param a_pPage Pointer to the physical guest page tracking structure.
1289	*/
1290	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1291
1292
1293	/** Gets the NEM state.
1294	* @returns NEM state value (two bits).
1295	* @param a_pPage Pointer to the physical guest page tracking structure.
1296	*/
1297	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1298
1299	/** Sets the NEM state.
1300	* @param a_pPage Pointer to the physical guest page tracking structure.
1301	* @param a_u2State The NEM state value (specific to NEM impl.).
1302	*/
1303	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1304	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1305
1306
1307	#if 0
1308	/** Enables sanity checking of write monitoring using CRC-32. */
1309	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1310	#endif
1311
1312	/**
1313	* Per page live save tracking data.
1314	*/
1315	typedef struct PGMLIVESAVERAMPAGE
1316	{
1317	/** Number of times it has been dirtied. */
1318	uint32_t cDirtied : 24;
1319	/** Whether it is currently dirty. */
1320	uint32_t fDirty : 1;
1321	/** Ignore the page.
1322	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1323	* deal with these after pausing the VM and DevPCI have said it bit about
1324	* remappings. */
1325	uint32_t fIgnore : 1;
1326	/** Was a ZERO page last time around. */
1327	uint32_t fZero : 1;
1328	/** Was a SHARED page last time around. */
1329	uint32_t fShared : 1;
1330	/** Whether the page is/was write monitored in a previous pass. */
1331	uint32_t fWriteMonitored : 1;
1332	/** Whether the page is/was write monitored earlier in this pass. */
1333	uint32_t fWriteMonitoredJustNow : 1;
1334	/** Bits reserved for future use. */
1335	uint32_t u2Reserved : 2;
1336	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1337	/** CRC-32 for the page. This is for internal consistency checks. */
1338	uint32_t u32Crc;
1339	#endif
1340	} PGMLIVESAVERAMPAGE;
1341	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1342	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1343	#else
1344	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1345	#endif
1346	/** Pointer to the per page live save tracking data. */
1347	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1348
1349	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1350	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1351
1352
1353	/**
1354	* RAM range lookup table entry.
1355	*/
1356	typedef union PGMRAMRANGELOOKUPENTRY
1357	{
1358	RT_GCC_EXTENSION struct
1359	{
1360	/** Page aligned start address of the range, with page offset holding the ID. */
1361	RTGCPHYS GCPhysFirstAndId;
1362	/** The last address in the range (inclusive). Page aligned (-1). */
1363	RTGCPHYS GCPhysLast;
1364	};
1365	/** Alternative 128-bit view for atomic updating. */
1366	RTUINT128U volatile u128Volatile;
1367	/** Alternative 128-bit view for atomic updating. */
1368	RTUINT128U u128Normal;
1369	} PGMRAMRANGELOOKUPENTRY;
1370	/** Pointer to a lookup table entry. */
1371	typedef PGMRAMRANGELOOKUPENTRY *PPGMRAMRANGELOOKUPENTRY;
1372
1373	/** Extracts the ID from PGMRAMRANGELOOKUPENTRY::GCPhysFirstAndId. */
1374	#define PGMRAMRANGELOOKUPENTRY_GET_ID(a_LookupEntry) ((uint32_t)((a_LookupEntry).GCPhysFirstAndId & GUEST_PAGE_OFFSET_MASK))
1375	/** Extracts the GCPhysFirst from PGMRAMRANGELOOKUPENTRY::GCPhysFirstAndId. */
1376	#define PGMRAMRANGELOOKUPENTRY_GET_FIRST(a_LookupEntry) (((a_LookupEntry).GCPhysFirstAndId) & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK)
1377
1378
1379	/**
1380	* RAM range for GC Phys to HC Phys & R3 Ptr conversion.
1381	*
1382	* This structure is addressed via context specific pointer tables. Lookup is
1383	* organized via the lookup table (PGMRAMRANGELOOKUPENTRY).
1384	*/
1385	typedef struct PGMRAMRANGE
1386	{
1387	/** Start of the range. Page aligned. */
1388	RTGCPHYS GCPhys;
1389	/** Size of the range. (Page aligned of course).
1390	* Ring-0 duplicates this in a PGMR0PERVM::acRamRangePages (shifted by
1391	* guest page size). */
1392	RTGCPHYS cb;
1393	/** PGM_RAM_RANGE_FLAGS_* flags. */
1394	uint32_t fFlags;
1395	/** NEM specific info, UINT32_MAX if not used. */
1396	uint32_t uNemRange;
1397	/** Last address in the range (inclusive). Page aligned (-1). */
1398	RTGCPHYS GCPhysLast;
1399	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1400	R3PTRTYPE(uint8_t *) pbR3;
1401	/** The RAM range identifier (index into the pointer table). */
1402	uint32_t idRange;
1403	#if HC_ARCH_BITS != 32
1404	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1405	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 0 : 1];
1406	#endif
1407	/** Live save per page tracking data. */
1408	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1409	/** The range description. */
1410	R3PTRTYPE(const char *) pszDesc;
1411
1412	/** Array of physical guest page tracking structures.
1413	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1414	PGMPAGE aPages[1];
1415	} PGMRAMRANGE;
1416	AssertCompileMemberAlignment(PGMRAMRANGE, aPages, 16);
1417	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1418	typedef PGMRAMRANGE *PPGMRAMRANGE;
1419
1420	/** @name PGMRAMRANGE::fFlags
1421	* @{ */
1422	/** Ad hoc RAM range for an ROM mapping. */
1423	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1424	/** Ad hoc RAM range for an MMIO mapping. */
1425	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1426	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1427	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1428	/** Valid RAM range flags. */
1429	#define PGM_RAM_RANGE_FLAGS_VALID_MASK (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX)
1430	/** @} */
1431
1432	/** Tests if a RAM range is an ad hoc one or not.
1433	* @returns true/false.
1434	* @param pRam The RAM range.
1435	*/
1436	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1437	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1438
1439	/** The number of entries in the RAM range TLBs (there is one for each
1440	* context). Must be a power of two. */
1441	#define PGM_RAMRANGE_TLB_ENTRIES 64
1442
1443	/**
1444	* Calculates the RAM range TLB index for the physical address.
1445	*
1446	* @returns RAM range TLB index.
1447	* @param a_GCPhys The guest physical address.
1448	*/
1449	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 19) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1450
1451	/**
1452	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1453	* mapping address.
1454	*/
1455	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1456	( (a_pRam)->pbR3 ? (a_pRam)->pbR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1457
1458
1459	/**
1460	* Per page tracking structure for ROM image.
1461	*
1462	* A ROM image may have a shadow page, in which case we may have two pages
1463	* backing it. This structure contains the PGMPAGE for both while
1464	* PGMRAMRANGE have a copy of the active one. It is important that these
1465	* aren't out of sync in any regard other than page pool tracking data.
1466	*/
1467	typedef struct PGMROMPAGE
1468	{
1469	/** The page structure for the virgin ROM page. */
1470	PGMPAGE Virgin;
1471	/** The page structure for the shadow RAM page. */
1472	PGMPAGE Shadow;
1473	/** The current protection setting. */
1474	PGMROMPROT enmProt;
1475	/** Live save status information. Makes use of unused alignment space. */
1476	struct
1477	{
1478	/** The previous protection value. */
1479	uint8_t u8Prot;
1480	/** Written to flag set by the handler. */
1481	bool fWrittenTo;
1482	/** Whether the shadow page is dirty or not. */
1483	bool fDirty;
1484	/** Whether it was dirtied in the recently. */
1485	bool fDirtiedRecently;
1486	} LiveSave;
1487	} PGMROMPAGE;
1488	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1489	/** Pointer to a ROM page tracking structure. */
1490	typedef PGMROMPAGE *PPGMROMPAGE;
1491
1492
1493	/**
1494	* A registered ROM image.
1495	*
1496	* This is needed to keep track of ROM image since they generally intrude
1497	* into a PGMRAMRANGE. It also keeps track of additional info like the
1498	* two page sets (read-only virgin and read-write shadow), the current
1499	* state of each page.
1500	*
1501	* Because access handlers cannot easily be executed in a different
1502	* context, the ROM ranges needs to be accessible and in all contexts.
1503	*/
1504	typedef struct PGMROMRANGE
1505	{
1506	/** Address of the range. */
1507	RTGCPHYS GCPhys;
1508	/** Address of the last byte in the range. */
1509	RTGCPHYS GCPhysLast;
1510	/** Size of the range. */
1511	RTGCPHYS cb;
1512	/** The flags (PGMPHYS_ROM_FLAGS_). /
1513	uint8_t fFlags;
1514	/** The saved state range ID. */
1515	uint8_t idSavedState;
1516	/** The ID of the associated RAM range. */
1517	#ifdef IN_RING0
1518	volatile
1519	#endif
1520	uint16_t idRamRange;
1521	/** The size bits pvOriginal points to. */
1522	uint32_t cbOriginal;
1523	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1524	* This is used for strictness checks. */
1525	R3PTRTYPE(const void *) pvOriginal;
1526	/** The ROM description. */
1527	R3PTRTYPE(const char *) pszDesc;
1528	#ifdef VBOX_WITH_PGM_NEM_MODE
1529	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1530	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1531	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1532	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1533	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1534	R3PTRTYPE(uint8_t *) pbR3Alternate;
1535	RTR3PTR pvAlignment2;
1536	#else
1537	RTR3PTR apvUnused[2];
1538	#endif
1539	/** The per page tracking structures. */
1540	PGMROMPAGE aPages[1];
1541	} PGMROMRANGE;
1542	/** Pointer to a ROM range. */
1543	typedef PGMROMRANGE *PPGMROMRANGE;
1544
1545
1546	/**
1547	* Live save per page data for an MMIO2 page.
1548	*
1549	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1550	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1551	* CRC-32 for detecting changes as well as special handling of zero pages. This
1552	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1553	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1554	* because of speed (2.5x and 6x slower).)
1555	*
1556	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1557	* save but normally is disabled. Since we can write monitor guest
1558	* accesses on our own, we only need this for host accesses. Shouldn't be
1559	* too difficult for DevVGA, VMMDev might be doable, the planned
1560	* networking fun will be fun since it involves ring-0.
1561	*/
1562	typedef struct PGMLIVESAVEMMIO2PAGE
1563	{
1564	/** Set if the page is considered dirty. */
1565	bool fDirty;
1566	/** The number of scans this page has remained unchanged for.
1567	* Only updated for dirty pages. */
1568	uint8_t cUnchangedScans;
1569	/** Whether this page was zero at the last scan. */
1570	bool fZero;
1571	/** Alignment padding. */
1572	bool fReserved;
1573	/** CRC-32 for the first half of the page.
1574	* This is used together with u32CrcH2 to quickly detect changes in the page
1575	* during the non-final passes. */
1576	uint32_t u32CrcH1;
1577	/** CRC-32 for the second half of the page. */
1578	uint32_t u32CrcH2;
1579	/** SHA-1 for the saved page.
1580	* This is used in the final pass to skip pages without changes. */
1581	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1582	} PGMLIVESAVEMMIO2PAGE;
1583	/** Pointer to a live save status data for an MMIO2 page. */
1584	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1585
1586	/**
1587	* A registered MMIO2 (= Device RAM) range.
1588	*
1589	* There are a few reason why we need to keep track of these registrations. One
1590	* of them is the deregistration & cleanup stuff, while another is that the
1591	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1592	* range list.
1593	*
1594	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1595	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1596	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1597	* overlap we will free all the existing RAM pages and put in the ram range
1598	* pages instead.
1599	*/
1600	typedef struct PGMREGMMIO2RANGE
1601	{
1602	/** The owner of the range (a device). */
1603	PPDMDEVINSR3 pDevInsR3;
1604	/** Pointer to the ring-3 mapping of the allocation. */
1605	R3PTRTYPE(uint8_t *) pbR3;
1606	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1607	uint16_t fFlags;
1608	/** The sub device number (internal PCI config (CFGM) number). */
1609	uint8_t iSubDev;
1610	/** The PCI region number. */
1611	uint8_t iRegion;
1612	/** The saved state range ID. */
1613	uint8_t idSavedState;
1614	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1615	uint8_t idMmio2;
1616	/** The ID of the associated RAM range. */
1617	#ifdef IN_RING0
1618	volatile
1619	#endif
1620	uint16_t idRamRange;
1621	/** The mapping address if mapped, NIL_RTGCPHYS if not. */
1622	RTGCPHYS GCPhys;
1623	/** The real size.
1624	* This may be larger than indicated by RamRange.cb if the range has been
1625	* reduced during saved state loading. */
1626	RTGCPHYS cbReal;
1627	/** Pointer to the physical handler for MMIO.
1628	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1629	* will be NULL. */
1630	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1631	/** Live save per page tracking data for MMIO2. */
1632	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1633	RTR3PTR R3PtrPadding;
1634	} PGMREGMMIO2RANGE;
1635	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1636	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1637
1638	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1639	* @{ */
1640	/** Set if this is the first chunk in the MMIO2 range. */
1641	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1642	/** Set if this is the last chunk in the MMIO2 range. */
1643	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1644	/** Set if the whole range is mapped. */
1645	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1646	/** Set if it's overlapping, clear if not. */
1647	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1648	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1649	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1650	/** Set if the access handler is registered. */
1651	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1652	/** Set if dirty page tracking is currently enabled. */
1653	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1654	/** Set if there are dirty pages in the range. */
1655	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1656	/** @} */
1657
1658
1659	/** @name Internal MMIO2 macros.
1660	* @{ */
1661	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1662	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1663	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1664	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1665	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1666	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1667	/** @} */
1668
1669
1670
1671	/**
1672	* PGMPhysRead/Write cache entry
1673	*/
1674	typedef struct PGMPHYSCACHEENTRY
1675	{
1676	/** R3 pointer to physical page. */
1677	R3PTRTYPE(uint8_t *) pbR3;
1678	/** GC Physical address for cache entry */
1679	RTGCPHYS GCPhys;
1680	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1681	RTGCPHYS u32Padding0; /*< alignment padding. /
1682	#endif
1683	} PGMPHYSCACHEENTRY;
1684
1685	/**
1686	* PGMPhysRead/Write cache to reduce REM memory access overhead
1687	*/
1688	typedef struct PGMPHYSCACHE
1689	{
1690	/** Bitmap of valid cache entries */
1691	uint64_t aEntries;
1692	/** Cache entries */
1693	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1694	} PGMPHYSCACHE;
1695
1696
1697	/** @name Ring-3 page mapping TLBs
1698	* @{ */
1699
1700	/** Pointer to an allocation chunk ring-3 mapping. */
1701	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1702	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1703	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1704
1705	/**
1706	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1707	*
1708	* The primary tree (Core) uses the chunk id as key.
1709	*/
1710	typedef struct PGMCHUNKR3MAP
1711	{
1712	/** The key is the chunk id. */
1713	AVLU32NODECORE Core;
1714	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1715	* selection. */
1716	uint32_t iLastUsed;
1717	/** The current reference count. */
1718	uint32_t volatile cRefs;
1719	/** The current permanent reference count. */
1720	uint32_t volatile cPermRefs;
1721	/** The mapping address. */
1722	void *pv;
1723	} PGMCHUNKR3MAP;
1724
1725	/**
1726	* Allocation chunk ring-3 mapping TLB entry.
1727	*/
1728	typedef struct PGMCHUNKR3MAPTLBE
1729	{
1730	/** The chunk id. */
1731	uint32_t volatile idChunk;
1732	#if HC_ARCH_BITS == 64
1733	uint32_t u32Padding; /*< alignment padding. /
1734	#endif
1735	/** The chunk map. */
1736	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1737	} PGMCHUNKR3MAPTLBE;
1738	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1739	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1740
1741	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1742	* @remark Must be a power of two value. */
1743	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1744
1745	/**
1746	* Allocation chunk ring-3 mapping TLB.
1747	*
1748	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1749	* At first glance this might look kinda odd since AVL trees are
1750	* supposed to give the most optimal lookup times of all trees
1751	* due to their balancing. However, take a tree with 1023 nodes
1752	* in it, that's 10 levels, meaning that most searches has to go
1753	* down 9 levels before they find what they want. This isn't fast
1754	* compared to a TLB hit. There is the factor of cache misses,
1755	* and of course the problem with trees and branch prediction.
1756	* This is why we use TLBs in front of most of the trees.
1757	*
1758	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1759	* difficult when we switch to the new inlined AVL trees (from kStuff).
1760	*/
1761	typedef struct PGMCHUNKR3MAPTLB
1762	{
1763	/** The TLB entries. */
1764	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1765	} PGMCHUNKR3MAPTLB;
1766
1767	/**
1768	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1769	* @returns Chunk TLB index.
1770	* @param idChunk The Chunk ID.
1771	*/
1772	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1773
1774
1775	/**
1776	* Ring-3 guest page mapping TLB entry.
1777	* @remarks used in ring-0 as well at the moment.
1778	*/
1779	typedef struct PGMPAGER3MAPTLBE
1780	{
1781	/** Address of the page. */
1782	RTGCPHYS volatile GCPhys;
1783	/** The guest page. */
1784	R3PTRTYPE(PPGMPAGE) volatile pPage;
1785	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1786	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1787	/** The address */
1788	R3PTRTYPE(void *) volatile pv;
1789	#if HC_ARCH_BITS == 32
1790	uint32_t u32Padding; /*< alignment padding. /
1791	#endif
1792	} PGMPAGER3MAPTLBE;
1793	/** Pointer to an entry in the HC physical TLB. */
1794	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1795
1796
1797	/** The number of entries in the ring-3 guest page mapping TLB.
1798	* @remarks The value must be a power of two. */
1799	#define PGM_PAGER3MAPTLB_ENTRIES 256
1800
1801	/**
1802	* Ring-3 guest page mapping TLB.
1803	* @remarks used in ring-0 as well at the moment.
1804	*/
1805	typedef struct PGMPAGER3MAPTLB
1806	{
1807	/** The TLB entries. */
1808	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1809	} PGMPAGER3MAPTLB;
1810	/** Pointer to the ring-3 guest page mapping TLB. */
1811	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1812
1813	/**
1814	* Calculates the index of the TLB entry for the specified guest page.
1815	* @returns Physical TLB index.
1816	* @param GCPhys The guest physical address.
1817	*/
1818	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1819
1820	/** @} */
1821
1822
1823	/** @name Ring-0 page mapping TLB
1824	* @{ */
1825	/**
1826	* Ring-0 guest page mapping TLB entry.
1827	*/
1828	typedef struct PGMPAGER0MAPTLBE
1829	{
1830	/** Address of the page. */
1831	RTGCPHYS volatile GCPhys;
1832	/** The guest page. */
1833	R0PTRTYPE(PPGMPAGE) volatile pPage;
1834	/** The address */
1835	R0PTRTYPE(void *) volatile pv;
1836	} PGMPAGER0MAPTLBE;
1837	/** Pointer to an entry in the HC physical TLB. */
1838	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1839
1840
1841	/** The number of entries in the ring-0 guest page mapping TLB.
1842	* @remarks The value must be a power of two. */
1843	#define PGM_PAGER0MAPTLB_ENTRIES 256
1844
1845	/**
1846	* Ring-0 guest page mapping TLB.
1847	*/
1848	typedef struct PGMPAGER0MAPTLB
1849	{
1850	/** The TLB entries. */
1851	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1852	} PGMPAGER0MAPTLB;
1853	/** Pointer to the ring-3 guest page mapping TLB. */
1854	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1855
1856	/**
1857	* Calculates the index of the TLB entry for the specified guest page.
1858	* @returns Physical TLB index.
1859	* @param GCPhys The guest physical address.
1860	*/
1861	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1862	/** @} */
1863
1864
1865	/** @name Context neutral page mapper TLB.
1866	*
1867	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1868	* code is writting in a kind of context neutral way. Time will show whether
1869	* this actually makes sense or not...
1870	*
1871	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1872	* context ends up using a global mapping cache on some platforms
1873	* (darwin).
1874	*
1875	* @{ */
1876	/** @typedef PPGMPAGEMAPTLB
1877	* The page mapper TLB pointer type for the current context. */
1878	/** @typedef PPGMPAGEMAPTLB
1879	* The page mapper TLB entry pointer type for the current context. */
1880	/** @typedef PPGMPAGEMAPTLB
1881	* The page mapper TLB entry pointer pointer type for the current context. */
1882	/** @def PGM_PAGEMAPTLB_ENTRIES
1883	* The number of TLB entries in the page mapper TLB for the current context. */
1884	/** @def PGM_PAGEMAPTLB_IDX
1885	* Calculate the TLB index for a guest physical address.
1886	* @returns The TLB index.
1887	* @param GCPhys The guest physical address. */
1888	/** @typedef PPGMPAGEMAP
1889	* Pointer to a page mapper unit for current context. */
1890	/** @typedef PPPGMPAGEMAP
1891	* Pointer to a page mapper unit pointer for current context. */
1892	#if defined(IN_RING0)
1893	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1894	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1895	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1896	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1897	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1898	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1899	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1900	#else
1901	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1902	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1903	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1904	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1905	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1906	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1907	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1908	#endif
1909	/** @} */
1910
1911
1912	/** @name PGM Pool Indexes.
1913	* Aka. the unique shadow page identifier.
1914	* @{ */
1915	/** NIL page pool IDX. */
1916	#define NIL_PGMPOOL_IDX 0
1917	/** The first normal index. There used to be 5 fictive pages up front, now
1918	* there is only the NIL page. */
1919	#define PGMPOOL_IDX_FIRST 1
1920	/** The last valid index. (inclusive, 14 bits) */
1921	#define PGMPOOL_IDX_LAST 0x3fff
1922	/** @} */
1923
1924	/** The NIL index for the parent chain. */
1925	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1926	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1927
1928	/**
1929	* Node in the chain linking a shadowed page to it's parent (user).
1930	*/
1931	#pragma pack(1)
1932	typedef struct PGMPOOLUSER
1933	{
1934	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1935	uint16_t iNext;
1936	/** The user page index. */
1937	uint16_t iUser;
1938	/** Index into the user table. */
1939	uint32_t iUserTable;
1940	} PGMPOOLUSER, *PPGMPOOLUSER;
1941	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1942	#pragma pack()
1943
1944
1945	/** The NIL index for the phys ext chain. */
1946	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1947	/** The NIL pte index for a phys ext chain slot. */
1948	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1949
1950	/**
1951	* Node in the chain of physical cross reference extents.
1952	* @todo Calling this an 'extent' is not quite right, find a better name.
1953	* @todo find out the optimal size of the aidx array
1954	*/
1955	#pragma pack(1)
1956	typedef struct PGMPOOLPHYSEXT
1957	{
1958	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1959	uint16_t iNext;
1960	/** Alignment. */
1961	uint16_t u16Align;
1962	/** The user page index. */
1963	uint16_t aidx[3];
1964	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1965	uint16_t apte[3];
1966	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1967	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1968	#pragma pack()
1969
1970
1971	/**
1972	* The kind of page that's being shadowed.
1973	*/
1974	typedef enum PGMPOOLKIND
1975	{
1976	/** The virtual invalid 0 entry. */
1977	PGMPOOLKIND_INVALID = 0,
1978	/** The entry is free (=unused). */
1979	PGMPOOLKIND_FREE,
1980
1981	/** Shw: 32-bit page table; Gst: no paging. */
1982	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1983	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1984	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1985	/** Shw: 32-bit page table; Gst: 4MB page. */
1986	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1987	/** Shw: PAE page table; Gst: no paging. */
1988	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1989	/** Shw: PAE page table; Gst: 32-bit page table. */
1990	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1991	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1992	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1993	/** Shw: PAE page table; Gst: PAE page table. */
1994	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1995	/** Shw: PAE page table; Gst: 2MB page. */
1996	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1997
1998	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1999	PGMPOOLKIND_32BIT_PD,
2000	/** Shw: 32-bit page directory. Gst: no paging. */
2001	PGMPOOLKIND_32BIT_PD_PHYS,
2002	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2003	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2004	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2005	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2006	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2007	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2008	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2009	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2010	/** Shw: PAE page directory; Gst: PAE page directory. */
2011	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2012	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2013	PGMPOOLKIND_PAE_PD_PHYS,
2014
2015	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2016	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2017	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2018	PGMPOOLKIND_PAE_PDPT,
2019	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2020	PGMPOOLKIND_PAE_PDPT_PHYS,
2021
2022	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2023	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2024	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2025	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2026	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2027	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2028	/** Shw: 64-bit page directory table; Gst: no paging. */
2029	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2030
2031	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2032	PGMPOOLKIND_64BIT_PML4,
2033
2034	/** Shw: EPT page directory pointer table; Gst: no paging. */
2035	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2036	/** Shw: EPT page directory table; Gst: no paging. */
2037	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2038	/** Shw: EPT page table; Gst: no paging. */
2039	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2040
2041	/** Shw: Root Nested paging table. */
2042	PGMPOOLKIND_ROOT_NESTED,
2043
2044	/** Shw: EPT page table; Gst: EPT page table. */
2045	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
2046	/** Shw: EPT page table; Gst: 2MB page. */
2047	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
2048	/** Shw: EPT page directory table; Gst: EPT page directory. */
2049	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
2050	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
2051	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
2052	/** Shw: EPT PML4; Gst: EPT PML4. */
2053	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
2054
2055	/** The last valid entry. */
2056	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
2057	} PGMPOOLKIND;
2058
2059	/**
2060	* The access attributes of the page; only applies to big pages.
2061	*/
2062	typedef enum
2063	{
2064	PGMPOOLACCESS_DONTCARE = 0,
2065	PGMPOOLACCESS_USER_RW,
2066	PGMPOOLACCESS_USER_R,
2067	PGMPOOLACCESS_USER_RW_NX,
2068	PGMPOOLACCESS_USER_R_NX,
2069	PGMPOOLACCESS_SUPERVISOR_RW,
2070	PGMPOOLACCESS_SUPERVISOR_R,
2071	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2072	PGMPOOLACCESS_SUPERVISOR_R_NX
2073	} PGMPOOLACCESS;
2074
2075	/**
2076	* The tracking data for a page in the pool.
2077	*/
2078	typedef struct PGMPOOLPAGE
2079	{
2080	/** AVL node code with the (HC) physical address of this page. */
2081	AVLOHCPHYSNODECORE Core;
2082	/** Pointer to the R3 mapping of the page. */
2083	R3PTRTYPE(void *) pvPageR3;
2084	/** Pointer to the R0 mapping of the page. */
2085	R0PTRTYPE(void *) pvPageR0;
2086	/** The guest physical address. */
2087	RTGCPHYS GCPhys;
2088	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2089	uint8_t enmKind;
2090	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2091	uint8_t enmAccess;
2092	/** This supplements enmKind and enmAccess */
2093	bool fA20Enabled : 1;
2094
2095	/** Used to indicate that the page is zeroed. */
2096	bool fZeroed : 1;
2097	/** Used to indicate that a PT has non-global entries. */
2098	bool fSeenNonGlobal : 1;
2099	/** Used to indicate that we're monitoring writes to the guest page. */
2100	bool fMonitored : 1;
2101	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2102	* (All pages are in the age list.) */
2103	bool fCached : 1;
2104	/** This is used by the R3 access handlers when invoked by an async thread.
2105	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2106	bool volatile fReusedFlushPending : 1;
2107	/** Used to mark the page as dirty (write monitoring is temporarily
2108	* off). */
2109	bool fDirty : 1;
2110	bool fPadding1 : 1;
2111	bool fPadding2;
2112
2113	/** The index of this page. */
2114	uint16_t idx;
2115	/** The next entry in the list this page currently resides in.
2116	* It's either in the free list or in the GCPhys hash. */
2117	uint16_t iNext;
2118	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2119	uint16_t iUserHead;
2120	/** The number of present entries. */
2121	uint16_t cPresent;
2122	/** The first entry in the table which is present. */
2123	uint16_t iFirstPresent;
2124	/** The number of modifications to the monitored page. */
2125	uint16_t cModifications;
2126	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2127	uint16_t iModifiedNext;
2128	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2129	uint16_t iModifiedPrev;
2130	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2131	uint16_t iMonitoredNext;
2132	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2133	uint16_t iMonitoredPrev;
2134	/** The next page in the age list. */
2135	uint16_t iAgeNext;
2136	/** The previous page in the age list. */
2137	uint16_t iAgePrev;
2138	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2139	uint8_t idxDirtyEntry;
2140
2141	/** @name Access handler statistics to determine whether the guest is
2142	* (re)initializing a page table.
2143	* @{ */
2144	RTGCPTR GCPtrLastAccessHandlerRip;
2145	RTGCPTR GCPtrLastAccessHandlerFault;
2146	uint64_t cLastAccessHandler;
2147	/** @} */
2148	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2149	uint32_t volatile cLocked;
2150	#if GC_ARCH_BITS == 64
2151	uint32_t u32Alignment3;
2152	#endif
2153	# ifdef VBOX_STRICT
2154	RTGCPTR GCPtrDirtyFault;
2155	# endif
2156	} PGMPOOLPAGE;
2157	/** Pointer to a pool page. */
2158	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2159	/** Pointer to a const pool page. */
2160	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2161	/** Pointer to a pool page pointer. */
2162	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2163
2164
2165	/** The hash table size. */
2166	# define PGMPOOL_HASH_SIZE 0x8000
2167	/** The hash function. */
2168	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2169
2170
2171	/**
2172	* The shadow page pool instance data.
2173	*
2174	* It's all one big allocation made at init time, except for the
2175	* pages that is. The user nodes follows immediately after the
2176	* page structures.
2177	*/
2178	typedef struct PGMPOOL
2179	{
2180	/** The VM handle - R3 Ptr. */
2181	PVMR3 pVMR3;
2182	/** The VM handle - R0 Ptr. */
2183	R0PTRTYPE(PVMCC) pVMR0;
2184	/** The ring-3 pointer to this structure. */
2185	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2186	/** The ring-0 pointer to this structure. */
2187	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2188	/** The max pool size. This includes the special IDs. */
2189	uint16_t cMaxPages;
2190	/** The current pool size. */
2191	uint16_t cCurPages;
2192	/** The head of the free page list. */
2193	uint16_t iFreeHead;
2194	/* Padding. */
2195	uint16_t u16Padding;
2196	/** Head of the chain of free user nodes. */
2197	uint16_t iUserFreeHead;
2198	/** The number of user nodes we've allocated. */
2199	uint16_t cMaxUsers;
2200	/** The number of present page table entries in the entire pool. */
2201	uint32_t cPresent;
2202	/** Pointer to the array of user nodes - R3 pointer. */
2203	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2204	/** Pointer to the array of user nodes - R0 pointer. */
2205	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2206	/** Head of the chain of free phys ext nodes. */
2207	uint16_t iPhysExtFreeHead;
2208	/** The number of user nodes we've allocated. */
2209	uint16_t cMaxPhysExts;
2210	uint32_t u32Padding0b;
2211	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2212	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2213	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2214	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2215	/** Hash table for GCPhys addresses. */
2216	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2217	/** The head of the age list. */
2218	uint16_t iAgeHead;
2219	/** The tail of the age list. */
2220	uint16_t iAgeTail;
2221	/** Set if the cache is enabled. */
2222	bool fCacheEnabled;
2223	/** Alignment padding. */
2224	bool afPadding1[3];
2225	/** Head of the list of modified pages. */
2226	uint16_t iModifiedHead;
2227	/** The current number of modified pages. */
2228	uint16_t cModifiedPages;
2229	/** Alignment padding. */
2230	uint32_t u32Padding2;
2231	/** Physical access handler type registration handle. */
2232	PGMPHYSHANDLERTYPE hAccessHandlerType;
2233	/** Next available slot (in aDirtyPages). */
2234	uint32_t idxFreeDirtyPage;
2235	/** Number of active dirty pages. */
2236	uint32_t cDirtyPages;
2237	/** Array of current dirty pgm pool page indices. */
2238	uint16_t aidxDirtyPages[16];
2239	/** Array running in parallel to aidxDirtyPages with the page data. */
2240	struct
2241	{
2242	uint64_t aPage[512];
2243	} aDirtyPages[16];
2244
2245	/** The number of pages currently in use. */
2246	uint16_t cUsedPages;
2247	#ifdef VBOX_WITH_STATISTICS
2248	/** The high water mark for cUsedPages. */
2249	uint16_t cUsedPagesHigh;
2250	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2251	/** Profiling pgmPoolAlloc(). */
2252	STAMPROFILEADV StatAlloc;
2253	/** Profiling pgmR3PoolClearDoIt(). */
2254	STAMPROFILE StatClearAll;
2255	/** Profiling pgmR3PoolReset(). */
2256	STAMPROFILE StatR3Reset;
2257	/** Profiling pgmPoolFlushPage(). */
2258	STAMPROFILE StatFlushPage;
2259	/** Profiling pgmPoolFree(). */
2260	STAMPROFILE StatFree;
2261	/** Counting explicit flushes by PGMPoolFlushPage(). */
2262	STAMCOUNTER StatForceFlushPage;
2263	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2264	STAMCOUNTER StatForceFlushDirtyPage;
2265	/** Counting flushes for reused pages. */
2266	STAMCOUNTER StatForceFlushReused;
2267	/** Profiling time spent zeroing pages. */
2268	STAMPROFILE StatZeroPage;
2269	/** Profiling of pgmPoolTrackDeref. */
2270	STAMPROFILE StatTrackDeref;
2271	/** Profiling pgmTrackFlushGCPhysPT. */
2272	STAMPROFILE StatTrackFlushGCPhysPT;
2273	/** Profiling pgmTrackFlushGCPhysPTs. */
2274	STAMPROFILE StatTrackFlushGCPhysPTs;
2275	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2276	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2277	/** Number of times we've been out of user records. */
2278	STAMCOUNTER StatTrackFreeUpOneUser;
2279	/** Nr of flushed entries. */
2280	STAMCOUNTER StatTrackFlushEntry;
2281	/** Nr of updated entries. */
2282	STAMCOUNTER StatTrackFlushEntryKeep;
2283	/** Profiling deref activity related tracking GC physical pages. */
2284	STAMPROFILE StatTrackDerefGCPhys;
2285	/** Number of linear searches for a HCPhys in the ram ranges. */
2286	STAMCOUNTER StatTrackLinearRamSearches;
2287	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2288	STAMCOUNTER StamTrackPhysExtAllocFailures;
2289
2290	/** Profiling the RC/R0 \#PF access handler. */
2291	STAMPROFILE StatMonitorPfRZ;
2292	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2293	STAMPROFILE StatMonitorPfRZHandled;
2294	/** Times we've failed interpreting the instruction. */
2295	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2296	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2297	STAMPROFILE StatMonitorPfRZFlushPage;
2298	/** Times we've detected a page table reinit. */
2299	STAMCOUNTER StatMonitorPfRZFlushReinit;
2300	/** Counting flushes for pages that are modified too often. */
2301	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2302	/** Times we've detected fork(). */
2303	STAMCOUNTER StatMonitorPfRZFork;
2304	/** Times we've failed interpreting a patch code instruction. */
2305	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2306	/** Times we've failed interpreting a patch code instruction during flushing. */
2307	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2308	/** The number of times we've seen rep prefixes we can't handle. */
2309	STAMCOUNTER StatMonitorPfRZRepPrefix;
2310	/** Profiling the REP STOSD cases we've handled. */
2311	STAMPROFILE StatMonitorPfRZRepStosd;
2312
2313	/** Profiling the R0/RC regular access handler. */
2314	STAMPROFILE StatMonitorRZ;
2315	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2316	STAMPROFILE StatMonitorRZFlushPage;
2317	/** Per access size counts indexed by size minus 1, last for larger. */
2318	STAMCOUNTER aStatMonitorRZSizes[16+3];
2319	/** Missaligned access counts indexed by offset - 1. */
2320	STAMCOUNTER aStatMonitorRZMisaligned[7];
2321
2322	/** Nr of handled PT faults. */
2323	STAMCOUNTER StatMonitorRZFaultPT;
2324	/** Nr of handled PD faults. */
2325	STAMCOUNTER StatMonitorRZFaultPD;
2326	/** Nr of handled PDPT faults. */
2327	STAMCOUNTER StatMonitorRZFaultPDPT;
2328	/** Nr of handled PML4 faults. */
2329	STAMCOUNTER StatMonitorRZFaultPML4;
2330
2331	/** Profiling the R3 access handler. */
2332	STAMPROFILE StatMonitorR3;
2333	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2334	STAMPROFILE StatMonitorR3FlushPage;
2335	/** Per access size counts indexed by size minus 1, last for larger. */
2336	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2337	/** Missaligned access counts indexed by offset - 1. */
2338	STAMCOUNTER aStatMonitorR3Misaligned[7];
2339	/** Nr of handled PT faults. */
2340	STAMCOUNTER StatMonitorR3FaultPT;
2341	/** Nr of handled PD faults. */
2342	STAMCOUNTER StatMonitorR3FaultPD;
2343	/** Nr of handled PDPT faults. */
2344	STAMCOUNTER StatMonitorR3FaultPDPT;
2345	/** Nr of handled PML4 faults. */
2346	STAMCOUNTER StatMonitorR3FaultPML4;
2347
2348	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2349	STAMCOUNTER StatResetDirtyPages;
2350	/** Times we've called pgmPoolAddDirtyPage. */
2351	STAMCOUNTER StatDirtyPage;
2352	/** Times we've had to flush duplicates for dirty page management. */
2353	STAMCOUNTER StatDirtyPageDupFlush;
2354	/** Times we've had to flush because of overflow. */
2355	STAMCOUNTER StatDirtyPageOverFlowFlush;
2356
2357	/** The high water mark for cModifiedPages. */
2358	uint16_t cModifiedPagesHigh;
2359	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2360
2361	/** The number of cache hits. */
2362	STAMCOUNTER StatCacheHits;
2363	/** The number of cache misses. */
2364	STAMCOUNTER StatCacheMisses;
2365	/** The number of times we've got a conflict of 'kind' in the cache. */
2366	STAMCOUNTER StatCacheKindMismatches;
2367	/** Number of times we've been out of pages. */
2368	STAMCOUNTER StatCacheFreeUpOne;
2369	/** The number of cacheable allocations. */
2370	STAMCOUNTER StatCacheCacheable;
2371	/** The number of uncacheable allocations. */
2372	STAMCOUNTER StatCacheUncacheable;
2373	#else
2374	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2375	#endif
2376	/** Profiling PGMR0PoolGrow(). */
2377	STAMPROFILE StatGrow;
2378	/** The AVL tree for looking up a page by its HC physical address. */
2379	AVLOHCPHYSTREE HCPhysTree;
2380	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2381	/** Array of pages. (cMaxPages in length)
2382	* The Id is the index into thist array.
2383	*/
2384	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2385	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2386	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2387	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2388	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2389	#ifdef VBOX_WITH_STATISTICS
2390	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2391	#endif
2392	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2393
2394
2395	/** @def PGMPOOL_PAGE_2_PTR
2396	* Maps a pool page pool into the current context.
2397	*
2398	* @returns VBox status code.
2399	* @param a_pVM Pointer to the VM.
2400	* @param a_pPage The pool page.
2401	*
2402	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2403	* small page window employeed by that function. Be careful.
2404	* @remark There is no need to assert on the result.
2405	*/
2406	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2407	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2408	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2409	{
2410	RT_NOREF(pszCaller);
2411	AssertPtr(a_pPage);
2412	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2413	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2414	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2415	return a_pPage->CTX_SUFF(pvPage);
2416	}
2417	#else
2418	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2419	#endif
2420
2421
2422	/** @def PGMPOOL_PAGE_2_PTR_V2
2423	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2424	*
2425	* @returns VBox status code.
2426	* @param a_pVM Pointer to the VM.
2427	* @param a_pVCpu The current CPU.
2428	* @param a_pPage The pool page.
2429	*
2430	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2431	* small page window employeed by that function. Be careful.
2432	* @remark There is no need to assert on the result.
2433	*/
2434	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2435
2436
2437	/** @def PGMPOOL_PAGE_IS_NESTED
2438	* Checks whether the given pool page is a nested-guest pool page.
2439	*
2440	* @returns @c true if a nested-guest pool page, @c false otherwise.
2441	* @param a_pPage The pool page.
2442	* @todo We can optimize the conditionals later.
2443	*/
2444	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2445	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2446	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2447	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2448	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2449	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2450
2451	/** @name Per guest page tracking data.
2452	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2453	* is to use more bits for it and split it up later on. But for now we'll play
2454	* safe and change as little as possible.
2455	*
2456	* The 16-bit word has two parts:
2457	*
2458	* The first 14-bit forms the @a idx field. It is either the index of a page in
2459	* the shadow page pool, or and index into the extent list.
2460	*
2461	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2462	* shadow page pool references to the page. If cRefs equals
2463	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2464	* (misnomer) table and not the shadow page pool.
2465	*
2466	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2467	* the 16-bit word.
2468	*
2469	* @{ */
2470	/** The shift count for getting to the cRefs part. */
2471	#define PGMPOOL_TD_CREFS_SHIFT 14
2472	/** The mask applied after shifting the tracking data down by
2473	* PGMPOOL_TD_CREFS_SHIFT. */
2474	#define PGMPOOL_TD_CREFS_MASK 0x3
2475	/** The cRefs value used to indicate that the idx is the head of a
2476	* physical cross reference list. */
2477	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2478	/** The shift used to get idx. */
2479	#define PGMPOOL_TD_IDX_SHIFT 0
2480	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2481	#define PGMPOOL_TD_IDX_MASK 0x3fff
2482	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2483	* simply too many mappings of this page. */
2484	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2485
2486	/** @def PGMPOOL_TD_MAKE
2487	* Makes a 16-bit tracking data word.
2488	*
2489	* @returns tracking data.
2490	* @param cRefs The @a cRefs field. Must be within bounds!
2491	* @param idx The @a idx field. Must also be within bounds! */
2492	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2493
2494	/** @def PGMPOOL_TD_GET_CREFS
2495	* Get the @a cRefs field from a tracking data word.
2496	*
2497	* @returns The @a cRefs field
2498	* @param u16 The tracking data word.
2499	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2500	* non-zero @a u16. */
2501	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2502
2503	/** @def PGMPOOL_TD_GET_IDX
2504	* Get the @a idx field from a tracking data word.
2505	*
2506	* @returns The @a idx field
2507	* @param u16 The tracking data word. */
2508	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2509	/** @} */
2510
2511
2512
2513	/** @name A20 gate macros
2514	* @{ */
2515	#define PGM_WITH_A20
2516	#ifdef PGM_WITH_A20
2517	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2518	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2519	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2520	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2521	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2522	#else
2523	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2524	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2525	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2526	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2527	#endif
2528	/** @} */
2529
2530
2531	/**
2532	* Guest page table walk for the AMD64 mode.
2533	*/
2534	typedef struct PGMPTWALKGSTAMD64
2535	{
2536	PX86PML4 pPml4;
2537	PX86PML4E pPml4e;
2538	X86PML4E Pml4e;
2539
2540	PX86PDPT pPdpt;
2541	PX86PDPE pPdpe;
2542	X86PDPE Pdpe;
2543
2544	PX86PDPAE pPd;
2545	PX86PDEPAE pPde;
2546	X86PDEPAE Pde;
2547
2548	PX86PTPAE pPt;
2549	PX86PTEPAE pPte;
2550	X86PTEPAE Pte;
2551	} PGMPTWALKGSTAMD64;
2552	/** Pointer to a AMD64 guest page table walk. */
2553	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2554	/** Pointer to a const AMD64 guest page table walk. */
2555	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2556
2557	/**
2558	* Guest page table walk for the EPT mode.
2559	*/
2560	typedef struct PGMPTWALKGSTEPT
2561	{
2562	PEPTPML4 pPml4;
2563	PEPTPML4E pPml4e;
2564	EPTPML4E Pml4e;
2565
2566	PEPTPDPT pPdpt;
2567	PEPTPDPTE pPdpte;
2568	EPTPDPTE Pdpte;
2569
2570	PEPTPD pPd;
2571	PEPTPDE pPde;
2572	EPTPDE Pde;
2573
2574	PEPTPT pPt;
2575	PEPTPTE pPte;
2576	EPTPTE Pte;
2577	} PGMPTWALKGSTEPT;
2578	/** Pointer to an EPT guest page table walk. */
2579	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2580	/** Pointer to a const EPT guest page table walk. */
2581	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2582
2583	/**
2584	* Guest page table walk for the PAE mode.
2585	*/
2586	typedef struct PGMPTWALKGSTPAE
2587	{
2588	PX86PDPT pPdpt;
2589	PX86PDPE pPdpe;
2590	X86PDPE Pdpe;
2591
2592	PX86PDPAE pPd;
2593	PX86PDEPAE pPde;
2594	X86PDEPAE Pde;
2595
2596	PX86PTPAE pPt;
2597	PX86PTEPAE pPte;
2598	X86PTEPAE Pte;
2599	} PGMPTWALKGSTPAE;
2600	/** Pointer to a PAE guest page table walk. */
2601	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2602	/** Pointer to a const AMD64 guest page table walk. */
2603	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2604
2605	/**
2606	* Guest page table walk for the 32-bit mode.
2607	*/
2608	typedef struct PGMPTWALKGST32BIT
2609	{
2610	PX86PD pPd;
2611	PX86PDE pPde;
2612	X86PDE Pde;
2613
2614	PX86PT pPt;
2615	PX86PTE pPte;
2616	X86PTE Pte;
2617	} PGMPTWALKGST32BIT;
2618	/** Pointer to a 32-bit guest page table walk. */
2619	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2620	/** Pointer to a const 32-bit guest page table walk. */
2621	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2622
2623	/**
2624	* Which part of PGMPTWALKGST that is valid.
2625	*/
2626	typedef enum PGMPTWALKGSTTYPE
2627	{
2628	/** Customary invalid 0 value. */
2629	PGMPTWALKGSTTYPE_INVALID = 0,
2630	/** PGMPTWALKGST::u.Amd64 is valid. */
2631	PGMPTWALKGSTTYPE_AMD64,
2632	/** PGMPTWALKGST::u.Pae is valid. */
2633	PGMPTWALKGSTTYPE_PAE,
2634	/** PGMPTWALKGST::u.Legacy is valid. */
2635	PGMPTWALKGSTTYPE_32BIT,
2636	/** PGMPTWALKGST::u.Ept is valid. */
2637	PGMPTWALKGSTTYPE_EPT,
2638	/** Customary 32-bit type hack. */
2639	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2640	} PGMPTWALKGSTTYPE;
2641
2642	/**
2643	* Combined guest page table walk result.
2644	*/
2645	typedef struct PGMPTWALKGST
2646	{
2647	union
2648	{
2649	/** The page walker for AMD64. */
2650	PGMPTWALKGSTAMD64 Amd64;
2651	/** The page walker for PAE (32-bit). */
2652	PGMPTWALKGSTPAE Pae;
2653	/** The page walker for 32-bit paging (called legacy due to C naming
2654	* convension). */
2655	PGMPTWALKGST32BIT Legacy;
2656	/** The page walker for EPT (SLAT). */
2657	PGMPTWALKGSTEPT Ept;
2658	} u;
2659	/** Indicates which part of the union is valid. */
2660	PGMPTWALKGSTTYPE enmType;
2661	} PGMPTWALKGST;
2662	/** Pointer to a combined guest page table walk result. */
2663	typedef PGMPTWALKGST *PPGMPTWALKGST;
2664	/** Pointer to a read-only combined guest page table walk result. */
2665	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2666
2667
2668	/** @name Paging mode macros
2669	* @{
2670	*/
2671	#ifdef IN_RING3
2672	# define PGM_CTX(a,b) a##R3##b
2673	# define PGM_CTX_STR(a,b) a "R3" b
2674	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2675	#elif defined(IN_RING0)
2676	# define PGM_CTX(a,b) a##R0##b
2677	# define PGM_CTX_STR(a,b) a "R0" b
2678	# define PGM_CTX_DECL(type) VMMDECL(type)
2679	#else
2680	# error "Not IN_RING3 or IN_RING0!"
2681	#endif
2682
2683	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2684	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2685	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2686	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2687	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2688	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2689	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2690	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2691	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2692	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2693	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2694	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2695	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2696	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2697	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2698	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2699
2700	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2701	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2702	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2703	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2704
2705	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2706	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2707	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2708	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2709	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2710	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2711	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2712	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2713	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2714	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2715	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2716	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2717	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2718	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2719	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2720	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2721	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2722	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2723	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2724	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2725	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2726	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2727	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2728	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2729	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2730
2731	/* Shw_Gst */
2732	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2733	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2734	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2735	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2736	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2737	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2738	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2739	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2740	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2741	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2742	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2743	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2744	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2745	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2746	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2747	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2748	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2749	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2750	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2751	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2752	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2753	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2754	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2755	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2756	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2757	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2758	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2759	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2760	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2761	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2762	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2763	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2764	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2765	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2766
2767	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2768	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2769	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2770	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2771	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2772	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2773	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2774	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2775	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2776	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2777	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2778	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2779	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2780	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2781	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2782	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2783	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2784	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2785	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2786	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2787	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2788	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2789	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2790	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2791	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2792	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2793	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2794	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2795
2796	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2797	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2798	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2799	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2800	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2801	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2802	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2803	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2804	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2805	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2806	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2807	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2808	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2809	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2810	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2811	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2812	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2813	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2814	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2815	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2816	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2817	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2818	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2819	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2820	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2821	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2822	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2823	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2824	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2825
2826	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2827	/** @} */
2828
2829
2830	/**
2831	* Function pointers for guest paging.
2832	*/
2833	typedef struct PGMMODEDATAGST
2834	{
2835	/** The guest mode type. */
2836	uint32_t uType;
2837	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2838	DECLCALLBACKMEMBER(int, pfnQueryPageFast,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags, PPGMPTWALKFAST pWalk));
2839	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2840	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2841	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2842	#ifdef IN_RING3
2843	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2844	#endif
2845	} PGMMODEDATAGST;
2846
2847	/** The length of g_aPgmGuestModeData. */
2848	#if VBOX_WITH_64_BITS_GUESTS
2849	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2850	#else
2851	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2852	#endif
2853	/** The guest mode data array. */
2854	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2855
2856
2857	/**
2858	* Function pointers for shadow paging.
2859	*/
2860	typedef struct PGMMODEDATASHW
2861	{
2862	/** The shadow mode type. */
2863	uint32_t uType;
2864	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2865	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2866	uint64_t fMask, uint32_t fOpFlags));
2867	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2868	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2869	#ifdef IN_RING3
2870	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2871	#endif
2872	} PGMMODEDATASHW;
2873
2874	/** The length of g_aPgmShadowModeData. */
2875	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2876	/** The shadow mode data array. */
2877	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2878
2879
2880	/**
2881	* Function pointers for guest+shadow paging.
2882	*/
2883	typedef struct PGMMODEDATABTH
2884	{
2885	/** The shadow mode type. */
2886	uint32_t uShwType;
2887	/** The guest mode type. */
2888	uint32_t uGstType;
2889
2890	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2891	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2892	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2893	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2894	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2895	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2896	#ifndef IN_RING3
2897	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2898	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2899	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2900	bool *pfLockTaken));
2901	#endif
2902	#ifdef VBOX_STRICT
2903	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2904	#endif
2905	} PGMMODEDATABTH;
2906
2907	/** The length of g_aPgmBothModeData. */
2908	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2909	/** The guest+shadow mode data array. */
2910	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2911
2912
2913	#ifdef VBOX_WITH_STATISTICS
2914	/**
2915	* PGM statistics.
2916	*/
2917	typedef struct PGMSTATS
2918	{
2919	/* R3 only: */
2920	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2921	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2922
2923	/* R3+RZ */
2924	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2925	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2926	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2927	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2928	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2929	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2930	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2931	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2932	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2933	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2934	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2935	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2936	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2937	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2938	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2939	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2940	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2941	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2942	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2943	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2944	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2945	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2946	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2947	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2948	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2949	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2950
2951	/* RC only: */
2952	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2953	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2954
2955	STAMCOUNTER StatRZPhysRead;
2956	STAMCOUNTER StatRZPhysReadBytes;
2957	STAMCOUNTER StatRZPhysWrite;
2958	STAMCOUNTER StatRZPhysWriteBytes;
2959	STAMCOUNTER StatR3PhysRead;
2960	STAMCOUNTER StatR3PhysReadBytes;
2961	STAMCOUNTER StatR3PhysWrite;
2962	STAMCOUNTER StatR3PhysWriteBytes;
2963	STAMCOUNTER StatRCPhysRead;
2964	STAMCOUNTER StatRCPhysReadBytes;
2965	STAMCOUNTER StatRCPhysWrite;
2966	STAMCOUNTER StatRCPhysWriteBytes;
2967
2968	STAMCOUNTER StatRZPhysSimpleRead;
2969	STAMCOUNTER StatRZPhysSimpleReadBytes;
2970	STAMCOUNTER StatRZPhysSimpleWrite;
2971	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2972	STAMCOUNTER StatR3PhysSimpleRead;
2973	STAMCOUNTER StatR3PhysSimpleReadBytes;
2974	STAMCOUNTER StatR3PhysSimpleWrite;
2975	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2976	STAMCOUNTER StatRCPhysSimpleRead;
2977	STAMCOUNTER StatRCPhysSimpleReadBytes;
2978	STAMCOUNTER StatRCPhysSimpleWrite;
2979	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2980
2981	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2982	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2983	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2984	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2985	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2986	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2987	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2988
2989	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2990	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2991	/** pgmPhysIsValidLargePage profiling - R3 */
2992	STAMPROFILE StatR3IsValidLargePage;
2993	/** pgmPhysIsValidLargePage profiling - RZ*/
2994	STAMPROFILE StatRZIsValidLargePage;
2995
2996	STAMPROFILE StatChunkAging;
2997	STAMPROFILE StatChunkFindCandidate;
2998	STAMPROFILE StatChunkUnmap;
2999	STAMPROFILE StatChunkMap;
3000	} PGMSTATS;
3001	#endif /* VBOX_WITH_STATISTICS */
3002
3003
3004	/**
3005	* PGM Data (part of VM)
3006	*/
3007	typedef struct PGM
3008	{
3009	/** The zero page. */
3010	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
3011	/** The MMIO placeholder page. */
3012	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
3013
3014	/** @name RAM, MMIO2 and ROM ranges
3015	* @{ */
3016	/** The RAM range lookup table. */
3017	PGMRAMRANGELOOKUPENTRY aRamRangeLookup[PGM_MAX_RAM_RANGES];
3018	/** The ring-3 RAM range pointer table. */
3019	R3PTRTYPE(PPGMRAMRANGE) apRamRanges[PGM_MAX_RAM_RANGES];
3020	/** MMIO2 ranges. Indexed by idMmio2 minus 1. */
3021	PGMREGMMIO2RANGE aMmio2Ranges[PGM_MAX_MMIO2_RANGES];
3022	/** The ring-3 RAM range pointer table running parallel to aMmio2Ranges. */
3023	R3PTRTYPE(PPGMRAMRANGE) apMmio2RamRanges[PGM_MAX_MMIO2_RANGES];
3024	/** The ring-3 ROM range pointer table. */
3025	R3PTRTYPE(PPGMROMRANGE) apRomRanges[PGM_MAX_ROM_RANGES];
3026	/** Union of generation ID and lookup count. */
3027	union PGMRAMRANGEGENANDLOOKUPCOUNT
3028	{
3029	/* Combined view of both the generation ID and the count for atomic updating/reading. */
3030	uint64_t volatile u64Combined;
3031	RT_GCC_EXTENSION struct
3032	{
3033	/** Generation ID for the RAM ranges.
3034	* This member is incremented twice everytime a RAM range is mapped or
3035	* unmapped, so odd numbers means aRamRangeLookup is being modified and even
3036	* means the update has completed. */
3037	uint32_t volatile idGeneration;
3038	/** The number of active entries in aRamRangeLookup. */
3039	uint32_t volatile cLookupEntries;
3040	};
3041	} RamRangeUnion;
3042	/** The max RAM range ID (mirroring PGMR0PERVM::idRamRangeMax). */
3043	uint32_t idRamRangeMax;
3044	/** The number of MMIO2 ranges (serves as the next MMIO2 ID). */
3045	uint8_t cMmio2Ranges;
3046	/** The number of ROM ranges. */
3047	uint8_t cRomRanges;
3048	uint8_t abAlignment1[2];
3049	/** @} */
3050
3051	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3052	/** @name The zero page (abPagePg).
3053	* @{ */
3054	/** The host physical address of the zero page. */
3055	RTHCPHYS HCPhysZeroPg;
3056	/** @}*/
3057
3058	/** @name The Invalid MMIO page (abMmioPg).
3059	* This page is filled with 0xfeedface.
3060	* @{ */
3061	/** The host physical address of the invalid MMIO page. */
3062	RTHCPHYS HCPhysMmioPg;
3063	/** The host pysical address of the invalid MMIO page plus all invalid
3064	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3065	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3066	RTHCPHYS HCPhysInvMmioPg;
3067	/** @} */
3068	#endif
3069
3070	/** @cfgm{/RamPreAlloc, boolean, false}
3071	* Indicates whether the base RAM should all be allocated before starting
3072	* the VM (default), or if it should be allocated when first written to.
3073	* This has no effect in NEM-mode.
3074	*/
3075	bool fRamPreAlloc;
3076	#ifndef VBOX_WITH_PGM_NEM_MODE
3077	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
3078	#elif defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
3079	# define PGM_IS_IN_NEM_MODE(a_pVM) (true)
3080	#else
3081	/** Set if we're operating in NEM memory mode.
3082	*
3083	* NEM mode implies that memory is allocated in big chunks for each RAM range
3084	* rather than on demand page by page. Memory is also not locked and PGM has
3085	* therefore no physical addresses for them. Page sharing is out of the
3086	* question. Ballooning depends on the native execution engine, but probably
3087	* pointless as well. */
3088	bool fNemMode;
3089	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
3090	#endif
3091	/** Indicates whether write monitoring is currently in use.
3092	* This is used to prevent conflicts between live saving and page sharing
3093	* detection. */
3094	bool fPhysWriteMonitoringEngaged;
3095	/** Set if the CPU has less than 52-bit physical address width.
3096	* This is used */
3097	bool fLessThan52PhysicalAddressBits;
3098	/** Set when nested paging is active.
3099	* This is meant to save calls to HMIsNestedPagingActive and let the
3100	* compilers optimize the code better. Whether we use nested paging or
3101	* not is something we find out during VMM initialization and we won't
3102	* change this later on. */
3103	bool fNestedPaging;
3104	/** We're not in a state which permits writes to guest memory.
3105	* (Only used in strict builds.) */
3106	bool fNoMorePhysWrites;
3107	/** @cfgm{/PageFusionAllowed, boolean, false}
3108	* Whether page fusion is allowed. */
3109	bool fPageFusionAllowed;
3110	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3111	* Whether PCI passthrough is enabled. */
3112	bool fPciPassthrough;
3113	/** Restore original ROM page content when resetting after loading state.
3114	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3115	* enables the VM to start using an updated ROM without requiring powering
3116	* down the VM, just rebooting or resetting it. */
3117	bool fRestoreRomPagesOnReset;
3118	/** Whether to automatically clear all RAM pages on reset. */
3119	bool fZeroRamPagesOnReset;
3120	/** Large page enabled flag. */
3121	bool fUseLargePages;
3122	/** Alignment padding. */
3123	#if !defined(VBOX_WITH_PGM_NEM_MODE) \|\| defined(VBOX_WITH_ONLY_PGM_NEM_MODE)
3124	bool afAlignment2[2];
3125	#else
3126	bool afAlignment2[1];
3127	#endif
3128	/** The host paging mode. (This is what SUPLib reports.) */
3129	SUPPAGINGMODE enmHostMode;
3130
3131	/** Physical access handler type for ROM protection. */
3132	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3133	/** Physical access handler type for MMIO2 dirty page tracing. */
3134	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3135
3136	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3137	RTGCPHYS GCPhys4MBPSEMask;
3138	/** Mask containing the invalid bits of a guest physical address.
3139	* @remarks this does not stop at bit 52. */
3140	RTGCPHYS GCPhysInvAddrMask;
3141
3142
3143	/** RAM range TLB for R3. */
3144	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3145	/** Shadow Page Pool - R3 Ptr. */
3146	R3PTRTYPE(PPGMPOOL) pPoolR3;
3147
3148	/** Shadow Page Pool - R0 Ptr. */
3149	R0PTRTYPE(PPGMPOOL) pPoolR0;
3150
3151	/** Hack: Number of deprecated page mapping locks taken by the current lock
3152	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3153	uint32_t cDeprecatedPageLocks;
3154
3155	/** Registered physical access handler types. */
3156	uint32_t cPhysHandlerTypes;
3157	/** Physical access handler types.
3158	* Initialized to callback causing guru meditations and invalid enmKind. */
3159	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3160	/** Physical handler allocator, ring-3 edition. */
3161	#ifdef IN_RING3
3162	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3163	#else
3164	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3165	#endif
3166	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3167	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3168	/** Caching the last physical handler we looked. */
3169	uint32_t idxLastPhysHandler;
3170
3171	uint32_t au32Padding3[9];
3172	#ifdef VBOX_WITH_ONLY_PGM_NEM_MODE
3173	uint64_t au64Padding4[3];
3174	#endif
3175
3176	/** PGM critical section.
3177	* This protects the physical, ram ranges, and the page flag updating (some of
3178	* it anyway).
3179	*/
3180	PDMCRITSECT CritSectX;
3181
3182	/**
3183	* Data associated with managing the ring-3 mappings of the allocation chunks.
3184	*/
3185	struct
3186	{
3187	/** The chunk mapping TLB. */
3188	PGMCHUNKR3MAPTLB Tlb;
3189	/** The chunk tree, ordered by chunk id. */
3190	R3PTRTYPE(PAVLU32NODECORE) pTree;
3191	#if HC_ARCH_BITS == 32
3192	uint32_t u32Alignment0;
3193	#endif
3194	/** The number of mapped chunks. */
3195	uint32_t c;
3196	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3197	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3198	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3199	uint32_t cMax;
3200	/** The current time. This is incremented whenever a chunk is inserted. */
3201	uint32_t iNow;
3202	/** Alignment padding. */
3203	uint32_t au32Alignment1[3];
3204	} ChunkR3Map;
3205
3206	/** The page mapping TLB for ring-3. */
3207	PGMPAGER3MAPTLB PhysTlbR3;
3208	/** The page mapping TLB for ring-0. */
3209	PGMPAGER0MAPTLB PhysTlbR0;
3210
3211	/** The number of handy pages. */
3212	uint32_t cHandyPages;
3213
3214	/** The number of large handy pages. */
3215	uint32_t cLargeHandyPages;
3216
3217	/**
3218	* Array of handy pages.
3219	*
3220	* This array is used in a two way communication between pgmPhysAllocPage
3221	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3222	* an intermediary.
3223	*
3224	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3225	* (The current size of 32 pages, means 128 KB of handy memory.)
3226	*/
3227	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3228
3229	/**
3230	* Array of large handy pages. (currently size 1)
3231	*
3232	* This array is used in a two way communication between pgmPhysAllocLargePage
3233	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3234	* an intermediary.
3235	*/
3236	GMMPAGEDESC aLargeHandyPage[1];
3237	/** When to try allocate large pages again after a failure. */
3238	uint64_t nsLargePageRetry;
3239	/** Number of repeated long allocation times. */
3240	uint32_t cLargePageLongAllocRepeats;
3241	uint32_t uPadding4;
3242
3243	/**
3244	* Live save data.
3245	*/
3246	struct
3247	{
3248	/** Per type statistics. */
3249	struct
3250	{
3251	/** The number of ready pages. */
3252	uint32_t cReadyPages;
3253	/** The number of dirty pages. */
3254	uint32_t cDirtyPages;
3255	/** The number of ready zero pages. */
3256	uint32_t cZeroPages;
3257	/** The number of write monitored pages. */
3258	uint32_t cMonitoredPages;
3259	} Rom,
3260	Mmio2,
3261	Ram;
3262	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3263	uint32_t cIgnoredPages;
3264	/** Indicates that a live save operation is active. */
3265	bool fActive;
3266	/** Padding. */
3267	bool afReserved[2];
3268	/** The next history index. */
3269	uint8_t iDirtyPagesHistory;
3270	/** History of the total amount of dirty pages. */
3271	uint32_t acDirtyPagesHistory[64];
3272	/** Short term dirty page average. */
3273	uint32_t cDirtyPagesShort;
3274	/** Long term dirty page average. */
3275	uint32_t cDirtyPagesLong;
3276	/** The number of saved pages. This is used to get some kind of estimate of the
3277	* link speed so we can decide when we're done. It is reset after the first
3278	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3279	* zero pages. */
3280	uint64_t cSavedPages;
3281	/** The nanosecond timestamp when cSavedPages was 0. */
3282	uint64_t uSaveStartNS;
3283	/** Pages per second (for statistics). */
3284	uint32_t cPagesPerSecond;
3285	uint32_t cAlignment;
3286	} LiveSave;
3287
3288	/** @name Error injection.
3289	* @{ */
3290	/** Inject handy page allocation errors pretending we're completely out of
3291	* memory. */
3292	bool volatile fErrInjHandyPages;
3293	/** Padding. */
3294	bool afReserved[3];
3295	/** @} */
3296
3297	/** @name Release Statistics
3298	* @{ */
3299	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3300	uint32_t cPrivatePages; /*< The number of private pages. /
3301	uint32_t cSharedPages; /*< The number of shared pages. /
3302	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3303	uint32_t cZeroPages; /*< The number of zero backed pages. /
3304	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3305	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3306	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3307	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3308	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3309	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3310	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3311	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3312	uint32_t cLargePages; /*< The number of large pages. /
3313	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3314	/* uint32_t aAlignment4[1]; */
3315
3316	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3317	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3318	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3319	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3320	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3321	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3322	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3323	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3324
3325	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3326
3327	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3328	/** @} */
3329
3330	#ifdef VBOX_WITH_STATISTICS
3331	/** These are optional statistics that used to be on the hyper heap. */
3332	PGMSTATS Stats;
3333	#endif
3334	} PGM;
3335	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3336	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3337	AssertCompileMemberAlignment(PGM, CritSectX, 16);
3338	AssertCompileMemberAlignment(PGM, CritSectX, 32);
3339	AssertCompileMemberAlignment(PGM, CritSectX, 64);
3340	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3341	AssertCompileMemberAlignment(PGM, PhysTlbR3, 8);
3342	AssertCompileMemberAlignment(PGM, PhysTlbR3, 16);
3343	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32);
3344	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3345	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3346	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3347	# endif
3348	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3349	#endif /* !IN_TSTVMSTRUCTGC */
3350	/** Pointer to the PGM instance data. */
3351	typedef PGM *PPGM;
3352
3353
3354	#ifdef VBOX_WITH_STATISTICS
3355	/**
3356	* Per CPU statistis for PGM (used to be on the heap).
3357	*/
3358	typedef struct PGMCPUSTATS
3359	{
3360	/* Common */
3361	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3362	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3363
3364	/* R0 only: */
3365	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3366	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3367
3368	/* RZ only: */
3369	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3370	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3371	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3372	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3373	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3374	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3375	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3376	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3377	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3378	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3379	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3380	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3381	STAMPROFILE StatRZTrap0eTime2PageZeroing; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a zero page that is being zeroed. /
3382	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3383	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3384	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3385	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3386	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3387	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3388	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3389	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3390	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3391	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3392	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3393	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3394	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3395	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3396	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3397	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3398	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3399	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3400	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3401	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3402	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3403	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3404	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3405	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3406	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3407	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3408	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3409	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3410	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3411	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3412	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3413	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3414	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3415	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3416	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3417	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3418	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3419	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3420	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3421	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3422	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3423	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3424	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3425	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3426	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3427	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3428	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3429	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3430	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3431	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3432	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3433	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3434	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3435	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3436	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3437	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3438	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3439
3440	/* HC - R3 and (maybe) R0: */
3441
3442	/* RZ & R3: */
3443	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3444	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3445	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3446	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3447	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3448	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3449	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3450	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3451	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3452	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3453	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3454	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3455	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3456	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3457	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3458	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3459	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3460	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3461	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3462	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3463	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3464	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3465	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3466	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3467	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3468	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3469	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3470	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3471	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3472	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3473	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3474	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3475	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3476	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3477	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3478	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3479	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3480	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3481	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3482	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3483	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3484	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3485	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3486	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3487	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3488	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3489	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3490	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits (lockless). /
3491	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Page mapper TLB hits (lockless). /
3492
3493	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3494	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3495	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3496	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3497	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3498	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3499	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3500	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3501	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3502	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3503	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3504	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3505	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3506	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3507	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3508	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3509	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3510	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3511	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3512	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3513	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3514	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3515	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3516	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3517	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3518	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3519	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3520	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3521	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3522	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3523	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3524	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3525	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3526	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3527	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3528	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3529	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3530	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3531	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3532	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3533	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3534	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3535	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3536	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3537	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3538	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3539	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits (lockless). /
3540	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Page mapper TLB hits (lockless). /
3541	} PGMCPUSTATS;
3542	#endif /* VBOX_WITH_STATISTICS */
3543
3544
3545	/**
3546	* PGMCPU Data (part of VMCPU).
3547	*/
3548	typedef struct PGMCPU
3549	{
3550	/** A20 gate mask.
3551	* Our current approach to A20 emulation is to let REM do it and don't bother
3552	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3553	* But whould need arrise, we'll subject physical addresses to this mask. */
3554	RTGCPHYS GCPhysA20Mask;
3555	/** A20 gate state - boolean! */
3556	bool fA20Enabled;
3557	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3558	bool fNoExecuteEnabled;
3559	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3560	* active. */
3561	bool fPaePdpesAndCr3MappedR3;
3562	bool fPaePdpesAndCr3MappedR0;
3563
3564	/** What needs syncing (PGM_SYNC_*).
3565	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3566	* PGMFlushTLB, and PGMR3Load. */
3567	uint32_t fSyncFlags;
3568
3569	/** The shadow paging mode. */
3570	PGMMODE enmShadowMode;
3571	/** The guest paging mode. */
3572	PGMMODE enmGuestMode;
3573	/** The guest second level address translation mode. */
3574	PGMSLAT enmGuestSlatMode;
3575	/** Guest mode data table index (PGM_TYPE_XXX). */
3576	uint8_t volatile idxGuestModeData;
3577	/** Shadow mode data table index (PGM_TYPE_XXX). */
3578	uint8_t volatile idxShadowModeData;
3579	/** Both mode data table index (complicated). */
3580	uint8_t volatile idxBothModeData;
3581	/** Alignment padding. */
3582	uint8_t abPadding[1];
3583
3584	/** The guest CR3.
3585	* When SLAT is active, this is the translated physical address.
3586	* When SLAT is inactive, this is the physical address in CR3. */
3587	RTGCPHYS GCPhysCR3;
3588
3589	/** The nested-guest CR3.
3590	* When SLAT is active, this is CR3 prior to translation.
3591	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3592	RTGCPHYS GCPhysNstGstCR3;
3593
3594	/** The cached guest CR3 when it has been mapped in PAE mode.
3595	* This allows us to skip remapping the CR3 and PAE PDPEs
3596	* (in PGMFlushTLB or similar) when it was already done as
3597	* part of MOV CRx instruction emulation.
3598	*/
3599	RTGCPHYS GCPhysPaeCR3;
3600
3601	/** @name 32-bit Guest Paging.
3602	* @{ */
3603	/** The guest's page directory, R3 pointer. */
3604	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3605	/** The guest's page directory, R0 pointer. */
3606	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3607	/** Mask containing the MBZ bits of a big page PDE. */
3608	uint32_t fGst32BitMbzBigPdeMask;
3609	/** Set if the page size extension (PSE) is enabled. */
3610	bool fGst32BitPageSizeExtension;
3611	/** Alignment padding. */
3612	bool afAlignment2[3];
3613	/** @} */
3614
3615	/** @name PAE Guest Paging.
3616	* @{ */
3617	/** The guest's page directory pointer table, R3 pointer. */
3618	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3619	/** The guest's page directory pointer table, R0 pointer. */
3620	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3621
3622	/** The guest's page directories, R3 pointers.
3623	* These are individual pointers and don't have to be adjacent.
3624	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3625	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3626	/** The guest's page directories, R0 pointers.
3627	* Same restrictions as apGstPaePDsR3. */
3628	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3629	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3630	RTGCPHYS aGCPhysGstPaePDs[4];
3631	/** Mask containing the MBZ PTE bits. */
3632	uint64_t fGstPaeMbzPteMask;
3633	/** Mask containing the MBZ PDE bits. */
3634	uint64_t fGstPaeMbzPdeMask;
3635	/** Mask containing the MBZ big page PDE bits. */
3636	uint64_t fGstPaeMbzBigPdeMask;
3637	/** Mask containing the MBZ PDPE bits. */
3638	uint64_t fGstPaeMbzPdpeMask;
3639	/** @} */
3640
3641	/** @name AMD64 Guest Paging.
3642	* @{ */
3643	/** The guest's page directory pointer table, R3 pointer. */
3644	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3645	/** The guest's page directory pointer table, R0 pointer. */
3646	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3647	/** Mask containing the MBZ PTE bits. */
3648	uint64_t fGstAmd64MbzPteMask;
3649	/** Mask containing the MBZ PDE bits. */
3650	uint64_t fGstAmd64MbzPdeMask;
3651	/** Mask containing the MBZ big page PDE bits. */
3652	uint64_t fGstAmd64MbzBigPdeMask;
3653	/** Mask containing the MBZ PDPE bits. */
3654	uint64_t fGstAmd64MbzPdpeMask;
3655	/** Mask containing the MBZ big page PDPE bits. */
3656	uint64_t fGstAmd64MbzBigPdpeMask;
3657	/** Mask containing the MBZ PML4E bits. */
3658	uint64_t fGstAmd64MbzPml4eMask;
3659	/** Mask containing the PDPE bits that we shadow. */
3660	uint64_t fGstAmd64ShadowedPdpeMask;
3661	/** Mask containing the PML4E bits that we shadow. */
3662	uint64_t fGstAmd64ShadowedPml4eMask;
3663	/** @} */
3664
3665	/** @name PAE and AMD64 Guest Paging.
3666	* @{ */
3667	/** Mask containing the PTE bits that we shadow. */
3668	uint64_t fGst64ShadowedPteMask;
3669	/** Mask containing the PDE bits that we shadow. */
3670	uint64_t fGst64ShadowedPdeMask;
3671	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3672	uint64_t fGst64ShadowedBigPdeMask;
3673	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3674	uint64_t fGst64ShadowedBigPde4PteMask;
3675	/** @} */
3676
3677	/** @name EPT Guest Paging.
3678	* @{ */
3679	/** The guest's EPT PML4 table, R3 pointer. */
3680	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3681	/** The guest's EPT PML4 table, R0 pointer. */
3682	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3683	/** The guest's EPT pointer (copy of virtual VMCS). */
3684	uint64_t uEptPtr;
3685	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3686	* change through the lifetime of the VM. */
3687	uint64_t uEptVpidCapMsr;
3688	/** Mask containing the MBZ PTE bits. */
3689	uint64_t fGstEptMbzPteMask;
3690	/** Mask containing the MBZ PDE bits. */
3691	uint64_t fGstEptMbzPdeMask;
3692	/** Mask containing the MBZ big page (2M) PDE bits. */
3693	uint64_t fGstEptMbzBigPdeMask;
3694	/** Mask containing the MBZ PDPTE bits. */
3695	uint64_t fGstEptMbzPdpteMask;
3696	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3697	uint64_t fGstEptMbzBigPdpteMask;
3698	/** Mask containing the MBZ PML4E bits. */
3699	uint64_t fGstEptMbzPml4eMask;
3700	/** Mask to determine whether an entry is present. */
3701	uint64_t fGstEptPresentMask;
3702
3703	/** Mask containing the EPT PTE bits we shadow. */
3704	uint64_t fGstEptShadowedPteMask;
3705	/** Mask containing the EPT PDE bits we shadow. */
3706	uint64_t fGstEptShadowedPdeMask;
3707	/** Mask containing the EPT PDE (2M) bits we shadow. */
3708	uint64_t fGstEptShadowedBigPdeMask;
3709	/** Mask containing the EPT PDPTE bits we shadow. */
3710	uint64_t fGstEptShadowedPdpteMask;
3711	/** Mask containing the EPT PML4E bits we shadow. */
3712	uint64_t fGstEptShadowedPml4eMask;
3713	/** @} */
3714
3715	#ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3716	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3717	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3718	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3719	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3720	#endif
3721
3722	/** For saving stack space, the disassembler state is allocated here instead of
3723	* on the stack. */
3724	DISSTATE Dis;
3725
3726	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3727	uint64_t cNetwareWp0Hacks;
3728
3729	/** Count the number of pgm pool access handler calls. */
3730	uint64_t cPoolAccessHandler;
3731
3732	/** Lockless RAM range TLB for R3. */
3733	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3734
3735	/** Lockless page mapping TLB for R3. */
3736	PGMPAGER3MAPTLB PhysTlb;
3737
3738	/** @name Release Statistics
3739	* @{ */
3740	/** The number of times the guest has switched mode since last reset or statistics reset. */
3741	STAMCOUNTER cGuestModeChanges;
3742	/** The number of times the guest has switched mode since last reset or statistics reset. */
3743	STAMCOUNTER cA20Changes;
3744
3745	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses (lockless). /
3746	STAMCOUNTER StatRZRamRangeTlbLocking; /*< RC/R0: RAM range TLB lookup redone with locking. /
3747	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Page mapper TLB misses (lockless -> locked). /
3748
3749	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses (lockless). /
3750	STAMCOUNTER StatR3RamRangeTlbLocking; /*< R3: RAM range TLB lookup redone with locking. /
3751	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Page mapper TLB misses (lockless -> locked). /
3752	/** @} */
3753
3754	#ifdef VBOX_WITH_STATISTICS
3755	/** These are statistics that used to be on the hyper heap. */
3756	PGMCPUSTATS Stats;
3757	#endif
3758	} PGMCPU;
3759	/** Pointer to the per-cpu PGM data. */
3760	typedef PGMCPU *PPGMCPU;
3761
3762
3763	/** @name PGM::fSyncFlags Flags
3764	* @note Was part of saved state a long time ago.
3765	* @{
3766	*/
3767	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3768	/** Always sync CR3. */
3769	#define PGM_SYNC_ALWAYS RT_BIT(1)
3770	/** Check guest mapping in SyncCR3. */
3771	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3772	/** Clear the page pool (a light weight flush). */
3773	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3774	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3775	/** @} */
3776
3777
3778	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3779
3780	/**
3781	* PGM GVMCPU instance data.
3782	*/
3783	typedef struct PGMR0PERVCPU
3784	{
3785	/** Lockless RAM range TLB for R0. */
3786	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3787
3788	# ifdef VBOX_WITH_STATISTICS
3789	/** R0: Which statistic this \#PF should be attributed to. */
3790	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3791	# endif
3792	} PGMR0PERVCPU;
3793
3794
3795	/**
3796	* PGM GVM instance data.
3797	*/
3798	typedef struct PGMR0PERVM
3799	{
3800	/** @name RAM ranges
3801	* @{ */
3802	/** The ring-0 RAM range pointer table. */
3803	R0PTRTYPE(PPGMRAMRANGE) apRamRanges[PGM_MAX_RAM_RANGES];
3804	/** Trusted RAM range page counts running parallel to apRamRanges.
3805	* This keeps the original page count when a range is reduced,
3806	* only the PGMRAMRANGE::cb member is changed then. */
3807	uint32_t acRamRangePages[PGM_MAX_RAM_RANGES];
3808	/** The memory objects for the RAM ranges (parallel to apRamRanges). */
3809	RTR0MEMOBJ ahRamRangeMemObjs[PGM_MAX_RAM_RANGES];
3810	/** The ring-3 mapping objects for the RAM ranges (parallel to apRamRanges). */
3811	RTR0MEMOBJ ahRamRangeMapObjs[PGM_MAX_RAM_RANGES];
3812	/** The max RAM range ID (safe). */
3813	uint32_t idRamRangeMax;
3814	uint8_t abAlignment1[64 - sizeof(uint32_t)];
3815	/** RAM range TLB for R0. */
3816	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlb[PGM_RAMRANGE_TLB_ENTRIES];
3817	/** @} */
3818
3819	/** @name MMIO2 ranges
3820	* @{ */
3821	/** The ring-0 RAM range pointer table running parallel to aMmio2Ranges. */
3822	R0PTRTYPE(PPGMRAMRANGE) apMmio2RamRanges[PGM_MAX_MMIO2_RANGES];
3823	/** The memory objects for the MMIO2 backing memory (parallel to
3824	* apMmio2RamRanges). */
3825	RTR0MEMOBJ ahMmio2MemObjs[PGM_MAX_MMIO2_RANGES];
3826	/** The ring-3 mapping objects for the MMIO2 backing memory (parallel
3827	* to apMmio2RamRanges & ahMmio2MemObjs). */
3828	RTR0MEMOBJ ahMmio2MapObjs[PGM_MAX_MMIO2_RANGES];
3829	/** Trusted MMIO2 range sizes (count of guest pages).
3830	* This keeps the original page count when a range is reduced,
3831	* only the PGMRAMRANGE::cb member is changed then. */
3832	uint32_t acMmio2RangePages[PGM_MAX_MMIO2_RANGES];
3833	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
3834	/** Pointer to the ring-0 mapping of the MMIO2 backings (parallel to
3835	* apMmio2RamRanges). */
3836	R0PTRTYPE(uint8_t *) apbMmio2Backing[PGM_MAX_MMIO2_RANGES];
3837	#endif
3838	/** @} */
3839
3840	/** @name ROM ranges
3841	* @{ */
3842	/** The ring-0 ROM range pointer table. */
3843	R0PTRTYPE(PPGMROMRANGE) apRomRanges[PGM_MAX_ROM_RANGES];
3844	/** The memory objects for each ROM range (parallel to apRomRanges). */
3845	RTR0MEMOBJ ahRomRangeMemObjs[PGM_MAX_ROM_RANGES];
3846	/** The ring-3 mapping objects for each ROM range (parallel to apRomRanges
3847	* & ahRamRangeMemObjs). */
3848	RTR0MEMOBJ ahRomRangeMapObjs[PGM_MAX_ROM_RANGES];
3849	/** Trusted ROM range sizes (count of guest pages). */
3850	uint32_t acRomRangePages[PGM_MAX_ROM_RANGES];
3851	/** @} */
3852
3853	/** @name PGM Pool related stuff.
3854	* @{ */
3855	/** Critical section for serializing pool growth. */
3856	RTCRITSECT PoolGrowCritSect;
3857	/** The memory objects for the pool pages. */
3858	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3859	/** The ring-3 mapping objects for the pool pages. */
3860	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3861	/** @} */
3862
3863	/** Physical access handler types for ring-0.
3864	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3865	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3866	/** Physical handler allocator, ring-3 edition. */
3867	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3868	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3869	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3870	/** The allocation object for the physical access handler tree. */
3871	RTR0MEMOBJ hPhysHandlerMemObj;
3872	/** The ring-3 mapping object for the physicall access handler tree. */
3873	RTR0MEMOBJ hPhysHandlerMapObj;
3874	} PGMR0PERVM;
3875
3876	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3877
3878	RT_C_DECLS_BEGIN
3879
3880	#if defined(VBOX_STRICT)
3881	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3882	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3883	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3884	#else
3885	int pgmLock(PVMCC pVM, bool fVoid);
3886	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3887	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3888	#endif
3889	void pgmUnlock(PVMCC pVM);
3890	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3891	/**
3892	* Asserts that the caller owns the PDM lock.
3893	* This is the internal variant of PGMIsLockOwner.
3894	* @param a_pVM Pointer to the VM.
3895	*/
3896	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3897	/**
3898	* Asserts that the caller owns the PDM lock.
3899	* This is the internal variant of PGMIsLockOwner.
3900	* @param a_pVM Pointer to the VM.
3901	* @param a_pVCpu The current CPU handle.
3902	*/
3903	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3904
3905	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3906	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3907	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3908	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3909	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3910	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3911	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3912	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3913	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3914	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam,
3915	bool fDoAccounting, bool fFlushIemTlbs);
3916	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3917	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3918	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3919	#ifndef IN_RING3
3920	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3921	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3922	#endif
3923
3924	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3925
3926	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3927	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3928	#ifdef IN_RING0
3929	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3930	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3931	#endif
3932	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3933	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3934	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3935	#ifdef IN_RING3
3936	DECLHIDDEN(int) pgmPhysPageLoadIntoLocklessTlbWithPage(PVMCPUCC pVCpu, PPGMPAGE pPage, RTGCPHYS GCPhys);
3937	#endif
3938	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3939	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3940	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3941	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3942	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3943	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3944	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3945	int pgmPhysGCPhys2CCPtrLockless(PVMCPUCC pVCpu, RTGCPHYS GCPhys, void **ppv);
3946	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3947	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3948	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3949	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3950	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3951	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3952	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3953	#ifndef IN_RING3
3954	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3955	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3956	#endif
3957	DECLHIDDEN(uint16_t) pgmPhysMmio2CalcChunkCount(RTGCPHYS cb, uint32_t *pcPagesPerChunk);
3958	DECLHIDDEN(int) pgmPhysMmio2RegisterWorker(PVMCC pVM, uint32_t const cGuestPages, uint8_t const idMmio2,
3959	const uint8_t cChunks, PPDMDEVINSR3 const pDevIns, uint8_t
3960	const iSubDev, uint8_t const iRegion, uint32_t const fFlags);
3961	DECLHIDDEN(int) pgmPhysMmio2DeregisterWorker(PVMCC pVM, uint8_t idMmio2, uint8_t cChunks, PPDMDEVINSR3 pDevIns);
3962	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3963	PGMPAGETYPE enmNewType);
3964	#ifdef VBOX_STRICT
3965	DECLHIDDEN(bool) pgmPhysAssertRamRangesLocked(PVMCC pVM, bool fInUpdate, bool fRamRelaxed);
3966	#endif
3967	DECLHIDDEN(void) pgmR3PhysChunkInvalidateTLB(PVM pVM, bool fInRendezvous);
3968	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3969	void pgmPhysInvalidatePageMapTLB(PVMCC pVM, bool fInRendezvous);
3970	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3971	DECLHIDDEN(PPGMRAMRANGE) pgmPhysGetRangeSlow(PVMCC pVM, RTGCPHYS GCPhys);
3972	DECLHIDDEN(PPGMRAMRANGE) pgmPhysGetRangeAtOrAboveSlow(PVMCC pVM, RTGCPHYS GCPhys);
3973	DECLHIDDEN(PPGMPAGE) pgmPhysGetPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3974	DECLHIDDEN(int) pgmPhysGetPageExSlow(PVMCC pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3975	DECLHIDDEN(int) pgmPhysGetPageAndRangeExSlow(PVMCC pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3976	DECLHIDDEN(int) pgmPhysGetPageAndRangeExSlowLockless(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
3977	PGMPAGE volatile ppPage, PGMRAMRANGE volatile ppRam);
3978	DECLHIDDEN(int) pgmPhysRamRangeAllocCommon(PVMCC pVM, uint32_t cPages, uint32_t fFlags, uint32_t *pidNewRange);
3979	DECLHIDDEN(int) pgmPhysRomRangeAllocCommon(PVMCC pVM, uint32_t cPages, uint8_t idRomRange, uint32_t fFlags);
3980	#ifdef VBOX_WITH_NATIVE_NEM
3981	DECLHIDDEN(void) pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3982	#endif
3983
3984	#ifdef IN_RING3
3985	# ifndef VBOX_WITH_ONLY_PGM_NEM_MODE
3986	int pgmR3PhysRamPreAllocate(PVM pVM);
3987	# endif
3988	int pgmR3PhysRamReset(PVM pVM);
3989	int pgmR3PhysRomReset(PVM pVM);
3990	int pgmR3PhysRamZeroAll(PVM pVM);
3991	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3992	int pgmR3PhysRamTerm(PVM pVM);
3993	void pgmR3PhysRomTerm(PVM pVM);
3994	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3995
3996	int pgmR3PoolInit(PVM pVM);
3997	void pgmR3PoolRelocate(PVM pVM);
3998	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3999	void pgmR3PoolReset(PVM pVM);
4000	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4001	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4002	void pgmR3PoolWriteProtectPages(PVM pVM);
4003
4004	#endif /* IN_RING3 */
4005	#ifdef IN_RING0
4006	int pgmR0PoolInitVM(PGVM pGVM);
4007	#endif
4008	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4009	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4010	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4011	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4012	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4013	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4014	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4015	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4016	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
4017	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
4018	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
4019	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
4020	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4021	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4022	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4023	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4024	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4025	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4026	FNPGMPHYSHANDLER pgmPoolAccessHandler;
4027	#ifndef IN_RING3
4028	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
4029	#endif
4030
4031	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4032	void pgmPoolResetDirtyPages(PVMCC pVM);
4033	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
4034
4035	/** Gets the ring-0 pointer for the given pool page. */
4036	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4037	{
4038	#ifdef IN_RING3
4039	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
4040	# ifdef VBOX_STRICT
4041	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
4042	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
4043	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
4044	# endif
4045	return pPool->pPoolR0 + offPage;
4046	#else
4047	RT_NOREF(pPool);
4048	return pPage;
4049	#endif
4050	}
4051
4052	/** Gets the ring-3 pointer for the given pool page. */
4053	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4054	{
4055	#ifdef IN_RING3
4056	RT_NOREF(pPool);
4057	return pPage;
4058	#else
4059	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
4060	# ifdef VBOX_STRICT
4061	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
4062	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
4063	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
4064	# endif
4065	return pPool->pPoolR3 + offPage;
4066	#endif
4067	}
4068
4069	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4070	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4071	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4072
4073	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4074	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4075	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4076
4077	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
4078	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
4079	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4080	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
4081	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
4082	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
4083	#endif
4084	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
4085	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
4086
4087	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4088	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4089	FNDBGCCMD pgmR3CmdShowSharedModules;
4090	# endif
4091
4092	void pgmLogState(PVM pVM);
4093
4094	RT_C_DECLS_END
4095
4096	/** @} */
4097
4098	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4099

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 107171

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