PGMInternal.h@ 97405

Last change on this file since 97405 was 97197, checked in by vboxsync, 2 years ago
VMM/PGM,IEM,EM: Changed FNPGMRZPHYSPFHANDLER, PGMTrap0eHandler and PGMR0Trap0eHandlerNPMisconfig to take PCPUMCTX instead of PCPUMCTXCORE parameters; dropped PCPUMCTXCORE parameters from IEMExecOneBypassEx, PGMInterpretInstruction and EMInterpretInstruction together with some associated cleanups.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 176.9 KB

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1	/* $Id: PGMInternal.h 97197 2022-10-18 11:09:55Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	//#if 0 /* disabled again while debugging */
79	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	//#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/**
118	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119	*/
120	#define PGM_MAX_PHYSCACHE_ENTRIES 64
121	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124	/** @def PGMPOOL_CFG_MAX_GROW
125	* The maximum number of pages to add to the pool in one go.
126	*/
127	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
131	*/
132	#ifdef VBOX_STRICT
133	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134	#endif
135
136	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137	* Enables the experimental lazy page allocation code. */
138	#ifdef DOXYGEN_RUNNING
139	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
140	#endif
141
142	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
143	* Enables real write monitoring of pages, i.e. mapping them read-only and
144	* only making them writable when getting a write access \#PF. */
145	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
146
147	/** @def VBOX_WITH_PGM_NEM_MODE
148	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
149	* details. */
150	#ifdef DOXYGEN_RUNNING
151	# define VBOX_WITH_PGM_NEM_MODE
152	#endif
153
154	/** @} */
155
156
157	/** @name PDPT and PML4 flags.
158	* These are placed in the three bits available for system programs in
159	* the PDPT and PML4 entries.
160	* @{ */
161	/** The entry is a permanent one and it's must always be present.
162	* Never free such an entry. */
163	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
164	/** PGM specific bits in PML4 entries. */
165	#define PGM_PML4_FLAGS 0
166	/** PGM specific bits in PDPT entries. */
167	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
168	/** @} */
169
170	/** @name Page directory flags.
171	* These are placed in the three bits available for system programs in
172	* the page directory entries.
173	* @{ */
174	/** Indicates the original entry was a big page.
175	* @remarks This is currently only used for statistics and can be recycled. */
176	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
177	/** Made read-only to facilitate dirty bit tracking. */
178	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
179	/** @} */
180
181	/** @name Page flags.
182	* These are placed in the three bits available for system programs in
183	* the page entries.
184	* @{ */
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
187
188	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
189	/** Scanned and approved by CSAM (tm).
190	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
191	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
192	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
193	#endif
194
195	/** @} */
196
197	/** @name Defines used to indicate the shadow and guest paging in the templates.
198	* @{ */
199	#define PGM_TYPE_REAL 1
200	#define PGM_TYPE_PROT 2
201	#define PGM_TYPE_32BIT 3
202	#define PGM_TYPE_PAE 4
203	#define PGM_TYPE_AMD64 5
204	#define PGM_TYPE_NESTED_32BIT 6
205	#define PGM_TYPE_NESTED_PAE 7
206	#define PGM_TYPE_NESTED_AMD64 8
207	#define PGM_TYPE_EPT 9
208	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
209	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
210	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
211	/** @} */
212
213	/** @name Defines used to indicate the second-level
214	* address translation (SLAT) modes in the templates.
215	* @{ */
216	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
217	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
218	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
219	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
220	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
221	/** @} */
222
223	/** Macro for checking if the guest is using paging.
224	* @param uGstType PGM_TYPE_*
225	* @param uShwType PGM_TYPE_*
226	* @remark ASSUMES certain order of the PGM_TYPE_* values.
227	*/
228	#define PGM_WITH_PAGING(uGstType, uShwType) \
229	( (uGstType) >= PGM_TYPE_32BIT \
230	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
231
232	/** Macro for checking if the guest supports the NX bit.
233	* @param uGstType PGM_TYPE_*
234	* @param uShwType PGM_TYPE_*
235	* @remark ASSUMES certain order of the PGM_TYPE_* values.
236	*/
237	#define PGM_WITH_NX(uGstType, uShwType) \
238	( (uGstType) >= PGM_TYPE_PAE \
239	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
240
241	/** Macro for checking for nested.
242	* @param uType PGM_TYPE_*
243	*/
244	#define PGM_TYPE_IS_NESTED(uType) \
245	( (uType) == PGM_TYPE_NESTED_32BIT \
246	\|\| (uType) == PGM_TYPE_NESTED_PAE \
247	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
248
249	/** Macro for checking for nested or EPT.
250	* @param uType PGM_TYPE_*
251	*/
252	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
253	( (uType) == PGM_TYPE_NESTED_32BIT \
254	\|\| (uType) == PGM_TYPE_NESTED_PAE \
255	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
256	\|\| (uType) == PGM_TYPE_EPT)
257
258
259
260	/** @def PGM_HCPHYS_2_PTR
261	* Maps a HC physical page pool address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM The cross context VM structure.
265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
266	* @param HCPhys The HC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast
268	* this.
269	*
270	* @remark There is no need to assert on the result.
271	*/
272	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
273
274	/** @def PGM_GCPHYS_2_PTR_V2
275	* Maps a GC physical page address to a virtual address.
276	*
277	* @returns VBox status code.
278	* @param pVM The cross context VM structure.
279	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
280	* @param GCPhys The GC physical address to map to a virtual one.
281	* @param ppv Where to store the virtual address. No need to cast this.
282	*
283	* @remark Use with care as we don't have so much dynamic mapping space in
284	* ring-0 on 32-bit darwin and in RC.
285	* @remark There is no need to assert on the result.
286	*/
287	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
288	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
289
290	/** @def PGM_GCPHYS_2_PTR
291	* Maps a GC physical page address to a virtual address.
292	*
293	* @returns VBox status code.
294	* @param pVM The cross context VM structure.
295	* @param GCPhys The GC physical address to map to a virtual one.
296	* @param ppv Where to store the virtual address. No need to cast this.
297	*
298	* @remark Use with care as we don't have so much dynamic mapping space in
299	* ring-0 on 32-bit darwin and in RC.
300	* @remark There is no need to assert on the result.
301	*/
302	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
303
304	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
305	* Maps a GC physical page address to a virtual address.
306	*
307	* @returns VBox status code.
308	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
309	* @param GCPhys The GC physical address to map to a virtual one.
310	* @param ppv Where to store the virtual address. No need to cast this.
311	*
312	* @remark Use with care as we don't have so much dynamic mapping space in
313	* ring-0 on 32-bit darwin and in RC.
314	* @remark There is no need to assert on the result.
315	*/
316	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
317
318	/** @def PGM_GCPHYS_2_PTR_EX
319	* Maps a unaligned GC physical page address to a virtual address.
320	*
321	* @returns VBox status code.
322	* @param pVM The cross context VM structure.
323	* @param GCPhys The GC physical address to map to a virtual one.
324	* @param ppv Where to store the virtual address. No need to cast this.
325	*
326	* @remark Use with care as we don't have so much dynamic mapping space in
327	* ring-0 on 32-bit darwin and in RC.
328	* @remark There is no need to assert on the result.
329	*/
330	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
331	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
332
333	/** @def PGM_DYNMAP_UNUSED_HINT
334	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
335	* is no longer used.
336	*
337	* For best effect only apply this to the page that was mapped most recently.
338	*
339	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
340	* @param pvPage The pool page.
341	*/
342	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
343
344	/** @def PGM_DYNMAP_UNUSED_HINT_VM
345	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
346	* is no longer used.
347	*
348	* For best effect only apply this to the page that was mapped most recently.
349	*
350	* @param pVM The cross context VM structure.
351	* @param pvPage The pool page.
352	*/
353	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
354
355
356	/** @def PGM_INVL_PG
357	* Invalidates a page.
358	*
359	* @param pVCpu The cross context virtual CPU structure.
360	* @param GCVirt The virtual address of the page to invalidate.
361	*/
362	#ifdef IN_RING0
363	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
364	#elif defined(IN_RING3)
365	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
366	#else
367	# error "Not IN_RING0 or IN_RING3!"
368	#endif
369
370	/** @def PGM_INVL_PG_ALL_VCPU
371	* Invalidates a page on all VCPUs
372	*
373	* @param pVM The cross context VM structure.
374	* @param GCVirt The virtual address of the page to invalidate.
375	*/
376	#ifdef IN_RING0
377	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
378	#else
379	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
380	#endif
381
382	/** @def PGM_INVL_BIG_PG
383	* Invalidates a 4MB page directory entry.
384	*
385	* @param pVCpu The cross context virtual CPU structure.
386	* @param GCVirt The virtual address within the page directory to invalidate.
387	*/
388	#ifdef IN_RING0
389	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
390	#else
391	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
392	#endif
393
394	/** @def PGM_INVL_VCPU_TLBS()
395	* Invalidates the TLBs of the specified VCPU
396	*
397	* @param pVCpu The cross context virtual CPU structure.
398	*/
399	#ifdef IN_RING0
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
401	#else
402	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
403	#endif
404
405	/** @def PGM_INVL_ALL_VCPU_TLBS()
406	* Invalidates the TLBs of all VCPUs
407	*
408	* @param pVM The cross context VM structure.
409	*/
410	#ifdef IN_RING0
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 1
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** The physical access handler type handle count (power of two). */
498	#define PGMPHYSHANDLERTYPE_COUNT 0x20
499	/** Mask for getting the array index from an access handler type handle.
500	* The other handle bits are random and non-zero to avoid mixups due to zero
501	* initialized fields. */
502	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
503
504	/**
505	* Physical page access handler type registration, ring-0 part.
506	*/
507	typedef struct PGMPHYSHANDLERTYPEINTR0
508	{
509	/** The handle value for verfication. */
510	PGMPHYSHANDLERTYPE hType;
511	/** The kind of accesses we're handling. */
512	PGMPHYSHANDLERKIND enmKind;
513	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
514	uint8_t uState;
515	/** Whether to keep the PGM lock when calling the handler.
516	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
517	bool fKeepPgmLock;
518	/** Set if this is registered by a device instance and uUser should be
519	* translated from a device instance ID to a pointer.
520	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
521	bool fRing0DevInsIdx;
522	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
523	bool fNotInHm : 1;
524	/** Pointer to the ring-0 callback function. */
525	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
526	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
527	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
528	/** Description / Name. For easing debugging. */
529	R0PTRTYPE(const char *) pszDesc;
530	} PGMPHYSHANDLERTYPEINTR0;
531	/** Pointer to a physical access handler type registration. */
532	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
533
534	/**
535	* Physical page access handler type registration, shared/ring-3 part.
536	*/
537	typedef struct PGMPHYSHANDLERTYPEINTR3
538	{
539	/** The handle value for verfication. */
540	PGMPHYSHANDLERTYPE hType;
541	/** The kind of accesses we're handling. */
542	PGMPHYSHANDLERKIND enmKind;
543	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
544	uint8_t uState;
545	/** Whether to keep the PGM lock when calling the handler.
546	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
547	bool fKeepPgmLock;
548	/** Set if this is registered by a device instance and uUser should be
549	* translated from a device instance ID to a pointer.
550	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
551	bool fRing0DevInsIdx;
552	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
553	bool fRing0Enabled : 1;
554	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
555	bool fNotInHm : 1;
556	/** Pointer to the ring-3 callback function. */
557	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
558	/** Description / Name. For easing debugging. */
559	R3PTRTYPE(const char *) pszDesc;
560	} PGMPHYSHANDLERTYPEINTR3;
561	/** Pointer to a physical access handler type registration. */
562	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
563
564	/** Pointer to a physical access handler type record for the current context. */
565	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
566	/** Pointer to a const physical access handler type record for the current context. */
567	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
568	/** Dummy physical access handler type record. */
569	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
570
571
572	/**
573	* Physical page access handler structure.
574	*
575	* This is used to keep track of physical address ranges
576	* which are being monitored in some kind of way.
577	*/
578	typedef struct PGMPHYSHANDLER
579	{
580	/** @name Tree stuff.
581	* @{ */
582	/** First address. */
583	RTGCPHYS Key;
584	/** Last address. */
585	RTGCPHYS KeyLast;
586	uint32_t idxLeft;
587	uint32_t idxRight;
588	uint8_t cHeight;
589	/** @} */
590	uint8_t abPadding[3];
591	/** Number of pages to update. */
592	uint32_t cPages;
593	/** Set if we have pages that have been aliased. */
594	uint32_t cAliasedPages;
595	/** Set if we have pages that have temporarily been disabled. */
596	uint32_t cTmpOffPages;
597	/** Registered handler type handle.
598	* @note Marked volatile to prevent re-reading after validation. */
599	PGMPHYSHANDLERTYPE volatile hType;
600	/** User argument for the handlers. */
601	uint64_t uUser;
602	/** Description / Name. For easing debugging. */
603	R3PTRTYPE(const char *) pszDesc;
604	/** Profiling of this handler.
605	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
606	STAMPROFILE Stat;
607	} PGMPHYSHANDLER;
608	AssertCompileSize(PGMPHYSHANDLER, 12*8);
609	/** Pointer to a physical page access handler structure. */
610	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
611
612	/**
613	* Gets the type record for a physical handler (no reference added).
614	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
615	* @param a_pVM The cross context VM structure.
616	* @param a_pPhysHandler Pointer to the physical handler structure
617	* (PGMPHYSHANDLER).
618	*/
619	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
620	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
621
622	/**
623	* Gets the type record for a physical handler, never returns NULL.
624	*
625	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
626	* @param a_pVM The cross context VM structure.
627	* @param a_pPhysHandler Pointer to the physical handler structure
628	* (PGMPHYSHANDLER).
629	*/
630	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
631	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
632
633	/** Physical access handler allocator. */
634	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
635
636	/** Physical access handler tree. */
637	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
638	/** Pointer to a physical access handler tree. */
639	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
640
641
642	/**
643	* A Physical Guest Page tracking structure.
644	*
645	* The format of this structure is complicated because we have to fit a lot
646	* of information into as few bits as possible. The format is also subject
647	* to change (there is one coming up soon). Which means that for we'll be
648	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
649	* accesses to the structure.
650	*/
651	typedef union PGMPAGE
652	{
653	/** Structured view. */
654	struct
655	{
656	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
657	uint64_t u2HandlerPhysStateY : 2;
658	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
659	uint64_t fHandlerPhysNotInHm : 1;
660	/** 3 - Flag indicating that a write monitored page was written to
661	* when set. */
662	uint64_t fWrittenToY : 1;
663	/** 7:4 - Unused. */
664	uint64_t u2Unused0 : 4;
665	/** 9:8 - Paging structure needed to map the page
666	* (PGM_PAGE_PDE_TYPE_). /
667	uint64_t u2PDETypeY : 2;
668	/** 11:10 - NEM state bits. */
669	uint64_t u2NemStateY : 2;
670	/** 12:48 - The host physical frame number (shift left to get the
671	* address). */
672	uint64_t HCPhysFN : 36;
673	/** 50:48 - The page state. */
674	uint64_t uStateY : 3;
675	/** 51:53 - The page type (PGMPAGETYPE). */
676	uint64_t uTypeY : 3;
677	/** 63:54 - PTE index for usage tracking (page pool). */
678	uint64_t u10PteIdx : 10;
679
680	/** The GMM page ID.
681	* @remarks In the current implementation, MMIO2 and pages aliased to
682	* MMIO2 pages will be exploiting this field to calculate the
683	* ring-3 mapping address corresponding to the page.
684	* Later we may consider including MMIO2 management into GMM. */
685	uint32_t idPage;
686	/** Usage tracking (page pool). */
687	uint16_t u16TrackingY;
688	/** The number of read locks on this page. */
689	uint8_t cReadLocksY;
690	/** The number of write locks on this page. */
691	uint8_t cWriteLocksY;
692	} s;
693
694	/** 64-bit integer view. */
695	uint64_t au64[2];
696	/** 16-bit view. */
697	uint32_t au32[4];
698	/** 16-bit view. */
699	uint16_t au16[8];
700	/** 8-bit view. */
701	uint8_t au8[16];
702	} PGMPAGE;
703	AssertCompileSize(PGMPAGE, 16);
704	/** Pointer to a physical guest page. */
705	typedef PGMPAGE *PPGMPAGE;
706	/** Pointer to a const physical guest page. */
707	typedef const PGMPAGE *PCPGMPAGE;
708	/** Pointer to a physical guest page pointer. */
709	typedef PPGMPAGE *PPPGMPAGE;
710
711
712	/**
713	* Clears the page structure.
714	* @param a_pPage Pointer to the physical guest page tracking structure.
715	*/
716	#define PGM_PAGE_CLEAR(a_pPage) \
717	do { \
718	(a_pPage)->au64[0] = 0; \
719	(a_pPage)->au64[1] = 0; \
720	} while (0)
721
722	/**
723	* Initializes the page structure.
724	* @param a_pPage Pointer to the physical guest page tracking structure.
725	* @param a_HCPhys The host physical address of the page.
726	* @param a_idPage The (GMM) page ID of the page.
727	* @param a_uType The page type (PGMPAGETYPE).
728	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
729	*/
730	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
731	do { \
732	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
733	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
734	(a_pPage)->au64[0] = SetHCPhysTmp; \
735	(a_pPage)->au64[1] = 0; \
736	(a_pPage)->s.idPage = (a_idPage); \
737	(a_pPage)->s.uStateY = (a_uState); \
738	(a_pPage)->s.uTypeY = (a_uType); \
739	} while (0)
740
741	/**
742	* Initializes the page structure of a ZERO page.
743	* @param a_pPage Pointer to the physical guest page tracking structure.
744	* @param a_pVM The VM handle (for getting the zero page address).
745	* @param a_uType The page type (PGMPAGETYPE).
746	*/
747	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
748	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
749
750
751	/** @name The Page state, PGMPAGE::uStateY.
752	* @{ */
753	/** The zero page.
754	* This is a per-VM page that's never ever mapped writable. */
755	#define PGM_PAGE_STATE_ZERO 0U
756	/** A allocated page.
757	* This is a per-VM page allocated from the page pool (or wherever
758	* we get MMIO2 pages from if the type is MMIO2).
759	*/
760	#define PGM_PAGE_STATE_ALLOCATED 1U
761	/** A allocated page that's being monitored for writes.
762	* The shadow page table mappings are read-only. When a write occurs, the
763	* fWrittenTo member is set, the page remapped as read-write and the state
764	* moved back to allocated. */
765	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
766	/** The page is shared, aka. copy-on-write.
767	* This is a page that's shared with other VMs. */
768	#define PGM_PAGE_STATE_SHARED 3U
769	/** The page is ballooned, so no longer available for this VM. */
770	#define PGM_PAGE_STATE_BALLOONED 4U
771	/** @} */
772
773
774	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
775	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
776	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
777	#else
778	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
779	#endif
780
781	/**
782	* Gets the page state.
783	* @returns page state (PGM_PAGE_STATE_*).
784	* @param a_pPage Pointer to the physical guest page tracking structure.
785	*
786	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
787	* builds.
788	*/
789	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
790	#if defined(__GNUC__) && defined(VBOX_STRICT)
791	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
792	#else
793	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
794	#endif
795
796	/**
797	* Sets the page state.
798	* @param a_pVM The VM handle, only used for lock ownership assertions.
799	* @param a_pPage Pointer to the physical guest page tracking structure.
800	* @param a_uState The new page state.
801	*/
802	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
803	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
804
805
806	/**
807	* Gets the host physical address of the guest page.
808	* @returns host physical address (RTHCPHYS).
809	* @param a_pPage Pointer to the physical guest page tracking structure.
810	*
811	* @remarks In strict builds on gcc platforms, this macro will make some ugly
812	* assumption about a valid pVM variable/parameter being in the
813	* current context. It will use this pVM variable to assert that the
814	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
815	* pVM is not around.
816	*/
817	#if 0
818	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
819	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
820	#else
821	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
822	# if defined(__GNUC__) && defined(VBOX_STRICT)
823	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
824	# else
825	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
826	# endif
827	#endif
828
829	/**
830	* Sets the host physical address of the guest page.
831	*
832	* @param a_pVM The VM handle, only used for lock ownership assertions.
833	* @param a_pPage Pointer to the physical guest page tracking structure.
834	* @param a_HCPhys The new host physical address.
835	*/
836	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
837	do { \
838	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
839	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
840	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
841	PGM_PAGE_ASSERT_LOCK(a_pVM); \
842	} while (0)
843
844	/**
845	* Get the Page ID.
846	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
847	* @param a_pPage Pointer to the physical guest page tracking structure.
848	*/
849	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
850
851	/**
852	* Sets the Page ID.
853	* @param a_pVM The VM handle, only used for lock ownership assertions.
854	* @param a_pPage Pointer to the physical guest page tracking structure.
855	* @param a_idPage The new page ID.
856	*/
857	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
858	do { \
859	(a_pPage)->s.idPage = (a_idPage); \
860	PGM_PAGE_ASSERT_LOCK(a_pVM); \
861	} while (0)
862
863	/**
864	* Get the Chunk ID.
865	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
866	* @param a_pPage Pointer to the physical guest page tracking structure.
867	*/
868	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
869
870	/**
871	* Get the index of the page within the allocation chunk.
872	* @returns The page index.
873	* @param a_pPage Pointer to the physical guest page tracking structure.
874	*/
875	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
876
877	/**
878	* Gets the page type.
879	* @returns The page type.
880	* @param a_pPage Pointer to the physical guest page tracking structure.
881	*
882	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
883	* builds.
884	*/
885	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
886	#if defined(__GNUC__) && defined(VBOX_STRICT)
887	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
888	#else
889	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
890	#endif
891
892	/**
893	* Sets the page type.
894	*
895	* @param a_pVM The VM handle, only used for lock ownership assertions.
896	* @param a_pPage Pointer to the physical guest page tracking structure.
897	* @param a_enmType The new page type (PGMPAGETYPE).
898	*/
899	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
900	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
901
902	/**
903	* Gets the page table index
904	* @returns The page table index.
905	* @param a_pPage Pointer to the physical guest page tracking structure.
906	*/
907	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
908
909	/**
910	* Sets the page table index.
911	* @param a_pVM The VM handle, only used for lock ownership assertions.
912	* @param a_pPage Pointer to the physical guest page tracking structure.
913	* @param a_iPte New page table index.
914	*/
915	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
916	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
917
918	/**
919	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
920	* @returns true/false.
921	* @param a_pPage Pointer to the physical guest page tracking structure.
922	*/
923	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
924
925	/**
926	* Checks if the page is marked for MMIO, including both aliases.
927	* @returns true/false.
928	* @param a_pPage Pointer to the physical guest page tracking structure.
929	*/
930	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
931	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
932	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
933	)
934
935	/**
936	* Checks if the page is marked for MMIO, including special aliases.
937	* @returns true/false.
938	* @param a_pPage Pointer to the physical guest page tracking structure.
939	*/
940	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
941	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
942
943	/**
944	* Checks if the page is a special aliased MMIO page.
945	* @returns true/false.
946	* @param a_pPage Pointer to the physical guest page tracking structure.
947	*/
948	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
949
950	/**
951	* Checks if the page is backed by the ZERO page.
952	* @returns true/false.
953	* @param a_pPage Pointer to the physical guest page tracking structure.
954	*/
955	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
956
957	/**
958	* Checks if the page is backed by a SHARED page.
959	* @returns true/false.
960	* @param a_pPage Pointer to the physical guest page tracking structure.
961	*/
962	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
963
964	/**
965	* Checks if the page is ballooned.
966	* @returns true/false.
967	* @param a_pPage Pointer to the physical guest page tracking structure.
968	*/
969	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
970
971	/**
972	* Checks if the page is allocated.
973	* @returns true/false.
974	* @param a_pPage Pointer to the physical guest page tracking structure.
975	*/
976	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
977
978	/**
979	* Marks the page as written to (for GMM change monitoring).
980	* @param a_pVM The VM handle, only used for lock ownership assertions.
981	* @param a_pPage Pointer to the physical guest page tracking structure.
982	*/
983	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
984	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
985
986	/**
987	* Clears the written-to indicator.
988	* @param a_pVM The VM handle, only used for lock ownership assertions.
989	* @param a_pPage Pointer to the physical guest page tracking structure.
990	*/
991	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
992	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
993
994	/**
995	* Checks if the page was marked as written-to.
996	* @returns true/false.
997	* @param a_pPage Pointer to the physical guest page tracking structure.
998	*/
999	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1000
1001
1002	/** @name PT usage values (PGMPAGE::u2PDEType).
1003	*
1004	* @{ */
1005	/** Either as a PT or PDE. */
1006	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1007	/** Must use a page table to map the range. */
1008	#define PGM_PAGE_PDE_TYPE_PT 1
1009	/** Can use a page directory entry to map the continuous range. */
1010	#define PGM_PAGE_PDE_TYPE_PDE 2
1011	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1012	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1013	/** @} */
1014
1015	/**
1016	* Set the PDE type of the page
1017	* @param a_pVM The VM handle, only used for lock ownership assertions.
1018	* @param a_pPage Pointer to the physical guest page tracking structure.
1019	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1020	*/
1021	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1022	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1023
1024	/**
1025	* Checks if the page was marked being part of a large page
1026	* @returns true/false.
1027	* @param a_pPage Pointer to the physical guest page tracking structure.
1028	*/
1029	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1030
1031	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1032	*
1033	* @remarks The values are assigned in order of priority, so we can calculate
1034	* the correct state for a page with different handlers installed.
1035	* @{ */
1036	/** No handler installed. */
1037	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1038	/** Monitoring is temporarily disabled. */
1039	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1040	/** Write access is monitored. */
1041	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1042	/** All access is monitored. */
1043	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1044	/** @} */
1045
1046	/**
1047	* Gets the physical access handler state of a page.
1048	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1049	* @param a_pPage Pointer to the physical guest page tracking structure.
1050	*/
1051	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1052
1053	/**
1054	* Sets the physical access handler state of a page.
1055	* @param a_pPage Pointer to the physical guest page tracking structure.
1056	* @param a_uState The new state value.
1057	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1058	*/
1059	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1060	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1061
1062	/**
1063	* Sets the physical access handler state of a page.
1064	* @param a_pPage Pointer to the physical guest page tracking structure.
1065	* @param a_uState The new state value.
1066	*/
1067	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1068	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1069
1070	/**
1071	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1072	* @returns true/false
1073	* @param a_pPage Pointer to the physical guest page tracking structure.
1074	*/
1075	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1076	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1077
1078	/**
1079	* Checks if the page has any active physical access handlers.
1080	* @returns true/false
1081	* @param a_pPage Pointer to the physical guest page tracking structure.
1082	*/
1083	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1084	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1085
1086	/**
1087	* Checks if the page has any access handlers, including temporarily disabled ones.
1088	* @returns true/false
1089	* @param a_pPage Pointer to the physical guest page tracking structure.
1090	*/
1091	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1092	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1093
1094	/**
1095	* Checks if the page has any active access handlers.
1096	* @returns true/false
1097	* @param a_pPage Pointer to the physical guest page tracking structure.
1098	*/
1099	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1100	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1101
1102	/**
1103	* Checks if the page has any active access handlers catching all accesses.
1104	* @returns true/false
1105	* @param a_pPage Pointer to the physical guest page tracking structure.
1106	*/
1107	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1108	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1109
1110	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1111	* Checks if the physical handlers of the page should be ignored in shadow page
1112	* tables and such.
1113	* @returns true/false
1114	* @param a_pPage Pointer to the physical guest page tracking structure.
1115	*/
1116	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1117
1118	/** @def PGM_PAGE_GET_TRACKING
1119	* Gets the packed shadow page pool tracking data associated with a guest page.
1120	* @returns uint16_t containing the data.
1121	* @param a_pPage Pointer to the physical guest page tracking structure.
1122	*/
1123	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1124	#if defined(__GNUC__) && defined(VBOX_STRICT)
1125	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1126	#else
1127	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1128	#endif
1129
1130	/** @def PGM_PAGE_SET_TRACKING
1131	* Sets the packed shadow page pool tracking data associated with a guest page.
1132	* @param a_pVM The VM handle, only used for lock ownership assertions.
1133	* @param a_pPage Pointer to the physical guest page tracking structure.
1134	* @param a_u16TrackingData The tracking data to store.
1135	*/
1136	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1137	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1138
1139	/** @def PGM_PAGE_GET_TD_CREFS
1140	* Gets the @a cRefs tracking data member.
1141	* @returns cRefs.
1142	* @param a_pPage Pointer to the physical guest page tracking structure.
1143	*/
1144	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1145	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1146	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1147	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1148
1149	/** @def PGM_PAGE_GET_TD_IDX
1150	* Gets the @a idx tracking data member.
1151	* @returns idx.
1152	* @param a_pPage Pointer to the physical guest page tracking structure.
1153	*/
1154	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1155	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1156	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1157	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1158
1159
1160	/** Max number of locks on a page. */
1161	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1162
1163	/** Get the read lock count.
1164	* @returns count.
1165	* @param a_pPage Pointer to the physical guest page tracking structure.
1166	*/
1167	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1168
1169	/** Get the write lock count.
1170	* @returns count.
1171	* @param a_pPage Pointer to the physical guest page tracking structure.
1172	*/
1173	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1174
1175	/** Decrement the read lock counter.
1176	* @param a_pPage Pointer to the physical guest page tracking structure.
1177	*/
1178	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1179
1180	/** Decrement the write lock counter.
1181	* @param a_pPage Pointer to the physical guest page tracking structure.
1182	*/
1183	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1184
1185	/** Increment the read lock counter.
1186	* @param a_pPage Pointer to the physical guest page tracking structure.
1187	*/
1188	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1189
1190	/** Increment the write lock counter.
1191	* @param a_pPage Pointer to the physical guest page tracking structure.
1192	*/
1193	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1194
1195
1196	/** Gets the NEM state.
1197	* @returns NEM state value (two bits).
1198	* @param a_pPage Pointer to the physical guest page tracking structure.
1199	*/
1200	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1201
1202	/** Sets the NEM state.
1203	* @param a_pPage Pointer to the physical guest page tracking structure.
1204	* @param a_u2State The NEM state value (specific to NEM impl.).
1205	*/
1206	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1207	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1208
1209
1210	#if 0
1211	/** Enables sanity checking of write monitoring using CRC-32. */
1212	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1213	#endif
1214
1215	/**
1216	* Per page live save tracking data.
1217	*/
1218	typedef struct PGMLIVESAVERAMPAGE
1219	{
1220	/** Number of times it has been dirtied. */
1221	uint32_t cDirtied : 24;
1222	/** Whether it is currently dirty. */
1223	uint32_t fDirty : 1;
1224	/** Ignore the page.
1225	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1226	* deal with these after pausing the VM and DevPCI have said it bit about
1227	* remappings. */
1228	uint32_t fIgnore : 1;
1229	/** Was a ZERO page last time around. */
1230	uint32_t fZero : 1;
1231	/** Was a SHARED page last time around. */
1232	uint32_t fShared : 1;
1233	/** Whether the page is/was write monitored in a previous pass. */
1234	uint32_t fWriteMonitored : 1;
1235	/** Whether the page is/was write monitored earlier in this pass. */
1236	uint32_t fWriteMonitoredJustNow : 1;
1237	/** Bits reserved for future use. */
1238	uint32_t u2Reserved : 2;
1239	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1240	/** CRC-32 for the page. This is for internal consistency checks. */
1241	uint32_t u32Crc;
1242	#endif
1243	} PGMLIVESAVERAMPAGE;
1244	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1245	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1246	#else
1247	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1248	#endif
1249	/** Pointer to the per page live save tracking data. */
1250	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1251
1252	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1253	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1254
1255
1256	/**
1257	* RAM range for GC Phys to HC Phys conversion.
1258	*
1259	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1260	* conversions too, but we'll let MM handle that for now.
1261	*
1262	* This structure is used by linked lists in both GC and HC.
1263	*/
1264	typedef struct PGMRAMRANGE
1265	{
1266	/** Start of the range. Page aligned. */
1267	RTGCPHYS GCPhys;
1268	/** Size of the range. (Page aligned of course). */
1269	RTGCPHYS cb;
1270	/** Pointer to the next RAM range - for R3. */
1271	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1272	/** Pointer to the next RAM range - for R0. */
1273	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1274	/** PGM_RAM_RANGE_FLAGS_* flags. */
1275	uint32_t fFlags;
1276	/** NEM specific info, UINT32_MAX if not used. */
1277	uint32_t uNemRange;
1278	/** Last address in the range (inclusive). Page aligned (-1). */
1279	RTGCPHYS GCPhysLast;
1280	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1281	R3PTRTYPE(void *) pvR3;
1282	/** Live save per page tracking data. */
1283	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1284	/** The range description. */
1285	R3PTRTYPE(const char *) pszDesc;
1286	/** Pointer to self - R0 pointer. */
1287	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1288
1289	/** Pointer to the left search three node - ring-3 context. */
1290	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1291	/** Pointer to the right search three node - ring-3 context. */
1292	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1293	/** Pointer to the left search three node - ring-0 context. */
1294	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1295	/** Pointer to the right search three node - ring-0 context. */
1296	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1297
1298	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1299	#if HC_ARCH_BITS == 32
1300	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1301	#endif
1302	/** Array of physical guest page tracking structures.
1303	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1304	PGMPAGE aPages[1];
1305	} PGMRAMRANGE;
1306	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1307	typedef PGMRAMRANGE *PPGMRAMRANGE;
1308
1309	/** @name PGMRAMRANGE::fFlags
1310	* @{ */
1311	/** The RAM range is floating around as an independent guest mapping. */
1312	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1313	/** Ad hoc RAM range for an ROM mapping. */
1314	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1315	/** Ad hoc RAM range for an MMIO mapping. */
1316	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1317	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1318	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1319	/** @} */
1320
1321	/** Tests if a RAM range is an ad hoc one or not.
1322	* @returns true/false.
1323	* @param pRam The RAM range.
1324	*/
1325	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1326	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1327
1328	/** The number of entries in the RAM range TLBs (there is one for each
1329	* context). Must be a power of two. */
1330	#define PGM_RAMRANGE_TLB_ENTRIES 8
1331
1332	/**
1333	* Calculates the RAM range TLB index for the physical address.
1334	*
1335	* @returns RAM range TLB index.
1336	* @param a_GCPhys The guest physical address.
1337	*/
1338	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1339
1340	/**
1341	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1342	* mapping address.
1343	*/
1344	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1345	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1346
1347
1348	/**
1349	* Per page tracking structure for ROM image.
1350	*
1351	* A ROM image may have a shadow page, in which case we may have two pages
1352	* backing it. This structure contains the PGMPAGE for both while
1353	* PGMRAMRANGE have a copy of the active one. It is important that these
1354	* aren't out of sync in any regard other than page pool tracking data.
1355	*/
1356	typedef struct PGMROMPAGE
1357	{
1358	/** The page structure for the virgin ROM page. */
1359	PGMPAGE Virgin;
1360	/** The page structure for the shadow RAM page. */
1361	PGMPAGE Shadow;
1362	/** The current protection setting. */
1363	PGMROMPROT enmProt;
1364	/** Live save status information. Makes use of unused alignment space. */
1365	struct
1366	{
1367	/** The previous protection value. */
1368	uint8_t u8Prot;
1369	/** Written to flag set by the handler. */
1370	bool fWrittenTo;
1371	/** Whether the shadow page is dirty or not. */
1372	bool fDirty;
1373	/** Whether it was dirtied in the recently. */
1374	bool fDirtiedRecently;
1375	} LiveSave;
1376	} PGMROMPAGE;
1377	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1378	/** Pointer to a ROM page tracking structure. */
1379	typedef PGMROMPAGE *PPGMROMPAGE;
1380
1381
1382	/**
1383	* A registered ROM image.
1384	*
1385	* This is needed to keep track of ROM image since they generally intrude
1386	* into a PGMRAMRANGE. It also keeps track of additional info like the
1387	* two page sets (read-only virgin and read-write shadow), the current
1388	* state of each page.
1389	*
1390	* Because access handlers cannot easily be executed in a different
1391	* context, the ROM ranges needs to be accessible and in all contexts.
1392	*/
1393	typedef struct PGMROMRANGE
1394	{
1395	/** Pointer to the next range - R3. */
1396	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1397	/** Pointer to the next range - R0. */
1398	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1399	/** Pointer to the this range - R0. */
1400	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1401	/** Address of the range. */
1402	RTGCPHYS GCPhys;
1403	/** Address of the last byte in the range. */
1404	RTGCPHYS GCPhysLast;
1405	/** Size of the range. */
1406	RTGCPHYS cb;
1407	/** The flags (PGMPHYS_ROM_FLAGS_). /
1408	uint8_t fFlags;
1409	/** The saved state range ID. */
1410	uint8_t idSavedState;
1411	/** Alignment padding. */
1412	uint8_t au8Alignment[2];
1413	/** The size bits pvOriginal points to. */
1414	uint32_t cbOriginal;
1415	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1416	* This is used for strictness checks. */
1417	R3PTRTYPE(const void *) pvOriginal;
1418	/** The ROM description. */
1419	R3PTRTYPE(const char *) pszDesc;
1420	#ifdef VBOX_WITH_PGM_NEM_MODE
1421	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1422	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1423	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1424	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1425	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1426	R3PTRTYPE(uint8_t *) pbR3Alternate;
1427	RTR3PTR pvAlignment2;
1428	#endif
1429	/** The per page tracking structures. */
1430	PGMROMPAGE aPages[1];
1431	} PGMROMRANGE;
1432	/** Pointer to a ROM range. */
1433	typedef PGMROMRANGE *PPGMROMRANGE;
1434
1435
1436	/**
1437	* Live save per page data for an MMIO2 page.
1438	*
1439	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1440	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1441	* CRC-32 for detecting changes as well as special handling of zero pages. This
1442	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1443	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1444	* because of speed (2.5x and 6x slower).)
1445	*
1446	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1447	* save but normally is disabled. Since we can write monitor guest
1448	* accesses on our own, we only need this for host accesses. Shouldn't be
1449	* too difficult for DevVGA, VMMDev might be doable, the planned
1450	* networking fun will be fun since it involves ring-0.
1451	*/
1452	typedef struct PGMLIVESAVEMMIO2PAGE
1453	{
1454	/** Set if the page is considered dirty. */
1455	bool fDirty;
1456	/** The number of scans this page has remained unchanged for.
1457	* Only updated for dirty pages. */
1458	uint8_t cUnchangedScans;
1459	/** Whether this page was zero at the last scan. */
1460	bool fZero;
1461	/** Alignment padding. */
1462	bool fReserved;
1463	/** CRC-32 for the first half of the page.
1464	* This is used together with u32CrcH2 to quickly detect changes in the page
1465	* during the non-final passes. */
1466	uint32_t u32CrcH1;
1467	/** CRC-32 for the second half of the page. */
1468	uint32_t u32CrcH2;
1469	/** SHA-1 for the saved page.
1470	* This is used in the final pass to skip pages without changes. */
1471	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1472	} PGMLIVESAVEMMIO2PAGE;
1473	/** Pointer to a live save status data for an MMIO2 page. */
1474	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1475
1476	/**
1477	* A registered MMIO2 (= Device RAM) range.
1478	*
1479	* There are a few reason why we need to keep track of these registrations. One
1480	* of them is the deregistration & cleanup stuff, while another is that the
1481	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1482	* range list.
1483	*
1484	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1485	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1486	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1487	* overlap we will free all the existing RAM pages and put in the ram range
1488	* pages instead.
1489	*/
1490	typedef struct PGMREGMMIO2RANGE
1491	{
1492	/** The owner of the range. (a device) */
1493	PPDMDEVINSR3 pDevInsR3;
1494	/** Pointer to the ring-3 mapping of the allocation. */
1495	RTR3PTR pvR3;
1496	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1497	/** Pointer to the ring-0 mapping of the allocation. */
1498	RTR0PTR pvR0;
1499	#endif
1500	/** Pointer to the next range - R3. */
1501	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1502	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1503	uint16_t fFlags;
1504	/** The sub device number (internal PCI config (CFGM) number). */
1505	uint8_t iSubDev;
1506	/** The PCI region number. */
1507	uint8_t iRegion;
1508	/** The saved state range ID. */
1509	uint8_t idSavedState;
1510	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1511	uint8_t idMmio2;
1512	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1513	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1514	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1515	#else
1516	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1517	#endif
1518	/** The real size.
1519	* This may be larger than indicated by RamRange.cb if the range has been
1520	* reduced during saved state loading. */
1521	RTGCPHYS cbReal;
1522	/** Pointer to the physical handler for MMIO.
1523	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1524	* will be NULL. */
1525	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1526	/** Live save per page tracking data for MMIO2. */
1527	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1528	/** The associated RAM range. */
1529	PGMRAMRANGE RamRange;
1530	} PGMREGMMIO2RANGE;
1531	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1532	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1533	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1534
1535	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1536	* @{ */
1537	/** Set if this is the first chunk in the MMIO2 range. */
1538	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1539	/** Set if this is the last chunk in the MMIO2 range. */
1540	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1541	/** Set if the whole range is mapped. */
1542	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1543	/** Set if it's overlapping, clear if not. */
1544	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1545	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1546	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1547	/** Set if the access handler is registered. */
1548	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1549	/** Set if dirty page tracking is currently enabled. */
1550	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1551	/** Set if there are dirty pages in the range. */
1552	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1553	/** @} */
1554
1555
1556	/** @name Internal MMIO2 constants.
1557	* @{ */
1558	/** The maximum number of MMIO2 ranges. */
1559	#define PGM_MMIO2_MAX_RANGES 32
1560	/** The maximum number of pages in a MMIO2 range. */
1561	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1562	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1563	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1564	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1565	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1566	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1567	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1568	/** @} */
1569
1570
1571
1572	/**
1573	* PGMPhysRead/Write cache entry
1574	*/
1575	typedef struct PGMPHYSCACHEENTRY
1576	{
1577	/** R3 pointer to physical page. */
1578	R3PTRTYPE(uint8_t *) pbR3;
1579	/** GC Physical address for cache entry */
1580	RTGCPHYS GCPhys;
1581	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1582	RTGCPHYS u32Padding0; /*< alignment padding. /
1583	#endif
1584	} PGMPHYSCACHEENTRY;
1585
1586	/**
1587	* PGMPhysRead/Write cache to reduce REM memory access overhead
1588	*/
1589	typedef struct PGMPHYSCACHE
1590	{
1591	/** Bitmap of valid cache entries */
1592	uint64_t aEntries;
1593	/** Cache entries */
1594	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1595	} PGMPHYSCACHE;
1596
1597
1598	/** @name Ring-3 page mapping TLBs
1599	* @{ */
1600
1601	/** Pointer to an allocation chunk ring-3 mapping. */
1602	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1603	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1604	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1605
1606	/**
1607	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1608	*
1609	* The primary tree (Core) uses the chunk id as key.
1610	*/
1611	typedef struct PGMCHUNKR3MAP
1612	{
1613	/** The key is the chunk id. */
1614	AVLU32NODECORE Core;
1615	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1616	* selection. */
1617	uint32_t iLastUsed;
1618	/** The current reference count. */
1619	uint32_t volatile cRefs;
1620	/** The current permanent reference count. */
1621	uint32_t volatile cPermRefs;
1622	/** The mapping address. */
1623	void *pv;
1624	} PGMCHUNKR3MAP;
1625
1626	/**
1627	* Allocation chunk ring-3 mapping TLB entry.
1628	*/
1629	typedef struct PGMCHUNKR3MAPTLBE
1630	{
1631	/** The chunk id. */
1632	uint32_t volatile idChunk;
1633	#if HC_ARCH_BITS == 64
1634	uint32_t u32Padding; /*< alignment padding. /
1635	#endif
1636	/** The chunk map. */
1637	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1638	} PGMCHUNKR3MAPTLBE;
1639	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1640	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1641
1642	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1643	* @remark Must be a power of two value. */
1644	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1645
1646	/**
1647	* Allocation chunk ring-3 mapping TLB.
1648	*
1649	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1650	* At first glance this might look kinda odd since AVL trees are
1651	* supposed to give the most optimal lookup times of all trees
1652	* due to their balancing. However, take a tree with 1023 nodes
1653	* in it, that's 10 levels, meaning that most searches has to go
1654	* down 9 levels before they find what they want. This isn't fast
1655	* compared to a TLB hit. There is the factor of cache misses,
1656	* and of course the problem with trees and branch prediction.
1657	* This is why we use TLBs in front of most of the trees.
1658	*
1659	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1660	* difficult when we switch to the new inlined AVL trees (from kStuff).
1661	*/
1662	typedef struct PGMCHUNKR3MAPTLB
1663	{
1664	/** The TLB entries. */
1665	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1666	} PGMCHUNKR3MAPTLB;
1667
1668	/**
1669	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1670	* @returns Chunk TLB index.
1671	* @param idChunk The Chunk ID.
1672	*/
1673	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1674
1675
1676	/**
1677	* Ring-3 guest page mapping TLB entry.
1678	* @remarks used in ring-0 as well at the moment.
1679	*/
1680	typedef struct PGMPAGER3MAPTLBE
1681	{
1682	/** Address of the page. */
1683	RTGCPHYS volatile GCPhys;
1684	/** The guest page. */
1685	R3PTRTYPE(PPGMPAGE) volatile pPage;
1686	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1687	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1688	/** The address */
1689	R3PTRTYPE(void *) volatile pv;
1690	#if HC_ARCH_BITS == 32
1691	uint32_t u32Padding; /*< alignment padding. /
1692	#endif
1693	} PGMPAGER3MAPTLBE;
1694	/** Pointer to an entry in the HC physical TLB. */
1695	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1696
1697
1698	/** The number of entries in the ring-3 guest page mapping TLB.
1699	* @remarks The value must be a power of two. */
1700	#define PGM_PAGER3MAPTLB_ENTRIES 256
1701
1702	/**
1703	* Ring-3 guest page mapping TLB.
1704	* @remarks used in ring-0 as well at the moment.
1705	*/
1706	typedef struct PGMPAGER3MAPTLB
1707	{
1708	/** The TLB entries. */
1709	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1710	} PGMPAGER3MAPTLB;
1711	/** Pointer to the ring-3 guest page mapping TLB. */
1712	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1713
1714	/**
1715	* Calculates the index of the TLB entry for the specified guest page.
1716	* @returns Physical TLB index.
1717	* @param GCPhys The guest physical address.
1718	*/
1719	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1720
1721	/** @} */
1722
1723
1724	/** @name Ring-0 page mapping TLB
1725	* @{ */
1726	/**
1727	* Ring-0 guest page mapping TLB entry.
1728	*/
1729	typedef struct PGMPAGER0MAPTLBE
1730	{
1731	/** Address of the page. */
1732	RTGCPHYS volatile GCPhys;
1733	/** The guest page. */
1734	R0PTRTYPE(PPGMPAGE) volatile pPage;
1735	/** The address */
1736	R0PTRTYPE(void *) volatile pv;
1737	} PGMPAGER0MAPTLBE;
1738	/** Pointer to an entry in the HC physical TLB. */
1739	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1740
1741
1742	/** The number of entries in the ring-3 guest page mapping TLB.
1743	* @remarks The value must be a power of two. */
1744	#define PGM_PAGER0MAPTLB_ENTRIES 256
1745
1746	/**
1747	* Ring-3 guest page mapping TLB.
1748	* @remarks used in ring-0 as well at the moment.
1749	*/
1750	typedef struct PGMPAGER0MAPTLB
1751	{
1752	/** The TLB entries. */
1753	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1754	} PGMPAGER0MAPTLB;
1755	/** Pointer to the ring-3 guest page mapping TLB. */
1756	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1757
1758	/**
1759	* Calculates the index of the TLB entry for the specified guest page.
1760	* @returns Physical TLB index.
1761	* @param GCPhys The guest physical address.
1762	*/
1763	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1764	/** @} */
1765
1766
1767	/** @name Context neutral page mapper TLB.
1768	*
1769	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1770	* code is writting in a kind of context neutral way. Time will show whether
1771	* this actually makes sense or not...
1772	*
1773	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1774	* context ends up using a global mapping cache on some platforms
1775	* (darwin).
1776	*
1777	* @{ */
1778	/** @typedef PPGMPAGEMAPTLB
1779	* The page mapper TLB pointer type for the current context. */
1780	/** @typedef PPGMPAGEMAPTLB
1781	* The page mapper TLB entry pointer type for the current context. */
1782	/** @typedef PPGMPAGEMAPTLB
1783	* The page mapper TLB entry pointer pointer type for the current context. */
1784	/** @def PGM_PAGEMAPTLB_ENTRIES
1785	* The number of TLB entries in the page mapper TLB for the current context. */
1786	/** @def PGM_PAGEMAPTLB_IDX
1787	* Calculate the TLB index for a guest physical address.
1788	* @returns The TLB index.
1789	* @param GCPhys The guest physical address. */
1790	/** @typedef PPGMPAGEMAP
1791	* Pointer to a page mapper unit for current context. */
1792	/** @typedef PPPGMPAGEMAP
1793	* Pointer to a page mapper unit pointer for current context. */
1794	#if defined(IN_RING0)
1795	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1796	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1797	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1798	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1799	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1800	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1801	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1802	#else
1803	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1804	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1805	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1806	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1807	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1808	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1809	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1810	#endif
1811	/** @} */
1812
1813
1814	/** @name PGM Pool Indexes.
1815	* Aka. the unique shadow page identifier.
1816	* @{ */
1817	/** NIL page pool IDX. */
1818	#define NIL_PGMPOOL_IDX 0
1819	/** The first normal index. There used to be 5 fictive pages up front, now
1820	* there is only the NIL page. */
1821	#define PGMPOOL_IDX_FIRST 1
1822	/** The last valid index. (inclusive, 14 bits) */
1823	#define PGMPOOL_IDX_LAST 0x3fff
1824	/** @} */
1825
1826	/** The NIL index for the parent chain. */
1827	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1828	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1829
1830	/**
1831	* Node in the chain linking a shadowed page to it's parent (user).
1832	*/
1833	#pragma pack(1)
1834	typedef struct PGMPOOLUSER
1835	{
1836	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1837	uint16_t iNext;
1838	/** The user page index. */
1839	uint16_t iUser;
1840	/** Index into the user table. */
1841	uint32_t iUserTable;
1842	} PGMPOOLUSER, *PPGMPOOLUSER;
1843	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1844	#pragma pack()
1845
1846
1847	/** The NIL index for the phys ext chain. */
1848	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1849	/** The NIL pte index for a phys ext chain slot. */
1850	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1851
1852	/**
1853	* Node in the chain of physical cross reference extents.
1854	* @todo Calling this an 'extent' is not quite right, find a better name.
1855	* @todo find out the optimal size of the aidx array
1856	*/
1857	#pragma pack(1)
1858	typedef struct PGMPOOLPHYSEXT
1859	{
1860	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1861	uint16_t iNext;
1862	/** Alignment. */
1863	uint16_t u16Align;
1864	/** The user page index. */
1865	uint16_t aidx[3];
1866	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1867	uint16_t apte[3];
1868	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1869	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1870	#pragma pack()
1871
1872
1873	/**
1874	* The kind of page that's being shadowed.
1875	*/
1876	typedef enum PGMPOOLKIND
1877	{
1878	/** The virtual invalid 0 entry. */
1879	PGMPOOLKIND_INVALID = 0,
1880	/** The entry is free (=unused). */
1881	PGMPOOLKIND_FREE,
1882
1883	/** Shw: 32-bit page table; Gst: no paging. */
1884	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1885	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1886	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1887	/** Shw: 32-bit page table; Gst: 4MB page. */
1888	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1889	/** Shw: PAE page table; Gst: no paging. */
1890	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1891	/** Shw: PAE page table; Gst: 32-bit page table. */
1892	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1893	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1894	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1895	/** Shw: PAE page table; Gst: PAE page table. */
1896	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1897	/** Shw: PAE page table; Gst: 2MB page. */
1898	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1899
1900	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1901	PGMPOOLKIND_32BIT_PD,
1902	/** Shw: 32-bit page directory. Gst: no paging. */
1903	PGMPOOLKIND_32BIT_PD_PHYS,
1904	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1905	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1906	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1907	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1908	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1909	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1910	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1911	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1912	/** Shw: PAE page directory; Gst: PAE page directory. */
1913	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1914	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1915	PGMPOOLKIND_PAE_PD_PHYS,
1916
1917	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1918	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1919	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1920	PGMPOOLKIND_PAE_PDPT,
1921	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1922	PGMPOOLKIND_PAE_PDPT_PHYS,
1923
1924	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1925	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1926	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1927	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1928	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1929	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1930	/** Shw: 64-bit page directory table; Gst: no paging. */
1931	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1932
1933	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1934	PGMPOOLKIND_64BIT_PML4,
1935
1936	/** Shw: EPT page directory pointer table; Gst: no paging. */
1937	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1938	/** Shw: EPT page directory table; Gst: no paging. */
1939	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1940	/** Shw: EPT page table; Gst: no paging. */
1941	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1942
1943	/** Shw: Root Nested paging table. */
1944	PGMPOOLKIND_ROOT_NESTED,
1945
1946	/** Shw: EPT page table; Gst: EPT page table. */
1947	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
1948	/** Shw: EPT page table; Gst: 2MB page. */
1949	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
1950	/** Shw: EPT page directory table; Gst: EPT page directory. */
1951	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
1952	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
1953	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
1954	/** Shw: EPT PML4; Gst: EPT PML4. */
1955	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
1956
1957	/** The last valid entry. */
1958	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
1959	} PGMPOOLKIND;
1960
1961	/**
1962	* The access attributes of the page; only applies to big pages.
1963	*/
1964	typedef enum
1965	{
1966	PGMPOOLACCESS_DONTCARE = 0,
1967	PGMPOOLACCESS_USER_RW,
1968	PGMPOOLACCESS_USER_R,
1969	PGMPOOLACCESS_USER_RW_NX,
1970	PGMPOOLACCESS_USER_R_NX,
1971	PGMPOOLACCESS_SUPERVISOR_RW,
1972	PGMPOOLACCESS_SUPERVISOR_R,
1973	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1974	PGMPOOLACCESS_SUPERVISOR_R_NX
1975	} PGMPOOLACCESS;
1976
1977	/**
1978	* The tracking data for a page in the pool.
1979	*/
1980	typedef struct PGMPOOLPAGE
1981	{
1982	/** AVL node code with the (HC) physical address of this page. */
1983	AVLOHCPHYSNODECORE Core;
1984	/** Pointer to the R3 mapping of the page. */
1985	R3PTRTYPE(void *) pvPageR3;
1986	/** Pointer to the R0 mapping of the page. */
1987	R0PTRTYPE(void *) pvPageR0;
1988	/** The guest physical address. */
1989	RTGCPHYS GCPhys;
1990	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1991	uint8_t enmKind;
1992	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1993	uint8_t enmAccess;
1994	/** This supplements enmKind and enmAccess */
1995	bool fA20Enabled : 1;
1996
1997	/** Used to indicate that the page is zeroed. */
1998	bool fZeroed : 1;
1999	/** Used to indicate that a PT has non-global entries. */
2000	bool fSeenNonGlobal : 1;
2001	/** Used to indicate that we're monitoring writes to the guest page. */
2002	bool fMonitored : 1;
2003	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2004	* (All pages are in the age list.) */
2005	bool fCached : 1;
2006	/** This is used by the R3 access handlers when invoked by an async thread.
2007	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2008	bool volatile fReusedFlushPending : 1;
2009	/** Used to mark the page as dirty (write monitoring is temporarily
2010	* off). */
2011	bool fDirty : 1;
2012	bool fPadding1 : 1;
2013	bool fPadding2;
2014
2015	/** The index of this page. */
2016	uint16_t idx;
2017	/** The next entry in the list this page currently resides in.
2018	* It's either in the free list or in the GCPhys hash. */
2019	uint16_t iNext;
2020	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2021	uint16_t iUserHead;
2022	/** The number of present entries. */
2023	uint16_t cPresent;
2024	/** The first entry in the table which is present. */
2025	uint16_t iFirstPresent;
2026	/** The number of modifications to the monitored page. */
2027	uint16_t cModifications;
2028	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2029	uint16_t iModifiedNext;
2030	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2031	uint16_t iModifiedPrev;
2032	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2033	uint16_t iMonitoredNext;
2034	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2035	uint16_t iMonitoredPrev;
2036	/** The next page in the age list. */
2037	uint16_t iAgeNext;
2038	/** The previous page in the age list. */
2039	uint16_t iAgePrev;
2040	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2041	uint8_t idxDirtyEntry;
2042
2043	/** @name Access handler statistics to determine whether the guest is
2044	* (re)initializing a page table.
2045	* @{ */
2046	RTGCPTR GCPtrLastAccessHandlerRip;
2047	RTGCPTR GCPtrLastAccessHandlerFault;
2048	uint64_t cLastAccessHandler;
2049	/** @} */
2050	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2051	uint32_t volatile cLocked;
2052	#if GC_ARCH_BITS == 64
2053	uint32_t u32Alignment3;
2054	#endif
2055	# ifdef VBOX_STRICT
2056	RTGCPTR GCPtrDirtyFault;
2057	# endif
2058	} PGMPOOLPAGE;
2059	/** Pointer to a pool page. */
2060	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2061	/** Pointer to a const pool page. */
2062	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2063	/** Pointer to a pool page pointer. */
2064	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2065
2066
2067	/** The hash table size. */
2068	# define PGMPOOL_HASH_SIZE 0x8000
2069	/** The hash function. */
2070	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2071
2072
2073	/**
2074	* The shadow page pool instance data.
2075	*
2076	* It's all one big allocation made at init time, except for the
2077	* pages that is. The user nodes follows immediately after the
2078	* page structures.
2079	*/
2080	typedef struct PGMPOOL
2081	{
2082	/** The VM handle - R3 Ptr. */
2083	PVMR3 pVMR3;
2084	/** The VM handle - R0 Ptr. */
2085	R0PTRTYPE(PVMCC) pVMR0;
2086	/** The ring-3 pointer to this structure. */
2087	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2088	/** The ring-0 pointer to this structure. */
2089	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2090	/** The max pool size. This includes the special IDs. */
2091	uint16_t cMaxPages;
2092	/** The current pool size. */
2093	uint16_t cCurPages;
2094	/** The head of the free page list. */
2095	uint16_t iFreeHead;
2096	/* Padding. */
2097	uint16_t u16Padding;
2098	/** Head of the chain of free user nodes. */
2099	uint16_t iUserFreeHead;
2100	/** The number of user nodes we've allocated. */
2101	uint16_t cMaxUsers;
2102	/** The number of present page table entries in the entire pool. */
2103	uint32_t cPresent;
2104	/** Pointer to the array of user nodes - R3 pointer. */
2105	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2106	/** Pointer to the array of user nodes - R0 pointer. */
2107	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2108	/** Head of the chain of free phys ext nodes. */
2109	uint16_t iPhysExtFreeHead;
2110	/** The number of user nodes we've allocated. */
2111	uint16_t cMaxPhysExts;
2112	uint32_t u32Padding0b;
2113	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2114	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2115	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2116	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2117	/** Hash table for GCPhys addresses. */
2118	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2119	/** The head of the age list. */
2120	uint16_t iAgeHead;
2121	/** The tail of the age list. */
2122	uint16_t iAgeTail;
2123	/** Set if the cache is enabled. */
2124	bool fCacheEnabled;
2125	/** Alignment padding. */
2126	bool afPadding1[3];
2127	/** Head of the list of modified pages. */
2128	uint16_t iModifiedHead;
2129	/** The current number of modified pages. */
2130	uint16_t cModifiedPages;
2131	/** Alignment padding. */
2132	uint32_t u32Padding2;
2133	/** Physical access handler type registration handle. */
2134	PGMPHYSHANDLERTYPE hAccessHandlerType;
2135	/** Next available slot (in aDirtyPages). */
2136	uint32_t idxFreeDirtyPage;
2137	/** Number of active dirty pages. */
2138	uint32_t cDirtyPages;
2139	/** Array of current dirty pgm pool page indices. */
2140	uint16_t aidxDirtyPages[16];
2141	/** Array running in parallel to aidxDirtyPages with the page data. */
2142	struct
2143	{
2144	uint64_t aPage[512];
2145	} aDirtyPages[16];
2146
2147	/** The number of pages currently in use. */
2148	uint16_t cUsedPages;
2149	#ifdef VBOX_WITH_STATISTICS
2150	/** The high water mark for cUsedPages. */
2151	uint16_t cUsedPagesHigh;
2152	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2153	/** Profiling pgmPoolAlloc(). */
2154	STAMPROFILEADV StatAlloc;
2155	/** Profiling pgmR3PoolClearDoIt(). */
2156	STAMPROFILE StatClearAll;
2157	/** Profiling pgmR3PoolReset(). */
2158	STAMPROFILE StatR3Reset;
2159	/** Profiling pgmPoolFlushPage(). */
2160	STAMPROFILE StatFlushPage;
2161	/** Profiling pgmPoolFree(). */
2162	STAMPROFILE StatFree;
2163	/** Counting explicit flushes by PGMPoolFlushPage(). */
2164	STAMCOUNTER StatForceFlushPage;
2165	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2166	STAMCOUNTER StatForceFlushDirtyPage;
2167	/** Counting flushes for reused pages. */
2168	STAMCOUNTER StatForceFlushReused;
2169	/** Profiling time spent zeroing pages. */
2170	STAMPROFILE StatZeroPage;
2171	/** Profiling of pgmPoolTrackDeref. */
2172	STAMPROFILE StatTrackDeref;
2173	/** Profiling pgmTrackFlushGCPhysPT. */
2174	STAMPROFILE StatTrackFlushGCPhysPT;
2175	/** Profiling pgmTrackFlushGCPhysPTs. */
2176	STAMPROFILE StatTrackFlushGCPhysPTs;
2177	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2178	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2179	/** Number of times we've been out of user records. */
2180	STAMCOUNTER StatTrackFreeUpOneUser;
2181	/** Nr of flushed entries. */
2182	STAMCOUNTER StatTrackFlushEntry;
2183	/** Nr of updated entries. */
2184	STAMCOUNTER StatTrackFlushEntryKeep;
2185	/** Profiling deref activity related tracking GC physical pages. */
2186	STAMPROFILE StatTrackDerefGCPhys;
2187	/** Number of linear searches for a HCPhys in the ram ranges. */
2188	STAMCOUNTER StatTrackLinearRamSearches;
2189	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2190	STAMCOUNTER StamTrackPhysExtAllocFailures;
2191
2192	/** Profiling the RC/R0 \#PF access handler. */
2193	STAMPROFILE StatMonitorPfRZ;
2194	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2195	STAMPROFILE StatMonitorPfRZHandled;
2196	/** Times we've failed interpreting the instruction. */
2197	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2198	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2199	STAMPROFILE StatMonitorPfRZFlushPage;
2200	/** Times we've detected a page table reinit. */
2201	STAMCOUNTER StatMonitorPfRZFlushReinit;
2202	/** Counting flushes for pages that are modified too often. */
2203	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2204	/** Times we've detected fork(). */
2205	STAMCOUNTER StatMonitorPfRZFork;
2206	/** Times we've failed interpreting a patch code instruction. */
2207	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2208	/** Times we've failed interpreting a patch code instruction during flushing. */
2209	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2210	/** The number of times we've seen rep prefixes we can't handle. */
2211	STAMCOUNTER StatMonitorPfRZRepPrefix;
2212	/** Profiling the REP STOSD cases we've handled. */
2213	STAMPROFILE StatMonitorPfRZRepStosd;
2214
2215	/** Profiling the R0/RC regular access handler. */
2216	STAMPROFILE StatMonitorRZ;
2217	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2218	STAMPROFILE StatMonitorRZFlushPage;
2219	/** Per access size counts indexed by size minus 1, last for larger. */
2220	STAMCOUNTER aStatMonitorRZSizes[16+3];
2221	/** Missaligned access counts indexed by offset - 1. */
2222	STAMCOUNTER aStatMonitorRZMisaligned[7];
2223
2224	/** Nr of handled PT faults. */
2225	STAMCOUNTER StatMonitorRZFaultPT;
2226	/** Nr of handled PD faults. */
2227	STAMCOUNTER StatMonitorRZFaultPD;
2228	/** Nr of handled PDPT faults. */
2229	STAMCOUNTER StatMonitorRZFaultPDPT;
2230	/** Nr of handled PML4 faults. */
2231	STAMCOUNTER StatMonitorRZFaultPML4;
2232
2233	/** Profiling the R3 access handler. */
2234	STAMPROFILE StatMonitorR3;
2235	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2236	STAMPROFILE StatMonitorR3FlushPage;
2237	/** Per access size counts indexed by size minus 1, last for larger. */
2238	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2239	/** Missaligned access counts indexed by offset - 1. */
2240	STAMCOUNTER aStatMonitorR3Misaligned[7];
2241	/** Nr of handled PT faults. */
2242	STAMCOUNTER StatMonitorR3FaultPT;
2243	/** Nr of handled PD faults. */
2244	STAMCOUNTER StatMonitorR3FaultPD;
2245	/** Nr of handled PDPT faults. */
2246	STAMCOUNTER StatMonitorR3FaultPDPT;
2247	/** Nr of handled PML4 faults. */
2248	STAMCOUNTER StatMonitorR3FaultPML4;
2249
2250	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2251	STAMCOUNTER StatResetDirtyPages;
2252	/** Times we've called pgmPoolAddDirtyPage. */
2253	STAMCOUNTER StatDirtyPage;
2254	/** Times we've had to flush duplicates for dirty page management. */
2255	STAMCOUNTER StatDirtyPageDupFlush;
2256	/** Times we've had to flush because of overflow. */
2257	STAMCOUNTER StatDirtyPageOverFlowFlush;
2258
2259	/** The high water mark for cModifiedPages. */
2260	uint16_t cModifiedPagesHigh;
2261	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2262
2263	/** The number of cache hits. */
2264	STAMCOUNTER StatCacheHits;
2265	/** The number of cache misses. */
2266	STAMCOUNTER StatCacheMisses;
2267	/** The number of times we've got a conflict of 'kind' in the cache. */
2268	STAMCOUNTER StatCacheKindMismatches;
2269	/** Number of times we've been out of pages. */
2270	STAMCOUNTER StatCacheFreeUpOne;
2271	/** The number of cacheable allocations. */
2272	STAMCOUNTER StatCacheCacheable;
2273	/** The number of uncacheable allocations. */
2274	STAMCOUNTER StatCacheUncacheable;
2275	#else
2276	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2277	#endif
2278	/** Profiling PGMR0PoolGrow(). */
2279	STAMPROFILE StatGrow;
2280	/** The AVL tree for looking up a page by its HC physical address. */
2281	AVLOHCPHYSTREE HCPhysTree;
2282	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2283	/** Array of pages. (cMaxPages in length)
2284	* The Id is the index into thist array.
2285	*/
2286	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2287	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2288	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2289	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2290	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2291	#ifdef VBOX_WITH_STATISTICS
2292	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2293	#endif
2294	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2295
2296
2297	/** @def PGMPOOL_PAGE_2_PTR
2298	* Maps a pool page pool into the current context.
2299	*
2300	* @returns VBox status code.
2301	* @param a_pVM Pointer to the VM.
2302	* @param a_pPage The pool page.
2303	*
2304	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2305	* small page window employeed by that function. Be careful.
2306	* @remark There is no need to assert on the result.
2307	*/
2308	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2309	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2310	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2311	{
2312	RT_NOREF(pszCaller);
2313	AssertPtr(a_pPage);
2314	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2315	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2316	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2317	return a_pPage->CTX_SUFF(pvPage);
2318	}
2319	#else
2320	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2321	#endif
2322
2323
2324	/** @def PGMPOOL_PAGE_2_PTR_V2
2325	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2326	*
2327	* @returns VBox status code.
2328	* @param a_pVM Pointer to the VM.
2329	* @param a_pVCpu The current CPU.
2330	* @param a_pPage The pool page.
2331	*
2332	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2333	* small page window employeed by that function. Be careful.
2334	* @remark There is no need to assert on the result.
2335	*/
2336	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2337
2338
2339	/** @def PGMPOOL_PAGE_IS_NESTED
2340	* Checks whether the given pool page is a nested-guest pool page.
2341	*
2342	* @returns @c true if a nested-guest pool page, @c false otherwise.
2343	* @param a_pPage The pool page.
2344	* @todo We can optimize the conditionals later.
2345	*/
2346	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2347	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2348	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2349	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2350	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2351	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2352
2353	/** @name Per guest page tracking data.
2354	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2355	* is to use more bits for it and split it up later on. But for now we'll play
2356	* safe and change as little as possible.
2357	*
2358	* The 16-bit word has two parts:
2359	*
2360	* The first 14-bit forms the @a idx field. It is either the index of a page in
2361	* the shadow page pool, or and index into the extent list.
2362	*
2363	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2364	* shadow page pool references to the page. If cRefs equals
2365	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2366	* (misnomer) table and not the shadow page pool.
2367	*
2368	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2369	* the 16-bit word.
2370	*
2371	* @{ */
2372	/** The shift count for getting to the cRefs part. */
2373	#define PGMPOOL_TD_CREFS_SHIFT 14
2374	/** The mask applied after shifting the tracking data down by
2375	* PGMPOOL_TD_CREFS_SHIFT. */
2376	#define PGMPOOL_TD_CREFS_MASK 0x3
2377	/** The cRefs value used to indicate that the idx is the head of a
2378	* physical cross reference list. */
2379	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2380	/** The shift used to get idx. */
2381	#define PGMPOOL_TD_IDX_SHIFT 0
2382	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2383	#define PGMPOOL_TD_IDX_MASK 0x3fff
2384	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2385	* simply too many mappings of this page. */
2386	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2387
2388	/** @def PGMPOOL_TD_MAKE
2389	* Makes a 16-bit tracking data word.
2390	*
2391	* @returns tracking data.
2392	* @param cRefs The @a cRefs field. Must be within bounds!
2393	* @param idx The @a idx field. Must also be within bounds! */
2394	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2395
2396	/** @def PGMPOOL_TD_GET_CREFS
2397	* Get the @a cRefs field from a tracking data word.
2398	*
2399	* @returns The @a cRefs field
2400	* @param u16 The tracking data word.
2401	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2402	* non-zero @a u16. */
2403	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2404
2405	/** @def PGMPOOL_TD_GET_IDX
2406	* Get the @a idx field from a tracking data word.
2407	*
2408	* @returns The @a idx field
2409	* @param u16 The tracking data word. */
2410	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2411	/** @} */
2412
2413
2414
2415	/** @name A20 gate macros
2416	* @{ */
2417	#define PGM_WITH_A20
2418	#ifdef PGM_WITH_A20
2419	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2420	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2421	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2422	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2423	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2424	#else
2425	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2426	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2427	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2428	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2429	#endif
2430	/** @} */
2431
2432
2433	/**
2434	* Guest page table walk for the AMD64 mode.
2435	*/
2436	typedef struct PGMPTWALKGSTAMD64
2437	{
2438	PX86PML4 pPml4;
2439	PX86PML4E pPml4e;
2440	X86PML4E Pml4e;
2441
2442	PX86PDPT pPdpt;
2443	PX86PDPE pPdpe;
2444	X86PDPE Pdpe;
2445
2446	PX86PDPAE pPd;
2447	PX86PDEPAE pPde;
2448	X86PDEPAE Pde;
2449
2450	PX86PTPAE pPt;
2451	PX86PTEPAE pPte;
2452	X86PTEPAE Pte;
2453	} PGMPTWALKGSTAMD64;
2454	/** Pointer to a AMD64 guest page table walk. */
2455	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2456	/** Pointer to a const AMD64 guest page table walk. */
2457	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2458
2459	/**
2460	* Guest page table walk for the EPT mode.
2461	*/
2462	typedef struct PGMPTWALKGSTEPT
2463	{
2464	PEPTPML4 pPml4;
2465	PEPTPML4E pPml4e;
2466	EPTPML4E Pml4e;
2467
2468	PEPTPDPT pPdpt;
2469	PEPTPDPTE pPdpte;
2470	EPTPDPTE Pdpte;
2471
2472	PEPTPD pPd;
2473	PEPTPDE pPde;
2474	EPTPDE Pde;
2475
2476	PEPTPT pPt;
2477	PEPTPTE pPte;
2478	EPTPTE Pte;
2479	} PGMPTWALKGSTEPT;
2480	/** Pointer to an EPT guest page table walk. */
2481	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2482	/** Pointer to a const EPT guest page table walk. */
2483	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2484
2485	/**
2486	* Guest page table walk for the PAE mode.
2487	*/
2488	typedef struct PGMPTWALKGSTPAE
2489	{
2490	PX86PDPT pPdpt;
2491	PX86PDPE pPdpe;
2492	X86PDPE Pdpe;
2493
2494	PX86PDPAE pPd;
2495	PX86PDEPAE pPde;
2496	X86PDEPAE Pde;
2497
2498	PX86PTPAE pPt;
2499	PX86PTEPAE pPte;
2500	X86PTEPAE Pte;
2501	} PGMPTWALKGSTPAE;
2502	/** Pointer to a PAE guest page table walk. */
2503	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2504	/** Pointer to a const AMD64 guest page table walk. */
2505	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2506
2507	/**
2508	* Guest page table walk for the 32-bit mode.
2509	*/
2510	typedef struct PGMPTWALKGST32BIT
2511	{
2512	PX86PD pPd;
2513	PX86PDE pPde;
2514	X86PDE Pde;
2515
2516	PX86PT pPt;
2517	PX86PTE pPte;
2518	X86PTE Pte;
2519	} PGMPTWALKGST32BIT;
2520	/** Pointer to a 32-bit guest page table walk. */
2521	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2522	/** Pointer to a const 32-bit guest page table walk. */
2523	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2524
2525	/**
2526	* Which part of PGMPTWALKGST that is valid.
2527	*/
2528	typedef enum PGMPTWALKGSTTYPE
2529	{
2530	/** Customary invalid 0 value. */
2531	PGMPTWALKGSTTYPE_INVALID = 0,
2532	/** PGMPTWALKGST::u.Amd64 is valid. */
2533	PGMPTWALKGSTTYPE_AMD64,
2534	/** PGMPTWALKGST::u.Pae is valid. */
2535	PGMPTWALKGSTTYPE_PAE,
2536	/** PGMPTWALKGST::u.Legacy is valid. */
2537	PGMPTWALKGSTTYPE_32BIT,
2538	/** PGMPTWALKGST::u.Ept is valid. */
2539	PGMPTWALKGSTTYPE_EPT,
2540	/** Customary 32-bit type hack. */
2541	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2542	} PGMPTWALKGSTTYPE;
2543
2544	/**
2545	* Combined guest page table walk result.
2546	*/
2547	typedef struct PGMPTWALKGST
2548	{
2549	union
2550	{
2551	/** The page walker for AMD64. */
2552	PGMPTWALKGSTAMD64 Amd64;
2553	/** The page walker for PAE (32-bit). */
2554	PGMPTWALKGSTPAE Pae;
2555	/** The page walker for 32-bit paging (called legacy due to C naming
2556	* convension). */
2557	PGMPTWALKGST32BIT Legacy;
2558	/** The page walker for EPT (SLAT). */
2559	PGMPTWALKGSTEPT Ept;
2560	} u;
2561	/** Indicates which part of the union is valid. */
2562	PGMPTWALKGSTTYPE enmType;
2563	} PGMPTWALKGST;
2564	/** Pointer to a combined guest page table walk result. */
2565	typedef PGMPTWALKGST *PPGMPTWALKGST;
2566	/** Pointer to a read-only combined guest page table walk result. */
2567	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2568
2569
2570	/** @name Paging mode macros
2571	* @{
2572	*/
2573	#ifdef IN_RING3
2574	# define PGM_CTX(a,b) a##R3##b
2575	# define PGM_CTX_STR(a,b) a "R3" b
2576	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2577	#elif defined(IN_RING0)
2578	# define PGM_CTX(a,b) a##R0##b
2579	# define PGM_CTX_STR(a,b) a "R0" b
2580	# define PGM_CTX_DECL(type) VMMDECL(type)
2581	#else
2582	# error "Not IN_RING3 or IN_RING0!"
2583	#endif
2584
2585	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2586	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2587	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2588	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2589	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2590	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2591	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2592	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2593	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2594	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2595	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2596	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2597	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2598	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2599	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2600	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2601
2602	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2603	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2604	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2605	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2606
2607	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2608	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2609	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2610	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2611	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2612	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2613	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2614	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2615	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2616	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2617	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2618	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2619	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2620	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2621	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2622	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2623	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2624	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2625	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2626	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2627	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2628	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2629	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2630	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2631	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2632
2633	/* Shw_Gst */
2634	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2635	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2636	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2637	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2638	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2639	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2640	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2641	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2642	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2643	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2644	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2645	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2646	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2647	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2648	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2649	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2650	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2651	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2652	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2653	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2654	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2655	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2656	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2657	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2658	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2659	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2660	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2661	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2662	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2663	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2664	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2665	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2666	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2667	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2668
2669	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2670	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2671	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2672	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2673	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2674	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2675	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2676	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2677	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2678	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2679	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2680	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2681	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2682	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2683	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2684	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2685	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2686	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2687	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2688	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2689	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2690	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2691	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2692	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2693	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2694	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2695	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2696	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2697
2698	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2699	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2700	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2701	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2702	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2703	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2704	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2705	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2706	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2707	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2708	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2709	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2710	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2711	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2712	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2713	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2714	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2715	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2716	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2717	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2718	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2719	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2720	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2721	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2722	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2723	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2724	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2725	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2726	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2727
2728	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2729	/** @} */
2730
2731
2732	/**
2733	* Function pointers for guest paging.
2734	*/
2735	typedef struct PGMMODEDATAGST
2736	{
2737	/** The guest mode type. */
2738	uint32_t uType;
2739	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2740	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2741	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2742	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2743	#ifdef IN_RING3
2744	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2745	#endif
2746	} PGMMODEDATAGST;
2747
2748	/** The length of g_aPgmGuestModeData. */
2749	#if VBOX_WITH_64_BITS_GUESTS
2750	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2751	#else
2752	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2753	#endif
2754	/** The guest mode data array. */
2755	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2756
2757
2758	/**
2759	* Function pointers for shadow paging.
2760	*/
2761	typedef struct PGMMODEDATASHW
2762	{
2763	/** The shadow mode type. */
2764	uint32_t uType;
2765	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2766	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2767	uint64_t fMask, uint32_t fOpFlags));
2768	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2769	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2770	#ifdef IN_RING3
2771	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2772	#endif
2773	} PGMMODEDATASHW;
2774
2775	/** The length of g_aPgmShadowModeData. */
2776	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2777	/** The shadow mode data array. */
2778	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2779
2780
2781	/**
2782	* Function pointers for guest+shadow paging.
2783	*/
2784	typedef struct PGMMODEDATABTH
2785	{
2786	/** The shadow mode type. */
2787	uint32_t uShwType;
2788	/** The guest mode type. */
2789	uint32_t uGstType;
2790
2791	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2792	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2793	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2794	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2795	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2796	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2797	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2798	#ifndef IN_RING3
2799	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2800	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2801	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2802	bool *pfLockTaken));
2803	#endif
2804	#ifdef VBOX_STRICT
2805	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2806	#endif
2807	} PGMMODEDATABTH;
2808
2809	/** The length of g_aPgmBothModeData. */
2810	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2811	/** The guest+shadow mode data array. */
2812	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2813
2814
2815	#ifdef VBOX_WITH_STATISTICS
2816	/**
2817	* PGM statistics.
2818	*/
2819	typedef struct PGMSTATS
2820	{
2821	/* R3 only: */
2822	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2823	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2824
2825	/* R3+RZ */
2826	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2827	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2828	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2829	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2830	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2831	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2832	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2833	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2834	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2835	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2836	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2837	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2838	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2839	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2840	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2841	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2842	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2843	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2844	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2845	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2846	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2847	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2848	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2849	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2850	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2851	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2852
2853	/* RC only: */
2854	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2855	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2856
2857	STAMCOUNTER StatRZPhysRead;
2858	STAMCOUNTER StatRZPhysReadBytes;
2859	STAMCOUNTER StatRZPhysWrite;
2860	STAMCOUNTER StatRZPhysWriteBytes;
2861	STAMCOUNTER StatR3PhysRead;
2862	STAMCOUNTER StatR3PhysReadBytes;
2863	STAMCOUNTER StatR3PhysWrite;
2864	STAMCOUNTER StatR3PhysWriteBytes;
2865	STAMCOUNTER StatRCPhysRead;
2866	STAMCOUNTER StatRCPhysReadBytes;
2867	STAMCOUNTER StatRCPhysWrite;
2868	STAMCOUNTER StatRCPhysWriteBytes;
2869
2870	STAMCOUNTER StatRZPhysSimpleRead;
2871	STAMCOUNTER StatRZPhysSimpleReadBytes;
2872	STAMCOUNTER StatRZPhysSimpleWrite;
2873	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2874	STAMCOUNTER StatR3PhysSimpleRead;
2875	STAMCOUNTER StatR3PhysSimpleReadBytes;
2876	STAMCOUNTER StatR3PhysSimpleWrite;
2877	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2878	STAMCOUNTER StatRCPhysSimpleRead;
2879	STAMCOUNTER StatRCPhysSimpleReadBytes;
2880	STAMCOUNTER StatRCPhysSimpleWrite;
2881	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2882
2883	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2884	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2885	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2886	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2887	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2888	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2889	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2890
2891	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2892	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2893	/** pgmPhysIsValidLargePage profiling - R3 */
2894	STAMPROFILE StatR3IsValidLargePage;
2895	/** pgmPhysIsValidLargePage profiling - RZ*/
2896	STAMPROFILE StatRZIsValidLargePage;
2897
2898	STAMPROFILE StatChunkAging;
2899	STAMPROFILE StatChunkFindCandidate;
2900	STAMPROFILE StatChunkUnmap;
2901	STAMPROFILE StatChunkMap;
2902	} PGMSTATS;
2903	#endif /* VBOX_WITH_STATISTICS */
2904
2905
2906	/**
2907	* PGM Data (part of VM)
2908	*/
2909	typedef struct PGM
2910	{
2911	/** The zero page. */
2912	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2913	/** The MMIO placeholder page. */
2914	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2915
2916	/** @name The zero page (abPagePg).
2917	* @{ */
2918	/** The host physical address of the zero page. */
2919	RTHCPHYS HCPhysZeroPg;
2920	/** @}*/
2921
2922	/** @name The Invalid MMIO page (abMmioPg).
2923	* This page is filled with 0xfeedface.
2924	* @{ */
2925	/** The host physical address of the invalid MMIO page. */
2926	RTHCPHYS HCPhysMmioPg;
2927	/** The host pysical address of the invalid MMIO page plus all invalid
2928	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2929	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2930	RTHCPHYS HCPhysInvMmioPg;
2931	/** @} */
2932
2933	/** @cfgm{/RamPreAlloc, boolean, false}
2934	* Indicates whether the base RAM should all be allocated before starting
2935	* the VM (default), or if it should be allocated when first written to.
2936	*/
2937	bool fRamPreAlloc;
2938	#ifdef VBOX_WITH_PGM_NEM_MODE
2939	/** Set if we're operating in NEM memory mode.
2940	*
2941	* NEM mode implies that memory is allocated in big chunks for each RAM range
2942	* rather than on demand page by page. Memory is also not locked and PGM has
2943	* therefore no physical addresses for them. Page sharing is out of the
2944	* question. Ballooning depends on the native execution engine, but probably
2945	* pointless as well. */
2946	bool fNemMode;
2947	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2948	#else
2949	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2950	#endif
2951	/** Indicates whether write monitoring is currently in use.
2952	* This is used to prevent conflicts between live saving and page sharing
2953	* detection. */
2954	bool fPhysWriteMonitoringEngaged;
2955	/** Set if the CPU has less than 52-bit physical address width.
2956	* This is used */
2957	bool fLessThan52PhysicalAddressBits;
2958	/** Set when nested paging is active.
2959	* This is meant to save calls to HMIsNestedPagingActive and let the
2960	* compilers optimize the code better. Whether we use nested paging or
2961	* not is something we find out during VMM initialization and we won't
2962	* change this later on. */
2963	bool fNestedPaging;
2964	/** We're not in a state which permits writes to guest memory.
2965	* (Only used in strict builds.) */
2966	bool fNoMorePhysWrites;
2967	/** @cfgm{/PageFusionAllowed, boolean, false}
2968	* Whether page fusion is allowed. */
2969	bool fPageFusionAllowed;
2970	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2971	* Whether PCI passthrough is enabled. */
2972	bool fPciPassthrough;
2973	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2974	uint8_t cMmio2Regions;
2975	/** Restore original ROM page content when resetting after loading state.
2976	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2977	* enables the VM to start using an updated ROM without requiring powering
2978	* down the VM, just rebooting or resetting it. */
2979	bool fRestoreRomPagesOnReset;
2980	/** Whether to automatically clear all RAM pages on reset. */
2981	bool fZeroRamPagesOnReset;
2982	/** Large page enabled flag. */
2983	bool fUseLargePages;
2984	/** Alignment padding. */
2985	#ifndef VBOX_WITH_PGM_NEM_MODE
2986	bool afAlignment3[1];
2987	#endif
2988	/** The host paging mode. (This is what SUPLib reports.) */
2989	SUPPAGINGMODE enmHostMode;
2990	bool afAlignment3b[2];
2991
2992	/** Generation ID for the RAM ranges. This member is incremented everytime
2993	* a RAM range is linked or unlinked. */
2994	uint32_t volatile idRamRangesGen;
2995
2996	/** Physical access handler type for ROM protection. */
2997	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2998	/** Physical access handler type for MMIO2 dirty page tracing. */
2999	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3000
3001	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3002	RTGCPHYS GCPhys4MBPSEMask;
3003	/** Mask containing the invalid bits of a guest physical address.
3004	* @remarks this does not stop at bit 52. */
3005	RTGCPHYS GCPhysInvAddrMask;
3006
3007
3008	/** RAM range TLB for R3. */
3009	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3010	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3011	* This is sorted by physical address and contains no overlapping ranges. */
3012	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3013	/** Root of the RAM range search tree for ring-3. */
3014	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3015	/** Shadow Page Pool - R3 Ptr. */
3016	R3PTRTYPE(PPGMPOOL) pPoolR3;
3017	/** Pointer to the list of ROM ranges - for R3.
3018	* This is sorted by physical address and contains no overlapping ranges. */
3019	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3020	/** Pointer to the list of MMIO2 ranges - for R3.
3021	* Registration order. */
3022	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3023	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3024	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3025
3026	/** RAM range TLB for R0. */
3027	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3028	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3029	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3030	/** Root of the RAM range search tree for ring-0. */
3031	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3032	/** Shadow Page Pool - R0 Ptr. */
3033	R0PTRTYPE(PPGMPOOL) pPoolR0;
3034	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3035	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3036	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3037	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3038
3039	/** Hack: Number of deprecated page mapping locks taken by the current lock
3040	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3041	uint32_t cDeprecatedPageLocks;
3042
3043	/** Registered physical access handler types. */
3044	uint32_t cPhysHandlerTypes;
3045	/** Physical access handler types.
3046	* Initialized to callback causing guru meditations and invalid enmKind. */
3047	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3048	/** Physical handler allocator, ring-3 edition. */
3049	#ifdef IN_RING3
3050	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3051	#else
3052	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3053	#endif
3054	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3055	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3056	/** Caching the last physical handler we looked. */
3057	uint32_t idxLastPhysHandler;
3058
3059	uint32_t au64Padding3[5];
3060
3061	/** PGM critical section.
3062	* This protects the physical, ram ranges, and the page flag updating (some of
3063	* it anyway).
3064	*/
3065	PDMCRITSECT CritSectX;
3066
3067	/**
3068	* Data associated with managing the ring-3 mappings of the allocation chunks.
3069	*/
3070	struct
3071	{
3072	/** The chunk mapping TLB. */
3073	PGMCHUNKR3MAPTLB Tlb;
3074	/** The chunk tree, ordered by chunk id. */
3075	R3PTRTYPE(PAVLU32NODECORE) pTree;
3076	#if HC_ARCH_BITS == 32
3077	uint32_t u32Alignment0;
3078	#endif
3079	/** The number of mapped chunks. */
3080	uint32_t c;
3081	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3082	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3083	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3084	uint32_t cMax;
3085	/** The current time. This is incremented whenever a chunk is inserted. */
3086	uint32_t iNow;
3087	/** Alignment padding. */
3088	uint32_t au32Alignment1[3];
3089	} ChunkR3Map;
3090
3091	/** The page mapping TLB for ring-3. */
3092	PGMPAGER3MAPTLB PhysTlbR3;
3093	/** The page mapping TLB for ring-0. */
3094	PGMPAGER0MAPTLB PhysTlbR0;
3095
3096	/** The number of handy pages. */
3097	uint32_t cHandyPages;
3098
3099	/** The number of large handy pages. */
3100	uint32_t cLargeHandyPages;
3101
3102	/**
3103	* Array of handy pages.
3104	*
3105	* This array is used in a two way communication between pgmPhysAllocPage
3106	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3107	* an intermediary.
3108	*
3109	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3110	* (The current size of 32 pages, means 128 KB of handy memory.)
3111	*/
3112	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3113
3114	/**
3115	* Array of large handy pages. (currently size 1)
3116	*
3117	* This array is used in a two way communication between pgmPhysAllocLargePage
3118	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3119	* an intermediary.
3120	*/
3121	GMMPAGEDESC aLargeHandyPage[1];
3122	/** When to try allocate large pages again after a failure. */
3123	uint64_t nsLargePageRetry;
3124	/** Number of repeated long allocation times. */
3125	uint32_t cLargePageLongAllocRepeats;
3126	uint32_t uPadding5;
3127
3128	/**
3129	* Live save data.
3130	*/
3131	struct
3132	{
3133	/** Per type statistics. */
3134	struct
3135	{
3136	/** The number of ready pages. */
3137	uint32_t cReadyPages;
3138	/** The number of dirty pages. */
3139	uint32_t cDirtyPages;
3140	/** The number of ready zero pages. */
3141	uint32_t cZeroPages;
3142	/** The number of write monitored pages. */
3143	uint32_t cMonitoredPages;
3144	} Rom,
3145	Mmio2,
3146	Ram;
3147	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3148	uint32_t cIgnoredPages;
3149	/** Indicates that a live save operation is active. */
3150	bool fActive;
3151	/** Padding. */
3152	bool afReserved[2];
3153	/** The next history index. */
3154	uint8_t iDirtyPagesHistory;
3155	/** History of the total amount of dirty pages. */
3156	uint32_t acDirtyPagesHistory[64];
3157	/** Short term dirty page average. */
3158	uint32_t cDirtyPagesShort;
3159	/** Long term dirty page average. */
3160	uint32_t cDirtyPagesLong;
3161	/** The number of saved pages. This is used to get some kind of estimate of the
3162	* link speed so we can decide when we're done. It is reset after the first
3163	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3164	* zero pages. */
3165	uint64_t cSavedPages;
3166	/** The nanosecond timestamp when cSavedPages was 0. */
3167	uint64_t uSaveStartNS;
3168	/** Pages per second (for statistics). */
3169	uint32_t cPagesPerSecond;
3170	uint32_t cAlignment;
3171	} LiveSave;
3172
3173	/** @name Error injection.
3174	* @{ */
3175	/** Inject handy page allocation errors pretending we're completely out of
3176	* memory. */
3177	bool volatile fErrInjHandyPages;
3178	/** Padding. */
3179	bool afReserved[3];
3180	/** @} */
3181
3182	/** @name Release Statistics
3183	* @{ */
3184	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3185	uint32_t cPrivatePages; /*< The number of private pages. /
3186	uint32_t cSharedPages; /*< The number of shared pages. /
3187	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3188	uint32_t cZeroPages; /*< The number of zero backed pages. /
3189	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3190	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3191	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3192	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3193	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3194	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3195	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3196	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3197	uint32_t cLargePages; /*< The number of large pages. /
3198	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3199	/* uint32_t aAlignment4[1]; */
3200
3201	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3202	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3203	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3204	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3205	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3206	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3207	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3208	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3209
3210	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3211
3212	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3213	/** @} */
3214
3215	#ifdef VBOX_WITH_STATISTICS
3216	/** These are optional statistics that used to be on the hyper heap. */
3217	PGMSTATS Stats;
3218	#endif
3219	} PGM;
3220	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3221	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3222	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3223	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3224	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3225	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3226	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3227	#endif /* !IN_TSTVMSTRUCTGC */
3228	/** Pointer to the PGM instance data. */
3229	typedef PGM *PPGM;
3230
3231
3232	#ifdef VBOX_WITH_STATISTICS
3233	/**
3234	* Per CPU statistis for PGM (used to be on the heap).
3235	*/
3236	typedef struct PGMCPUSTATS
3237	{
3238	/* Common */
3239	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3240	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3241
3242	/* R0 only: */
3243	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3244	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3245
3246	/* RZ only: */
3247	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3248	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3249	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3250	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3251	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3252	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3253	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3254	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3255	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3256	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3257	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3258	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3259	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3260	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3261	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3262	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3263	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3264	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3265	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3266	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3267	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3268	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3269	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3270	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3271	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3272	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3273	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3274	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3275	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3276	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3277	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3278	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3279	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3280	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3281	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3282	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3283	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3284	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3285	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3286	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3287	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3288	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3289	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3290	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3291	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3292	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3293	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3294	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3295	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3296	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3297	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3298	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3299	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3300	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3301	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3302	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3303	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3304	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3305	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3306	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3307	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3308	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3309	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3310	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3311	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3312	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3313	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3314	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3315	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3316	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3317
3318	/* HC - R3 and (maybe) R0: */
3319
3320	/* RZ & R3: */
3321	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3322	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3323	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3324	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3325	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3326	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3327	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3328	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3329	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3330	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3331	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3332	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3333	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3334	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3335	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3336	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3337	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3338	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3339	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3340	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3341	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3342	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3343	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3344	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3345	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3346	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3347	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3348	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3349	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3350	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3351	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3352	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3353	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3354	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3355	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3356	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3357	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3358	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3359	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3360	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3361	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3362	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3363	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3364	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3365	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3366	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3367	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3368
3369	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3370	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3371	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3372	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3373	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3374	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3375	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3376	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3377	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3378	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3379	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3380	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3381	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3382	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3383	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3384	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3385	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3386	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3387	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3388	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3389	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3390	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3391	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3392	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3393	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3394	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3395	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3396	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3397	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3398	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3399	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3400	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3401	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3402	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3403	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3404	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3405	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3406	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3407	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3408	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3409	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3410	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3411	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3412	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3413	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3414	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3415	} PGMCPUSTATS;
3416	#endif /* VBOX_WITH_STATISTICS */
3417
3418
3419	/**
3420	* PGMCPU Data (part of VMCPU).
3421	*/
3422	typedef struct PGMCPU
3423	{
3424	/** A20 gate mask.
3425	* Our current approach to A20 emulation is to let REM do it and don't bother
3426	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3427	* But whould need arrise, we'll subject physical addresses to this mask. */
3428	RTGCPHYS GCPhysA20Mask;
3429	/** A20 gate state - boolean! */
3430	bool fA20Enabled;
3431	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3432	bool fNoExecuteEnabled;
3433	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3434	* active. */
3435	bool fPaePdpesAndCr3MappedR3;
3436	bool fPaePdpesAndCr3MappedR0;
3437
3438	/** What needs syncing (PGM_SYNC_*).
3439	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3440	* PGMFlushTLB, and PGMR3Load. */
3441	uint32_t fSyncFlags;
3442
3443	/** The shadow paging mode. */
3444	PGMMODE enmShadowMode;
3445	/** The guest paging mode. */
3446	PGMMODE enmGuestMode;
3447	/** The guest second level address translation mode. */
3448	PGMSLAT enmGuestSlatMode;
3449	/** Guest mode data table index (PGM_TYPE_XXX). */
3450	uint8_t volatile idxGuestModeData;
3451	/** Shadow mode data table index (PGM_TYPE_XXX). */
3452	uint8_t volatile idxShadowModeData;
3453	/** Both mode data table index (complicated). */
3454	uint8_t volatile idxBothModeData;
3455	/** Alignment padding. */
3456	uint8_t abPadding[1];
3457
3458	/** The guest CR3.
3459	* When SLAT is active, this is the translated physical address.
3460	* When SLAT is inactive, this is the physical address in CR3. */
3461	RTGCPHYS GCPhysCR3;
3462
3463	/** The nested-guest CR3.
3464	* When SLAT is active, this is CR3 prior to translation.
3465	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3466	RTGCPHYS GCPhysNstGstCR3;
3467
3468	/** The cached guest CR3 when it has been mapped in PAE mode.
3469	* This allows us to skip remapping the CR3 and PAE PDPEs
3470	* (in PGMFlushTLB or similar) when it was already done as
3471	* part of MOV CRx instruction emulation.
3472	*/
3473	RTGCPHYS GCPhysPaeCR3;
3474
3475	/** @name 32-bit Guest Paging.
3476	* @{ */
3477	/** The guest's page directory, R3 pointer. */
3478	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3479	/** The guest's page directory, R0 pointer. */
3480	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3481	/** Mask containing the MBZ bits of a big page PDE. */
3482	uint32_t fGst32BitMbzBigPdeMask;
3483	/** Set if the page size extension (PSE) is enabled. */
3484	bool fGst32BitPageSizeExtension;
3485	/** Alignment padding. */
3486	bool afAlignment2[3];
3487	/** @} */
3488
3489	/** @name PAE Guest Paging.
3490	* @{ */
3491	/** The guest's page directory pointer table, R3 pointer. */
3492	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3493	/** The guest's page directory pointer table, R0 pointer. */
3494	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3495
3496	/** The guest's page directories, R3 pointers.
3497	* These are individual pointers and don't have to be adjacent.
3498	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3499	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3500	/** The guest's page directories, R0 pointers.
3501	* Same restrictions as apGstPaePDsR3. */
3502	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3503	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3504	RTGCPHYS aGCPhysGstPaePDs[4];
3505	/** Mask containing the MBZ PTE bits. */
3506	uint64_t fGstPaeMbzPteMask;
3507	/** Mask containing the MBZ PDE bits. */
3508	uint64_t fGstPaeMbzPdeMask;
3509	/** Mask containing the MBZ big page PDE bits. */
3510	uint64_t fGstPaeMbzBigPdeMask;
3511	/** Mask containing the MBZ PDPE bits. */
3512	uint64_t fGstPaeMbzPdpeMask;
3513	/** @} */
3514
3515	/** @name AMD64 Guest Paging.
3516	* @{ */
3517	/** The guest's page directory pointer table, R3 pointer. */
3518	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3519	/** The guest's page directory pointer table, R0 pointer. */
3520	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3521	/** Mask containing the MBZ PTE bits. */
3522	uint64_t fGstAmd64MbzPteMask;
3523	/** Mask containing the MBZ PDE bits. */
3524	uint64_t fGstAmd64MbzPdeMask;
3525	/** Mask containing the MBZ big page PDE bits. */
3526	uint64_t fGstAmd64MbzBigPdeMask;
3527	/** Mask containing the MBZ PDPE bits. */
3528	uint64_t fGstAmd64MbzPdpeMask;
3529	/** Mask containing the MBZ big page PDPE bits. */
3530	uint64_t fGstAmd64MbzBigPdpeMask;
3531	/** Mask containing the MBZ PML4E bits. */
3532	uint64_t fGstAmd64MbzPml4eMask;
3533	/** Mask containing the PDPE bits that we shadow. */
3534	uint64_t fGstAmd64ShadowedPdpeMask;
3535	/** Mask containing the PML4E bits that we shadow. */
3536	uint64_t fGstAmd64ShadowedPml4eMask;
3537	/** @} */
3538
3539	/** @name PAE and AMD64 Guest Paging.
3540	* @{ */
3541	/** Mask containing the PTE bits that we shadow. */
3542	uint64_t fGst64ShadowedPteMask;
3543	/** Mask containing the PDE bits that we shadow. */
3544	uint64_t fGst64ShadowedPdeMask;
3545	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3546	uint64_t fGst64ShadowedBigPdeMask;
3547	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3548	uint64_t fGst64ShadowedBigPde4PteMask;
3549	/** @} */
3550
3551	/** @name EPT Guest Paging.
3552	* @{ */
3553	/** The guest's EPT PML4 table, R3 pointer. */
3554	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3555	/** The guest's EPT PML4 table, R0 pointer. */
3556	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3557	/** The guest's EPT pointer (copy of virtual VMCS). */
3558	uint64_t uEptPtr;
3559	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3560	* change through the lifetime of the VM. */
3561	uint64_t uEptVpidCapMsr;
3562	/** Mask containing the MBZ PTE bits. */
3563	uint64_t fGstEptMbzPteMask;
3564	/** Mask containing the MBZ PDE bits. */
3565	uint64_t fGstEptMbzPdeMask;
3566	/** Mask containing the MBZ big page (2M) PDE bits. */
3567	uint64_t fGstEptMbzBigPdeMask;
3568	/** Mask containing the MBZ PDPTE bits. */
3569	uint64_t fGstEptMbzPdpteMask;
3570	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3571	uint64_t fGstEptMbzBigPdpteMask;
3572	/** Mask containing the MBZ PML4E bits. */
3573	uint64_t fGstEptMbzPml4eMask;
3574	/** Mask to determine whether an entry is present. */
3575	uint64_t fGstEptPresentMask;
3576
3577	/** Mask containing the EPT PTE bits we shadow. */
3578	uint64_t fGstEptShadowedPteMask;
3579	/** Mask containing the EPT PDE bits we shadow. */
3580	uint64_t fGstEptShadowedPdeMask;
3581	/** Mask containing the EPT PDE (2M) bits we shadow. */
3582	uint64_t fGstEptShadowedBigPdeMask;
3583	/** Mask containing the EPT PDPTE bits we shadow. */
3584	uint64_t fGstEptShadowedPdpteMask;
3585	/** Mask containing the EPT PML4E bits we shadow. */
3586	uint64_t fGstEptShadowedPml4eMask;
3587	/** @} */
3588
3589	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3590	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3591	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3592	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3593
3594	/** For saving stack space, the disassembler state is allocated here instead of
3595	* on the stack. */
3596	DISCPUSTATE DisState;
3597
3598	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3599	uint64_t cNetwareWp0Hacks;
3600
3601	/** Count the number of pgm pool access handler calls. */
3602	uint64_t cPoolAccessHandler;
3603
3604	/** @name Release Statistics
3605	* @{ */
3606	/** The number of times the guest has switched mode since last reset or statistics reset. */
3607	STAMCOUNTER cGuestModeChanges;
3608	/** The number of times the guest has switched mode since last reset or statistics reset. */
3609	STAMCOUNTER cA20Changes;
3610	/** @} */
3611
3612	#ifdef VBOX_WITH_STATISTICS
3613	/** These are statistics that used to be on the hyper heap. */
3614	PGMCPUSTATS Stats;
3615	#endif
3616	} PGMCPU;
3617	/** Pointer to the per-cpu PGM data. */
3618	typedef PGMCPU *PPGMCPU;
3619
3620
3621	/** @name PGM::fSyncFlags Flags
3622	* @note Was part of saved state a long time ago.
3623	* @{
3624	*/
3625	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3626	/** Always sync CR3. */
3627	#define PGM_SYNC_ALWAYS RT_BIT(1)
3628	/** Check guest mapping in SyncCR3. */
3629	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3630	/** Clear the page pool (a light weight flush). */
3631	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3632	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3633	/** @} */
3634
3635
3636	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3637
3638	/**
3639	* PGM GVMCPU instance data.
3640	*/
3641	typedef struct PGMR0PERVCPU
3642	{
3643	# ifdef VBOX_WITH_STATISTICS
3644	/** R0: Which statistic this \#PF should be attributed to. */
3645	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3646	# endif
3647	uint64_t u64Dummy;
3648	} PGMR0PERVCPU;
3649
3650
3651	/**
3652	* PGM GVM instance data.
3653	*/
3654	typedef struct PGMR0PERVM
3655	{
3656	/** @name PGM Pool related stuff.
3657	* @{ */
3658	/** Critical section for serializing pool growth. */
3659	RTCRITSECT PoolGrowCritSect;
3660	/** The memory objects for the pool pages. */
3661	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3662	/** The ring-3 mapping objects for the pool pages. */
3663	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3664	/** @} */
3665
3666	/** Physical access handler types for ring-0.
3667	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3668	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3669	/** Physical handler allocator, ring-3 edition. */
3670	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3671	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3672	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3673	/** The allocation object for the physical access handler tree. */
3674	RTR0MEMOBJ hPhysHandlerMemObj;
3675	/** The ring-3 mapping object for the physicall access handler tree. */
3676	RTR0MEMOBJ hPhysHandlerMapObj;
3677	} PGMR0PERVM;
3678
3679	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3680
3681	RT_C_DECLS_BEGIN
3682
3683	#if defined(VBOX_STRICT)
3684	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3685	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3686	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3687	#else
3688	int pgmLock(PVMCC pVM, bool fVoid);
3689	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3690	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3691	#endif
3692	void pgmUnlock(PVMCC pVM);
3693	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3694	/**
3695	* Asserts that the caller owns the PDM lock.
3696	* This is the internal variant of PGMIsLockOwner.
3697	* @param a_pVM Pointer to the VM.
3698	*/
3699	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3700	/**
3701	* Asserts that the caller owns the PDM lock.
3702	* This is the internal variant of PGMIsLockOwner.
3703	* @param a_pVM Pointer to the VM.
3704	* @param a_pVCpu The current CPU handle.
3705	*/
3706	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3707
3708	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3709	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3710	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3711	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3712	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3713	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3714	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3715	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3716	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3717	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3718	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3719	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3720	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3721	#ifndef IN_RING3
3722	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3723	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3724	#endif
3725
3726	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3727
3728	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3729	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3730	#ifdef IN_RING0
3731	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3732	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3733	#endif
3734	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3735	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3736	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3737	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3738	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3739	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3740	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3741	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3742	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3743	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3744	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3745	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3746	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3747	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3748	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3749	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3750	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3751	#ifndef IN_RING3
3752	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3753	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3754	#endif
3755	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3756	PGMPAGETYPE enmNewType);
3757	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3758	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3759	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3760	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3761	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3762	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3763	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3764	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3765	#ifdef VBOX_WITH_NATIVE_NEM
3766	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3767	#endif
3768
3769	#ifdef IN_RING3
3770	void pgmR3PhysRelinkRamRanges(PVM pVM);
3771	int pgmR3PhysRamPreAllocate(PVM pVM);
3772	int pgmR3PhysRamReset(PVM pVM);
3773	int pgmR3PhysRomReset(PVM pVM);
3774	int pgmR3PhysRamZeroAll(PVM pVM);
3775	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3776	int pgmR3PhysRamTerm(PVM pVM);
3777	void pgmR3PhysRomTerm(PVM pVM);
3778	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3779
3780	int pgmR3PoolInit(PVM pVM);
3781	void pgmR3PoolRelocate(PVM pVM);
3782	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3783	void pgmR3PoolReset(PVM pVM);
3784	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3785	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3786	void pgmR3PoolWriteProtectPages(PVM pVM);
3787
3788	#endif /* IN_RING3 */
3789	#ifdef IN_RING0
3790	int pgmR0PoolInitVM(PGVM pGVM);
3791	#endif
3792	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3793	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3794	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3795	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3796	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3797	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3798	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3799	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3800	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3801	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3802	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3803	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3804	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3805	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3806	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3807	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3808	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3809	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3810	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3811	#ifndef IN_RING3
3812	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3813	#endif
3814
3815	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3816	void pgmPoolResetDirtyPages(PVMCC pVM);
3817	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3818
3819	/** Gets the ring-0 pointer for the given pool page. */
3820	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3821	{
3822	#ifdef IN_RING3
3823	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3824	# ifdef VBOX_STRICT
3825	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3826	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3827	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3828	# endif
3829	return pPool->pPoolR0 + offPage;
3830	#else
3831	RT_NOREF(pPool);
3832	return pPage;
3833	#endif
3834	}
3835
3836	/** Gets the ring-3 pointer for the given pool page. */
3837	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3838	{
3839	#ifdef IN_RING3
3840	RT_NOREF(pPool);
3841	return pPage;
3842	#else
3843	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3844	# ifdef VBOX_STRICT
3845	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3846	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3847	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3848	# endif
3849	return pPool->pPoolR3 + offPage;
3850	#endif
3851	}
3852
3853	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3854	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3855	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3856
3857	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3858	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3859	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3860
3861	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3862	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3863	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3864	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3865	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3866	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3867	#endif
3868	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3869	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3870
3871	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3872	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3873	FNDBGCCMD pgmR3CmdShowSharedModules;
3874	# endif
3875
3876	void pgmLogState(PVM pVM);
3877
3878	RT_C_DECLS_END
3879
3880	/** @} */
3881
3882	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3883

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 97405

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