PGMInternal.h@ 96933

Last change on this file since 96933 was 96900, checked in by vboxsync, 2 years ago
VMM/PGM: Drop the fIs64BitsPagingMode parameter to PGM_SHW_DECL(int, Enter), it was for 32-bit AMD-V hosts. bugref:10092
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1	/* $Id: PGMInternal.h 96900 2022-09-27 13:30:45Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	//#if 0 /* disabled again while debugging */
79	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	//#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/**
118	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119	*/
120	#define PGM_MAX_PHYSCACHE_ENTRIES 64
121	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124	/** @def PGMPOOL_CFG_MAX_GROW
125	* The maximum number of pages to add to the pool in one go.
126	*/
127	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
131	*/
132	#ifdef VBOX_STRICT
133	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134	#endif
135
136	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137	* Enables the experimental lazy page allocation code. */
138	#ifdef DOXYGEN_RUNNING
139	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
140	#endif
141
142	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
143	* Enables real write monitoring of pages, i.e. mapping them read-only and
144	* only making them writable when getting a write access \#PF. */
145	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
146
147	/** @def VBOX_WITH_PGM_NEM_MODE
148	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
149	* details. */
150	#ifdef DOXYGEN_RUNNING
151	# define VBOX_WITH_PGM_NEM_MODE
152	#endif
153
154	/** @} */
155
156
157	/** @name PDPT and PML4 flags.
158	* These are placed in the three bits available for system programs in
159	* the PDPT and PML4 entries.
160	* @{ */
161	/** The entry is a permanent one and it's must always be present.
162	* Never free such an entry. */
163	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
164	/** PGM specific bits in PML4 entries. */
165	#define PGM_PML4_FLAGS 0
166	/** PGM specific bits in PDPT entries. */
167	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
168	/** @} */
169
170	/** @name Page directory flags.
171	* These are placed in the three bits available for system programs in
172	* the page directory entries.
173	* @{ */
174	/** Indicates the original entry was a big page.
175	* @remarks This is currently only used for statistics and can be recycled. */
176	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
177	/** Made read-only to facilitate dirty bit tracking. */
178	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
179	/** @} */
180
181	/** @name Page flags.
182	* These are placed in the three bits available for system programs in
183	* the page entries.
184	* @{ */
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
187
188	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
189	/** Scanned and approved by CSAM (tm).
190	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
191	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
192	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
193	#endif
194
195	/** @} */
196
197	/** @name Defines used to indicate the shadow and guest paging in the templates.
198	* @{ */
199	#define PGM_TYPE_REAL 1
200	#define PGM_TYPE_PROT 2
201	#define PGM_TYPE_32BIT 3
202	#define PGM_TYPE_PAE 4
203	#define PGM_TYPE_AMD64 5
204	#define PGM_TYPE_NESTED_32BIT 6
205	#define PGM_TYPE_NESTED_PAE 7
206	#define PGM_TYPE_NESTED_AMD64 8
207	#define PGM_TYPE_EPT 9
208	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
209	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
210	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
211	/** @} */
212
213	/** @name Defines used to indicate the second-level
214	* address translation (SLAT) modes in the templates.
215	* @{ */
216	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
217	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
218	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
219	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
220	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
221	/** @} */
222
223	/** Macro for checking if the guest is using paging.
224	* @param uGstType PGM_TYPE_*
225	* @param uShwType PGM_TYPE_*
226	* @remark ASSUMES certain order of the PGM_TYPE_* values.
227	*/
228	#define PGM_WITH_PAGING(uGstType, uShwType) \
229	( (uGstType) >= PGM_TYPE_32BIT \
230	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
231
232	/** Macro for checking if the guest supports the NX bit.
233	* @param uGstType PGM_TYPE_*
234	* @param uShwType PGM_TYPE_*
235	* @remark ASSUMES certain order of the PGM_TYPE_* values.
236	*/
237	#define PGM_WITH_NX(uGstType, uShwType) \
238	( (uGstType) >= PGM_TYPE_PAE \
239	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
240
241	/** Macro for checking for nested.
242	* @param uType PGM_TYPE_*
243	*/
244	#define PGM_TYPE_IS_NESTED(uType) \
245	( (uType) == PGM_TYPE_NESTED_32BIT \
246	\|\| (uType) == PGM_TYPE_NESTED_PAE \
247	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
248
249	/** Macro for checking for nested or EPT.
250	* @param uType PGM_TYPE_*
251	*/
252	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
253	( (uType) == PGM_TYPE_NESTED_32BIT \
254	\|\| (uType) == PGM_TYPE_NESTED_PAE \
255	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
256	\|\| (uType) == PGM_TYPE_EPT)
257
258
259
260	/** @def PGM_HCPHYS_2_PTR
261	* Maps a HC physical page pool address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM The cross context VM structure.
265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
266	* @param HCPhys The HC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast
268	* this.
269	*
270	* @remark There is no need to assert on the result.
271	*/
272	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
273
274	/** @def PGM_GCPHYS_2_PTR_V2
275	* Maps a GC physical page address to a virtual address.
276	*
277	* @returns VBox status code.
278	* @param pVM The cross context VM structure.
279	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
280	* @param GCPhys The GC physical address to map to a virtual one.
281	* @param ppv Where to store the virtual address. No need to cast this.
282	*
283	* @remark Use with care as we don't have so much dynamic mapping space in
284	* ring-0 on 32-bit darwin and in RC.
285	* @remark There is no need to assert on the result.
286	*/
287	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
288	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
289
290	/** @def PGM_GCPHYS_2_PTR
291	* Maps a GC physical page address to a virtual address.
292	*
293	* @returns VBox status code.
294	* @param pVM The cross context VM structure.
295	* @param GCPhys The GC physical address to map to a virtual one.
296	* @param ppv Where to store the virtual address. No need to cast this.
297	*
298	* @remark Use with care as we don't have so much dynamic mapping space in
299	* ring-0 on 32-bit darwin and in RC.
300	* @remark There is no need to assert on the result.
301	*/
302	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
303
304	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
305	* Maps a GC physical page address to a virtual address.
306	*
307	* @returns VBox status code.
308	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
309	* @param GCPhys The GC physical address to map to a virtual one.
310	* @param ppv Where to store the virtual address. No need to cast this.
311	*
312	* @remark Use with care as we don't have so much dynamic mapping space in
313	* ring-0 on 32-bit darwin and in RC.
314	* @remark There is no need to assert on the result.
315	*/
316	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
317
318	/** @def PGM_GCPHYS_2_PTR_EX
319	* Maps a unaligned GC physical page address to a virtual address.
320	*
321	* @returns VBox status code.
322	* @param pVM The cross context VM structure.
323	* @param GCPhys The GC physical address to map to a virtual one.
324	* @param ppv Where to store the virtual address. No need to cast this.
325	*
326	* @remark Use with care as we don't have so much dynamic mapping space in
327	* ring-0 on 32-bit darwin and in RC.
328	* @remark There is no need to assert on the result.
329	*/
330	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
331	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
332
333	/** @def PGM_DYNMAP_UNUSED_HINT
334	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
335	* is no longer used.
336	*
337	* For best effect only apply this to the page that was mapped most recently.
338	*
339	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
340	* @param pvPage The pool page.
341	*/
342	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
343
344	/** @def PGM_DYNMAP_UNUSED_HINT_VM
345	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
346	* is no longer used.
347	*
348	* For best effect only apply this to the page that was mapped most recently.
349	*
350	* @param pVM The cross context VM structure.
351	* @param pvPage The pool page.
352	*/
353	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
354
355
356	/** @def PGM_INVL_PG
357	* Invalidates a page.
358	*
359	* @param pVCpu The cross context virtual CPU structure.
360	* @param GCVirt The virtual address of the page to invalidate.
361	*/
362	#ifdef IN_RING0
363	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
364	#elif defined(IN_RING3)
365	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
366	#else
367	# error "Not IN_RING0 or IN_RING3!"
368	#endif
369
370	/** @def PGM_INVL_PG_ALL_VCPU
371	* Invalidates a page on all VCPUs
372	*
373	* @param pVM The cross context VM structure.
374	* @param GCVirt The virtual address of the page to invalidate.
375	*/
376	#ifdef IN_RING0
377	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
378	#else
379	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
380	#endif
381
382	/** @def PGM_INVL_BIG_PG
383	* Invalidates a 4MB page directory entry.
384	*
385	* @param pVCpu The cross context virtual CPU structure.
386	* @param GCVirt The virtual address within the page directory to invalidate.
387	*/
388	#ifdef IN_RING0
389	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
390	#else
391	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
392	#endif
393
394	/** @def PGM_INVL_VCPU_TLBS()
395	* Invalidates the TLBs of the specified VCPU
396	*
397	* @param pVCpu The cross context virtual CPU structure.
398	*/
399	#ifdef IN_RING0
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
401	#else
402	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
403	#endif
404
405	/** @def PGM_INVL_ALL_VCPU_TLBS()
406	* Invalidates the TLBs of all VCPUs
407	*
408	* @param pVM The cross context VM structure.
409	*/
410	#ifdef IN_RING0
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 1
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** The physical access handler type handle count (power of two). */
498	#define PGMPHYSHANDLERTYPE_COUNT 0x20
499	/** Mask for getting the array index from an access handler type handle.
500	* The other handle bits are random and non-zero to avoid mixups due to zero
501	* initialized fields. */
502	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
503
504	/**
505	* Physical page access handler type registration, ring-0 part.
506	*/
507	typedef struct PGMPHYSHANDLERTYPEINTR0
508	{
509	/** The handle value for verfication. */
510	PGMPHYSHANDLERTYPE hType;
511	/** The kind of accesses we're handling. */
512	PGMPHYSHANDLERKIND enmKind;
513	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
514	uint8_t uState;
515	/** Whether to keep the PGM lock when calling the handler.
516	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
517	bool fKeepPgmLock;
518	/** Set if this is registered by a device instance and uUser should be
519	* translated from a device instance ID to a pointer.
520	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
521	bool fRing0DevInsIdx;
522	bool afPadding[1];
523	/** Pointer to the ring-0 callback function. */
524	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
525	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
526	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
527	/** Description / Name. For easing debugging. */
528	R0PTRTYPE(const char *) pszDesc;
529	} PGMPHYSHANDLERTYPEINTR0;
530	/** Pointer to a physical access handler type registration. */
531	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
532
533	/**
534	* Physical page access handler type registration, shared/ring-3 part.
535	*/
536	typedef struct PGMPHYSHANDLERTYPEINTR3
537	{
538	/** The handle value for verfication. */
539	PGMPHYSHANDLERTYPE hType;
540	/** The kind of accesses we're handling. */
541	PGMPHYSHANDLERKIND enmKind;
542	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
543	uint8_t uState;
544	/** Whether to keep the PGM lock when calling the handler.
545	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
546	bool fKeepPgmLock;
547	/** Set if this is registered by a device instance and uUser should be
548	* translated from a device instance ID to a pointer.
549	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
550	bool fRing0DevInsIdx;
551	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
552	bool fRing0Enabled : 1;
553	/** Pointer to the ring-3 callback function. */
554	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
555	/** Description / Name. For easing debugging. */
556	R3PTRTYPE(const char *) pszDesc;
557	} PGMPHYSHANDLERTYPEINTR3;
558	/** Pointer to a physical access handler type registration. */
559	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
560
561	/** Pointer to a physical access handler type record for the current context. */
562	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
563	/** Pointer to a const physical access handler type record for the current context. */
564	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
565	/** Dummy physical access handler type record. */
566	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
567
568
569	/**
570	* Physical page access handler structure.
571	*
572	* This is used to keep track of physical address ranges
573	* which are being monitored in some kind of way.
574	*/
575	typedef struct PGMPHYSHANDLER
576	{
577	/** @name Tree stuff.
578	* @{ */
579	/** First address. */
580	RTGCPHYS Key;
581	/** Last address. */
582	RTGCPHYS KeyLast;
583	uint32_t idxLeft;
584	uint32_t idxRight;
585	uint8_t cHeight;
586	/** @} */
587	uint8_t abPadding[3];
588	/** Number of pages to update. */
589	uint32_t cPages;
590	/** Set if we have pages that have been aliased. */
591	uint32_t cAliasedPages;
592	/** Set if we have pages that have temporarily been disabled. */
593	uint32_t cTmpOffPages;
594	/** Registered handler type handle.
595	* @note Marked volatile to prevent re-reading after validation. */
596	PGMPHYSHANDLERTYPE volatile hType;
597	/** User argument for the handlers. */
598	uint64_t uUser;
599	/** Description / Name. For easing debugging. */
600	R3PTRTYPE(const char *) pszDesc;
601	/** Profiling of this handler.
602	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
603	STAMPROFILE Stat;
604	} PGMPHYSHANDLER;
605	AssertCompileSize(PGMPHYSHANDLER, 12*8);
606	/** Pointer to a physical page access handler structure. */
607	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
608
609	/**
610	* Gets the type record for a physical handler (no reference added).
611	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
612	* @param a_pVM The cross context VM structure.
613	* @param a_pPhysHandler Pointer to the physical handler structure
614	* (PGMPHYSHANDLER).
615	*/
616	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
617	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
618
619	/**
620	* Gets the type record for a physical handler, never returns NULL.
621	*
622	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
623	* @param a_pVM The cross context VM structure.
624	* @param a_pPhysHandler Pointer to the physical handler structure
625	* (PGMPHYSHANDLER).
626	*/
627	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
628	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
629
630	/** Physical access handler allocator. */
631	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
632
633	/** Physical access handler tree. */
634	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
635	/** Pointer to a physical access handler tree. */
636	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
637
638
639	/**
640	* A Physical Guest Page tracking structure.
641	*
642	* The format of this structure is complicated because we have to fit a lot
643	* of information into as few bits as possible. The format is also subject
644	* to change (there is one coming up soon). Which means that for we'll be
645	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
646	* accesses to the structure.
647	*/
648	typedef union PGMPAGE
649	{
650	/** Structured view. */
651	struct
652	{
653	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
654	uint64_t u2HandlerPhysStateY : 2;
655	/** 3:2 - Paging structure needed to map the page
656	* (PGM_PAGE_PDE_TYPE_). /
657	uint64_t u2PDETypeY : 2;
658	/** 4 - Unused (was used by FTE for dirty tracking). */
659	uint64_t fUnused1 : 1;
660	/** 5 - Flag indicating that a write monitored page was written to
661	* when set. */
662	uint64_t fWrittenToY : 1;
663	/** 7:6 - Unused. */
664	uint64_t u2Unused0 : 2;
665	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
666	uint64_t u2Unused1 : 2;
667	/** 11:10 - NEM state bits. */
668	uint64_t u2NemStateY : 2;
669	/** 12:48 - The host physical frame number (shift left to get the
670	* address). */
671	uint64_t HCPhysFN : 36;
672	/** 50:48 - The page state. */
673	uint64_t uStateY : 3;
674	/** 51:53 - The page type (PGMPAGETYPE). */
675	uint64_t uTypeY : 3;
676	/** 63:54 - PTE index for usage tracking (page pool). */
677	uint64_t u10PteIdx : 10;
678
679	/** The GMM page ID.
680	* @remarks In the current implementation, MMIO2 and pages aliased to
681	* MMIO2 pages will be exploiting this field to calculate the
682	* ring-3 mapping address corresponding to the page.
683	* Later we may consider including MMIO2 management into GMM. */
684	uint32_t idPage;
685	/** Usage tracking (page pool). */
686	uint16_t u16TrackingY;
687	/** The number of read locks on this page. */
688	uint8_t cReadLocksY;
689	/** The number of write locks on this page. */
690	uint8_t cWriteLocksY;
691	} s;
692
693	/** 64-bit integer view. */
694	uint64_t au64[2];
695	/** 16-bit view. */
696	uint32_t au32[4];
697	/** 16-bit view. */
698	uint16_t au16[8];
699	/** 8-bit view. */
700	uint8_t au8[16];
701	} PGMPAGE;
702	AssertCompileSize(PGMPAGE, 16);
703	/** Pointer to a physical guest page. */
704	typedef PGMPAGE *PPGMPAGE;
705	/** Pointer to a const physical guest page. */
706	typedef const PGMPAGE *PCPGMPAGE;
707	/** Pointer to a physical guest page pointer. */
708	typedef PPGMPAGE *PPPGMPAGE;
709
710
711	/**
712	* Clears the page structure.
713	* @param a_pPage Pointer to the physical guest page tracking structure.
714	*/
715	#define PGM_PAGE_CLEAR(a_pPage) \
716	do { \
717	(a_pPage)->au64[0] = 0; \
718	(a_pPage)->au64[1] = 0; \
719	} while (0)
720
721	/**
722	* Initializes the page structure.
723	* @param a_pPage Pointer to the physical guest page tracking structure.
724	* @param a_HCPhys The host physical address of the page.
725	* @param a_idPage The (GMM) page ID of the page.
726	* @param a_uType The page type (PGMPAGETYPE).
727	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
728	*/
729	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
730	do { \
731	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
732	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
733	(a_pPage)->au64[0] = SetHCPhysTmp; \
734	(a_pPage)->au64[1] = 0; \
735	(a_pPage)->s.idPage = (a_idPage); \
736	(a_pPage)->s.uStateY = (a_uState); \
737	(a_pPage)->s.uTypeY = (a_uType); \
738	} while (0)
739
740	/**
741	* Initializes the page structure of a ZERO page.
742	* @param a_pPage Pointer to the physical guest page tracking structure.
743	* @param a_pVM The VM handle (for getting the zero page address).
744	* @param a_uType The page type (PGMPAGETYPE).
745	*/
746	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
747	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
748
749
750	/** @name The Page state, PGMPAGE::uStateY.
751	* @{ */
752	/** The zero page.
753	* This is a per-VM page that's never ever mapped writable. */
754	#define PGM_PAGE_STATE_ZERO 0U
755	/** A allocated page.
756	* This is a per-VM page allocated from the page pool (or wherever
757	* we get MMIO2 pages from if the type is MMIO2).
758	*/
759	#define PGM_PAGE_STATE_ALLOCATED 1U
760	/** A allocated page that's being monitored for writes.
761	* The shadow page table mappings are read-only. When a write occurs, the
762	* fWrittenTo member is set, the page remapped as read-write and the state
763	* moved back to allocated. */
764	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
765	/** The page is shared, aka. copy-on-write.
766	* This is a page that's shared with other VMs. */
767	#define PGM_PAGE_STATE_SHARED 3U
768	/** The page is ballooned, so no longer available for this VM. */
769	#define PGM_PAGE_STATE_BALLOONED 4U
770	/** @} */
771
772
773	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
774	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
775	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
776	#else
777	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
778	#endif
779
780	/**
781	* Gets the page state.
782	* @returns page state (PGM_PAGE_STATE_*).
783	* @param a_pPage Pointer to the physical guest page tracking structure.
784	*
785	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
786	* builds.
787	*/
788	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
789	#if defined(__GNUC__) && defined(VBOX_STRICT)
790	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
791	#else
792	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
793	#endif
794
795	/**
796	* Sets the page state.
797	* @param a_pVM The VM handle, only used for lock ownership assertions.
798	* @param a_pPage Pointer to the physical guest page tracking structure.
799	* @param a_uState The new page state.
800	*/
801	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
802	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
803
804
805	/**
806	* Gets the host physical address of the guest page.
807	* @returns host physical address (RTHCPHYS).
808	* @param a_pPage Pointer to the physical guest page tracking structure.
809	*
810	* @remarks In strict builds on gcc platforms, this macro will make some ugly
811	* assumption about a valid pVM variable/parameter being in the
812	* current context. It will use this pVM variable to assert that the
813	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
814	* pVM is not around.
815	*/
816	#if 0
817	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
818	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
819	#else
820	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
821	# if defined(__GNUC__) && defined(VBOX_STRICT)
822	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
823	# else
824	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
825	# endif
826	#endif
827
828	/**
829	* Sets the host physical address of the guest page.
830	*
831	* @param a_pVM The VM handle, only used for lock ownership assertions.
832	* @param a_pPage Pointer to the physical guest page tracking structure.
833	* @param a_HCPhys The new host physical address.
834	*/
835	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
836	do { \
837	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
838	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
839	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
840	PGM_PAGE_ASSERT_LOCK(a_pVM); \
841	} while (0)
842
843	/**
844	* Get the Page ID.
845	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
846	* @param a_pPage Pointer to the physical guest page tracking structure.
847	*/
848	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
849
850	/**
851	* Sets the Page ID.
852	* @param a_pVM The VM handle, only used for lock ownership assertions.
853	* @param a_pPage Pointer to the physical guest page tracking structure.
854	* @param a_idPage The new page ID.
855	*/
856	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
857	do { \
858	(a_pPage)->s.idPage = (a_idPage); \
859	PGM_PAGE_ASSERT_LOCK(a_pVM); \
860	} while (0)
861
862	/**
863	* Get the Chunk ID.
864	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
865	* @param a_pPage Pointer to the physical guest page tracking structure.
866	*/
867	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
868
869	/**
870	* Get the index of the page within the allocation chunk.
871	* @returns The page index.
872	* @param a_pPage Pointer to the physical guest page tracking structure.
873	*/
874	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
875
876	/**
877	* Gets the page type.
878	* @returns The page type.
879	* @param a_pPage Pointer to the physical guest page tracking structure.
880	*
881	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
882	* builds.
883	*/
884	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
885	#if defined(__GNUC__) && defined(VBOX_STRICT)
886	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
887	#else
888	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
889	#endif
890
891	/**
892	* Sets the page type.
893	*
894	* @param a_pVM The VM handle, only used for lock ownership assertions.
895	* @param a_pPage Pointer to the physical guest page tracking structure.
896	* @param a_enmType The new page type (PGMPAGETYPE).
897	*/
898	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
899	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
900
901	/**
902	* Gets the page table index
903	* @returns The page table index.
904	* @param a_pPage Pointer to the physical guest page tracking structure.
905	*/
906	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
907
908	/**
909	* Sets the page table index.
910	* @param a_pVM The VM handle, only used for lock ownership assertions.
911	* @param a_pPage Pointer to the physical guest page tracking structure.
912	* @param a_iPte New page table index.
913	*/
914	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
915	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
916
917	/**
918	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
919	* @returns true/false.
920	* @param a_pPage Pointer to the physical guest page tracking structure.
921	*/
922	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
923
924	/**
925	* Checks if the page is marked for MMIO, including both aliases.
926	* @returns true/false.
927	* @param a_pPage Pointer to the physical guest page tracking structure.
928	*/
929	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
930	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
931	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
932	)
933
934	/**
935	* Checks if the page is marked for MMIO, including special aliases.
936	* @returns true/false.
937	* @param a_pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
940	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
941
942	/**
943	* Checks if the page is a special aliased MMIO page.
944	* @returns true/false.
945	* @param a_pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
948
949	/**
950	* Checks if the page is backed by the ZERO page.
951	* @returns true/false.
952	* @param a_pPage Pointer to the physical guest page tracking structure.
953	*/
954	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
955
956	/**
957	* Checks if the page is backed by a SHARED page.
958	* @returns true/false.
959	* @param a_pPage Pointer to the physical guest page tracking structure.
960	*/
961	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
962
963	/**
964	* Checks if the page is ballooned.
965	* @returns true/false.
966	* @param a_pPage Pointer to the physical guest page tracking structure.
967	*/
968	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
969
970	/**
971	* Checks if the page is allocated.
972	* @returns true/false.
973	* @param a_pPage Pointer to the physical guest page tracking structure.
974	*/
975	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
976
977	/**
978	* Marks the page as written to (for GMM change monitoring).
979	* @param a_pVM The VM handle, only used for lock ownership assertions.
980	* @param a_pPage Pointer to the physical guest page tracking structure.
981	*/
982	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
983	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
984
985	/**
986	* Clears the written-to indicator.
987	* @param a_pVM The VM handle, only used for lock ownership assertions.
988	* @param a_pPage Pointer to the physical guest page tracking structure.
989	*/
990	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
991	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
992
993	/**
994	* Checks if the page was marked as written-to.
995	* @returns true/false.
996	* @param a_pPage Pointer to the physical guest page tracking structure.
997	*/
998	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
999
1000
1001	/** @name PT usage values (PGMPAGE::u2PDEType).
1002	*
1003	* @{ */
1004	/** Either as a PT or PDE. */
1005	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1006	/** Must use a page table to map the range. */
1007	#define PGM_PAGE_PDE_TYPE_PT 1
1008	/** Can use a page directory entry to map the continuous range. */
1009	#define PGM_PAGE_PDE_TYPE_PDE 2
1010	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1011	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1012	/** @} */
1013
1014	/**
1015	* Set the PDE type of the page
1016	* @param a_pVM The VM handle, only used for lock ownership assertions.
1017	* @param a_pPage Pointer to the physical guest page tracking structure.
1018	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1019	*/
1020	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1021	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1022
1023	/**
1024	* Checks if the page was marked being part of a large page
1025	* @returns true/false.
1026	* @param a_pPage Pointer to the physical guest page tracking structure.
1027	*/
1028	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1029
1030	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1031	*
1032	* @remarks The values are assigned in order of priority, so we can calculate
1033	* the correct state for a page with different handlers installed.
1034	* @{ */
1035	/** No handler installed. */
1036	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1037	/** Monitoring is temporarily disabled. */
1038	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1039	/** Write access is monitored. */
1040	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1041	/** All access is monitored. */
1042	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1043	/** @} */
1044
1045	/**
1046	* Gets the physical access handler state of a page.
1047	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1048	* @param a_pPage Pointer to the physical guest page tracking structure.
1049	*/
1050	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1051
1052	/**
1053	* Sets the physical access handler state of a page.
1054	* @param a_pPage Pointer to the physical guest page tracking structure.
1055	* @param a_uState The new state value.
1056	*/
1057	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1058	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1059
1060	/**
1061	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1062	* @returns true/false
1063	* @param a_pPage Pointer to the physical guest page tracking structure.
1064	*/
1065	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1066	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1067
1068	/**
1069	* Checks if the page has any active physical access handlers.
1070	* @returns true/false
1071	* @param a_pPage Pointer to the physical guest page tracking structure.
1072	*/
1073	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1074	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1075
1076	/**
1077	* Checks if the page has any access handlers, including temporarily disabled ones.
1078	* @returns true/false
1079	* @param a_pPage Pointer to the physical guest page tracking structure.
1080	*/
1081	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1082	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1083
1084	/**
1085	* Checks if the page has any active access handlers.
1086	* @returns true/false
1087	* @param a_pPage Pointer to the physical guest page tracking structure.
1088	*/
1089	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1090	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1091
1092	/**
1093	* Checks if the page has any active access handlers catching all accesses.
1094	* @returns true/false
1095	* @param a_pPage Pointer to the physical guest page tracking structure.
1096	*/
1097	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1098	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1099
1100
1101	/** @def PGM_PAGE_GET_TRACKING
1102	* Gets the packed shadow page pool tracking data associated with a guest page.
1103	* @returns uint16_t containing the data.
1104	* @param a_pPage Pointer to the physical guest page tracking structure.
1105	*/
1106	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1107	#if defined(__GNUC__) && defined(VBOX_STRICT)
1108	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1109	#else
1110	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1111	#endif
1112
1113	/** @def PGM_PAGE_SET_TRACKING
1114	* Sets the packed shadow page pool tracking data associated with a guest page.
1115	* @param a_pVM The VM handle, only used for lock ownership assertions.
1116	* @param a_pPage Pointer to the physical guest page tracking structure.
1117	* @param a_u16TrackingData The tracking data to store.
1118	*/
1119	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1120	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1121
1122	/** @def PGM_PAGE_GET_TD_CREFS
1123	* Gets the @a cRefs tracking data member.
1124	* @returns cRefs.
1125	* @param a_pPage Pointer to the physical guest page tracking structure.
1126	*/
1127	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1128	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1129	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1130	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1131
1132	/** @def PGM_PAGE_GET_TD_IDX
1133	* Gets the @a idx tracking data member.
1134	* @returns idx.
1135	* @param a_pPage Pointer to the physical guest page tracking structure.
1136	*/
1137	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1138	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1139	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1140	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1141
1142
1143	/** Max number of locks on a page. */
1144	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1145
1146	/** Get the read lock count.
1147	* @returns count.
1148	* @param a_pPage Pointer to the physical guest page tracking structure.
1149	*/
1150	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1151
1152	/** Get the write lock count.
1153	* @returns count.
1154	* @param a_pPage Pointer to the physical guest page tracking structure.
1155	*/
1156	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1157
1158	/** Decrement the read lock counter.
1159	* @param a_pPage Pointer to the physical guest page tracking structure.
1160	*/
1161	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1162
1163	/** Decrement the write lock counter.
1164	* @param a_pPage Pointer to the physical guest page tracking structure.
1165	*/
1166	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1167
1168	/** Increment the read lock counter.
1169	* @param a_pPage Pointer to the physical guest page tracking structure.
1170	*/
1171	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1172
1173	/** Increment the write lock counter.
1174	* @param a_pPage Pointer to the physical guest page tracking structure.
1175	*/
1176	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1177
1178
1179	/** Gets the NEM state.
1180	* @returns NEM state value (two bits).
1181	* @param a_pPage Pointer to the physical guest page tracking structure.
1182	*/
1183	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1184
1185	/** Sets the NEM state.
1186	* @param a_pPage Pointer to the physical guest page tracking structure.
1187	* @param a_u2State The NEM state value (specific to NEM impl.).
1188	*/
1189	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1190	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1191
1192
1193	#if 0
1194	/** Enables sanity checking of write monitoring using CRC-32. */
1195	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1196	#endif
1197
1198	/**
1199	* Per page live save tracking data.
1200	*/
1201	typedef struct PGMLIVESAVERAMPAGE
1202	{
1203	/** Number of times it has been dirtied. */
1204	uint32_t cDirtied : 24;
1205	/** Whether it is currently dirty. */
1206	uint32_t fDirty : 1;
1207	/** Ignore the page.
1208	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1209	* deal with these after pausing the VM and DevPCI have said it bit about
1210	* remappings. */
1211	uint32_t fIgnore : 1;
1212	/** Was a ZERO page last time around. */
1213	uint32_t fZero : 1;
1214	/** Was a SHARED page last time around. */
1215	uint32_t fShared : 1;
1216	/** Whether the page is/was write monitored in a previous pass. */
1217	uint32_t fWriteMonitored : 1;
1218	/** Whether the page is/was write monitored earlier in this pass. */
1219	uint32_t fWriteMonitoredJustNow : 1;
1220	/** Bits reserved for future use. */
1221	uint32_t u2Reserved : 2;
1222	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1223	/** CRC-32 for the page. This is for internal consistency checks. */
1224	uint32_t u32Crc;
1225	#endif
1226	} PGMLIVESAVERAMPAGE;
1227	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1228	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1229	#else
1230	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1231	#endif
1232	/** Pointer to the per page live save tracking data. */
1233	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1234
1235	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1236	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1237
1238
1239	/**
1240	* RAM range for GC Phys to HC Phys conversion.
1241	*
1242	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1243	* conversions too, but we'll let MM handle that for now.
1244	*
1245	* This structure is used by linked lists in both GC and HC.
1246	*/
1247	typedef struct PGMRAMRANGE
1248	{
1249	/** Start of the range. Page aligned. */
1250	RTGCPHYS GCPhys;
1251	/** Size of the range. (Page aligned of course). */
1252	RTGCPHYS cb;
1253	/** Pointer to the next RAM range - for R3. */
1254	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1255	/** Pointer to the next RAM range - for R0. */
1256	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1257	/** PGM_RAM_RANGE_FLAGS_* flags. */
1258	uint32_t fFlags;
1259	/** NEM specific info, UINT32_MAX if not used. */
1260	uint32_t uNemRange;
1261	/** Last address in the range (inclusive). Page aligned (-1). */
1262	RTGCPHYS GCPhysLast;
1263	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1264	R3PTRTYPE(void *) pvR3;
1265	/** Live save per page tracking data. */
1266	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1267	/** The range description. */
1268	R3PTRTYPE(const char *) pszDesc;
1269	/** Pointer to self - R0 pointer. */
1270	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1271
1272	/** Pointer to the left search three node - ring-3 context. */
1273	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1274	/** Pointer to the right search three node - ring-3 context. */
1275	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1276	/** Pointer to the left search three node - ring-0 context. */
1277	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1278	/** Pointer to the right search three node - ring-0 context. */
1279	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1280
1281	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1282	#if HC_ARCH_BITS == 32
1283	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1284	#endif
1285	/** Array of physical guest page tracking structures.
1286	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1287	PGMPAGE aPages[1];
1288	} PGMRAMRANGE;
1289	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1290	typedef PGMRAMRANGE *PPGMRAMRANGE;
1291
1292	/** @name PGMRAMRANGE::fFlags
1293	* @{ */
1294	/** The RAM range is floating around as an independent guest mapping. */
1295	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1296	/** Ad hoc RAM range for an ROM mapping. */
1297	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1298	/** Ad hoc RAM range for an MMIO mapping. */
1299	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1300	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1301	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1302	/** @} */
1303
1304	/** Tests if a RAM range is an ad hoc one or not.
1305	* @returns true/false.
1306	* @param pRam The RAM range.
1307	*/
1308	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1309	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1310
1311	/** The number of entries in the RAM range TLBs (there is one for each
1312	* context). Must be a power of two. */
1313	#define PGM_RAMRANGE_TLB_ENTRIES 8
1314
1315	/**
1316	* Calculates the RAM range TLB index for the physical address.
1317	*
1318	* @returns RAM range TLB index.
1319	* @param a_GCPhys The guest physical address.
1320	*/
1321	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1322
1323	/**
1324	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1325	* mapping address.
1326	*/
1327	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1328	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1329
1330
1331	/**
1332	* Per page tracking structure for ROM image.
1333	*
1334	* A ROM image may have a shadow page, in which case we may have two pages
1335	* backing it. This structure contains the PGMPAGE for both while
1336	* PGMRAMRANGE have a copy of the active one. It is important that these
1337	* aren't out of sync in any regard other than page pool tracking data.
1338	*/
1339	typedef struct PGMROMPAGE
1340	{
1341	/** The page structure for the virgin ROM page. */
1342	PGMPAGE Virgin;
1343	/** The page structure for the shadow RAM page. */
1344	PGMPAGE Shadow;
1345	/** The current protection setting. */
1346	PGMROMPROT enmProt;
1347	/** Live save status information. Makes use of unused alignment space. */
1348	struct
1349	{
1350	/** The previous protection value. */
1351	uint8_t u8Prot;
1352	/** Written to flag set by the handler. */
1353	bool fWrittenTo;
1354	/** Whether the shadow page is dirty or not. */
1355	bool fDirty;
1356	/** Whether it was dirtied in the recently. */
1357	bool fDirtiedRecently;
1358	} LiveSave;
1359	} PGMROMPAGE;
1360	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1361	/** Pointer to a ROM page tracking structure. */
1362	typedef PGMROMPAGE *PPGMROMPAGE;
1363
1364
1365	/**
1366	* A registered ROM image.
1367	*
1368	* This is needed to keep track of ROM image since they generally intrude
1369	* into a PGMRAMRANGE. It also keeps track of additional info like the
1370	* two page sets (read-only virgin and read-write shadow), the current
1371	* state of each page.
1372	*
1373	* Because access handlers cannot easily be executed in a different
1374	* context, the ROM ranges needs to be accessible and in all contexts.
1375	*/
1376	typedef struct PGMROMRANGE
1377	{
1378	/** Pointer to the next range - R3. */
1379	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1380	/** Pointer to the next range - R0. */
1381	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1382	/** Pointer to the this range - R0. */
1383	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1384	/** Address of the range. */
1385	RTGCPHYS GCPhys;
1386	/** Address of the last byte in the range. */
1387	RTGCPHYS GCPhysLast;
1388	/** Size of the range. */
1389	RTGCPHYS cb;
1390	/** The flags (PGMPHYS_ROM_FLAGS_). /
1391	uint8_t fFlags;
1392	/** The saved state range ID. */
1393	uint8_t idSavedState;
1394	/** Alignment padding. */
1395	uint8_t au8Alignment[2];
1396	/** The size bits pvOriginal points to. */
1397	uint32_t cbOriginal;
1398	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1399	* This is used for strictness checks. */
1400	R3PTRTYPE(const void *) pvOriginal;
1401	/** The ROM description. */
1402	R3PTRTYPE(const char *) pszDesc;
1403	#ifdef VBOX_WITH_PGM_NEM_MODE
1404	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1405	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1406	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1407	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1408	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1409	R3PTRTYPE(uint8_t *) pbR3Alternate;
1410	RTR3PTR pvAlignment2;
1411	#endif
1412	/** The per page tracking structures. */
1413	PGMROMPAGE aPages[1];
1414	} PGMROMRANGE;
1415	/** Pointer to a ROM range. */
1416	typedef PGMROMRANGE *PPGMROMRANGE;
1417
1418
1419	/**
1420	* Live save per page data for an MMIO2 page.
1421	*
1422	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1423	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1424	* CRC-32 for detecting changes as well as special handling of zero pages. This
1425	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1426	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1427	* because of speed (2.5x and 6x slower).)
1428	*
1429	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1430	* save but normally is disabled. Since we can write monitor guest
1431	* accesses on our own, we only need this for host accesses. Shouldn't be
1432	* too difficult for DevVGA, VMMDev might be doable, the planned
1433	* networking fun will be fun since it involves ring-0.
1434	*/
1435	typedef struct PGMLIVESAVEMMIO2PAGE
1436	{
1437	/** Set if the page is considered dirty. */
1438	bool fDirty;
1439	/** The number of scans this page has remained unchanged for.
1440	* Only updated for dirty pages. */
1441	uint8_t cUnchangedScans;
1442	/** Whether this page was zero at the last scan. */
1443	bool fZero;
1444	/** Alignment padding. */
1445	bool fReserved;
1446	/** CRC-32 for the first half of the page.
1447	* This is used together with u32CrcH2 to quickly detect changes in the page
1448	* during the non-final passes. */
1449	uint32_t u32CrcH1;
1450	/** CRC-32 for the second half of the page. */
1451	uint32_t u32CrcH2;
1452	/** SHA-1 for the saved page.
1453	* This is used in the final pass to skip pages without changes. */
1454	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1455	} PGMLIVESAVEMMIO2PAGE;
1456	/** Pointer to a live save status data for an MMIO2 page. */
1457	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1458
1459	/**
1460	* A registered MMIO2 (= Device RAM) range.
1461	*
1462	* There are a few reason why we need to keep track of these registrations. One
1463	* of them is the deregistration & cleanup stuff, while another is that the
1464	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1465	* range list.
1466	*
1467	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1468	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1469	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1470	* overlap we will free all the existing RAM pages and put in the ram range
1471	* pages instead.
1472	*/
1473	typedef struct PGMREGMMIO2RANGE
1474	{
1475	/** The owner of the range. (a device) */
1476	PPDMDEVINSR3 pDevInsR3;
1477	/** Pointer to the ring-3 mapping of the allocation. */
1478	RTR3PTR pvR3;
1479	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1480	/** Pointer to the ring-0 mapping of the allocation. */
1481	RTR0PTR pvR0;
1482	#endif
1483	/** Pointer to the next range - R3. */
1484	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1485	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1486	uint16_t fFlags;
1487	/** The sub device number (internal PCI config (CFGM) number). */
1488	uint8_t iSubDev;
1489	/** The PCI region number. */
1490	uint8_t iRegion;
1491	/** The saved state range ID. */
1492	uint8_t idSavedState;
1493	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1494	uint8_t idMmio2;
1495	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1496	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1497	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1498	#else
1499	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1500	#endif
1501	/** The real size.
1502	* This may be larger than indicated by RamRange.cb if the range has been
1503	* reduced during saved state loading. */
1504	RTGCPHYS cbReal;
1505	/** Pointer to the physical handler for MMIO.
1506	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1507	* will be NULL. */
1508	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1509	/** Live save per page tracking data for MMIO2. */
1510	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1511	/** The associated RAM range. */
1512	PGMRAMRANGE RamRange;
1513	} PGMREGMMIO2RANGE;
1514	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1515	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1516	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1517
1518	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1519	* @{ */
1520	/** Set if this is the first chunk in the MMIO2 range. */
1521	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1522	/** Set if this is the last chunk in the MMIO2 range. */
1523	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1524	/** Set if the whole range is mapped. */
1525	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1526	/** Set if it's overlapping, clear if not. */
1527	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1528	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1529	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1530	/** Set if the access handler is registered. */
1531	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1532	/** Set if dirty page tracking is currently enabled. */
1533	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1534	/** Set if there are dirty pages in the range. */
1535	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1536	/** @} */
1537
1538
1539	/** @name Internal MMIO2 constants.
1540	* @{ */
1541	/** The maximum number of MMIO2 ranges. */
1542	#define PGM_MMIO2_MAX_RANGES 32
1543	/** The maximum number of pages in a MMIO2 range. */
1544	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1545	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1546	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1547	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1548	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1549	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1550	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1551	/** @} */
1552
1553
1554
1555	/**
1556	* PGMPhysRead/Write cache entry
1557	*/
1558	typedef struct PGMPHYSCACHEENTRY
1559	{
1560	/** R3 pointer to physical page. */
1561	R3PTRTYPE(uint8_t *) pbR3;
1562	/** GC Physical address for cache entry */
1563	RTGCPHYS GCPhys;
1564	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1565	RTGCPHYS u32Padding0; /*< alignment padding. /
1566	#endif
1567	} PGMPHYSCACHEENTRY;
1568
1569	/**
1570	* PGMPhysRead/Write cache to reduce REM memory access overhead
1571	*/
1572	typedef struct PGMPHYSCACHE
1573	{
1574	/** Bitmap of valid cache entries */
1575	uint64_t aEntries;
1576	/** Cache entries */
1577	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1578	} PGMPHYSCACHE;
1579
1580
1581	/** @name Ring-3 page mapping TLBs
1582	* @{ */
1583
1584	/** Pointer to an allocation chunk ring-3 mapping. */
1585	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1586	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1587	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1588
1589	/**
1590	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1591	*
1592	* The primary tree (Core) uses the chunk id as key.
1593	*/
1594	typedef struct PGMCHUNKR3MAP
1595	{
1596	/** The key is the chunk id. */
1597	AVLU32NODECORE Core;
1598	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1599	* selection. */
1600	uint32_t iLastUsed;
1601	/** The current reference count. */
1602	uint32_t volatile cRefs;
1603	/** The current permanent reference count. */
1604	uint32_t volatile cPermRefs;
1605	/** The mapping address. */
1606	void *pv;
1607	} PGMCHUNKR3MAP;
1608
1609	/**
1610	* Allocation chunk ring-3 mapping TLB entry.
1611	*/
1612	typedef struct PGMCHUNKR3MAPTLBE
1613	{
1614	/** The chunk id. */
1615	uint32_t volatile idChunk;
1616	#if HC_ARCH_BITS == 64
1617	uint32_t u32Padding; /*< alignment padding. /
1618	#endif
1619	/** The chunk map. */
1620	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1621	} PGMCHUNKR3MAPTLBE;
1622	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1623	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1624
1625	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1626	* @remark Must be a power of two value. */
1627	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1628
1629	/**
1630	* Allocation chunk ring-3 mapping TLB.
1631	*
1632	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1633	* At first glance this might look kinda odd since AVL trees are
1634	* supposed to give the most optimal lookup times of all trees
1635	* due to their balancing. However, take a tree with 1023 nodes
1636	* in it, that's 10 levels, meaning that most searches has to go
1637	* down 9 levels before they find what they want. This isn't fast
1638	* compared to a TLB hit. There is the factor of cache misses,
1639	* and of course the problem with trees and branch prediction.
1640	* This is why we use TLBs in front of most of the trees.
1641	*
1642	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1643	* difficult when we switch to the new inlined AVL trees (from kStuff).
1644	*/
1645	typedef struct PGMCHUNKR3MAPTLB
1646	{
1647	/** The TLB entries. */
1648	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1649	} PGMCHUNKR3MAPTLB;
1650
1651	/**
1652	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1653	* @returns Chunk TLB index.
1654	* @param idChunk The Chunk ID.
1655	*/
1656	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1657
1658
1659	/**
1660	* Ring-3 guest page mapping TLB entry.
1661	* @remarks used in ring-0 as well at the moment.
1662	*/
1663	typedef struct PGMPAGER3MAPTLBE
1664	{
1665	/** Address of the page. */
1666	RTGCPHYS volatile GCPhys;
1667	/** The guest page. */
1668	R3PTRTYPE(PPGMPAGE) volatile pPage;
1669	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1670	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1671	/** The address */
1672	R3PTRTYPE(void *) volatile pv;
1673	#if HC_ARCH_BITS == 32
1674	uint32_t u32Padding; /*< alignment padding. /
1675	#endif
1676	} PGMPAGER3MAPTLBE;
1677	/** Pointer to an entry in the HC physical TLB. */
1678	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1679
1680
1681	/** The number of entries in the ring-3 guest page mapping TLB.
1682	* @remarks The value must be a power of two. */
1683	#define PGM_PAGER3MAPTLB_ENTRIES 256
1684
1685	/**
1686	* Ring-3 guest page mapping TLB.
1687	* @remarks used in ring-0 as well at the moment.
1688	*/
1689	typedef struct PGMPAGER3MAPTLB
1690	{
1691	/** The TLB entries. */
1692	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1693	} PGMPAGER3MAPTLB;
1694	/** Pointer to the ring-3 guest page mapping TLB. */
1695	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1696
1697	/**
1698	* Calculates the index of the TLB entry for the specified guest page.
1699	* @returns Physical TLB index.
1700	* @param GCPhys The guest physical address.
1701	*/
1702	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1703
1704	/** @} */
1705
1706
1707	/** @name Ring-0 page mapping TLB
1708	* @{ */
1709	/**
1710	* Ring-0 guest page mapping TLB entry.
1711	*/
1712	typedef struct PGMPAGER0MAPTLBE
1713	{
1714	/** Address of the page. */
1715	RTGCPHYS volatile GCPhys;
1716	/** The guest page. */
1717	R0PTRTYPE(PPGMPAGE) volatile pPage;
1718	/** The address */
1719	R0PTRTYPE(void *) volatile pv;
1720	} PGMPAGER0MAPTLBE;
1721	/** Pointer to an entry in the HC physical TLB. */
1722	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1723
1724
1725	/** The number of entries in the ring-3 guest page mapping TLB.
1726	* @remarks The value must be a power of two. */
1727	#define PGM_PAGER0MAPTLB_ENTRIES 256
1728
1729	/**
1730	* Ring-3 guest page mapping TLB.
1731	* @remarks used in ring-0 as well at the moment.
1732	*/
1733	typedef struct PGMPAGER0MAPTLB
1734	{
1735	/** The TLB entries. */
1736	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1737	} PGMPAGER0MAPTLB;
1738	/** Pointer to the ring-3 guest page mapping TLB. */
1739	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1740
1741	/**
1742	* Calculates the index of the TLB entry for the specified guest page.
1743	* @returns Physical TLB index.
1744	* @param GCPhys The guest physical address.
1745	*/
1746	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1747	/** @} */
1748
1749
1750	/** @name Context neutral page mapper TLB.
1751	*
1752	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1753	* code is writting in a kind of context neutral way. Time will show whether
1754	* this actually makes sense or not...
1755	*
1756	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1757	* context ends up using a global mapping cache on some platforms
1758	* (darwin).
1759	*
1760	* @{ */
1761	/** @typedef PPGMPAGEMAPTLB
1762	* The page mapper TLB pointer type for the current context. */
1763	/** @typedef PPGMPAGEMAPTLB
1764	* The page mapper TLB entry pointer type for the current context. */
1765	/** @typedef PPGMPAGEMAPTLB
1766	* The page mapper TLB entry pointer pointer type for the current context. */
1767	/** @def PGM_PAGEMAPTLB_ENTRIES
1768	* The number of TLB entries in the page mapper TLB for the current context. */
1769	/** @def PGM_PAGEMAPTLB_IDX
1770	* Calculate the TLB index for a guest physical address.
1771	* @returns The TLB index.
1772	* @param GCPhys The guest physical address. */
1773	/** @typedef PPGMPAGEMAP
1774	* Pointer to a page mapper unit for current context. */
1775	/** @typedef PPPGMPAGEMAP
1776	* Pointer to a page mapper unit pointer for current context. */
1777	#if defined(IN_RING0)
1778	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1779	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1780	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1781	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1782	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1783	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1784	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1785	#else
1786	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1787	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1788	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1789	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1790	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1791	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1792	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1793	#endif
1794	/** @} */
1795
1796
1797	/** @name PGM Pool Indexes.
1798	* Aka. the unique shadow page identifier.
1799	* @{ */
1800	/** NIL page pool IDX. */
1801	#define NIL_PGMPOOL_IDX 0
1802	/** The first normal index. There used to be 5 fictive pages up front, now
1803	* there is only the NIL page. */
1804	#define PGMPOOL_IDX_FIRST 1
1805	/** The last valid index. (inclusive, 14 bits) */
1806	#define PGMPOOL_IDX_LAST 0x3fff
1807	/** @} */
1808
1809	/** The NIL index for the parent chain. */
1810	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1811	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1812
1813	/**
1814	* Node in the chain linking a shadowed page to it's parent (user).
1815	*/
1816	#pragma pack(1)
1817	typedef struct PGMPOOLUSER
1818	{
1819	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1820	uint16_t iNext;
1821	/** The user page index. */
1822	uint16_t iUser;
1823	/** Index into the user table. */
1824	uint32_t iUserTable;
1825	} PGMPOOLUSER, *PPGMPOOLUSER;
1826	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1827	#pragma pack()
1828
1829
1830	/** The NIL index for the phys ext chain. */
1831	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1832	/** The NIL pte index for a phys ext chain slot. */
1833	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1834
1835	/**
1836	* Node in the chain of physical cross reference extents.
1837	* @todo Calling this an 'extent' is not quite right, find a better name.
1838	* @todo find out the optimal size of the aidx array
1839	*/
1840	#pragma pack(1)
1841	typedef struct PGMPOOLPHYSEXT
1842	{
1843	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1844	uint16_t iNext;
1845	/** Alignment. */
1846	uint16_t u16Align;
1847	/** The user page index. */
1848	uint16_t aidx[3];
1849	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1850	uint16_t apte[3];
1851	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1852	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1853	#pragma pack()
1854
1855
1856	/**
1857	* The kind of page that's being shadowed.
1858	*/
1859	typedef enum PGMPOOLKIND
1860	{
1861	/** The virtual invalid 0 entry. */
1862	PGMPOOLKIND_INVALID = 0,
1863	/** The entry is free (=unused). */
1864	PGMPOOLKIND_FREE,
1865
1866	/** Shw: 32-bit page table; Gst: no paging. */
1867	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1868	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1869	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1870	/** Shw: 32-bit page table; Gst: 4MB page. */
1871	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1872	/** Shw: PAE page table; Gst: no paging. */
1873	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1874	/** Shw: PAE page table; Gst: 32-bit page table. */
1875	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1876	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1877	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1878	/** Shw: PAE page table; Gst: PAE page table. */
1879	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1880	/** Shw: PAE page table; Gst: 2MB page. */
1881	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1882
1883	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1884	PGMPOOLKIND_32BIT_PD,
1885	/** Shw: 32-bit page directory. Gst: no paging. */
1886	PGMPOOLKIND_32BIT_PD_PHYS,
1887	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1888	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1889	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1890	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1891	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1892	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1893	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1894	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1895	/** Shw: PAE page directory; Gst: PAE page directory. */
1896	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1897	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1898	PGMPOOLKIND_PAE_PD_PHYS,
1899
1900	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1901	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1902	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1903	PGMPOOLKIND_PAE_PDPT,
1904	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1905	PGMPOOLKIND_PAE_PDPT_PHYS,
1906
1907	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1908	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1909	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1910	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1911	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1912	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1913	/** Shw: 64-bit page directory table; Gst: no paging. */
1914	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1915
1916	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1917	PGMPOOLKIND_64BIT_PML4,
1918
1919	/** Shw: EPT page directory pointer table; Gst: no paging. */
1920	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1921	/** Shw: EPT page directory table; Gst: no paging. */
1922	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1923	/** Shw: EPT page table; Gst: no paging. */
1924	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1925
1926	/** Shw: Root Nested paging table. */
1927	PGMPOOLKIND_ROOT_NESTED,
1928
1929	/** Shw: EPT page table; Gst: EPT page table. */
1930	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
1931	/** Shw: EPT page directory table; Gst: EPT page directory. */
1932	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
1933	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
1934	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
1935	/** Shw: EPT PML4; Gst: EPT PML4. */
1936	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
1937
1938	/** The last valid entry. */
1939	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
1940	} PGMPOOLKIND;
1941
1942	/**
1943	* The access attributes of the page; only applies to big pages.
1944	*/
1945	typedef enum
1946	{
1947	PGMPOOLACCESS_DONTCARE = 0,
1948	PGMPOOLACCESS_USER_RW,
1949	PGMPOOLACCESS_USER_R,
1950	PGMPOOLACCESS_USER_RW_NX,
1951	PGMPOOLACCESS_USER_R_NX,
1952	PGMPOOLACCESS_SUPERVISOR_RW,
1953	PGMPOOLACCESS_SUPERVISOR_R,
1954	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1955	PGMPOOLACCESS_SUPERVISOR_R_NX
1956	} PGMPOOLACCESS;
1957
1958	/**
1959	* The tracking data for a page in the pool.
1960	*/
1961	typedef struct PGMPOOLPAGE
1962	{
1963	/** AVL node code with the (HC) physical address of this page. */
1964	AVLOHCPHYSNODECORE Core;
1965	/** Pointer to the R3 mapping of the page. */
1966	R3PTRTYPE(void *) pvPageR3;
1967	/** Pointer to the R0 mapping of the page. */
1968	R0PTRTYPE(void *) pvPageR0;
1969	/** The guest physical address. */
1970	RTGCPHYS GCPhys;
1971	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1972	uint8_t enmKind;
1973	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1974	uint8_t enmAccess;
1975	/** This supplements enmKind and enmAccess */
1976	bool fA20Enabled : 1;
1977
1978	/** Used to indicate that the page is zeroed. */
1979	bool fZeroed : 1;
1980	/** Used to indicate that a PT has non-global entries. */
1981	bool fSeenNonGlobal : 1;
1982	/** Used to indicate that we're monitoring writes to the guest page. */
1983	bool fMonitored : 1;
1984	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1985	* (All pages are in the age list.) */
1986	bool fCached : 1;
1987	/** This is used by the R3 access handlers when invoked by an async thread.
1988	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1989	bool volatile fReusedFlushPending : 1;
1990	/** Used to mark the page as dirty (write monitoring is temporarily
1991	* off). */
1992	bool fDirty : 1;
1993	bool fPadding1 : 1;
1994	bool fPadding2;
1995
1996	/** The index of this page. */
1997	uint16_t idx;
1998	/** The next entry in the list this page currently resides in.
1999	* It's either in the free list or in the GCPhys hash. */
2000	uint16_t iNext;
2001	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2002	uint16_t iUserHead;
2003	/** The number of present entries. */
2004	uint16_t cPresent;
2005	/** The first entry in the table which is present. */
2006	uint16_t iFirstPresent;
2007	/** The number of modifications to the monitored page. */
2008	uint16_t cModifications;
2009	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2010	uint16_t iModifiedNext;
2011	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2012	uint16_t iModifiedPrev;
2013	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2014	uint16_t iMonitoredNext;
2015	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2016	uint16_t iMonitoredPrev;
2017	/** The next page in the age list. */
2018	uint16_t iAgeNext;
2019	/** The previous page in the age list. */
2020	uint16_t iAgePrev;
2021	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2022	uint8_t idxDirtyEntry;
2023
2024	/** @name Access handler statistics to determine whether the guest is
2025	* (re)initializing a page table.
2026	* @{ */
2027	RTGCPTR GCPtrLastAccessHandlerRip;
2028	RTGCPTR GCPtrLastAccessHandlerFault;
2029	uint64_t cLastAccessHandler;
2030	/** @} */
2031	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2032	uint32_t volatile cLocked;
2033	#if GC_ARCH_BITS == 64
2034	uint32_t u32Alignment3;
2035	#endif
2036	# ifdef VBOX_STRICT
2037	RTGCPTR GCPtrDirtyFault;
2038	# endif
2039	} PGMPOOLPAGE;
2040	/** Pointer to a pool page. */
2041	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2042	/** Pointer to a const pool page. */
2043	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2044	/** Pointer to a pool page pointer. */
2045	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2046
2047
2048	/** The hash table size. */
2049	# define PGMPOOL_HASH_SIZE 0x40
2050	/** The hash function. */
2051	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2052
2053
2054	/**
2055	* The shadow page pool instance data.
2056	*
2057	* It's all one big allocation made at init time, except for the
2058	* pages that is. The user nodes follows immediately after the
2059	* page structures.
2060	*/
2061	typedef struct PGMPOOL
2062	{
2063	/** The VM handle - R3 Ptr. */
2064	PVMR3 pVMR3;
2065	/** The VM handle - R0 Ptr. */
2066	R0PTRTYPE(PVMCC) pVMR0;
2067	/** The ring-3 pointer to this structure. */
2068	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2069	/** The ring-0 pointer to this structure. */
2070	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2071	/** The max pool size. This includes the special IDs. */
2072	uint16_t cMaxPages;
2073	/** The current pool size. */
2074	uint16_t cCurPages;
2075	/** The head of the free page list. */
2076	uint16_t iFreeHead;
2077	/* Padding. */
2078	uint16_t u16Padding;
2079	/** Head of the chain of free user nodes. */
2080	uint16_t iUserFreeHead;
2081	/** The number of user nodes we've allocated. */
2082	uint16_t cMaxUsers;
2083	/** The number of present page table entries in the entire pool. */
2084	uint32_t cPresent;
2085	/** Pointer to the array of user nodes - R3 pointer. */
2086	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2087	/** Pointer to the array of user nodes - R0 pointer. */
2088	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2089	/** Head of the chain of free phys ext nodes. */
2090	uint16_t iPhysExtFreeHead;
2091	/** The number of user nodes we've allocated. */
2092	uint16_t cMaxPhysExts;
2093	uint32_t u32Padding0b;
2094	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2095	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2096	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2097	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2098	/** Hash table for GCPhys addresses. */
2099	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2100	/** The head of the age list. */
2101	uint16_t iAgeHead;
2102	/** The tail of the age list. */
2103	uint16_t iAgeTail;
2104	/** Set if the cache is enabled. */
2105	bool fCacheEnabled;
2106	/** Alignment padding. */
2107	bool afPadding1[3];
2108	/** Head of the list of modified pages. */
2109	uint16_t iModifiedHead;
2110	/** The current number of modified pages. */
2111	uint16_t cModifiedPages;
2112	/** Alignment padding. */
2113	uint32_t u32Padding2;
2114	/** Physical access handler type registration handle. */
2115	PGMPHYSHANDLERTYPE hAccessHandlerType;
2116	/** Next available slot (in aDirtyPages). */
2117	uint32_t idxFreeDirtyPage;
2118	/** Number of active dirty pages. */
2119	uint32_t cDirtyPages;
2120	/** Array of current dirty pgm pool page indices. */
2121	uint16_t aidxDirtyPages[16];
2122	/** Array running in parallel to aidxDirtyPages with the page data. */
2123	struct
2124	{
2125	uint64_t aPage[512];
2126	} aDirtyPages[16];
2127
2128	/** The number of pages currently in use. */
2129	uint16_t cUsedPages;
2130	#ifdef VBOX_WITH_STATISTICS
2131	/** The high water mark for cUsedPages. */
2132	uint16_t cUsedPagesHigh;
2133	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2134	/** Profiling pgmPoolAlloc(). */
2135	STAMPROFILEADV StatAlloc;
2136	/** Profiling pgmR3PoolClearDoIt(). */
2137	STAMPROFILE StatClearAll;
2138	/** Profiling pgmR3PoolReset(). */
2139	STAMPROFILE StatR3Reset;
2140	/** Profiling pgmPoolFlushPage(). */
2141	STAMPROFILE StatFlushPage;
2142	/** Profiling pgmPoolFree(). */
2143	STAMPROFILE StatFree;
2144	/** Counting explicit flushes by PGMPoolFlushPage(). */
2145	STAMCOUNTER StatForceFlushPage;
2146	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2147	STAMCOUNTER StatForceFlushDirtyPage;
2148	/** Counting flushes for reused pages. */
2149	STAMCOUNTER StatForceFlushReused;
2150	/** Profiling time spent zeroing pages. */
2151	STAMPROFILE StatZeroPage;
2152	/** Profiling of pgmPoolTrackDeref. */
2153	STAMPROFILE StatTrackDeref;
2154	/** Profiling pgmTrackFlushGCPhysPT. */
2155	STAMPROFILE StatTrackFlushGCPhysPT;
2156	/** Profiling pgmTrackFlushGCPhysPTs. */
2157	STAMPROFILE StatTrackFlushGCPhysPTs;
2158	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2159	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2160	/** Number of times we've been out of user records. */
2161	STAMCOUNTER StatTrackFreeUpOneUser;
2162	/** Nr of flushed entries. */
2163	STAMCOUNTER StatTrackFlushEntry;
2164	/** Nr of updated entries. */
2165	STAMCOUNTER StatTrackFlushEntryKeep;
2166	/** Profiling deref activity related tracking GC physical pages. */
2167	STAMPROFILE StatTrackDerefGCPhys;
2168	/** Number of linear searches for a HCPhys in the ram ranges. */
2169	STAMCOUNTER StatTrackLinearRamSearches;
2170	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2171	STAMCOUNTER StamTrackPhysExtAllocFailures;
2172
2173	/** Profiling the RC/R0 \#PF access handler. */
2174	STAMPROFILE StatMonitorPfRZ;
2175	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2176	STAMPROFILE StatMonitorPfRZHandled;
2177	/** Times we've failed interpreting the instruction. */
2178	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2179	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2180	STAMPROFILE StatMonitorPfRZFlushPage;
2181	/** Times we've detected a page table reinit. */
2182	STAMCOUNTER StatMonitorPfRZFlushReinit;
2183	/** Counting flushes for pages that are modified too often. */
2184	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2185	/** Times we've detected fork(). */
2186	STAMCOUNTER StatMonitorPfRZFork;
2187	/** Times we've failed interpreting a patch code instruction. */
2188	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2189	/** Times we've failed interpreting a patch code instruction during flushing. */
2190	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2191	/** The number of times we've seen rep prefixes we can't handle. */
2192	STAMCOUNTER StatMonitorPfRZRepPrefix;
2193	/** Profiling the REP STOSD cases we've handled. */
2194	STAMPROFILE StatMonitorPfRZRepStosd;
2195
2196	/** Profiling the R0/RC regular access handler. */
2197	STAMPROFILE StatMonitorRZ;
2198	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2199	STAMPROFILE StatMonitorRZFlushPage;
2200	/** Per access size counts indexed by size minus 1, last for larger. */
2201	STAMCOUNTER aStatMonitorRZSizes[16+3];
2202	/** Missaligned access counts indexed by offset - 1. */
2203	STAMCOUNTER aStatMonitorRZMisaligned[7];
2204
2205	/** Nr of handled PT faults. */
2206	STAMCOUNTER StatMonitorRZFaultPT;
2207	/** Nr of handled PD faults. */
2208	STAMCOUNTER StatMonitorRZFaultPD;
2209	/** Nr of handled PDPT faults. */
2210	STAMCOUNTER StatMonitorRZFaultPDPT;
2211	/** Nr of handled PML4 faults. */
2212	STAMCOUNTER StatMonitorRZFaultPML4;
2213
2214	/** Profiling the R3 access handler. */
2215	STAMPROFILE StatMonitorR3;
2216	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2217	STAMPROFILE StatMonitorR3FlushPage;
2218	/** Per access size counts indexed by size minus 1, last for larger. */
2219	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2220	/** Missaligned access counts indexed by offset - 1. */
2221	STAMCOUNTER aStatMonitorR3Misaligned[7];
2222	/** Nr of handled PT faults. */
2223	STAMCOUNTER StatMonitorR3FaultPT;
2224	/** Nr of handled PD faults. */
2225	STAMCOUNTER StatMonitorR3FaultPD;
2226	/** Nr of handled PDPT faults. */
2227	STAMCOUNTER StatMonitorR3FaultPDPT;
2228	/** Nr of handled PML4 faults. */
2229	STAMCOUNTER StatMonitorR3FaultPML4;
2230
2231	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2232	STAMCOUNTER StatResetDirtyPages;
2233	/** Times we've called pgmPoolAddDirtyPage. */
2234	STAMCOUNTER StatDirtyPage;
2235	/** Times we've had to flush duplicates for dirty page management. */
2236	STAMCOUNTER StatDirtyPageDupFlush;
2237	/** Times we've had to flush because of overflow. */
2238	STAMCOUNTER StatDirtyPageOverFlowFlush;
2239
2240	/** The high water mark for cModifiedPages. */
2241	uint16_t cModifiedPagesHigh;
2242	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2243
2244	/** The number of cache hits. */
2245	STAMCOUNTER StatCacheHits;
2246	/** The number of cache misses. */
2247	STAMCOUNTER StatCacheMisses;
2248	/** The number of times we've got a conflict of 'kind' in the cache. */
2249	STAMCOUNTER StatCacheKindMismatches;
2250	/** Number of times we've been out of pages. */
2251	STAMCOUNTER StatCacheFreeUpOne;
2252	/** The number of cacheable allocations. */
2253	STAMCOUNTER StatCacheCacheable;
2254	/** The number of uncacheable allocations. */
2255	STAMCOUNTER StatCacheUncacheable;
2256	#else
2257	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2258	#endif
2259	/** Profiling PGMR0PoolGrow(). */
2260	STAMPROFILE StatGrow;
2261	/** The AVL tree for looking up a page by its HC physical address. */
2262	AVLOHCPHYSTREE HCPhysTree;
2263	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2264	/** Array of pages. (cMaxPages in length)
2265	* The Id is the index into thist array.
2266	*/
2267	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2268	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2269	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2270	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2271	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2272	#ifdef VBOX_WITH_STATISTICS
2273	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2274	#endif
2275	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2276
2277
2278	/** @def PGMPOOL_PAGE_2_PTR
2279	* Maps a pool page pool into the current context.
2280	*
2281	* @returns VBox status code.
2282	* @param a_pVM Pointer to the VM.
2283	* @param a_pPage The pool page.
2284	*
2285	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2286	* small page window employeed by that function. Be careful.
2287	* @remark There is no need to assert on the result.
2288	*/
2289	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2290	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2291	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2292	{
2293	RT_NOREF(pszCaller);
2294	AssertPtr(a_pPage);
2295	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2296	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2297	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2298	return a_pPage->CTX_SUFF(pvPage);
2299	}
2300	#else
2301	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2302	#endif
2303
2304
2305	/** @def PGMPOOL_PAGE_2_PTR_V2
2306	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2307	*
2308	* @returns VBox status code.
2309	* @param a_pVM Pointer to the VM.
2310	* @param a_pVCpu The current CPU.
2311	* @param a_pPage The pool page.
2312	*
2313	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2314	* small page window employeed by that function. Be careful.
2315	* @remark There is no need to assert on the result.
2316	*/
2317	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2318
2319
2320	/** @def PGMPOOL_PAGE_IS_NESTED
2321	* Checks whether the given pool page is a nested-guest pool page.
2322	*
2323	* @returns @c true if a nested-guest pool page, @c false otherwise.
2324	* @param a_pPage The pool page.
2325	* @todo We can optimize the conditionals later.
2326	*/
2327	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2328	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2329	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2330	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2331	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2332
2333	/** @name Per guest page tracking data.
2334	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2335	* is to use more bits for it and split it up later on. But for now we'll play
2336	* safe and change as little as possible.
2337	*
2338	* The 16-bit word has two parts:
2339	*
2340	* The first 14-bit forms the @a idx field. It is either the index of a page in
2341	* the shadow page pool, or and index into the extent list.
2342	*
2343	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2344	* shadow page pool references to the page. If cRefs equals
2345	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2346	* (misnomer) table and not the shadow page pool.
2347	*
2348	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2349	* the 16-bit word.
2350	*
2351	* @{ */
2352	/** The shift count for getting to the cRefs part. */
2353	#define PGMPOOL_TD_CREFS_SHIFT 14
2354	/** The mask applied after shifting the tracking data down by
2355	* PGMPOOL_TD_CREFS_SHIFT. */
2356	#define PGMPOOL_TD_CREFS_MASK 0x3
2357	/** The cRefs value used to indicate that the idx is the head of a
2358	* physical cross reference list. */
2359	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2360	/** The shift used to get idx. */
2361	#define PGMPOOL_TD_IDX_SHIFT 0
2362	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2363	#define PGMPOOL_TD_IDX_MASK 0x3fff
2364	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2365	* simply too many mappings of this page. */
2366	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2367
2368	/** @def PGMPOOL_TD_MAKE
2369	* Makes a 16-bit tracking data word.
2370	*
2371	* @returns tracking data.
2372	* @param cRefs The @a cRefs field. Must be within bounds!
2373	* @param idx The @a idx field. Must also be within bounds! */
2374	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2375
2376	/** @def PGMPOOL_TD_GET_CREFS
2377	* Get the @a cRefs field from a tracking data word.
2378	*
2379	* @returns The @a cRefs field
2380	* @param u16 The tracking data word.
2381	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2382	* non-zero @a u16. */
2383	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2384
2385	/** @def PGMPOOL_TD_GET_IDX
2386	* Get the @a idx field from a tracking data word.
2387	*
2388	* @returns The @a idx field
2389	* @param u16 The tracking data word. */
2390	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2391	/** @} */
2392
2393
2394
2395	/** @name A20 gate macros
2396	* @{ */
2397	#define PGM_WITH_A20
2398	#ifdef PGM_WITH_A20
2399	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2400	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2401	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2402	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2403	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2404	#else
2405	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2406	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2407	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2408	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2409	#endif
2410	/** @} */
2411
2412
2413	/**
2414	* Guest page table walk for the AMD64 mode.
2415	*/
2416	typedef struct PGMPTWALKGSTAMD64
2417	{
2418	PX86PML4 pPml4;
2419	PX86PML4E pPml4e;
2420	X86PML4E Pml4e;
2421
2422	PX86PDPT pPdpt;
2423	PX86PDPE pPdpe;
2424	X86PDPE Pdpe;
2425
2426	PX86PDPAE pPd;
2427	PX86PDEPAE pPde;
2428	X86PDEPAE Pde;
2429
2430	PX86PTPAE pPt;
2431	PX86PTEPAE pPte;
2432	X86PTEPAE Pte;
2433	} PGMPTWALKGSTAMD64;
2434	/** Pointer to a AMD64 guest page table walk. */
2435	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2436	/** Pointer to a const AMD64 guest page table walk. */
2437	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2438
2439	/**
2440	* Guest page table walk for the EPT mode.
2441	*/
2442	typedef struct PGMPTWALKGSTEPT
2443	{
2444	PEPTPML4 pPml4;
2445	PEPTPML4E pPml4e;
2446	EPTPML4E Pml4e;
2447
2448	PEPTPDPT pPdpt;
2449	PEPTPDPTE pPdpte;
2450	EPTPDPTE Pdpte;
2451
2452	PEPTPD pPd;
2453	PEPTPDE pPde;
2454	EPTPDE Pde;
2455
2456	PEPTPT pPt;
2457	PEPTPTE pPte;
2458	EPTPTE Pte;
2459	} PGMPTWALKGSTEPT;
2460	/** Pointer to an EPT guest page table walk. */
2461	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2462	/** Pointer to a const EPT guest page table walk. */
2463	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2464
2465	/**
2466	* Guest page table walk for the PAE mode.
2467	*/
2468	typedef struct PGMPTWALKGSTPAE
2469	{
2470	PX86PDPT pPdpt;
2471	PX86PDPE pPdpe;
2472	X86PDPE Pdpe;
2473
2474	PX86PDPAE pPd;
2475	PX86PDEPAE pPde;
2476	X86PDEPAE Pde;
2477
2478	PX86PTPAE pPt;
2479	PX86PTEPAE pPte;
2480	X86PTEPAE Pte;
2481	} PGMPTWALKGSTPAE;
2482	/** Pointer to a PAE guest page table walk. */
2483	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2484	/** Pointer to a const AMD64 guest page table walk. */
2485	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2486
2487	/**
2488	* Guest page table walk for the 32-bit mode.
2489	*/
2490	typedef struct PGMPTWALKGST32BIT
2491	{
2492	PX86PD pPd;
2493	PX86PDE pPde;
2494	X86PDE Pde;
2495
2496	PX86PT pPt;
2497	PX86PTE pPte;
2498	X86PTE Pte;
2499	} PGMPTWALKGST32BIT;
2500	/** Pointer to a 32-bit guest page table walk. */
2501	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2502	/** Pointer to a const 32-bit guest page table walk. */
2503	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2504
2505	/**
2506	* Which part of PGMPTWALKGST that is valid.
2507	*/
2508	typedef enum PGMPTWALKGSTTYPE
2509	{
2510	/** Customary invalid 0 value. */
2511	PGMPTWALKGSTTYPE_INVALID = 0,
2512	/** PGMPTWALKGST::u.Amd64 is valid. */
2513	PGMPTWALKGSTTYPE_AMD64,
2514	/** PGMPTWALKGST::u.Pae is valid. */
2515	PGMPTWALKGSTTYPE_PAE,
2516	/** PGMPTWALKGST::u.Legacy is valid. */
2517	PGMPTWALKGSTTYPE_32BIT,
2518	/** PGMPTWALKGST::u.Ept is valid. */
2519	PGMPTWALKGSTTYPE_EPT,
2520	/** Customary 32-bit type hack. */
2521	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2522	} PGMPTWALKGSTTYPE;
2523
2524	/**
2525	* Combined guest page table walk result.
2526	*/
2527	typedef struct PGMPTWALKGST
2528	{
2529	union
2530	{
2531	/** The page walker for AMD64. */
2532	PGMPTWALKGSTAMD64 Amd64;
2533	/** The page walker for PAE (32-bit). */
2534	PGMPTWALKGSTPAE Pae;
2535	/** The page walker for 32-bit paging (called legacy due to C naming
2536	* convension). */
2537	PGMPTWALKGST32BIT Legacy;
2538	/** The page walker for EPT (SLAT). */
2539	PGMPTWALKGSTEPT Ept;
2540	} u;
2541	/** Indicates which part of the union is valid. */
2542	PGMPTWALKGSTTYPE enmType;
2543	} PGMPTWALKGST;
2544	/** Pointer to a combined guest page table walk result. */
2545	typedef PGMPTWALKGST *PPGMPTWALKGST;
2546	/** Pointer to a read-only combined guest page table walk result. */
2547	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2548
2549
2550	/** @name Paging mode macros
2551	* @{
2552	*/
2553	#ifdef IN_RING3
2554	# define PGM_CTX(a,b) a##R3##b
2555	# define PGM_CTX_STR(a,b) a "R3" b
2556	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2557	#elif defined(IN_RING0)
2558	# define PGM_CTX(a,b) a##R0##b
2559	# define PGM_CTX_STR(a,b) a "R0" b
2560	# define PGM_CTX_DECL(type) VMMDECL(type)
2561	#else
2562	# error "Not IN_RING3 or IN_RING0!"
2563	#endif
2564
2565	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2566	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2567	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2568	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2569	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2570	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2571	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2572	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2573	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2574	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2575	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2576	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2577	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2578	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2579	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2580	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2581
2582	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2583	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2584	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2585	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2586
2587	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2588	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2589	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2590	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2591	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2592	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2593	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2594	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2595	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2596	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2597	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2598	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2599	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2600	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2601	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2602	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2603	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2604	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2605	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2606	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2607	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2608	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2609	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2610	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2611	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2612
2613	/* Shw_Gst */
2614	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2615	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2616	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2617	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2618	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2619	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2620	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2621	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2622	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2623	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2624	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2625	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2626	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2627	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2628	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2629	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2630	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2631	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2632	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2633	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2634	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2635	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2636	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2637	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2638	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2639	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2640	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2641	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2642	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2643	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2644	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2645	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2646	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2647	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2648
2649	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2650	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2651	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2652	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2653	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2654	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2655	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2656	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2657	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2658	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2659	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2660	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2661	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2662	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2663	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2664	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2665	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2666	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2667	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2668	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2669	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2670	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2671	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2672	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2673	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2674	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2675	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2676	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2677
2678	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2679	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2680	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2681	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2682	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2683	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2684	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2685	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2686	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2687	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2688	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2689	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2690	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2691	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2692	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2693	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2694	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2695	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2696	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2697	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2698	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2699	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2700	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2701	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2702	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2703	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2704	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2705	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2706	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2707
2708	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2709	/** @} */
2710
2711
2712	/**
2713	* Function pointers for guest paging.
2714	*/
2715	typedef struct PGMMODEDATAGST
2716	{
2717	/** The guest mode type. */
2718	uint32_t uType;
2719	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2720	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2721	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2722	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2723	#ifdef IN_RING3
2724	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2725	#endif
2726	} PGMMODEDATAGST;
2727
2728	/** The length of g_aPgmGuestModeData. */
2729	#if VBOX_WITH_64_BITS_GUESTS
2730	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2731	#else
2732	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2733	#endif
2734	/** The guest mode data array. */
2735	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2736
2737
2738	/**
2739	* Function pointers for shadow paging.
2740	*/
2741	typedef struct PGMMODEDATASHW
2742	{
2743	/** The shadow mode type. */
2744	uint32_t uType;
2745	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2746	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2747	uint64_t fMask, uint32_t fOpFlags));
2748	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2749	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2750	#ifdef IN_RING3
2751	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2752	#endif
2753	} PGMMODEDATASHW;
2754
2755	/** The length of g_aPgmShadowModeData. */
2756	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2757	/** The shadow mode data array. */
2758	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2759
2760
2761	/**
2762	* Function pointers for guest+shadow paging.
2763	*/
2764	typedef struct PGMMODEDATABTH
2765	{
2766	/** The shadow mode type. */
2767	uint32_t uShwType;
2768	/** The guest mode type. */
2769	uint32_t uGstType;
2770
2771	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2772	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2773	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2774	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2775	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2776	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2777	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2778	#ifndef IN_RING3
2779	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2780	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNested,
2781	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2782	bool *pfLockTaken));
2783	#endif
2784	#ifdef VBOX_STRICT
2785	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2786	#endif
2787	} PGMMODEDATABTH;
2788
2789	/** The length of g_aPgmBothModeData. */
2790	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2791	/** The guest+shadow mode data array. */
2792	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2793
2794
2795	#ifdef VBOX_WITH_STATISTICS
2796	/**
2797	* PGM statistics.
2798	*/
2799	typedef struct PGMSTATS
2800	{
2801	/* R3 only: */
2802	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2803	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2804
2805	/* R3+RZ */
2806	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2807	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2808	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2809	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2810	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2811	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2812	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2813	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2814	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2815	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2816	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2817	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2818	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2819	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2820	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2821	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2822	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2823	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2824	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2825	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2826	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2827	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2828	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2829	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2830	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2831	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2832
2833	/* RC only: */
2834	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2835	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2836
2837	STAMCOUNTER StatRZPhysRead;
2838	STAMCOUNTER StatRZPhysReadBytes;
2839	STAMCOUNTER StatRZPhysWrite;
2840	STAMCOUNTER StatRZPhysWriteBytes;
2841	STAMCOUNTER StatR3PhysRead;
2842	STAMCOUNTER StatR3PhysReadBytes;
2843	STAMCOUNTER StatR3PhysWrite;
2844	STAMCOUNTER StatR3PhysWriteBytes;
2845	STAMCOUNTER StatRCPhysRead;
2846	STAMCOUNTER StatRCPhysReadBytes;
2847	STAMCOUNTER StatRCPhysWrite;
2848	STAMCOUNTER StatRCPhysWriteBytes;
2849
2850	STAMCOUNTER StatRZPhysSimpleRead;
2851	STAMCOUNTER StatRZPhysSimpleReadBytes;
2852	STAMCOUNTER StatRZPhysSimpleWrite;
2853	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2854	STAMCOUNTER StatR3PhysSimpleRead;
2855	STAMCOUNTER StatR3PhysSimpleReadBytes;
2856	STAMCOUNTER StatR3PhysSimpleWrite;
2857	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2858	STAMCOUNTER StatRCPhysSimpleRead;
2859	STAMCOUNTER StatRCPhysSimpleReadBytes;
2860	STAMCOUNTER StatRCPhysSimpleWrite;
2861	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2862
2863	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2864	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2865	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2866	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2867	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2868	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2869	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2870
2871	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2872	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2873	/** pgmPhysIsValidLargePage profiling - R3 */
2874	STAMPROFILE StatR3IsValidLargePage;
2875	/** pgmPhysIsValidLargePage profiling - RZ*/
2876	STAMPROFILE StatRZIsValidLargePage;
2877
2878	STAMPROFILE StatChunkAging;
2879	STAMPROFILE StatChunkFindCandidate;
2880	STAMPROFILE StatChunkUnmap;
2881	STAMPROFILE StatChunkMap;
2882	} PGMSTATS;
2883	#endif /* VBOX_WITH_STATISTICS */
2884
2885
2886	/**
2887	* PGM Data (part of VM)
2888	*/
2889	typedef struct PGM
2890	{
2891	/** The zero page. */
2892	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2893	/** The MMIO placeholder page. */
2894	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2895
2896	/** @name The zero page (abPagePg).
2897	* @{ */
2898	/** The host physical address of the zero page. */
2899	RTHCPHYS HCPhysZeroPg;
2900	/** @}*/
2901
2902	/** @name The Invalid MMIO page (abMmioPg).
2903	* This page is filled with 0xfeedface.
2904	* @{ */
2905	/** The host physical address of the invalid MMIO page. */
2906	RTHCPHYS HCPhysMmioPg;
2907	/** The host pysical address of the invalid MMIO page plus all invalid
2908	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2909	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2910	RTHCPHYS HCPhysInvMmioPg;
2911	/** @} */
2912
2913	/** @cfgm{/RamPreAlloc, boolean, false}
2914	* Indicates whether the base RAM should all be allocated before starting
2915	* the VM (default), or if it should be allocated when first written to.
2916	*/
2917	bool fRamPreAlloc;
2918	#ifdef VBOX_WITH_PGM_NEM_MODE
2919	/** Set if we're operating in NEM memory mode.
2920	*
2921	* NEM mode implies that memory is allocated in big chunks for each RAM range
2922	* rather than on demand page by page. Memory is also not locked and PGM has
2923	* therefore no physical addresses for them. Page sharing is out of the
2924	* question. Ballooning depends on the native execution engine, but probably
2925	* pointless as well. */
2926	bool fNemMode;
2927	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2928	#else
2929	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2930	#endif
2931	/** Indicates whether write monitoring is currently in use.
2932	* This is used to prevent conflicts between live saving and page sharing
2933	* detection. */
2934	bool fPhysWriteMonitoringEngaged;
2935	/** Set if the CPU has less than 52-bit physical address width.
2936	* This is used */
2937	bool fLessThan52PhysicalAddressBits;
2938	/** Set when nested paging is active.
2939	* This is meant to save calls to HMIsNestedPagingActive and let the
2940	* compilers optimize the code better. Whether we use nested paging or
2941	* not is something we find out during VMM initialization and we won't
2942	* change this later on. */
2943	bool fNestedPaging;
2944	/** We're not in a state which permits writes to guest memory.
2945	* (Only used in strict builds.) */
2946	bool fNoMorePhysWrites;
2947	/** @cfgm{/PageFusionAllowed, boolean, false}
2948	* Whether page fusion is allowed. */
2949	bool fPageFusionAllowed;
2950	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2951	* Whether PCI passthrough is enabled. */
2952	bool fPciPassthrough;
2953	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2954	uint8_t cMmio2Regions;
2955	/** Restore original ROM page content when resetting after loading state.
2956	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2957	* enables the VM to start using an updated ROM without requiring powering
2958	* down the VM, just rebooting or resetting it. */
2959	bool fRestoreRomPagesOnReset;
2960	/** Whether to automatically clear all RAM pages on reset. */
2961	bool fZeroRamPagesOnReset;
2962	/** Large page enabled flag. */
2963	bool fUseLargePages;
2964	/** Alignment padding. */
2965	#ifndef VBOX_WITH_PGM_NEM_MODE
2966	bool afAlignment3[1];
2967	#endif
2968	/** The host paging mode. (This is what SUPLib reports.) */
2969	SUPPAGINGMODE enmHostMode;
2970	bool afAlignment3b[2];
2971
2972	/** Generation ID for the RAM ranges. This member is incremented everytime
2973	* a RAM range is linked or unlinked. */
2974	uint32_t volatile idRamRangesGen;
2975
2976	/** Physical access handler type for ROM protection. */
2977	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2978	/** Physical access handler type for MMIO2 dirty page tracing. */
2979	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
2980
2981	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2982	RTGCPHYS GCPhys4MBPSEMask;
2983	/** Mask containing the invalid bits of a guest physical address.
2984	* @remarks this does not stop at bit 52. */
2985	RTGCPHYS GCPhysInvAddrMask;
2986
2987
2988	/** RAM range TLB for R3. */
2989	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2990	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2991	* This is sorted by physical address and contains no overlapping ranges. */
2992	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2993	/** Root of the RAM range search tree for ring-3. */
2994	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2995	/** Shadow Page Pool - R3 Ptr. */
2996	R3PTRTYPE(PPGMPOOL) pPoolR3;
2997	/** Pointer to the list of ROM ranges - for R3.
2998	* This is sorted by physical address and contains no overlapping ranges. */
2999	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3000	/** Pointer to the list of MMIO2 ranges - for R3.
3001	* Registration order. */
3002	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3003	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3004	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3005
3006	/** RAM range TLB for R0. */
3007	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3008	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3009	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3010	/** Root of the RAM range search tree for ring-0. */
3011	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3012	/** Shadow Page Pool - R0 Ptr. */
3013	R0PTRTYPE(PPGMPOOL) pPoolR0;
3014	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3015	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3016	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3017	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3018
3019	/** Hack: Number of deprecated page mapping locks taken by the current lock
3020	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3021	uint32_t cDeprecatedPageLocks;
3022
3023	/** Registered physical access handler types. */
3024	uint32_t cPhysHandlerTypes;
3025	/** Physical access handler types.
3026	* Initialized to callback causing guru meditations and invalid enmKind. */
3027	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3028	/** Physical handler allocator, ring-3 edition. */
3029	#ifdef IN_RING3
3030	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3031	#else
3032	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3033	#endif
3034	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3035	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3036	/** Caching the last physical handler we looked. */
3037	uint32_t idxLastPhysHandler;
3038
3039	uint32_t au64Padding3[5];
3040
3041	/** PGM critical section.
3042	* This protects the physical, ram ranges, and the page flag updating (some of
3043	* it anyway).
3044	*/
3045	PDMCRITSECT CritSectX;
3046
3047	/**
3048	* Data associated with managing the ring-3 mappings of the allocation chunks.
3049	*/
3050	struct
3051	{
3052	/** The chunk mapping TLB. */
3053	PGMCHUNKR3MAPTLB Tlb;
3054	/** The chunk tree, ordered by chunk id. */
3055	R3PTRTYPE(PAVLU32NODECORE) pTree;
3056	#if HC_ARCH_BITS == 32
3057	uint32_t u32Alignment0;
3058	#endif
3059	/** The number of mapped chunks. */
3060	uint32_t c;
3061	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3062	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3063	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3064	uint32_t cMax;
3065	/** The current time. This is incremented whenever a chunk is inserted. */
3066	uint32_t iNow;
3067	/** Alignment padding. */
3068	uint32_t au32Alignment1[3];
3069	} ChunkR3Map;
3070
3071	/** The page mapping TLB for ring-3. */
3072	PGMPAGER3MAPTLB PhysTlbR3;
3073	/** The page mapping TLB for ring-0. */
3074	PGMPAGER0MAPTLB PhysTlbR0;
3075
3076	/** The number of handy pages. */
3077	uint32_t cHandyPages;
3078
3079	/** The number of large handy pages. */
3080	uint32_t cLargeHandyPages;
3081
3082	/**
3083	* Array of handy pages.
3084	*
3085	* This array is used in a two way communication between pgmPhysAllocPage
3086	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3087	* an intermediary.
3088	*
3089	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3090	* (The current size of 32 pages, means 128 KB of handy memory.)
3091	*/
3092	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3093
3094	/**
3095	* Array of large handy pages. (currently size 1)
3096	*
3097	* This array is used in a two way communication between pgmPhysAllocLargePage
3098	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3099	* an intermediary.
3100	*/
3101	GMMPAGEDESC aLargeHandyPage[1];
3102	/** When to try allocate large pages again after a failure. */
3103	uint64_t nsLargePageRetry;
3104	/** Number of repeated long allocation times. */
3105	uint32_t cLargePageLongAllocRepeats;
3106	uint32_t uPadding5;
3107
3108	/**
3109	* Live save data.
3110	*/
3111	struct
3112	{
3113	/** Per type statistics. */
3114	struct
3115	{
3116	/** The number of ready pages. */
3117	uint32_t cReadyPages;
3118	/** The number of dirty pages. */
3119	uint32_t cDirtyPages;
3120	/** The number of ready zero pages. */
3121	uint32_t cZeroPages;
3122	/** The number of write monitored pages. */
3123	uint32_t cMonitoredPages;
3124	} Rom,
3125	Mmio2,
3126	Ram;
3127	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3128	uint32_t cIgnoredPages;
3129	/** Indicates that a live save operation is active. */
3130	bool fActive;
3131	/** Padding. */
3132	bool afReserved[2];
3133	/** The next history index. */
3134	uint8_t iDirtyPagesHistory;
3135	/** History of the total amount of dirty pages. */
3136	uint32_t acDirtyPagesHistory[64];
3137	/** Short term dirty page average. */
3138	uint32_t cDirtyPagesShort;
3139	/** Long term dirty page average. */
3140	uint32_t cDirtyPagesLong;
3141	/** The number of saved pages. This is used to get some kind of estimate of the
3142	* link speed so we can decide when we're done. It is reset after the first
3143	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3144	* zero pages. */
3145	uint64_t cSavedPages;
3146	/** The nanosecond timestamp when cSavedPages was 0. */
3147	uint64_t uSaveStartNS;
3148	/** Pages per second (for statistics). */
3149	uint32_t cPagesPerSecond;
3150	uint32_t cAlignment;
3151	} LiveSave;
3152
3153	/** @name Error injection.
3154	* @{ */
3155	/** Inject handy page allocation errors pretending we're completely out of
3156	* memory. */
3157	bool volatile fErrInjHandyPages;
3158	/** Padding. */
3159	bool afReserved[3];
3160	/** @} */
3161
3162	/** @name Release Statistics
3163	* @{ */
3164	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3165	uint32_t cPrivatePages; /*< The number of private pages. /
3166	uint32_t cSharedPages; /*< The number of shared pages. /
3167	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3168	uint32_t cZeroPages; /*< The number of zero backed pages. /
3169	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3170	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3171	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3172	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3173	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3174	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3175	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3176	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3177	uint32_t cLargePages; /*< The number of large pages. /
3178	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3179	/* uint32_t aAlignment4[1]; */
3180
3181	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3182	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3183	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3184	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3185	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3186	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3187	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3188	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3189
3190	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3191
3192	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3193	/** @} */
3194
3195	#ifdef VBOX_WITH_STATISTICS
3196	/** These are optional statistics that used to be on the hyper heap. */
3197	PGMSTATS Stats;
3198	#endif
3199	} PGM;
3200	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3201	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3202	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3203	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3204	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3205	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3206	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3207	#endif /* !IN_TSTVMSTRUCTGC */
3208	/** Pointer to the PGM instance data. */
3209	typedef PGM *PPGM;
3210
3211
3212	#ifdef VBOX_WITH_STATISTICS
3213	/**
3214	* Per CPU statistis for PGM (used to be on the heap).
3215	*/
3216	typedef struct PGMCPUSTATS
3217	{
3218	/* Common */
3219	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3220	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3221
3222	/* R0 only: */
3223	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3224	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3225
3226	/* RZ only: */
3227	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3228	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3229	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3230	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3231	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3232	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3233	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3234	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3235	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3236	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3237	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3238	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3239	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3240	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3241	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3242	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3243	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3244	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3245	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3246	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3247	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3248	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3249	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3250	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3251	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3252	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3253	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3254	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3255	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3256	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3257	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3258	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3259	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3260	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3261	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3262	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3263	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3264	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3265	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3266	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3267	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3268	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3269	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3270	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3271	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3272	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3273	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3274	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3275	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3276	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3277	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3278	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3279	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3280	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3281	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3282	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3283	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3284	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3285	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3286	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3287	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3288	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3289	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3290	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3291	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3292	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3293	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3294	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3295	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3296	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3297
3298	/* HC - R3 and (maybe) R0: */
3299
3300	/* RZ & R3: */
3301	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3302	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3303	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3304	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3305	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3306	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3307	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3308	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3309	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3310	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3311	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3312	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3313	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3314	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3315	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3316	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3317	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3318	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3319	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3320	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3321	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3322	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3323	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3324	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3325	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3326	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3327	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3328	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3329	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3330	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3331	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3332	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3333	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3334	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3335	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3336	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3337	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3338	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3339	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3340	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3341	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3342	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3343	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3344	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3345	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3346	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3347	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3348
3349	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3350	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3351	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3352	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3353	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3354	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3355	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3356	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3357	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3358	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3359	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3360	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3361	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3362	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3363	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3364	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3365	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3366	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3367	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3368	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3369	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3370	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3371	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3372	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3373	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3374	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3375	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3376	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3377	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3378	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3379	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3380	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3381	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3382	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3383	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3384	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3385	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3386	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3387	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3388	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3389	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3390	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3391	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3392	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3393	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3394	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3395	} PGMCPUSTATS;
3396	#endif /* VBOX_WITH_STATISTICS */
3397
3398
3399	/**
3400	* PGMCPU Data (part of VMCPU).
3401	*/
3402	typedef struct PGMCPU
3403	{
3404	/** A20 gate mask.
3405	* Our current approach to A20 emulation is to let REM do it and don't bother
3406	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3407	* But whould need arrise, we'll subject physical addresses to this mask. */
3408	RTGCPHYS GCPhysA20Mask;
3409	/** A20 gate state - boolean! */
3410	bool fA20Enabled;
3411	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3412	bool fNoExecuteEnabled;
3413	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3414	* active. */
3415	bool fPaePdpesAndCr3MappedR3;
3416	bool fPaePdpesAndCr3MappedR0;
3417
3418	/** What needs syncing (PGM_SYNC_*).
3419	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3420	* PGMFlushTLB, and PGMR3Load. */
3421	uint32_t fSyncFlags;
3422
3423	/** The shadow paging mode. */
3424	PGMMODE enmShadowMode;
3425	/** The guest paging mode. */
3426	PGMMODE enmGuestMode;
3427	/** The guest second level address translation mode. */
3428	PGMSLAT enmGuestSlatMode;
3429	/** Guest mode data table index (PGM_TYPE_XXX). */
3430	uint8_t volatile idxGuestModeData;
3431	/** Shadow mode data table index (PGM_TYPE_XXX). */
3432	uint8_t volatile idxShadowModeData;
3433	/** Both mode data table index (complicated). */
3434	uint8_t volatile idxBothModeData;
3435	/** Alignment padding. */
3436	uint8_t abPadding[1];
3437
3438	/** The guest CR3.
3439	* When SLAT is active, this is the translated physical address.
3440	* When SLAT is inactive, this is the physical address in CR3. */
3441	RTGCPHYS GCPhysCR3;
3442
3443	/** The nested-guest CR3.
3444	* When SLAT is active, this is CR3 prior to translation.
3445	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3446	RTGCPHYS GCPhysNstGstCR3;
3447
3448	/** The cached guest CR3 when it has been mapped in PAE mode.
3449	* This allows us to skip remapping the CR3 and PAE PDPEs
3450	* (in PGMFlushTLB or similar) when it was already done as
3451	* part of MOV CRx instruction emulation.
3452	*/
3453	RTGCPHYS GCPhysPaeCR3;
3454
3455	/** @name 32-bit Guest Paging.
3456	* @{ */
3457	/** The guest's page directory, R3 pointer. */
3458	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3459	/** The guest's page directory, R0 pointer. */
3460	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3461	/** Mask containing the MBZ bits of a big page PDE. */
3462	uint32_t fGst32BitMbzBigPdeMask;
3463	/** Set if the page size extension (PSE) is enabled. */
3464	bool fGst32BitPageSizeExtension;
3465	/** Alignment padding. */
3466	bool afAlignment2[3];
3467	/** @} */
3468
3469	/** @name PAE Guest Paging.
3470	* @{ */
3471	/** The guest's page directory pointer table, R3 pointer. */
3472	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3473	/** The guest's page directory pointer table, R0 pointer. */
3474	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3475
3476	/** The guest's page directories, R3 pointers.
3477	* These are individual pointers and don't have to be adjacent.
3478	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3479	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3480	/** The guest's page directories, R0 pointers.
3481	* Same restrictions as apGstPaePDsR3. */
3482	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3483	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3484	RTGCPHYS aGCPhysGstPaePDs[4];
3485	/** The physical addresses of the monitored guest page directories (PAE). */
3486	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3487	/** Mask containing the MBZ PTE bits. */
3488	uint64_t fGstPaeMbzPteMask;
3489	/** Mask containing the MBZ PDE bits. */
3490	uint64_t fGstPaeMbzPdeMask;
3491	/** Mask containing the MBZ big page PDE bits. */
3492	uint64_t fGstPaeMbzBigPdeMask;
3493	/** Mask containing the MBZ PDPE bits. */
3494	uint64_t fGstPaeMbzPdpeMask;
3495	/** @} */
3496
3497	/** @name AMD64 Guest Paging.
3498	* @{ */
3499	/** The guest's page directory pointer table, R3 pointer. */
3500	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3501	/** The guest's page directory pointer table, R0 pointer. */
3502	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3503	/** Mask containing the MBZ PTE bits. */
3504	uint64_t fGstAmd64MbzPteMask;
3505	/** Mask containing the MBZ PDE bits. */
3506	uint64_t fGstAmd64MbzPdeMask;
3507	/** Mask containing the MBZ big page PDE bits. */
3508	uint64_t fGstAmd64MbzBigPdeMask;
3509	/** Mask containing the MBZ PDPE bits. */
3510	uint64_t fGstAmd64MbzPdpeMask;
3511	/** Mask containing the MBZ big page PDPE bits. */
3512	uint64_t fGstAmd64MbzBigPdpeMask;
3513	/** Mask containing the MBZ PML4E bits. */
3514	uint64_t fGstAmd64MbzPml4eMask;
3515	/** Mask containing the PDPE bits that we shadow. */
3516	uint64_t fGstAmd64ShadowedPdpeMask;
3517	/** Mask containing the PML4E bits that we shadow. */
3518	uint64_t fGstAmd64ShadowedPml4eMask;
3519	/** @} */
3520
3521	/** @name PAE and AMD64 Guest Paging.
3522	* @{ */
3523	/** Mask containing the PTE bits that we shadow. */
3524	uint64_t fGst64ShadowedPteMask;
3525	/** Mask containing the PDE bits that we shadow. */
3526	uint64_t fGst64ShadowedPdeMask;
3527	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3528	uint64_t fGst64ShadowedBigPdeMask;
3529	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3530	uint64_t fGst64ShadowedBigPde4PteMask;
3531	/** @} */
3532
3533	/** @name EPT Guest Paging.
3534	* @{ */
3535	/** The guest's EPT PML4 table, R3 pointer. */
3536	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3537	/** The guest's EPT PML4 table, R0 pointer. */
3538	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3539	/** The guest's EPT pointer (copy of virtual VMCS). */
3540	uint64_t uEptPtr;
3541	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3542	* change through the lifetime of the VM. */
3543	uint64_t uEptVpidCapMsr;
3544	/** Mask containing the MBZ PTE bits. */
3545	uint64_t fGstEptMbzPteMask;
3546	/** Mask containing the MBZ PDE bits. */
3547	uint64_t fGstEptMbzPdeMask;
3548	/** Mask containing the MBZ big page (2M) PDE bits. */
3549	uint64_t fGstEptMbzBigPdeMask;
3550	/** Mask containing the MBZ PDPTE bits. */
3551	uint64_t fGstEptMbzPdpteMask;
3552	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3553	uint64_t fGstEptMbzBigPdpteMask;
3554	/** Mask containing the MBZ PML4E bits. */
3555	uint64_t fGstEptMbzPml4eMask;
3556	/** Mask to determine whether an entry is present. */
3557	uint64_t fGstEptPresentMask;
3558
3559	/** Mask containing the EPT PTE bits we shadow. */
3560	uint64_t fGstEptShadowedPteMask;
3561	/** Mask containing the EPT PDE bits we shadow. */
3562	uint64_t fGstEptShadowedPdeMask;
3563	/** Mask containing the EPT PDPTE bits we shadow. */
3564	uint64_t fGstEptShadowedPdpteMask;
3565	/** Mask containing the EPT PML4E bits we shadow. */
3566	uint64_t fGstEptShadowedPml4eMask;
3567	/** @} */
3568
3569	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3570	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3571	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3572	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3573
3574	/** For saving stack space, the disassembler state is allocated here instead of
3575	* on the stack. */
3576	DISCPUSTATE DisState;
3577
3578	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3579	uint64_t cNetwareWp0Hacks;
3580
3581	/** Count the number of pgm pool access handler calls. */
3582	uint64_t cPoolAccessHandler;
3583
3584	/** @name Release Statistics
3585	* @{ */
3586	/** The number of times the guest has switched mode since last reset or statistics reset. */
3587	STAMCOUNTER cGuestModeChanges;
3588	/** The number of times the guest has switched mode since last reset or statistics reset. */
3589	STAMCOUNTER cA20Changes;
3590	/** @} */
3591
3592	#ifdef VBOX_WITH_STATISTICS
3593	/** These are statistics that used to be on the hyper heap. */
3594	PGMCPUSTATS Stats;
3595	#endif
3596	} PGMCPU;
3597	/** Pointer to the per-cpu PGM data. */
3598	typedef PGMCPU *PPGMCPU;
3599
3600
3601	/** @name PGM::fSyncFlags Flags
3602	* @note Was part of saved state a long time ago.
3603	* @{
3604	*/
3605	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3606	/** Always sync CR3. */
3607	#define PGM_SYNC_ALWAYS RT_BIT(1)
3608	/** Check guest mapping in SyncCR3. */
3609	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3610	/** Clear the page pool (a light weight flush). */
3611	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3612	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3613	/** @} */
3614
3615
3616	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3617
3618	/**
3619	* PGM GVMCPU instance data.
3620	*/
3621	typedef struct PGMR0PERVCPU
3622	{
3623	# ifdef VBOX_WITH_STATISTICS
3624	/** R0: Which statistic this \#PF should be attributed to. */
3625	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3626	# endif
3627	uint64_t u64Dummy;
3628	} PGMR0PERVCPU;
3629
3630
3631	/**
3632	* PGM GVM instance data.
3633	*/
3634	typedef struct PGMR0PERVM
3635	{
3636	/** @name PGM Pool related stuff.
3637	* @{ */
3638	/** Critical section for serializing pool growth. */
3639	RTCRITSECT PoolGrowCritSect;
3640	/** The memory objects for the pool pages. */
3641	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3642	/** The ring-3 mapping objects for the pool pages. */
3643	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3644	/** @} */
3645
3646	/** Physical access handler types for ring-0.
3647	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3648	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3649	/** Physical handler allocator, ring-3 edition. */
3650	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3651	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3652	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3653	/** The allocation object for the physical access handler tree. */
3654	RTR0MEMOBJ hPhysHandlerMemObj;
3655	/** The ring-3 mapping object for the physicall access handler tree. */
3656	RTR0MEMOBJ hPhysHandlerMapObj;
3657	} PGMR0PERVM;
3658
3659	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3660
3661	RT_C_DECLS_BEGIN
3662
3663	#if defined(VBOX_STRICT)
3664	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3665	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3666	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3667	#else
3668	int pgmLock(PVMCC pVM, bool fVoid);
3669	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3670	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3671	#endif
3672	void pgmUnlock(PVMCC pVM);
3673	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3674	/**
3675	* Asserts that the caller owns the PDM lock.
3676	* This is the internal variant of PGMIsLockOwner.
3677	* @param a_pVM Pointer to the VM.
3678	*/
3679	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3680	/**
3681	* Asserts that the caller owns the PDM lock.
3682	* This is the internal variant of PGMIsLockOwner.
3683	* @param a_pVM Pointer to the VM.
3684	* @param a_pVCpu The current CPU handle.
3685	*/
3686	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3687
3688	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3689	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3690	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3691	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3692	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3693	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3694	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3695	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3696	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3697	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3698	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3699	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3700	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3701	#ifndef IN_RING3
3702	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3703	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3704	#endif
3705
3706	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3707
3708	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3709	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3710	#ifdef IN_RING0
3711	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3712	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3713	#endif
3714	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3715	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3716	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3717	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3718	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3719	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3720	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3721	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3722	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3723	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3724	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3725	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3726	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3727	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3728	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3729	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3730	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3731	#ifndef IN_RING3
3732	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3733	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3734	#endif
3735	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3736	PGMPAGETYPE enmNewType);
3737	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3738	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3739	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3740	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3741	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3742	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3743	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3744	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3745	#ifdef VBOX_WITH_NATIVE_NEM
3746	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3747	#endif
3748
3749	#ifdef IN_RING3
3750	void pgmR3PhysRelinkRamRanges(PVM pVM);
3751	int pgmR3PhysRamPreAllocate(PVM pVM);
3752	int pgmR3PhysRamReset(PVM pVM);
3753	int pgmR3PhysRomReset(PVM pVM);
3754	int pgmR3PhysRamZeroAll(PVM pVM);
3755	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3756	int pgmR3PhysRamTerm(PVM pVM);
3757	void pgmR3PhysRomTerm(PVM pVM);
3758	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3759
3760	int pgmR3PoolInit(PVM pVM);
3761	void pgmR3PoolRelocate(PVM pVM);
3762	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3763	void pgmR3PoolReset(PVM pVM);
3764	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3765	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3766	void pgmR3PoolWriteProtectPages(PVM pVM);
3767
3768	#endif /* IN_RING3 */
3769	#ifdef IN_RING0
3770	int pgmR0PoolInitVM(PGVM pGVM);
3771	#endif
3772	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3773	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3774	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3775	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3776	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3777	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3778	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3779	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3780	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3781	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3782	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3783	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3784	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3785	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3786	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3787	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3788	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3789	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3790	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3791	#ifndef IN_RING3
3792	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3793	#endif
3794
3795	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3796	void pgmPoolResetDirtyPages(PVMCC pVM);
3797	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3798
3799	/** Gets the ring-0 pointer for the given pool page. */
3800	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3801	{
3802	#ifdef IN_RING3
3803	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3804	# ifdef VBOX_STRICT
3805	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3806	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3807	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3808	# endif
3809	return pPool->pPoolR0 + offPage;
3810	#else
3811	RT_NOREF(pPool);
3812	return pPage;
3813	#endif
3814	}
3815
3816	/** Gets the ring-3 pointer for the given pool page. */
3817	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3818	{
3819	#ifdef IN_RING3
3820	RT_NOREF(pPool);
3821	return pPage;
3822	#else
3823	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3824	# ifdef VBOX_STRICT
3825	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3826	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3827	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3828	# endif
3829	return pPool->pPoolR3 + offPage;
3830	#endif
3831	}
3832
3833	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3834	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3835	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3836
3837	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3838	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3839	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3840
3841	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3842	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3843	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3844	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3845	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3846	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3847	#endif
3848	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3849	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3850
3851	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3852	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3853	FNDBGCCMD pgmR3CmdShowSharedModules;
3854	# endif
3855
3856	void pgmLogState(PVM pVM);
3857
3858	RT_C_DECLS_END
3859
3860	/** @} */
3861
3862	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3863

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 96933

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