VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 94156

Last change on this file since 94156 was 93991, checked in by vboxsync, 3 years ago

VMM: Fix a possible PDM queue leak when destroying a VM, bugref:10093
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 75.7 KB
Line 
1/* $Id: PDMInternal.h 93991 2022-02-28 16:29:55Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/pdmasynccompletion.h>
31#ifdef VBOX_WITH_NETSHAPER
32# include <VBox/vmm/pdmnetshaper.h>
33#endif
34#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35# include <VBox/vmm/pdmasynccompletion.h>
36#endif
37#include <VBox/vmm/pdmblkcache.h>
38#include <VBox/vmm/pdmcommon.h>
39#include <VBox/vmm/pdmtask.h>
40#include <VBox/sup.h>
41#include <VBox/msi.h>
42#include <iprt/assert.h>
43#include <iprt/critsect.h>
44#ifdef IN_RING3
45# include <iprt/thread.h>
46#endif
47
48RT_C_DECLS_BEGIN
49
50
51/** @defgroup grp_pdm_int Internal
52 * @ingroup grp_pdm
53 * @internal
54 * @{
55 */
56
57/** @def PDM_WITH_R3R0_CRIT_SECT
58 * Enables or disabled ring-3/ring-0 critical sections. */
59#if defined(DOXYGEN_RUNNING) || 1
60# define PDM_WITH_R3R0_CRIT_SECT
61#endif
62
63/** @def PDMCRITSECT_STRICT
64 * Enables/disables PDM critsect strictness like deadlock detection. */
65#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
66 || defined(DOXYGEN_RUNNING)
67# define PDMCRITSECT_STRICT
68#endif
69
70/** @def PDMCRITSECT_STRICT
71 * Enables/disables PDM read/write critsect strictness like deadlock
72 * detection. */
73#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
74 || defined(DOXYGEN_RUNNING)
75# define PDMCRITSECTRW_STRICT
76#endif
77
78/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
79#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
80/** The maximum device instance (total) size, ring-3 only devices. */
81#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
82/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
83#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK HOST_PAGE_SIZE
84
85
86
87/*******************************************************************************
88* Structures and Typedefs *
89*******************************************************************************/
90
91/** Pointer to a PDM Device. */
92typedef struct PDMDEV *PPDMDEV;
93/** Pointer to a pointer to a PDM Device. */
94typedef PPDMDEV *PPPDMDEV;
95
96/** Pointer to a PDM USB Device. */
97typedef struct PDMUSB *PPDMUSB;
98/** Pointer to a pointer to a PDM USB Device. */
99typedef PPDMUSB *PPPDMUSB;
100
101/** Pointer to a PDM Driver. */
102typedef struct PDMDRV *PPDMDRV;
103/** Pointer to a pointer to a PDM Driver. */
104typedef PPDMDRV *PPPDMDRV;
105
106/** Pointer to a PDM Logical Unit. */
107typedef struct PDMLUN *PPDMLUN;
108/** Pointer to a pointer to a PDM Logical Unit. */
109typedef PPDMLUN *PPPDMLUN;
110
111/** Pointer to a DMAC instance. */
112typedef struct PDMDMAC *PPDMDMAC;
113/** Pointer to a RTC instance. */
114typedef struct PDMRTC *PPDMRTC;
115
116/** Pointer to an USB HUB registration record. */
117typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119/**
120 * Supported asynchronous completion endpoint classes.
121 */
122typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123{
124 /** File class. */
125 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126 /** Number of supported classes. */
127 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128 /** 32bit hack. */
129 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132
133/**
134 * MMIO/IO port registration tracking structure for DBGF tracing.
135 */
136typedef struct PDMDEVINSDBGFTRACK
137{
138 /** Flag whether this tracks a IO port or MMIO registration. */
139 bool fMmio;
140 /** Opaque user data passed during registration. */
141 void *pvUser;
142 /** Type dependent data. */
143 union
144 {
145 /** I/O port registration. */
146 struct
147 {
148 /** IOM I/O port handle. */
149 IOMIOPORTHANDLE hIoPorts;
150 /** Original OUT handler of the device. */
151 PFNIOMIOPORTNEWOUT pfnOut;
152 /** Original IN handler of the device. */
153 PFNIOMIOPORTNEWIN pfnIn;
154 /** Original string OUT handler of the device. */
155 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
156 /** Original string IN handler of the device. */
157 PFNIOMIOPORTNEWINSTRING pfnInStr;
158 } IoPort;
159 /** MMIO registration. */
160 struct
161 {
162 /** IOM MMIO region handle. */
163 IOMMMIOHANDLE hMmioRegion;
164 /** Original MMIO write handler of the device. */
165 PFNIOMMMIONEWWRITE pfnWrite;
166 /** Original MMIO read handler of the device. */
167 PFNIOMMMIONEWREAD pfnRead;
168 /** Original MMIO fill handler of the device. */
169 PFNIOMMMIONEWFILL pfnFill;
170 } Mmio;
171 } u;
172} PDMDEVINSDBGFTRACK;
173/** Pointer to a MMIO/IO port registration tracking structure. */
174typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
175/** Pointer to a const MMIO/IO port registration tracking structure. */
176typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
177
178
179/**
180 * Private device instance data, ring-3.
181 */
182typedef struct PDMDEVINSINTR3
183{
184 /** Pointer to the next instance.
185 * (Head is pointed to by PDM::pDevInstances.) */
186 R3PTRTYPE(PPDMDEVINS) pNextR3;
187 /** Pointer to the next per device instance.
188 * (Head is pointed to by PDMDEV::pInstances.) */
189 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
190 /** Pointer to device structure. */
191 R3PTRTYPE(PPDMDEV) pDevR3;
192 /** Pointer to the list of logical units associated with the device. (FIFO) */
193 R3PTRTYPE(PPDMLUN) pLunsR3;
194 /** Pointer to the asynchronous notification callback set while in
195 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
196 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
197 /** Configuration handle to the instance node. */
198 R3PTRTYPE(PCFGMNODE) pCfgHandle;
199
200 /** R3 pointer to the VM this instance was created for. */
201 PVMR3 pVMR3;
202 /** DBGF trace event source handle if tracing is configured. */
203 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
204 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
205 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
206 /** Index of the next entry to use for tracking. */
207 uint32_t idxDbgfTraceTrackNext;
208 /** Maximum number of records fitting into the single page. */
209 uint32_t cDbgfTraceTrackMax;
210
211 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
212 uint32_t fIntFlags;
213 /** The last IRQ tag (for tracing it thru clearing). */
214 uint32_t uLastIrqTag;
215 /** The ring-0 device index (for making ring-0 calls). */
216 uint32_t idxR0Device;
217} PDMDEVINSINTR3;
218
219
220/**
221 * Private device instance data, ring-0.
222 */
223typedef struct PDMDEVINSINTR0
224{
225 /** Pointer to the VM this instance was created for. */
226 R0PTRTYPE(PGVM) pGVM;
227 /** Pointer to device structure. */
228 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
229 /** The ring-0 module reference. */
230 RTR0PTR hMod;
231 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
232 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
233 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
234 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
235 /** DBGF trace event source handle if tracing is configured. */
236 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
237 /** The device instance memory. */
238 RTR0MEMOBJ hMemObj;
239 /** The ring-3 mapping object. */
240 RTR0MEMOBJ hMapObj;
241 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
242 RTR0MEMOBJ hDbgfTraceObj;
243 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
244 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
245 /** Index of the next entry to use for tracking. */
246 uint32_t idxDbgfTraceTrackNext;
247 /** Maximum number of records fitting into the single page. */
248 uint32_t cDbgfTraceTrackMax;
249 /** Index into PDMR0PERVM::apDevInstances. */
250 uint32_t idxR0Device;
251} PDMDEVINSINTR0;
252
253
254/**
255 * Private device instance data, raw-mode
256 */
257typedef struct PDMDEVINSINTRC
258{
259 /** Pointer to the VM this instance was created for. */
260 RGPTRTYPE(PVM) pVMRC;
261} PDMDEVINSINTRC;
262
263
264/**
265 * Private device instance data.
266 */
267typedef struct PDMDEVINSINT
268{
269 /** Pointer to the next instance (HC Ptr).
270 * (Head is pointed to by PDM::pDevInstances.) */
271 R3PTRTYPE(PPDMDEVINS) pNextR3;
272 /** Pointer to the next per device instance (HC Ptr).
273 * (Head is pointed to by PDMDEV::pInstances.) */
274 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
275 /** Pointer to device structure - HC Ptr. */
276 R3PTRTYPE(PPDMDEV) pDevR3;
277 /** Pointer to the list of logical units associated with the device. (FIFO) */
278 R3PTRTYPE(PPDMLUN) pLunsR3;
279 /** Pointer to the asynchronous notification callback set while in
280 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
281 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
282 /** Configuration handle to the instance node. */
283 R3PTRTYPE(PCFGMNODE) pCfgHandle;
284
285 /** R3 pointer to the VM this instance was created for. */
286 PVMR3 pVMR3;
287
288 /** R0 pointer to the VM this instance was created for. */
289 R0PTRTYPE(PVMCC) pVMR0;
290
291 /** RC pointer to the VM this instance was created for. */
292 PVMRC pVMRC;
293
294 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
295 uint32_t fIntFlags;
296 /** The last IRQ tag (for tracing it thru clearing). */
297 uint32_t uLastIrqTag;
298} PDMDEVINSINT;
299
300/** @name PDMDEVINSINT::fIntFlags
301 * @{ */
302/** Used by pdmR3Load to mark device instances it found in the saved state. */
303#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
304/** Indicates that the device hasn't been powered on or resumed.
305 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
306 * to make sure each device gets exactly one notification for each of those
307 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
308 * a failure (already resumed/powered-on devices are suspended).
309 * PDMR3PowerOff resets this flag once before going through the devices to make sure
310 * every device gets the power off notification even if it was suspended before with
311 * PDMR3Suspend.
312 */
313#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
314/** Indicates that the device has been reset already. Used by PDMR3Reset. */
315#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
316#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
317#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
318/** Set if we've called the ring-0 constructor. */
319#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
320/** Set if using non-default critical section. */
321#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
322/** @} */
323
324
325/**
326 * Private USB device instance data.
327 */
328typedef struct PDMUSBINSINT
329{
330 /** The UUID of this instance. */
331 RTUUID Uuid;
332 /** Pointer to the next instance.
333 * (Head is pointed to by PDM::pUsbInstances.) */
334 R3PTRTYPE(PPDMUSBINS) pNext;
335 /** Pointer to the next per USB device instance.
336 * (Head is pointed to by PDMUSB::pInstances.) */
337 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
338
339 /** Pointer to device structure. */
340 R3PTRTYPE(PPDMUSB) pUsbDev;
341
342 /** Pointer to the VM this instance was created for. */
343 PVMR3 pVM;
344 /** Pointer to the list of logical units associated with the device. (FIFO) */
345 R3PTRTYPE(PPDMLUN) pLuns;
346 /** The per instance device configuration. */
347 R3PTRTYPE(PCFGMNODE) pCfg;
348 /** Same as pCfg if the configuration should be deleted when detaching the device. */
349 R3PTRTYPE(PCFGMNODE) pCfgDelete;
350 /** The global device configuration. */
351 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
352
353 /** Pointer to the USB hub this device is attached to.
354 * This is NULL if the device isn't connected to any HUB. */
355 R3PTRTYPE(PPDMUSBHUB) pHub;
356 /** The port number that we're connected to. */
357 uint32_t iPort;
358 /** Indicates that the USB device hasn't been powered on or resumed.
359 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
360 bool fVMSuspended;
361 /** Indicates that the USB device has been reset. */
362 bool fVMReset;
363 /** Pointer to the asynchronous notification callback set while in
364 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
365 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
366} PDMUSBINSINT;
367
368
369/**
370 * Private driver instance data.
371 */
372typedef struct PDMDRVINSINT
373{
374 /** Pointer to the driver instance above.
375 * This is NULL for the topmost drive. */
376 R3PTRTYPE(PPDMDRVINS) pUp;
377 /** Pointer to the driver instance below.
378 * This is NULL for the bottommost driver. */
379 R3PTRTYPE(PPDMDRVINS) pDown;
380 /** Pointer to the logical unit this driver chained on. */
381 R3PTRTYPE(PPDMLUN) pLun;
382 /** Pointer to driver structure from which this was instantiated. */
383 R3PTRTYPE(PPDMDRV) pDrv;
384 /** Pointer to the VM this instance was created for, ring-3 context. */
385 PVMR3 pVMR3;
386 /** Pointer to the VM this instance was created for, ring-0 context. */
387 R0PTRTYPE(PVMCC) pVMR0;
388 /** Pointer to the VM this instance was created for, raw-mode context. */
389 PVMRC pVMRC;
390 /** Flag indicating that the driver is being detached and destroyed.
391 * (Helps detect potential recursive detaching.) */
392 bool fDetaching;
393 /** Indicates that the driver hasn't been powered on or resumed.
394 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
395 bool fVMSuspended;
396 /** Indicates that the driver has been reset already. */
397 bool fVMReset;
398 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
399 bool fHyperHeap;
400 /** Pointer to the asynchronous notification callback set while in
401 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
402 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
403 /** Configuration handle to the instance node. */
404 R3PTRTYPE(PCFGMNODE) pCfgHandle;
405 /** Pointer to the ring-0 request handler function. */
406 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
407} PDMDRVINSINT;
408
409
410/**
411 * Private critical section data.
412 */
413typedef struct PDMCRITSECTINT
414{
415 /** The critical section core which is shared with IPRT.
416 * @note The semaphore is a SUPSEMEVENT. */
417 RTCRITSECT Core;
418 /** Pointer to the next critical section.
419 * This chain is used for device cleanup and the dbgf info item. */
420 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
421 /** Owner identifier.
422 * This is pDevIns if the owner is a device. Similarly for a driver or service.
423 * PDMR3CritSectInit() sets this to point to the critsect itself. */
424 RTR3PTR pvKey;
425 /** Set if this critical section is the automatically created default
426 * section of a device. */
427 bool fAutomaticDefaultCritsect;
428 /** Set if the critical section is used by a timer or similar.
429 * See PDMR3DevGetCritSect. */
430 bool fUsedByTimerOrSimilar;
431 /** Alignment padding. */
432 bool afPadding[2+4];
433 /** Support driver event semaphore that is scheduled to be signaled upon leaving
434 * the critical section. This is only for Ring-3 and Ring-0. */
435 SUPSEMEVENT volatile hEventToSignal;
436 /** The lock name. */
437 R3PTRTYPE(const char *) pszName;
438 /** The ring-3 pointer to this critical section, for leave queueing. */
439 R3PTRTYPE(PPDMCRITSECT) pSelfR3;
440 /** R0/RC lock contention. */
441 STAMCOUNTER StatContentionRZLock;
442 /** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
443 STAMCOUNTER StatContentionRZLockBusy;
444 /** R0/RC lock contention: Profiling waiting time. */
445 STAMPROFILE StatContentionRZWait;
446 /** R0/RC unlock contention. */
447 STAMCOUNTER StatContentionRZUnlock;
448 /** R3 lock contention. */
449 STAMCOUNTER StatContentionR3;
450 /** R3 lock contention: Profiling waiting time. */
451 STAMPROFILE StatContentionR3Wait;
452 /** Profiling the time the section is locked. */
453 STAMPROFILEADV StatLocked;
454} PDMCRITSECTINT;
455AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
456/** Pointer to private critical section data. */
457typedef PDMCRITSECTINT *PPDMCRITSECTINT;
458
459/** Special magic value set when we failed to abort entering in ring-0 due to a
460 * timeout, interruption or pending thread termination. */
461#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
462/** Special magic value set if we detected data/state corruption. */
463#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
464
465/** Indicates that the critical section is queued for unlock.
466 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
467#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
468
469
470/**
471 * Private critical section data.
472 */
473typedef struct PDMCRITSECTRWINT
474{
475 /** The read/write critical section core which is shared with IPRT.
476 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
477 RTCRITSECTRW Core;
478
479 /** Pointer to the next critical section.
480 * This chain is used for device cleanup and the dbgf info item. */
481 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
482 /** Self pointer. */
483 R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
484 /** Owner identifier.
485 * This is pDevIns if the owner is a device. Similarly for a driver or service.
486 * PDMR3CritSectRwInit() sets this to point to the critsect itself. */
487 RTR3PTR pvKey;
488 /** The lock name. */
489 R3PTRTYPE(const char *) pszName;
490
491 /** R0/RC write lock contention. */
492 STAMCOUNTER StatContentionRZEnterExcl;
493 /** R0/RC write unlock contention. */
494 STAMCOUNTER StatContentionRZLeaveExcl;
495 /** R0/RC read lock contention. */
496 STAMCOUNTER StatContentionRZEnterShared;
497 /** R0/RC read unlock contention. */
498 STAMCOUNTER StatContentionRZLeaveShared;
499 /** R0/RC writes. */
500 STAMCOUNTER StatRZEnterExcl;
501 /** R0/RC reads. */
502 STAMCOUNTER StatRZEnterShared;
503 /** R3 write lock contention. */
504 STAMCOUNTER StatContentionR3EnterExcl;
505 /** R3 write unlock contention. */
506 STAMCOUNTER StatContentionR3LeaveExcl;
507 /** R3 read lock contention. */
508 STAMCOUNTER StatContentionR3EnterShared;
509 /** R3 writes. */
510 STAMCOUNTER StatR3EnterExcl;
511 /** R3 reads. */
512 STAMCOUNTER StatR3EnterShared;
513 /** Profiling the time the section is write locked. */
514 STAMPROFILEADV StatWriteLocked;
515} PDMCRITSECTRWINT;
516AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
517AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u, 16);
518AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u.s.u64State, 8);
519/** Pointer to private critical section data. */
520typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
521
522/** Special magic value we set the structure has become corrupted. */
523#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
524
525
526/**
527 * The usual device/driver/internal/external stuff.
528 */
529typedef enum
530{
531 /** The usual invalid entry. */
532 PDMTHREADTYPE_INVALID = 0,
533 /** Device type. */
534 PDMTHREADTYPE_DEVICE,
535 /** USB Device type. */
536 PDMTHREADTYPE_USB,
537 /** Driver type. */
538 PDMTHREADTYPE_DRIVER,
539 /** Internal type. */
540 PDMTHREADTYPE_INTERNAL,
541 /** External type. */
542 PDMTHREADTYPE_EXTERNAL,
543 /** The usual 32-bit hack. */
544 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
545} PDMTHREADTYPE;
546
547
548/**
549 * The internal structure for the thread.
550 */
551typedef struct PDMTHREADINT
552{
553 /** The VM pointer. */
554 PVMR3 pVM;
555 /** The event semaphore the thread blocks on when not running. */
556 RTSEMEVENTMULTI BlockEvent;
557 /** The event semaphore the thread sleeps on while running. */
558 RTSEMEVENTMULTI SleepEvent;
559 /** Pointer to the next thread. */
560 R3PTRTYPE(struct PDMTHREAD *) pNext;
561 /** The thread type. */
562 PDMTHREADTYPE enmType;
563} PDMTHREADINT;
564
565
566
567/* Must be included after PDMDEVINSINT is defined. */
568#define PDMDEVINSINT_DECLARED
569#define PDMUSBINSINT_DECLARED
570#define PDMDRVINSINT_DECLARED
571#define PDMCRITSECTINT_DECLARED
572#define PDMCRITSECTRWINT_DECLARED
573#define PDMTHREADINT_DECLARED
574#ifdef ___VBox_pdm_h
575# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
576#endif
577RT_C_DECLS_END
578#include <VBox/vmm/pdm.h>
579RT_C_DECLS_BEGIN
580
581/**
582 * PDM Logical Unit.
583 *
584 * This typically the representation of a physical port on a
585 * device, like for instance the PS/2 keyboard port on the
586 * keyboard controller device. The LUNs are chained on the
587 * device they belong to (PDMDEVINSINT::pLunsR3).
588 */
589typedef struct PDMLUN
590{
591 /** The LUN - The Logical Unit Number. */
592 RTUINT iLun;
593 /** Pointer to the next LUN. */
594 PPDMLUN pNext;
595 /** Pointer to the top driver in the driver chain. */
596 PPDMDRVINS pTop;
597 /** Pointer to the bottom driver in the driver chain. */
598 PPDMDRVINS pBottom;
599 /** Pointer to the device instance which the LUN belongs to.
600 * Either this is set or pUsbIns is set. Both is never set at the same time. */
601 PPDMDEVINS pDevIns;
602 /** Pointer to the USB device instance which the LUN belongs to. */
603 PPDMUSBINS pUsbIns;
604 /** Pointer to the device base interface. */
605 PPDMIBASE pBase;
606 /** Description of this LUN. */
607 const char *pszDesc;
608} PDMLUN;
609
610
611/**
612 * PDM Device, ring-3.
613 */
614typedef struct PDMDEV
615{
616 /** Pointer to the next device (R3 Ptr). */
617 R3PTRTYPE(PPDMDEV) pNext;
618 /** Device name length. (search optimization) */
619 uint32_t cchName;
620 /** Registration structure. */
621 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
622 /** Number of instances. */
623 uint32_t cInstances;
624 /** Pointer to chain of instances (R3 Ptr). */
625 PPDMDEVINSR3 pInstances;
626 /** The search path for raw-mode context modules (';' as separator). */
627 char *pszRCSearchPath;
628 /** The search path for ring-0 context modules (';' as separator). */
629 char *pszR0SearchPath;
630} PDMDEV;
631
632
633#if 0
634/**
635 * PDM Device, ring-0.
636 */
637typedef struct PDMDEVR0
638{
639 /** Pointer to the next device. */
640 R0PTRTYPE(PPDMDEVR0) pNext;
641 /** Device name length. (search optimization) */
642 uint32_t cchName;
643 /** Registration structure. */
644 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
645 /** Number of instances. */
646 uint32_t cInstances;
647 /** Pointer to chain of instances. */
648 PPDMDEVINSR0 pInstances;
649} PDMDEVR0;
650#endif
651
652
653/**
654 * PDM USB Device.
655 */
656typedef struct PDMUSB
657{
658 /** Pointer to the next device (R3 Ptr). */
659 R3PTRTYPE(PPDMUSB) pNext;
660 /** Device name length. (search optimization) */
661 RTUINT cchName;
662 /** Registration structure. */
663 R3PTRTYPE(const struct PDMUSBREG *) pReg;
664 /** Next instance number. */
665 uint32_t iNextInstance;
666 /** Pointer to chain of instances (R3 Ptr). */
667 R3PTRTYPE(PPDMUSBINS) pInstances;
668} PDMUSB;
669
670
671/**
672 * PDM Driver.
673 */
674typedef struct PDMDRV
675{
676 /** Pointer to the next device. */
677 PPDMDRV pNext;
678 /** Registration structure. */
679 const struct PDMDRVREG * pReg;
680 /** Current number of instances. */
681 uint32_t cInstances;
682 /** The next instance number. */
683 uint32_t iNextInstance;
684 /** The search path for raw-mode context modules (';' as separator). */
685 char *pszRCSearchPath;
686 /** The search path for ring-0 context modules (';' as separator). */
687 char *pszR0SearchPath;
688} PDMDRV;
689
690
691/**
692 * PDM IOMMU, shared ring-3.
693 */
694typedef struct PDMIOMMUR3
695{
696 /** IOMMU index. */
697 uint32_t idxIommu;
698 uint32_t uPadding0; /**< Alignment padding.*/
699
700 /** Pointer to the IOMMU device instance - R3. */
701 PPDMDEVINSR3 pDevInsR3;
702 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
703 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
704 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
705 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
706 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
707 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
708 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
709 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
710} PDMIOMMUR3;
711/** Pointer to a PDM IOMMU instance. */
712typedef PDMIOMMUR3 *PPDMIOMMUR3;
713/** Pointer to a const PDM IOMMU instance. */
714typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
715
716
717/**
718 * PDM IOMMU, ring-0.
719 */
720typedef struct PDMIOMMUR0
721{
722 /** IOMMU index. */
723 uint32_t idxIommu;
724 uint32_t uPadding0; /**< Alignment padding.*/
725
726 /** Pointer to IOMMU device instance. */
727 PPDMDEVINSR0 pDevInsR0;
728 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
729 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
730 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
731 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
732 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
733 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
734 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
735 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
736} PDMIOMMUR0;
737/** Pointer to a ring-0 IOMMU data. */
738typedef PDMIOMMUR0 *PPDMIOMMUR0;
739/** Pointer to a const ring-0 IOMMU data. */
740typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
741
742/** Pointer to a PDM IOMMU for the current context. */
743#ifdef IN_RING3
744typedef PPDMIOMMUR3 PPDMIOMMU;
745#else
746typedef PPDMIOMMUR0 PPDMIOMMU;
747#endif
748
749
750/**
751 * PDM registered PIC device.
752 */
753typedef struct PDMPIC
754{
755 /** Pointer to the PIC device instance - R3. */
756 PPDMDEVINSR3 pDevInsR3;
757 /** @copydoc PDMPICREG::pfnSetIrq */
758 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
759 /** @copydoc PDMPICREG::pfnGetInterrupt */
760 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
761
762 /** Pointer to the PIC device instance - R0. */
763 PPDMDEVINSR0 pDevInsR0;
764 /** @copydoc PDMPICREG::pfnSetIrq */
765 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
766 /** @copydoc PDMPICREG::pfnGetInterrupt */
767 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
768
769 /** Pointer to the PIC device instance - RC. */
770 PPDMDEVINSRC pDevInsRC;
771 /** @copydoc PDMPICREG::pfnSetIrq */
772 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
773 /** @copydoc PDMPICREG::pfnGetInterrupt */
774 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
775 /** Alignment padding. */
776 RTRCPTR RCPtrPadding;
777} PDMPIC;
778
779
780/**
781 * PDM registered APIC device.
782 */
783typedef struct PDMAPIC
784{
785 /** Pointer to the APIC device instance - R3 Ptr. */
786 PPDMDEVINSR3 pDevInsR3;
787 /** Pointer to the APIC device instance - R0 Ptr. */
788 PPDMDEVINSR0 pDevInsR0;
789 /** Pointer to the APIC device instance - RC Ptr. */
790 PPDMDEVINSRC pDevInsRC;
791 uint8_t Alignment[4];
792} PDMAPIC;
793
794
795/**
796 * PDM registered I/O APIC device.
797 */
798typedef struct PDMIOAPIC
799{
800 /** Pointer to the I/O APIC device instance - R3 Ptr. */
801 PPDMDEVINSR3 pDevInsR3;
802 /** @copydoc PDMIOAPICREG::pfnSetIrq */
803 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
804 /** @copydoc PDMIOAPICREG::pfnSendMsi */
805 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
806 /** @copydoc PDMIOAPICREG::pfnSetEoi */
807 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
808
809 /** Pointer to the I/O APIC device instance - R0. */
810 PPDMDEVINSR0 pDevInsR0;
811 /** @copydoc PDMIOAPICREG::pfnSetIrq */
812 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
813 /** @copydoc PDMIOAPICREG::pfnSendMsi */
814 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
815 /** @copydoc PDMIOAPICREG::pfnSetEoi */
816 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
817
818 /** Pointer to the I/O APIC device instance - RC Ptr. */
819 PPDMDEVINSRC pDevInsRC;
820 /** @copydoc PDMIOAPICREG::pfnSetIrq */
821 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
822 /** @copydoc PDMIOAPICREG::pfnSendMsi */
823 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
824 /** @copydoc PDMIOAPICREG::pfnSendMsi */
825 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
826} PDMIOAPIC;
827/** Pointer to a PDM IOAPIC instance. */
828typedef PDMIOAPIC *PPDMIOAPIC;
829/** Pointer to a const PDM IOAPIC instance. */
830typedef PDMIOAPIC const *PCPDMIOAPIC;
831
832/** Maximum number of PCI busses for a VM. */
833#define PDM_PCI_BUSSES_MAX 8
834/** Maximum number of IOMMUs (at most one per PCI bus). */
835#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
836
837
838#ifdef IN_RING3
839/**
840 * PDM registered firmware device.
841 */
842typedef struct PDMFW
843{
844 /** Pointer to the firmware device instance. */
845 PPDMDEVINSR3 pDevIns;
846 /** Copy of the registration structure. */
847 PDMFWREG Reg;
848} PDMFW;
849/** Pointer to a firmware instance. */
850typedef PDMFW *PPDMFW;
851#endif
852
853
854/**
855 * PDM PCI bus instance.
856 */
857typedef struct PDMPCIBUS
858{
859 /** PCI bus number. */
860 uint32_t iBus;
861 uint32_t uPadding0; /**< Alignment padding.*/
862
863 /** Pointer to PCI bus device instance. */
864 PPDMDEVINSR3 pDevInsR3;
865 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
866 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
867
868 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
869 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
870 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
871 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
872 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
873 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
874 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
875 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
876 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
877 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
878 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
879 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
880 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
881 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
882 uint32_t uAddress, unsigned cb, uint32_t u32Value));
883 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
884 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
885 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
886} PDMPCIBUS;
887/** Pointer to a PDM PCI Bus instance. */
888typedef PDMPCIBUS *PPDMPCIBUS;
889/** Pointer to a const PDM PCI Bus instance. */
890typedef const PDMPCIBUS *PCPDMPCIBUS;
891
892
893/**
894 * Ring-0 PDM PCI bus instance data.
895 */
896typedef struct PDMPCIBUSR0
897{
898 /** PCI bus number. */
899 uint32_t iBus;
900 uint32_t uPadding0; /**< Alignment padding.*/
901 /** Pointer to PCI bus device instance. */
902 PPDMDEVINSR0 pDevInsR0;
903 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
904 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
905} PDMPCIBUSR0;
906/** Pointer to the ring-0 PCI bus data. */
907typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
908/** Pointer to the const ring-0 PCI bus data. */
909typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
910
911
912#ifdef IN_RING3
913/**
914 * PDM registered DMAC (DMA Controller) device.
915 */
916typedef struct PDMDMAC
917{
918 /** Pointer to the DMAC device instance. */
919 PPDMDEVINSR3 pDevIns;
920 /** Copy of the registration structure. */
921 PDMDMACREG Reg;
922} PDMDMAC;
923
924
925/**
926 * PDM registered RTC (Real Time Clock) device.
927 */
928typedef struct PDMRTC
929{
930 /** Pointer to the RTC device instance. */
931 PPDMDEVINSR3 pDevIns;
932 /** Copy of the registration structure. */
933 PDMRTCREG Reg;
934} PDMRTC;
935
936#endif /* IN_RING3 */
937
938/**
939 * Module type.
940 */
941typedef enum PDMMODTYPE
942{
943 /** Raw-mode (RC) context module. */
944 PDMMOD_TYPE_RC,
945 /** Ring-0 (host) context module. */
946 PDMMOD_TYPE_R0,
947 /** Ring-3 (host) context module. */
948 PDMMOD_TYPE_R3
949} PDMMODTYPE;
950
951
952/** The module name length including the terminator. */
953#define PDMMOD_NAME_LEN 32
954
955/**
956 * Loaded module instance.
957 */
958typedef struct PDMMOD
959{
960 /** Module name. This is used for referring to
961 * the module internally, sort of like a handle. */
962 char szName[PDMMOD_NAME_LEN];
963 /** Module type. */
964 PDMMODTYPE eType;
965 /** Loader module handle. Not used for R0 modules. */
966 RTLDRMOD hLdrMod;
967 /** Loaded address.
968 * This is the 'handle' for R0 modules. */
969 RTUINTPTR ImageBase;
970 /** Old loaded address.
971 * This is used during relocation of GC modules. Not used for R0 modules. */
972 RTUINTPTR OldImageBase;
973 /** Where the R3 HC bits are stored.
974 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
975 void *pvBits;
976
977 /** Pointer to next module. */
978 struct PDMMOD *pNext;
979 /** Module filename. */
980 char szFilename[1];
981} PDMMOD;
982/** Pointer to loaded module instance. */
983typedef PDMMOD *PPDMMOD;
984
985
986
987/** Max number of items in a queue. */
988#define PDMQUEUE_MAX_ITEMS _16K
989/** Max item size. */
990#define PDMQUEUE_MAX_ITEM_SIZE _1M
991/** Max total queue item size for ring-0 capable queues. */
992#define PDMQUEUE_MAX_TOTAL_SIZE_R0 _8M
993/** Max total queue item size for ring-3 only queues. */
994#define PDMQUEUE_MAX_TOTAL_SIZE_R3 _32M
995
996/**
997 * Queue type.
998 */
999typedef enum PDMQUEUETYPE
1000{
1001 /** Device consumer. */
1002 PDMQUEUETYPE_DEV = 1,
1003 /** Driver consumer. */
1004 PDMQUEUETYPE_DRV,
1005 /** Internal consumer. */
1006 PDMQUEUETYPE_INTERNAL,
1007 /** External consumer. */
1008 PDMQUEUETYPE_EXTERNAL
1009} PDMQUEUETYPE;
1010
1011/**
1012 * PDM Queue.
1013 */
1014typedef struct PDMQUEUE
1015{
1016 /** Magic value (PDMQUEUE_MAGIC). */
1017 uint32_t u32Magic;
1018 /** Item size (bytes). */
1019 uint32_t cbItem;
1020 /** Number of items in the queue. */
1021 uint32_t cItems;
1022 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1023 uint32_t offItems;
1024
1025 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1026 TMTIMERHANDLE hTimer;
1027 /** The interval between checking the queue for events.
1028 * The realtime timer below is used to do the waiting.
1029 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1030 uint32_t cMilliesInterval;
1031
1032 /** This is VINF_SUCCESS if the queue is okay, error status if not. */
1033 int32_t rcOkay;
1034 uint32_t u32Padding;
1035
1036 /** Queue type. */
1037 PDMQUEUETYPE enmType;
1038 /** Type specific data. */
1039 union
1040 {
1041 /** PDMQUEUETYPE_DEV */
1042 struct
1043 {
1044 /** Pointer to consumer function. */
1045 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1046 /** Pointer to the device instance owning the queue. */
1047 R3PTRTYPE(PPDMDEVINS) pDevIns;
1048 } Dev;
1049 /** PDMQUEUETYPE_DRV */
1050 struct
1051 {
1052 /** Pointer to consumer function. */
1053 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1054 /** Pointer to the driver instance owning the queue. */
1055 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1056 } Drv;
1057 /** PDMQUEUETYPE_INTERNAL */
1058 struct
1059 {
1060 /** Pointer to consumer function. */
1061 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1062 } Int;
1063 /** PDMQUEUETYPE_EXTERNAL */
1064 struct
1065 {
1066 /** Pointer to consumer function. */
1067 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1068 /** Pointer to user argument. */
1069 R3PTRTYPE(void *) pvUser;
1070 } Ext;
1071 struct
1072 {
1073 /** Generic callback pointer. */
1074 RTR3PTR pfnCallback;
1075 /** Generic owner pointer. */
1076 RTR3PTR pvOwner;
1077 } Gen;
1078 } u;
1079
1080 /** Unique queue name. */
1081 char szName[40];
1082
1083 /** LIFO of pending items (item index), UINT32_MAX if empty. */
1084 uint32_t volatile iPending;
1085
1086 /** State: Pending items. */
1087 uint32_t volatile cStatPending;
1088 /** Stat: Times PDMQueueAlloc fails. */
1089 STAMCOUNTER StatAllocFailures;
1090 /** Stat: PDMQueueInsert calls. */
1091 STAMCOUNTER StatInsert;
1092 /** Stat: Queue flushes. */
1093 STAMCOUNTER StatFlush;
1094 /** Stat: Queue flushes with pending items left over. */
1095 STAMCOUNTER StatFlushLeftovers;
1096 /** State: Profiling the flushing. */
1097 STAMPROFILE StatFlushPrf;
1098 uint64_t au64Padding[3];
1099
1100 /** Allocation bitmap: Set bits means free, clear means allocated. */
1101 RT_FLEXIBLE_ARRAY_EXTENSION
1102 uint64_t bmAlloc[RT_FLEXIBLE_ARRAY];
1103 /* The items follows after the end of the bitmap */
1104} PDMQUEUE;
1105AssertCompileMemberAlignment(PDMQUEUE, bmAlloc, 64);
1106/** Pointer to a PDM Queue. */
1107typedef struct PDMQUEUE *PPDMQUEUE;
1108
1109/** Magic value PDMQUEUE::u32Magic (Bud Powell). */
1110#define PDMQUEUE_MAGIC UINT32_C(0x19240927)
1111/** Magic value PDMQUEUE::u32Magic after destroy. */
1112#define PDMQUEUE_MAGIC_DEAD UINT32_C(0x19660731)
1113
1114/** @name PDM::fQueueFlushing
1115 * @{ */
1116/** Used to make sure only one EMT will flush the queues.
1117 * Set when an EMT is flushing queues, clear otherwise. */
1118#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1119/** Indicating there are queues with items pending.
1120 * This is make sure we don't miss inserts happening during flushing. The FF
1121 * cannot be used for this since it has to be cleared immediately to prevent
1122 * other EMTs from spinning. */
1123#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1124/** @} */
1125
1126/**
1127 * Ring-0 queue
1128 *
1129 * @author bird (2022-02-04)
1130 */
1131typedef struct PDMQUEUER0
1132{
1133 /** Pointer to the shared queue data. */
1134 R0PTRTYPE(PPDMQUEUE) pQueue;
1135 /** The memory allocation. */
1136 RTR0MEMOBJ hMemObj;
1137 /** The ring-3 mapping object. */
1138 RTR0MEMOBJ hMapObj;
1139 /** The owner pointer. This is NULL if not allocated. */
1140 RTR0PTR pvOwner;
1141 /** Queue item size. */
1142 uint32_t cbItem;
1143 /** Number of queue items. */
1144 uint32_t cItems;
1145 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1146 uint32_t offItems;
1147 uint32_t u32Reserved;
1148} PDMQUEUER0;
1149
1150
1151/** @name PDM task structures.
1152 * @{ */
1153
1154/**
1155 * A asynchronous user mode task.
1156 */
1157typedef struct PDMTASK
1158{
1159 /** Task owner type. */
1160 PDMTASKTYPE volatile enmType;
1161 /** Queue flags. */
1162 uint32_t volatile fFlags;
1163 /** User argument for the callback. */
1164 R3PTRTYPE(void *) volatile pvUser;
1165 /** The callback (will be cast according to enmType before callout). */
1166 R3PTRTYPE(PFNRT) volatile pfnCallback;
1167 /** The owner identifier. */
1168 R3PTRTYPE(void *) volatile pvOwner;
1169 /** Task name. */
1170 R3PTRTYPE(const char *) pszName;
1171 /** Number of times already triggered when PDMTaskTrigger was called. */
1172 uint32_t volatile cAlreadyTrigged;
1173 /** Number of runs. */
1174 uint32_t cRuns;
1175} PDMTASK;
1176/** Pointer to a PDM task. */
1177typedef PDMTASK *PPDMTASK;
1178
1179/**
1180 * A task set.
1181 *
1182 * This is served by one task executor thread.
1183 */
1184typedef struct PDMTASKSET
1185{
1186 /** Magic value (PDMTASKSET_MAGIC). */
1187 uint32_t u32Magic;
1188 /** Set if this task set works for ring-0 and raw-mode. */
1189 bool fRZEnabled;
1190 /** Number of allocated taks. */
1191 uint8_t volatile cAllocated;
1192 /** Base handle value for this set. */
1193 uint16_t uHandleBase;
1194 /** The task executor thread. */
1195 R3PTRTYPE(RTTHREAD) hThread;
1196 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1197 SUPSEMEVENT hEventR0;
1198 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1199 R3PTRTYPE(RTSEMEVENT) hEventR3;
1200 /** The VM pointer. */
1201 PVM pVM;
1202 /** Padding so fTriggered is in its own cacheline. */
1203 uint64_t au64Padding2[3];
1204
1205 /** Bitmask of triggered tasks. */
1206 uint64_t volatile fTriggered;
1207 /** Shutdown thread indicator. */
1208 bool volatile fShutdown;
1209 /** Padding. */
1210 bool volatile afPadding3[3];
1211 /** Task currently running, UINT32_MAX if idle. */
1212 uint32_t volatile idxRunning;
1213 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1214 uint64_t volatile au64Padding3[6];
1215
1216 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1217 PDMTASK aTasks[64];
1218} PDMTASKSET;
1219AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1220AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1221/** Magic value for PDMTASKSET::u32Magic (Quincy Delight Jones Jr.). */
1222#define PDMTASKSET_MAGIC UINT32_C(0x19330314)
1223/** Pointer to a task set. */
1224typedef PDMTASKSET *PPDMTASKSET;
1225
1226/** @} */
1227
1228
1229/** @name PDM Network Shaper
1230 * @{ */
1231
1232/**
1233 * Bandwidth group.
1234 */
1235typedef struct PDMNSBWGROUP
1236{
1237 /** Critical section protecting all members below. */
1238 PDMCRITSECT Lock;
1239 /** List of filters in this group (PDMNSFILTER). */
1240 RTLISTANCHORR3 FilterList;
1241 /** Reference counter - How many filters are associated with this group. */
1242 volatile uint32_t cRefs;
1243 uint32_t uPadding1;
1244 /** The group name. */
1245 char szName[PDM_NET_SHAPER_MAX_NAME_LEN + 1];
1246 /** Maximum number of bytes filters are allowed to transfer. */
1247 volatile uint64_t cbPerSecMax;
1248 /** Number of bytes we are allowed to transfer in one burst. */
1249 volatile uint32_t cbBucket;
1250 /** Number of bytes we were allowed to transfer at the last update. */
1251 volatile uint32_t cbTokensLast;
1252 /** Timestamp of the last update */
1253 volatile uint64_t tsUpdatedLast;
1254 /** Number of times a filter was choked. */
1255 volatile uint64_t cTotalChokings;
1256 /** Pad the structure to a multiple of 64 bytes. */
1257 uint64_t au64Padding[1];
1258} PDMNSBWGROUP;
1259AssertCompileSizeAlignment(PDMNSBWGROUP, 64);
1260/** Pointer to a bandwidth group. */
1261typedef PDMNSBWGROUP *PPDMNSBWGROUP;
1262
1263/* @} */
1264
1265
1266/**
1267 * Queue device helper task operation.
1268 */
1269typedef enum PDMDEVHLPTASKOP
1270{
1271 /** The usual invalid 0 entry. */
1272 PDMDEVHLPTASKOP_INVALID = 0,
1273 /** IsaSetIrq, IoApicSetIrq */
1274 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1275 /** PciSetIrq */
1276 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1277 /** PciSetIrq */
1278 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1279 /** IoApicSendMsi */
1280 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1281 /** IoApicSettEoi */
1282 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1283 /** The usual 32-bit hack. */
1284 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1285} PDMDEVHLPTASKOP;
1286
1287/**
1288 * Queued Device Helper Task.
1289 */
1290typedef struct PDMDEVHLPTASK
1291{
1292 /** The queue item core (don't touch). */
1293 PDMQUEUEITEMCORE Core;
1294 /** Pointer to the device instance (R3 Ptr). */
1295 PPDMDEVINSR3 pDevInsR3;
1296 /** This operation to perform. */
1297 PDMDEVHLPTASKOP enmOp;
1298#if HC_ARCH_BITS == 64
1299 uint32_t Alignment0;
1300#endif
1301 /** Parameters to the operation. */
1302 union PDMDEVHLPTASKPARAMS
1303 {
1304 /**
1305 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1306 */
1307 struct PDMDEVHLPTASKISASETIRQ
1308 {
1309 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1310 PCIBDF uBusDevFn;
1311 /** The IRQ */
1312 int iIrq;
1313 /** The new level. */
1314 int iLevel;
1315 /** The IRQ tag and source. */
1316 uint32_t uTagSrc;
1317 } IsaSetIrq, IoApicSetIrq;
1318
1319 /**
1320 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1321 */
1322 struct PDMDEVHLPTASKPCISETIRQ
1323 {
1324 /** Index of the PCI device (into PDMDEVINSR3::apPciDevs). */
1325 uint32_t idxPciDev;
1326 /** The IRQ */
1327 int32_t iIrq;
1328 /** The new level. */
1329 int32_t iLevel;
1330 /** The IRQ tag and source. */
1331 uint32_t uTagSrc;
1332 } PciSetIrq;
1333
1334 /**
1335 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1336 */
1337 struct PDMDEVHLPTASKIOAPICSENDMSI
1338 {
1339 /** The bus:device:function of the device sending the MSI. */
1340 PCIBDF uBusDevFn;
1341 /** The MSI. */
1342 MSIMSG Msi;
1343 /** The IRQ tag and source. */
1344 uint32_t uTagSrc;
1345 } IoApicSendMsi;
1346
1347 /**
1348 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1349 */
1350 struct PDMDEVHLPTASKIOAPICSETEOI
1351 {
1352 /** The vector corresponding to the EOI. */
1353 uint8_t uVector;
1354 } IoApicSetEoi;
1355
1356 /** Expanding the structure. */
1357 uint64_t au64[3];
1358 } u;
1359} PDMDEVHLPTASK;
1360/** Pointer to a queued Device Helper Task. */
1361typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1362/** Pointer to a const queued Device Helper Task. */
1363typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1364
1365
1366
1367/**
1368 * An USB hub registration record.
1369 */
1370typedef struct PDMUSBHUB
1371{
1372 /** The USB versions this hub support.
1373 * Note that 1.1 hubs can take on 2.0 devices. */
1374 uint32_t fVersions;
1375 /** The number of ports on the hub. */
1376 uint32_t cPorts;
1377 /** The number of available ports (0..cPorts). */
1378 uint32_t cAvailablePorts;
1379 /** The driver instance of the hub. */
1380 PPDMDRVINS pDrvIns;
1381 /** Copy of the to the registration structure. */
1382 PDMUSBHUBREG Reg;
1383
1384 /** Pointer to the next hub in the list. */
1385 struct PDMUSBHUB *pNext;
1386} PDMUSBHUB;
1387
1388/** Pointer to a const USB HUB registration record. */
1389typedef const PDMUSBHUB *PCPDMUSBHUB;
1390
1391/** Pointer to a PDM Async I/O template. */
1392typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1393
1394/** Pointer to the main PDM Async completion endpoint class. */
1395typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1396
1397/** Pointer to the global block cache structure. */
1398typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1399
1400/**
1401 * PDM VMCPU Instance data.
1402 * Changes to this must checked against the padding of the pdm union in VMCPU!
1403 */
1404typedef struct PDMCPU
1405{
1406 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1407 * in use. */
1408 uint32_t cQueuedCritSectLeaves;
1409 uint32_t uPadding0; /**< Alignment padding.*/
1410 /** Critical sections queued in RC/R0 because of contention preventing leave to
1411 * complete. (R3 Ptrs)
1412 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1413 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1414
1415 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1416 * currently in use. */
1417 uint32_t cQueuedCritSectRwExclLeaves;
1418 uint32_t uPadding1; /**< Alignment padding.*/
1419 /** Read/write critical sections queued in RC/R0 because of contention
1420 * preventing exclusive leave to complete. (R3 Ptrs)
1421 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1422 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1423
1424 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1425 * currently in use. */
1426 uint32_t cQueuedCritSectRwShrdLeaves;
1427 uint32_t uPadding2; /**< Alignment padding.*/
1428 /** Read/write critical sections queued in RC/R0 because of contention
1429 * preventing shared leave to complete. (R3 Ptrs)
1430 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1431 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1432} PDMCPU;
1433
1434
1435/** Max number of ring-0 device instances. */
1436#define PDM_MAX_RING0_DEVICE_INSTANCES 190
1437
1438
1439/**
1440 * PDM VM Instance data.
1441 * Changes to this must checked against the padding of the cfgm union in VM!
1442 */
1443typedef struct PDM
1444{
1445 /** The PDM lock.
1446 * This is used to protect everything that deals with interrupts, i.e.
1447 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1448 PDMCRITSECT CritSect;
1449 /** The NOP critical section.
1450 * This is a dummy critical section that will not do any thread
1451 * serialization but instead let all threads enter immediately and
1452 * concurrently. */
1453 PDMCRITSECT NopCritSect;
1454
1455 /** The ring-0 capable task sets (max 128). */
1456 PDMTASKSET aTaskSets[2];
1457 /** Pointer to task sets (max 512). */
1458 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1459
1460 /** PCI Buses. */
1461 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1462 /** IOMMU devices. */
1463 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1464 /** The register PIC device. */
1465 PDMPIC Pic;
1466 /** The registered APIC device. */
1467 PDMAPIC Apic;
1468 /** The registered I/O APIC device. */
1469 PDMIOAPIC IoApic;
1470 /** The registered HPET device. */
1471 PPDMDEVINSR3 pHpet;
1472
1473 /** List of registered devices. (FIFO) */
1474 R3PTRTYPE(PPDMDEV) pDevs;
1475 /** List of devices instances. (FIFO) */
1476 PPDMDEVINSR3 pDevInstances;
1477 /** This runs parallel to PDMR0PERVM::apDevInstances and is used with
1478 * physical access handlers to get the ring-3 device instance for passing down
1479 * as uUser. */
1480 PPDMDEVINSR3 apDevRing0Instances[PDM_MAX_RING0_DEVICE_INSTANCES];
1481
1482 /** List of registered USB devices. (FIFO) */
1483 R3PTRTYPE(PPDMUSB) pUsbDevs;
1484 /** List of USB devices instances. (FIFO) */
1485 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1486 /** List of registered drivers. (FIFO) */
1487 R3PTRTYPE(PPDMDRV) pDrvs;
1488 /** The registered firmware device (can be NULL). */
1489 R3PTRTYPE(PPDMFW) pFirmware;
1490 /** The registered DMAC device. */
1491 R3PTRTYPE(PPDMDMAC) pDmac;
1492 /** The registered RTC device. */
1493 R3PTRTYPE(PPDMRTC) pRtc;
1494 /** The registered USB HUBs. (FIFO) */
1495 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1496
1497 /** @name Queues
1498 * @{ */
1499 /** Number of ring-0 capable queues in apQueues. */
1500 uint32_t cRing0Queues;
1501 uint32_t u32Padding1;
1502 /** Array of ring-0 capable queues running in parallel to PDMR0PERVM::aQueues. */
1503 R3PTRTYPE(PPDMQUEUE) apRing0Queues[16];
1504 /** Number of ring-3 only queues */
1505 uint32_t cRing3Queues;
1506 /** The allocation size of the ring-3 queue handle table. */
1507 uint32_t cRing3QueuesAlloc;
1508 /** Handle table for the ring-3 only queues. */
1509 R3PTRTYPE(PPDMQUEUE *) papRing3Queues;
1510
1511 /** Queue in which devhlp tasks are queued for R3 execution. */
1512 PDMQUEUEHANDLE hDevHlpQueue;
1513 /** Bitmask controlling the queue flushing.
1514 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1515 uint32_t volatile fQueueFlushing;
1516 /** @} */
1517
1518 /** The current IRQ tag (tracing purposes). */
1519 uint32_t volatile uIrqTag;
1520
1521 /** Pending reset flags (PDMVMRESET_F_XXX). */
1522 uint32_t volatile fResetFlags;
1523
1524 /** Set by pdmR3LoadExec for use in assertions. */
1525 bool fStateLoaded;
1526 /** Alignment padding. */
1527 bool afPadding1[3];
1528
1529 /** The tracing ID of the next device instance.
1530 *
1531 * @remarks We keep the device tracing ID seperate from the rest as these are
1532 * then more likely to end up with the same ID from one run to
1533 * another, making analysis somewhat easier. Drivers and USB devices
1534 * are more volatile and can be changed at runtime, thus these are much
1535 * less likely to remain stable, so just heap them all together. */
1536 uint32_t idTracingDev;
1537 /** The tracing ID of the next driver instance, USB device instance or other
1538 * PDM entity requiring an ID. */
1539 uint32_t idTracingOther;
1540
1541 /** @name VMM device heap
1542 * @{ */
1543 /** The heap size. */
1544 uint32_t cbVMMDevHeap;
1545 /** Free space. */
1546 uint32_t cbVMMDevHeapLeft;
1547 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1548 RTR3PTR pvVMMDevHeap;
1549 /** Ring-3 mapping/unmapping notification callback for the user. */
1550 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1551 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1552 RTGCPHYS GCPhysVMMDevHeap;
1553 /** @} */
1554
1555 /** @name Network Shaper
1556 * @{ */
1557 /** Thread that processes choked filter drivers after
1558 * the a PDM_NETSHAPER_MAX_LATENCY period has elapsed. */
1559 PPDMTHREAD pNsUnchokeThread;
1560 /** Semaphore that the TX thread waits on. */
1561 RTSEMEVENT hNsUnchokeEvt;
1562 /** Timer handle for waking up pNsUnchokeThread. */
1563 TMTIMERHANDLE hNsUnchokeTimer;
1564 /** Indicates whether the unchoke timer has been armed already or not. */
1565 bool volatile fNsUnchokeTimerArmed;
1566 /** Align aNsGroups on a cacheline. */
1567 bool afPadding2[19+16];
1568 /** Number of network shaper groups.
1569 * @note Marked volatile to prevent re-reading after validation. */
1570 uint32_t volatile cNsGroups;
1571 /** The network shaper groups. */
1572 PDMNSBWGROUP aNsGroups[PDM_NET_SHAPER_MAX_GROUPS];
1573 /** Critical section protecting attaching, detaching and unchoking.
1574 * This helps making sure pNsTxThread can do unchoking w/o needing to lock the
1575 * individual groups and cause unnecessary contention. */
1576 RTCRITSECT NsLock;
1577 /** @} */
1578
1579 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1580 STAMCOUNTER StatQueuedCritSectLeaves;
1581 /** Number of times we've successfully aborted a wait in ring-0. */
1582 STAMCOUNTER StatAbortedCritSectEnters;
1583 /** Number of times we've got the critical section ownership while trying to
1584 * abort a wait due to VERR_INTERRUPTED. */
1585 STAMCOUNTER StatCritSectEntersWhileAborting;
1586 STAMCOUNTER StatCritSectVerrTimeout;
1587 STAMCOUNTER StatCritSectVerrInterrupted;
1588 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1589
1590 STAMCOUNTER StatCritSectRwExclVerrTimeout;
1591 STAMCOUNTER StatCritSectRwExclVerrInterrupted;
1592 STAMCOUNTER StatCritSectRwExclNonInterruptibleWaits;
1593
1594 STAMCOUNTER StatCritSectRwEnterSharedWhileAborting;
1595 STAMCOUNTER StatCritSectRwSharedVerrTimeout;
1596 STAMCOUNTER StatCritSectRwSharedVerrInterrupted;
1597 STAMCOUNTER StatCritSectRwSharedNonInterruptibleWaits;
1598} PDM;
1599AssertCompileMemberAlignment(PDM, CritSect, 8);
1600AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1601AssertCompileMemberAlignment(PDM, aNsGroups, 8);
1602AssertCompileMemberAlignment(PDM, aNsGroups, 16);
1603AssertCompileMemberAlignment(PDM, aNsGroups, 32);
1604AssertCompileMemberAlignment(PDM, aNsGroups, 64);
1605AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1606AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1607/** Pointer to PDM VM instance data. */
1608typedef PDM *PPDM;
1609
1610
1611/**
1612 * PDM data kept in the ring-0 GVM.
1613 */
1614typedef struct PDMR0PERVM
1615{
1616 /** PCI Buses, ring-0 data. */
1617 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1618 /** IOMMUs, ring-0 data. */
1619 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1620 /** Number of valid ring-0 device instances (apDevInstances). */
1621 uint32_t cDevInstances;
1622 uint32_t u32Padding1;
1623 /** Pointer to ring-0 device instances. */
1624 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[PDM_MAX_RING0_DEVICE_INSTANCES];
1625 /** Number of valid ring-0 queue instances (aQueues). */
1626 uint32_t cQueues;
1627 uint32_t u32Padding2;
1628 /** Array of ring-0 queues. */
1629 PDMQUEUER0 aQueues[16];
1630} PDMR0PERVM;
1631
1632
1633/**
1634 * PDM data kept in the UVM.
1635 */
1636typedef struct PDMUSERPERVM
1637{
1638 /** @todo move more stuff over here. */
1639
1640 /** Lock protecting the lists below it. */
1641 RTCRITSECT ListCritSect;
1642 /** Pointer to list of loaded modules. */
1643 PPDMMOD pModules;
1644 /** List of initialized critical sections. (LIFO) */
1645 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1646 /** List of initialized read/write critical sections. (LIFO) */
1647 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1648 /** Head of the PDM Thread list. (singly linked) */
1649 R3PTRTYPE(PPDMTHREAD) pThreads;
1650 /** Tail of the PDM Thread list. (singly linked) */
1651 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1652
1653 /** @name PDM Async Completion
1654 * @{ */
1655 /** Pointer to the array of supported endpoint classes. */
1656 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1657 /** Head of the templates. Singly linked, protected by ListCritSect. */
1658 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1659 /** @} */
1660
1661 /** Global block cache data. */
1662 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1663} PDMUSERPERVM;
1664/** Pointer to the PDM data kept in the UVM. */
1665typedef PDMUSERPERVM *PPDMUSERPERVM;
1666
1667
1668
1669/*******************************************************************************
1670* Global Variables *
1671*******************************************************************************/
1672#ifdef IN_RING3
1673extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1674extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1675# ifdef VBOX_WITH_DBGF_TRACING
1676extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1677# endif
1678extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1679extern const PDMPICHLP g_pdmR3DevPicHlp;
1680extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1681extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1682extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1683extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1684extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1685extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1686extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1687extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1688#endif
1689
1690
1691/*******************************************************************************
1692* Defined Constants And Macros *
1693*******************************************************************************/
1694/** @def PDMDEV_ASSERT_DEVINS
1695 * Asserts the validity of the device instance.
1696 */
1697#ifdef VBOX_STRICT
1698# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1699 do { \
1700 AssertPtr(pDevIns); \
1701 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1702 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1703 } while (0)
1704#else
1705# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1706#endif
1707
1708/** @def PDMDRV_ASSERT_DRVINS
1709 * Asserts the validity of the driver instance.
1710 */
1711#ifdef VBOX_STRICT
1712# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1713 do { \
1714 AssertPtr(pDrvIns); \
1715 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1716 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1717 } while (0)
1718#else
1719# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1720#endif
1721
1722
1723/*******************************************************************************
1724* Internal Functions *
1725*******************************************************************************/
1726#ifdef IN_RING3
1727bool pdmR3IsValidName(const char *pszName);
1728
1729int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1730int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1731int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1732int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1733 const char *pszNameFmt, va_list va);
1734int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1735 const char *pszNameFmt, ...);
1736int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1737 const char *pszNameFmt, ...);
1738int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1739 const char *pszNameFmt, va_list va);
1740int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1741 const char *pszNameFmt, ...);
1742int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1743 const char *pszNameFmt, ...);
1744
1745int pdmR3DevInit(PVM pVM);
1746int pdmR3DevInitComplete(PVM pVM);
1747PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1748int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1749DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1750
1751int pdmR3UsbLoadModules(PVM pVM);
1752int pdmR3UsbInstantiateDevices(PVM pVM);
1753PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1754int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1755int pdmR3UsbVMInitComplete(PVM pVM);
1756
1757int pdmR3DrvInit(PVM pVM);
1758int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1759 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1760int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1761void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1762PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1763
1764int pdmR3LdrInitU(PUVM pUVM);
1765void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1766char *pdmR3FileR3(const char *pszFile, bool fShared);
1767int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1768#endif /* IN_RING3 */
1769
1770void pdmQueueInit(PPDMQUEUE pQueue, uint32_t cbBitmap, uint32_t cbItem, uint32_t cItems,
1771 const char *pszName, PDMQUEUETYPE enmType, RTR3PTR pfnCallback, RTR3PTR pvOwner);
1772
1773#ifdef IN_RING3
1774int pdmR3TaskInit(PVM pVM);
1775void pdmR3TaskTerm(PVM pVM);
1776
1777int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1778 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1779int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1780 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1781int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1782 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1783int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1784int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1785int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1786void pdmR3ThreadDestroyAll(PVM pVM);
1787int pdmR3ThreadResumeAll(PVM pVM);
1788int pdmR3ThreadSuspendAll(PVM pVM);
1789
1790# ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1791int pdmR3AsyncCompletionInit(PVM pVM);
1792int pdmR3AsyncCompletionTerm(PVM pVM);
1793void pdmR3AsyncCompletionResume(PVM pVM);
1794int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1795int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1796 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1797int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1798int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1799int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1800int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1801# endif
1802
1803# ifdef VBOX_WITH_NETSHAPER
1804int pdmR3NetShaperInit(PVM pVM);
1805void pdmR3NetShaperTerm(PVM pVM);
1806# endif
1807
1808int pdmR3BlkCacheInit(PVM pVM);
1809void pdmR3BlkCacheTerm(PVM pVM);
1810int pdmR3BlkCacheResume(PVM pVM);
1811
1812DECLHIDDEN(void) pdmR3QueueTerm(PVM pVM);
1813#endif /* IN_RING3 */
1814
1815void pdmLock(PVMCC pVM);
1816int pdmLockEx(PVMCC pVM, int rcBusy);
1817void pdmUnlock(PVMCC pVM);
1818bool pdmLockIsOwner(PVMCC pVM);
1819
1820#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1821bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1822int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1823int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1824int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1825# ifdef IN_RING3
1826int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1827int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1828int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1829int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1830# endif
1831#endif
1832
1833#if defined(IN_RING3) || defined(IN_RING0)
1834void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1835void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1836#endif
1837
1838#ifdef IN_RING0
1839DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1840DECLHIDDEN(void) pdmR0QueueDestroy(PGVM pGVM, uint32_t iQueue);
1841
1842#endif
1843
1844#ifdef VBOX_WITH_DBGF_TRACING
1845# ifdef IN_RING3
1846DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1847 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1848 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1849 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1850DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1851DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1852DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1853 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1854 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1855 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1856DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1857DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1858DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1859DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1860DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1861DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1862DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1863DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1864DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1865DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1866# elif defined(IN_RING0)
1867DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1868 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1869 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1870 void *pvUser);
1871DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1872 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1873DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1874DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1875DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1876DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1877DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1878DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1879DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1880DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1881# else
1882# error "Invalid environment selected"
1883# endif
1884#endif
1885
1886
1887/** @} */
1888
1889RT_C_DECLS_END
1890
1891#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1892
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