VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 89163

Last change on this file since 89163 was 88641, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 PDM naming consistency.
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File size: 69.7 KB
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1/* $Id: PDMInternal.h 88641 2021-04-22 06:20:26Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/pdmasynccompletion.h>
31#ifdef VBOX_WITH_NETSHAPER
32# include <VBox/vmm/pdmnetshaper.h>
33#endif
34#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35# include <VBox/vmm/pdmasynccompletion.h>
36#endif
37#include <VBox/vmm/pdmblkcache.h>
38#include <VBox/vmm/pdmcommon.h>
39#include <VBox/vmm/pdmtask.h>
40#include <VBox/sup.h>
41#include <VBox/msi.h>
42#include <iprt/assert.h>
43#include <iprt/critsect.h>
44#ifdef IN_RING3
45# include <iprt/thread.h>
46#endif
47
48RT_C_DECLS_BEGIN
49
50
51/** @defgroup grp_pdm_int Internal
52 * @ingroup grp_pdm
53 * @internal
54 * @{
55 */
56
57/** @def PDM_WITH_R3R0_CRIT_SECT
58 * Enables or disabled ring-3/ring-0 critical sections. */
59#if defined(DOXYGEN_RUNNING) || 1
60# define PDM_WITH_R3R0_CRIT_SECT
61#endif
62
63/** @def PDMCRITSECT_STRICT
64 * Enables/disables PDM critsect strictness like deadlock detection. */
65#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
66 || defined(DOXYGEN_RUNNING)
67# define PDMCRITSECT_STRICT
68#endif
69
70/** @def PDMCRITSECT_STRICT
71 * Enables/disables PDM read/write critsect strictness like deadlock
72 * detection. */
73#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
74 || defined(DOXYGEN_RUNNING)
75# define PDMCRITSECTRW_STRICT
76#endif
77
78/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
79#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
80/** The maximum device instance (total) size, ring-3 only devices. */
81#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
82/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
83#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK PAGE_SIZE
84
85
86
87/*******************************************************************************
88* Structures and Typedefs *
89*******************************************************************************/
90
91/** Pointer to a PDM Device. */
92typedef struct PDMDEV *PPDMDEV;
93/** Pointer to a pointer to a PDM Device. */
94typedef PPDMDEV *PPPDMDEV;
95
96/** Pointer to a PDM USB Device. */
97typedef struct PDMUSB *PPDMUSB;
98/** Pointer to a pointer to a PDM USB Device. */
99typedef PPDMUSB *PPPDMUSB;
100
101/** Pointer to a PDM Driver. */
102typedef struct PDMDRV *PPDMDRV;
103/** Pointer to a pointer to a PDM Driver. */
104typedef PPDMDRV *PPPDMDRV;
105
106/** Pointer to a PDM Logical Unit. */
107typedef struct PDMLUN *PPDMLUN;
108/** Pointer to a pointer to a PDM Logical Unit. */
109typedef PPDMLUN *PPPDMLUN;
110
111/** Pointer to a DMAC instance. */
112typedef struct PDMDMAC *PPDMDMAC;
113/** Pointer to a RTC instance. */
114typedef struct PDMRTC *PPDMRTC;
115
116/** Pointer to an USB HUB registration record. */
117typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119/**
120 * Supported asynchronous completion endpoint classes.
121 */
122typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123{
124 /** File class. */
125 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126 /** Number of supported classes. */
127 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128 /** 32bit hack. */
129 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132
133/**
134 * MMIO/IO port registration tracking structure for DBGF tracing.
135 */
136typedef struct PDMDEVINSDBGFTRACK
137{
138 /** Flag whether this tracks a IO port or MMIO registration. */
139 bool fMmio;
140 /** Opaque user data passed during registration. */
141 void *pvUser;
142 /** Type dependent data. */
143 union
144 {
145 /** I/O port registration. */
146 struct
147 {
148 /** IOM I/O port handle. */
149 IOMIOPORTHANDLE hIoPorts;
150 /** Original OUT handler of the device. */
151 PFNIOMIOPORTNEWOUT pfnOut;
152 /** Original IN handler of the device. */
153 PFNIOMIOPORTNEWIN pfnIn;
154 /** Original string OUT handler of the device. */
155 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
156 /** Original string IN handler of the device. */
157 PFNIOMIOPORTNEWINSTRING pfnInStr;
158 } IoPort;
159 /** MMIO registration. */
160 struct
161 {
162 /** IOM MMIO region handle. */
163 IOMMMIOHANDLE hMmioRegion;
164 /** Original MMIO write handler of the device. */
165 PFNIOMMMIONEWWRITE pfnWrite;
166 /** Original MMIO read handler of the device. */
167 PFNIOMMMIONEWREAD pfnRead;
168 /** Original MMIO fill handler of the device. */
169 PFNIOMMMIONEWFILL pfnFill;
170 } Mmio;
171 } u;
172} PDMDEVINSDBGFTRACK;
173/** Pointer to a MMIO/IO port registration tracking structure. */
174typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
175/** Pointer to a const MMIO/IO port registration tracking structure. */
176typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
177
178
179/**
180 * Private device instance data, ring-3.
181 */
182typedef struct PDMDEVINSINTR3
183{
184 /** Pointer to the next instance.
185 * (Head is pointed to by PDM::pDevInstances.) */
186 R3PTRTYPE(PPDMDEVINS) pNextR3;
187 /** Pointer to the next per device instance.
188 * (Head is pointed to by PDMDEV::pInstances.) */
189 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
190 /** Pointer to device structure. */
191 R3PTRTYPE(PPDMDEV) pDevR3;
192 /** Pointer to the list of logical units associated with the device. (FIFO) */
193 R3PTRTYPE(PPDMLUN) pLunsR3;
194 /** Pointer to the asynchronous notification callback set while in
195 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
196 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
197 /** Configuration handle to the instance node. */
198 R3PTRTYPE(PCFGMNODE) pCfgHandle;
199
200 /** R3 pointer to the VM this instance was created for. */
201 PVMR3 pVMR3;
202 /** DBGF trace event source handle if tracing is configured. */
203 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
204 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
205 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
206 /** Index of the next entry to use for tracking. */
207 uint32_t idxDbgfTraceTrackNext;
208 /** Maximum number of records fitting into the single page. */
209 uint32_t cDbgfTraceTrackMax;
210
211 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
212 uint32_t fIntFlags;
213 /** The last IRQ tag (for tracing it thru clearing). */
214 uint32_t uLastIrqTag;
215 /** The ring-0 device index (for making ring-0 calls). */
216 uint32_t idxR0Device;
217} PDMDEVINSINTR3;
218
219
220/**
221 * Private device instance data, ring-0.
222 */
223typedef struct PDMDEVINSINTR0
224{
225 /** Pointer to the VM this instance was created for. */
226 R0PTRTYPE(PGVM) pGVM;
227 /** Pointer to device structure. */
228 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
229 /** The ring-0 module reference. */
230 RTR0PTR hMod;
231 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
232 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
233 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
234 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
235 /** DBGF trace event source handle if tracing is configured. */
236 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
237 /** The device instance memory. */
238 RTR0MEMOBJ hMemObj;
239 /** The ring-3 mapping object. */
240 RTR0MEMOBJ hMapObj;
241 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
242 RTR0MEMOBJ hDbgfTraceObj;
243 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
244 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
245 /** Index of the next entry to use for tracking. */
246 uint32_t idxDbgfTraceTrackNext;
247 /** Maximum number of records fitting into the single page. */
248 uint32_t cDbgfTraceTrackMax;
249 /** Index into PDMR0PERVM::apDevInstances. */
250 uint32_t idxR0Device;
251} PDMDEVINSINTR0;
252
253
254/**
255 * Private device instance data, raw-mode
256 */
257typedef struct PDMDEVINSINTRC
258{
259 /** Pointer to the VM this instance was created for. */
260 RGPTRTYPE(PVM) pVMRC;
261} PDMDEVINSINTRC;
262
263
264/**
265 * Private device instance data.
266 */
267typedef struct PDMDEVINSINT
268{
269 /** Pointer to the next instance (HC Ptr).
270 * (Head is pointed to by PDM::pDevInstances.) */
271 R3PTRTYPE(PPDMDEVINS) pNextR3;
272 /** Pointer to the next per device instance (HC Ptr).
273 * (Head is pointed to by PDMDEV::pInstances.) */
274 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
275 /** Pointer to device structure - HC Ptr. */
276 R3PTRTYPE(PPDMDEV) pDevR3;
277 /** Pointer to the list of logical units associated with the device. (FIFO) */
278 R3PTRTYPE(PPDMLUN) pLunsR3;
279 /** Pointer to the asynchronous notification callback set while in
280 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
281 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
282 /** Configuration handle to the instance node. */
283 R3PTRTYPE(PCFGMNODE) pCfgHandle;
284
285 /** R3 pointer to the VM this instance was created for. */
286 PVMR3 pVMR3;
287
288 /** R0 pointer to the VM this instance was created for. */
289 R0PTRTYPE(PVMCC) pVMR0;
290
291 /** RC pointer to the VM this instance was created for. */
292 PVMRC pVMRC;
293
294 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
295 uint32_t fIntFlags;
296 /** The last IRQ tag (for tracing it thru clearing). */
297 uint32_t uLastIrqTag;
298} PDMDEVINSINT;
299
300/** @name PDMDEVINSINT::fIntFlags
301 * @{ */
302/** Used by pdmR3Load to mark device instances it found in the saved state. */
303#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
304/** Indicates that the device hasn't been powered on or resumed.
305 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
306 * to make sure each device gets exactly one notification for each of those
307 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
308 * a failure (already resumed/powered-on devices are suspended).
309 * PDMR3PowerOff resets this flag once before going through the devices to make sure
310 * every device gets the power off notification even if it was suspended before with
311 * PDMR3Suspend.
312 */
313#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
314/** Indicates that the device has been reset already. Used by PDMR3Reset. */
315#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
316#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
317#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
318/** Set if we've called the ring-0 constructor. */
319#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
320/** Set if using non-default critical section. */
321#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
322/** @} */
323
324
325/**
326 * Private USB device instance data.
327 */
328typedef struct PDMUSBINSINT
329{
330 /** The UUID of this instance. */
331 RTUUID Uuid;
332 /** Pointer to the next instance.
333 * (Head is pointed to by PDM::pUsbInstances.) */
334 R3PTRTYPE(PPDMUSBINS) pNext;
335 /** Pointer to the next per USB device instance.
336 * (Head is pointed to by PDMUSB::pInstances.) */
337 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
338
339 /** Pointer to device structure. */
340 R3PTRTYPE(PPDMUSB) pUsbDev;
341
342 /** Pointer to the VM this instance was created for. */
343 PVMR3 pVM;
344 /** Pointer to the list of logical units associated with the device. (FIFO) */
345 R3PTRTYPE(PPDMLUN) pLuns;
346 /** The per instance device configuration. */
347 R3PTRTYPE(PCFGMNODE) pCfg;
348 /** Same as pCfg if the configuration should be deleted when detaching the device. */
349 R3PTRTYPE(PCFGMNODE) pCfgDelete;
350 /** The global device configuration. */
351 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
352
353 /** Pointer to the USB hub this device is attached to.
354 * This is NULL if the device isn't connected to any HUB. */
355 R3PTRTYPE(PPDMUSBHUB) pHub;
356 /** The port number that we're connected to. */
357 uint32_t iPort;
358 /** Indicates that the USB device hasn't been powered on or resumed.
359 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
360 bool fVMSuspended;
361 /** Indicates that the USB device has been reset. */
362 bool fVMReset;
363 /** Pointer to the asynchronous notification callback set while in
364 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
365 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
366} PDMUSBINSINT;
367
368
369/**
370 * Private driver instance data.
371 */
372typedef struct PDMDRVINSINT
373{
374 /** Pointer to the driver instance above.
375 * This is NULL for the topmost drive. */
376 R3PTRTYPE(PPDMDRVINS) pUp;
377 /** Pointer to the driver instance below.
378 * This is NULL for the bottommost driver. */
379 R3PTRTYPE(PPDMDRVINS) pDown;
380 /** Pointer to the logical unit this driver chained on. */
381 R3PTRTYPE(PPDMLUN) pLun;
382 /** Pointer to driver structure from which this was instantiated. */
383 R3PTRTYPE(PPDMDRV) pDrv;
384 /** Pointer to the VM this instance was created for, ring-3 context. */
385 PVMR3 pVMR3;
386 /** Pointer to the VM this instance was created for, ring-0 context. */
387 R0PTRTYPE(PVMCC) pVMR0;
388 /** Pointer to the VM this instance was created for, raw-mode context. */
389 PVMRC pVMRC;
390 /** Flag indicating that the driver is being detached and destroyed.
391 * (Helps detect potential recursive detaching.) */
392 bool fDetaching;
393 /** Indicates that the driver hasn't been powered on or resumed.
394 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
395 bool fVMSuspended;
396 /** Indicates that the driver has been reset already. */
397 bool fVMReset;
398 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
399 bool fHyperHeap;
400 /** Pointer to the asynchronous notification callback set while in
401 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
402 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
403 /** Configuration handle to the instance node. */
404 R3PTRTYPE(PCFGMNODE) pCfgHandle;
405 /** Pointer to the ring-0 request handler function. */
406 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
407} PDMDRVINSINT;
408
409
410/**
411 * Private critical section data.
412 */
413typedef struct PDMCRITSECTINT
414{
415 /** The critical section core which is shared with IPRT.
416 * @note The semaphore is a SUPSEMEVENT. */
417 RTCRITSECT Core;
418 /** Pointer to the next critical section.
419 * This chain is used for relocating pVMRC and device cleanup. */
420 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
421 /** Owner identifier.
422 * This is pDevIns if the owner is a device. Similarly for a driver or service.
423 * PDMR3CritSectInit() sets this to point to the critsect itself. */
424 RTR3PTR pvKey;
425 /** Pointer to the VM - R3Ptr. */
426 PVMR3 pVMR3;
427 /** Pointer to the VM - R0Ptr. */
428 R0PTRTYPE(PVMCC) pVMR0;
429 /** Pointer to the VM - GCPtr. */
430 PVMRC pVMRC;
431 /** Set if this critical section is the automatically created default
432 * section of a device. */
433 bool fAutomaticDefaultCritsect;
434 /** Set if the critical section is used by a timer or similar.
435 * See PDMR3DevGetCritSect. */
436 bool fUsedByTimerOrSimilar;
437 /** Alignment padding. */
438 bool afPadding[2];
439 /** Support driver event semaphore that is scheduled to be signaled upon leaving
440 * the critical section. This is only for Ring-3 and Ring-0. */
441 SUPSEMEVENT hEventToSignal;
442 /** The lock name. */
443 R3PTRTYPE(const char *) pszName;
444 /** R0/RC lock contention. */
445 STAMCOUNTER StatContentionRZLock;
446 /** R0/RC unlock contention. */
447 STAMCOUNTER StatContentionRZUnlock;
448 /** R3 lock contention. */
449 STAMCOUNTER StatContentionR3;
450 /** Profiling the time the section is locked. */
451 STAMPROFILEADV StatLocked;
452} PDMCRITSECTINT;
453AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
454/** Pointer to private critical section data. */
455typedef PDMCRITSECTINT *PPDMCRITSECTINT;
456
457/** Indicates that the critical section is queued for unlock.
458 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
459#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
460
461
462/**
463 * Private critical section data.
464 */
465typedef struct PDMCRITSECTRWINT
466{
467 /** The read/write critical section core which is shared with IPRT.
468 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
469 RTCRITSECTRW Core;
470
471 /** Pointer to the next critical section.
472 * This chain is used for relocating pVMRC and device cleanup. */
473 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
474 /** Owner identifier.
475 * This is pDevIns if the owner is a device. Similarly for a driver or service.
476 * PDMR3CritSectInit() sets this to point to the critsect itself. */
477 RTR3PTR pvKey;
478 /** Pointer to the VM - R3Ptr. */
479 PVMR3 pVMR3;
480 /** Pointer to the VM - R0Ptr. */
481 R0PTRTYPE(PVMCC) pVMR0;
482 /** Pointer to the VM - GCPtr. */
483 PVMRC pVMRC;
484#if HC_ARCH_BITS == 64
485 /** Alignment padding. */
486 RTRCPTR RCPtrPadding;
487#endif
488 /** The lock name. */
489 R3PTRTYPE(const char *) pszName;
490 /** R0/RC write lock contention. */
491 STAMCOUNTER StatContentionRZEnterExcl;
492 /** R0/RC write unlock contention. */
493 STAMCOUNTER StatContentionRZLeaveExcl;
494 /** R0/RC read lock contention. */
495 STAMCOUNTER StatContentionRZEnterShared;
496 /** R0/RC read unlock contention. */
497 STAMCOUNTER StatContentionRZLeaveShared;
498 /** R0/RC writes. */
499 STAMCOUNTER StatRZEnterExcl;
500 /** R0/RC reads. */
501 STAMCOUNTER StatRZEnterShared;
502 /** R3 write lock contention. */
503 STAMCOUNTER StatContentionR3EnterExcl;
504 /** R3 read lock contention. */
505 STAMCOUNTER StatContentionR3EnterShared;
506 /** R3 writes. */
507 STAMCOUNTER StatR3EnterExcl;
508 /** R3 reads. */
509 STAMCOUNTER StatR3EnterShared;
510 /** Profiling the time the section is write locked. */
511 STAMPROFILEADV StatWriteLocked;
512} PDMCRITSECTRWINT;
513AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
514AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
515/** Pointer to private critical section data. */
516typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
517
518
519
520/**
521 * The usual device/driver/internal/external stuff.
522 */
523typedef enum
524{
525 /** The usual invalid entry. */
526 PDMTHREADTYPE_INVALID = 0,
527 /** Device type. */
528 PDMTHREADTYPE_DEVICE,
529 /** USB Device type. */
530 PDMTHREADTYPE_USB,
531 /** Driver type. */
532 PDMTHREADTYPE_DRIVER,
533 /** Internal type. */
534 PDMTHREADTYPE_INTERNAL,
535 /** External type. */
536 PDMTHREADTYPE_EXTERNAL,
537 /** The usual 32-bit hack. */
538 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
539} PDMTHREADTYPE;
540
541
542/**
543 * The internal structure for the thread.
544 */
545typedef struct PDMTHREADINT
546{
547 /** The VM pointer. */
548 PVMR3 pVM;
549 /** The event semaphore the thread blocks on when not running. */
550 RTSEMEVENTMULTI BlockEvent;
551 /** The event semaphore the thread sleeps on while running. */
552 RTSEMEVENTMULTI SleepEvent;
553 /** Pointer to the next thread. */
554 R3PTRTYPE(struct PDMTHREAD *) pNext;
555 /** The thread type. */
556 PDMTHREADTYPE enmType;
557} PDMTHREADINT;
558
559
560
561/* Must be included after PDMDEVINSINT is defined. */
562#define PDMDEVINSINT_DECLARED
563#define PDMUSBINSINT_DECLARED
564#define PDMDRVINSINT_DECLARED
565#define PDMCRITSECTINT_DECLARED
566#define PDMCRITSECTRWINT_DECLARED
567#define PDMTHREADINT_DECLARED
568#ifdef ___VBox_pdm_h
569# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
570#endif
571RT_C_DECLS_END
572#include <VBox/vmm/pdm.h>
573RT_C_DECLS_BEGIN
574
575/**
576 * PDM Logical Unit.
577 *
578 * This typically the representation of a physical port on a
579 * device, like for instance the PS/2 keyboard port on the
580 * keyboard controller device. The LUNs are chained on the
581 * device they belong to (PDMDEVINSINT::pLunsR3).
582 */
583typedef struct PDMLUN
584{
585 /** The LUN - The Logical Unit Number. */
586 RTUINT iLun;
587 /** Pointer to the next LUN. */
588 PPDMLUN pNext;
589 /** Pointer to the top driver in the driver chain. */
590 PPDMDRVINS pTop;
591 /** Pointer to the bottom driver in the driver chain. */
592 PPDMDRVINS pBottom;
593 /** Pointer to the device instance which the LUN belongs to.
594 * Either this is set or pUsbIns is set. Both is never set at the same time. */
595 PPDMDEVINS pDevIns;
596 /** Pointer to the USB device instance which the LUN belongs to. */
597 PPDMUSBINS pUsbIns;
598 /** Pointer to the device base interface. */
599 PPDMIBASE pBase;
600 /** Description of this LUN. */
601 const char *pszDesc;
602} PDMLUN;
603
604
605/**
606 * PDM Device, ring-3.
607 */
608typedef struct PDMDEV
609{
610 /** Pointer to the next device (R3 Ptr). */
611 R3PTRTYPE(PPDMDEV) pNext;
612 /** Device name length. (search optimization) */
613 uint32_t cchName;
614 /** Registration structure. */
615 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
616 /** Number of instances. */
617 uint32_t cInstances;
618 /** Pointer to chain of instances (R3 Ptr). */
619 PPDMDEVINSR3 pInstances;
620 /** The search path for raw-mode context modules (';' as separator). */
621 char *pszRCSearchPath;
622 /** The search path for ring-0 context modules (';' as separator). */
623 char *pszR0SearchPath;
624} PDMDEV;
625
626
627#if 0
628/**
629 * PDM Device, ring-0.
630 */
631typedef struct PDMDEVR0
632{
633 /** Pointer to the next device. */
634 R0PTRTYPE(PPDMDEVR0) pNext;
635 /** Device name length. (search optimization) */
636 uint32_t cchName;
637 /** Registration structure. */
638 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
639 /** Number of instances. */
640 uint32_t cInstances;
641 /** Pointer to chain of instances. */
642 PPDMDEVINSR0 pInstances;
643} PDMDEVR0;
644#endif
645
646
647/**
648 * PDM USB Device.
649 */
650typedef struct PDMUSB
651{
652 /** Pointer to the next device (R3 Ptr). */
653 R3PTRTYPE(PPDMUSB) pNext;
654 /** Device name length. (search optimization) */
655 RTUINT cchName;
656 /** Registration structure. */
657 R3PTRTYPE(const struct PDMUSBREG *) pReg;
658 /** Next instance number. */
659 uint32_t iNextInstance;
660 /** Pointer to chain of instances (R3 Ptr). */
661 R3PTRTYPE(PPDMUSBINS) pInstances;
662} PDMUSB;
663
664
665/**
666 * PDM Driver.
667 */
668typedef struct PDMDRV
669{
670 /** Pointer to the next device. */
671 PPDMDRV pNext;
672 /** Registration structure. */
673 const struct PDMDRVREG * pReg;
674 /** Current number of instances. */
675 uint32_t cInstances;
676 /** The next instance number. */
677 uint32_t iNextInstance;
678 /** The search path for raw-mode context modules (';' as separator). */
679 char *pszRCSearchPath;
680 /** The search path for ring-0 context modules (';' as separator). */
681 char *pszR0SearchPath;
682} PDMDRV;
683
684
685/**
686 * PDM IOMMU, shared ring-3.
687 */
688typedef struct PDMIOMMUR3
689{
690 /** IOMMU index. */
691 uint32_t idxIommu;
692 uint32_t uPadding0; /**< Alignment padding.*/
693
694 /** Pointer to the IOMMU device instance - R3. */
695 PPDMDEVINSR3 pDevInsR3;
696 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
697 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
698 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
699 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
700 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
701 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
702 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
703 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
704} PDMIOMMUR3;
705/** Pointer to a PDM IOMMU instance. */
706typedef PDMIOMMUR3 *PPDMIOMMUR3;
707/** Pointer to a const PDM IOMMU instance. */
708typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
709
710
711/**
712 * PDM IOMMU, ring-0.
713 */
714typedef struct PDMIOMMUR0
715{
716 /** IOMMU index. */
717 uint32_t idxIommu;
718 uint32_t uPadding0; /**< Alignment padding.*/
719
720 /** Pointer to IOMMU device instance. */
721 PPDMDEVINSR0 pDevInsR0;
722 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
723 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
724 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
725 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
726 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
727 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
728 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
729 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
730} PDMIOMMUR0;
731/** Pointer to a ring-0 IOMMU data. */
732typedef PDMIOMMUR0 *PPDMIOMMUR0;
733/** Pointer to a const ring-0 IOMMU data. */
734typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
735
736/** Pointer to a PDM IOMMU for the current context. */
737#ifdef IN_RING3
738typedef PPDMIOMMUR3 PPDMIOMMU;
739#else
740typedef PPDMIOMMUR0 PPDMIOMMU;
741#endif
742
743
744/**
745 * PDM registered PIC device.
746 */
747typedef struct PDMPIC
748{
749 /** Pointer to the PIC device instance - R3. */
750 PPDMDEVINSR3 pDevInsR3;
751 /** @copydoc PDMPICREG::pfnSetIrq */
752 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
753 /** @copydoc PDMPICREG::pfnGetInterrupt */
754 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
755
756 /** Pointer to the PIC device instance - R0. */
757 PPDMDEVINSR0 pDevInsR0;
758 /** @copydoc PDMPICREG::pfnSetIrq */
759 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
760 /** @copydoc PDMPICREG::pfnGetInterrupt */
761 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
762
763 /** Pointer to the PIC device instance - RC. */
764 PPDMDEVINSRC pDevInsRC;
765 /** @copydoc PDMPICREG::pfnSetIrq */
766 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
767 /** @copydoc PDMPICREG::pfnGetInterrupt */
768 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
769 /** Alignment padding. */
770 RTRCPTR RCPtrPadding;
771} PDMPIC;
772
773
774/**
775 * PDM registered APIC device.
776 */
777typedef struct PDMAPIC
778{
779 /** Pointer to the APIC device instance - R3 Ptr. */
780 PPDMDEVINSR3 pDevInsR3;
781 /** Pointer to the APIC device instance - R0 Ptr. */
782 PPDMDEVINSR0 pDevInsR0;
783 /** Pointer to the APIC device instance - RC Ptr. */
784 PPDMDEVINSRC pDevInsRC;
785 uint8_t Alignment[4];
786} PDMAPIC;
787
788
789/**
790 * PDM registered I/O APIC device.
791 */
792typedef struct PDMIOAPIC
793{
794 /** Pointer to the I/O APIC device instance - R3 Ptr. */
795 PPDMDEVINSR3 pDevInsR3;
796 /** @copydoc PDMIOAPICREG::pfnSetIrq */
797 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
798 /** @copydoc PDMIOAPICREG::pfnSendMsi */
799 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
800 /** @copydoc PDMIOAPICREG::pfnSetEoi */
801 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
802
803 /** Pointer to the I/O APIC device instance - R0. */
804 PPDMDEVINSR0 pDevInsR0;
805 /** @copydoc PDMIOAPICREG::pfnSetIrq */
806 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
807 /** @copydoc PDMIOAPICREG::pfnSendMsi */
808 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
809 /** @copydoc PDMIOAPICREG::pfnSetEoi */
810 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
811
812 /** Pointer to the I/O APIC device instance - RC Ptr. */
813 PPDMDEVINSRC pDevInsRC;
814 /** @copydoc PDMIOAPICREG::pfnSetIrq */
815 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
816 /** @copydoc PDMIOAPICREG::pfnSendMsi */
817 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
818 /** @copydoc PDMIOAPICREG::pfnSendMsi */
819 DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
820} PDMIOAPIC;
821
822/** Maximum number of PCI busses for a VM. */
823#define PDM_PCI_BUSSES_MAX 8
824/** Maximum number of IOMMUs (at most one per PCI bus). */
825#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
826
827
828#ifdef IN_RING3
829/**
830 * PDM registered firmware device.
831 */
832typedef struct PDMFW
833{
834 /** Pointer to the firmware device instance. */
835 PPDMDEVINSR3 pDevIns;
836 /** Copy of the registration structure. */
837 PDMFWREG Reg;
838} PDMFW;
839/** Pointer to a firmware instance. */
840typedef PDMFW *PPDMFW;
841#endif
842
843
844/**
845 * PDM PCI bus instance.
846 */
847typedef struct PDMPCIBUS
848{
849 /** PCI bus number. */
850 uint32_t iBus;
851 uint32_t uPadding0; /**< Alignment padding.*/
852
853 /** Pointer to PCI bus device instance. */
854 PPDMDEVINSR3 pDevInsR3;
855 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
856 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
857
858 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
859 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
860 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
861 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
862 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
863 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
864 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
865 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
866 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
867 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
868 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
869 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
870 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
871 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
872 uint32_t uAddress, unsigned cb, uint32_t u32Value));
873 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
874 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
875 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
876} PDMPCIBUS;
877/** Pointer to a PDM PCI Bus instance. */
878typedef PDMPCIBUS *PPDMPCIBUS;
879/** Pointer to a const PDM PCI Bus instance. */
880typedef const PDMPCIBUS *PCPDMPCIBUS;
881
882
883/**
884 * Ring-0 PDM PCI bus instance data.
885 */
886typedef struct PDMPCIBUSR0
887{
888 /** PCI bus number. */
889 uint32_t iBus;
890 uint32_t uPadding0; /**< Alignment padding.*/
891 /** Pointer to PCI bus device instance. */
892 PPDMDEVINSR0 pDevInsR0;
893 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
894 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
895} PDMPCIBUSR0;
896/** Pointer to the ring-0 PCI bus data. */
897typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
898/** Pointer to the const ring-0 PCI bus data. */
899typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
900
901
902#ifdef IN_RING3
903/**
904 * PDM registered DMAC (DMA Controller) device.
905 */
906typedef struct PDMDMAC
907{
908 /** Pointer to the DMAC device instance. */
909 PPDMDEVINSR3 pDevIns;
910 /** Copy of the registration structure. */
911 PDMDMACREG Reg;
912} PDMDMAC;
913
914
915/**
916 * PDM registered RTC (Real Time Clock) device.
917 */
918typedef struct PDMRTC
919{
920 /** Pointer to the RTC device instance. */
921 PPDMDEVINSR3 pDevIns;
922 /** Copy of the registration structure. */
923 PDMRTCREG Reg;
924} PDMRTC;
925
926#endif /* IN_RING3 */
927
928/**
929 * Module type.
930 */
931typedef enum PDMMODTYPE
932{
933 /** Raw-mode (RC) context module. */
934 PDMMOD_TYPE_RC,
935 /** Ring-0 (host) context module. */
936 PDMMOD_TYPE_R0,
937 /** Ring-3 (host) context module. */
938 PDMMOD_TYPE_R3
939} PDMMODTYPE;
940
941
942/** The module name length including the terminator. */
943#define PDMMOD_NAME_LEN 32
944
945/**
946 * Loaded module instance.
947 */
948typedef struct PDMMOD
949{
950 /** Module name. This is used for referring to
951 * the module internally, sort of like a handle. */
952 char szName[PDMMOD_NAME_LEN];
953 /** Module type. */
954 PDMMODTYPE eType;
955 /** Loader module handle. Not used for R0 modules. */
956 RTLDRMOD hLdrMod;
957 /** Loaded address.
958 * This is the 'handle' for R0 modules. */
959 RTUINTPTR ImageBase;
960 /** Old loaded address.
961 * This is used during relocation of GC modules. Not used for R0 modules. */
962 RTUINTPTR OldImageBase;
963 /** Where the R3 HC bits are stored.
964 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
965 void *pvBits;
966
967 /** Pointer to next module. */
968 struct PDMMOD *pNext;
969 /** Module filename. */
970 char szFilename[1];
971} PDMMOD;
972/** Pointer to loaded module instance. */
973typedef PDMMOD *PPDMMOD;
974
975
976
977/** Extra space in the free array. */
978#define PDMQUEUE_FREE_SLACK 16
979
980/**
981 * Queue type.
982 */
983typedef enum PDMQUEUETYPE
984{
985 /** Device consumer. */
986 PDMQUEUETYPE_DEV = 1,
987 /** Driver consumer. */
988 PDMQUEUETYPE_DRV,
989 /** Internal consumer. */
990 PDMQUEUETYPE_INTERNAL,
991 /** External consumer. */
992 PDMQUEUETYPE_EXTERNAL
993} PDMQUEUETYPE;
994
995/** Pointer to a PDM Queue. */
996typedef struct PDMQUEUE *PPDMQUEUE;
997
998/**
999 * PDM Queue.
1000 */
1001typedef struct PDMQUEUE
1002{
1003 /** Pointer to the next queue in the list. */
1004 R3PTRTYPE(PPDMQUEUE) pNext;
1005 /** Type specific data. */
1006 union
1007 {
1008 /** PDMQUEUETYPE_DEV */
1009 struct
1010 {
1011 /** Pointer to consumer function. */
1012 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1013 /** Pointer to the device instance owning the queue. */
1014 R3PTRTYPE(PPDMDEVINS) pDevIns;
1015 } Dev;
1016 /** PDMQUEUETYPE_DRV */
1017 struct
1018 {
1019 /** Pointer to consumer function. */
1020 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1021 /** Pointer to the driver instance owning the queue. */
1022 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1023 } Drv;
1024 /** PDMQUEUETYPE_INTERNAL */
1025 struct
1026 {
1027 /** Pointer to consumer function. */
1028 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1029 } Int;
1030 /** PDMQUEUETYPE_EXTERNAL */
1031 struct
1032 {
1033 /** Pointer to consumer function. */
1034 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1035 /** Pointer to user argument. */
1036 R3PTRTYPE(void *) pvUser;
1037 } Ext;
1038 } u;
1039 /** Queue type. */
1040 PDMQUEUETYPE enmType;
1041 /** The interval between checking the queue for events.
1042 * The realtime timer below is used to do the waiting.
1043 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1044 uint32_t cMilliesInterval;
1045 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1046 TMTIMERHANDLE hTimer;
1047 /** Pointer to the VM - R3. */
1048 PVMR3 pVMR3;
1049 /** LIFO of pending items - R3. */
1050 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
1051 /** Pointer to the VM - R0. */
1052 PVMR0 pVMR0;
1053 /** LIFO of pending items - R0. */
1054 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
1055 /** Pointer to the GC VM and indicator for GC enabled queue.
1056 * If this is NULL, the queue cannot be used in GC.
1057 */
1058 PVMRC pVMRC;
1059 /** LIFO of pending items - GC. */
1060 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
1061
1062 /** Item size (bytes). */
1063 uint32_t cbItem;
1064 /** Number of items in the queue. */
1065 uint32_t cItems;
1066 /** Index to the free head (where we insert). */
1067 uint32_t volatile iFreeHead;
1068 /** Index to the free tail (where we remove). */
1069 uint32_t volatile iFreeTail;
1070
1071 /** Unique queue name. */
1072 R3PTRTYPE(const char *) pszName;
1073#if HC_ARCH_BITS == 32
1074 RTR3PTR Alignment1;
1075#endif
1076 /** Stat: Times PDMQueueAlloc fails. */
1077 STAMCOUNTER StatAllocFailures;
1078 /** Stat: PDMQueueInsert calls. */
1079 STAMCOUNTER StatInsert;
1080 /** Stat: Queue flushes. */
1081 STAMCOUNTER StatFlush;
1082 /** Stat: Queue flushes with pending items left over. */
1083 STAMCOUNTER StatFlushLeftovers;
1084#ifdef VBOX_WITH_STATISTICS
1085 /** State: Profiling the flushing. */
1086 STAMPROFILE StatFlushPrf;
1087 /** State: Pending items. */
1088 uint32_t volatile cStatPending;
1089 uint32_t volatile cAlignment;
1090#endif
1091
1092 /** Array of pointers to free items. Variable size. */
1093 struct PDMQUEUEFREEITEM
1094 {
1095 /** Pointer to the free item - HC Ptr. */
1096 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1097 /** Pointer to the free item - HC Ptr. */
1098 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1099 /** Pointer to the free item - GC Ptr. */
1100 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1101#if HC_ARCH_BITS == 64
1102 RTRCPTR Alignment0;
1103#endif
1104 } aFreeItems[1];
1105} PDMQUEUE;
1106
1107/** @name PDM::fQueueFlushing
1108 * @{ */
1109/** Used to make sure only one EMT will flush the queues.
1110 * Set when an EMT is flushing queues, clear otherwise. */
1111#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1112/** Indicating there are queues with items pending.
1113 * This is make sure we don't miss inserts happening during flushing. The FF
1114 * cannot be used for this since it has to be cleared immediately to prevent
1115 * other EMTs from spinning. */
1116#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1117/** @} */
1118
1119
1120/** @name PDM task structures.
1121 * @{ */
1122
1123/**
1124 * A asynchronous user mode task.
1125 */
1126typedef struct PDMTASK
1127{
1128 /** Task owner type. */
1129 PDMTASKTYPE volatile enmType;
1130 /** Queue flags. */
1131 uint32_t volatile fFlags;
1132 /** User argument for the callback. */
1133 R3PTRTYPE(void *) volatile pvUser;
1134 /** The callback (will be cast according to enmType before callout). */
1135 R3PTRTYPE(PFNRT) volatile pfnCallback;
1136 /** The owner identifier. */
1137 R3PTRTYPE(void *) volatile pvOwner;
1138 /** Task name. */
1139 R3PTRTYPE(const char *) pszName;
1140 /** Number of times already triggered when PDMTaskTrigger was called. */
1141 uint32_t volatile cAlreadyTrigged;
1142 /** Number of runs. */
1143 uint32_t cRuns;
1144} PDMTASK;
1145/** Pointer to a PDM task. */
1146typedef PDMTASK *PPDMTASK;
1147
1148/**
1149 * A task set.
1150 *
1151 * This is served by one task executor thread.
1152 */
1153typedef struct PDMTASKSET
1154{
1155 /** Magic value (PDMTASKSET_MAGIC). */
1156 uint32_t u32Magic;
1157 /** Set if this task set works for ring-0 and raw-mode. */
1158 bool fRZEnabled;
1159 /** Number of allocated taks. */
1160 uint8_t volatile cAllocated;
1161 /** Base handle value for this set. */
1162 uint16_t uHandleBase;
1163 /** The task executor thread. */
1164 R3PTRTYPE(RTTHREAD) hThread;
1165 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1166 SUPSEMEVENT hEventR0;
1167 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1168 R3PTRTYPE(RTSEMEVENT) hEventR3;
1169 /** The VM pointer. */
1170 PVM pVM;
1171 /** Padding so fTriggered is in its own cacheline. */
1172 uint64_t au64Padding2[3];
1173
1174 /** Bitmask of triggered tasks. */
1175 uint64_t volatile fTriggered;
1176 /** Shutdown thread indicator. */
1177 bool volatile fShutdown;
1178 /** Padding. */
1179 bool volatile afPadding3[3];
1180 /** Task currently running, UINT32_MAX if idle. */
1181 uint32_t volatile idxRunning;
1182 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1183 uint64_t volatile au64Padding3[6];
1184
1185 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1186 PDMTASK aTasks[64];
1187} PDMTASKSET;
1188AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1189AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1190/** Magic value for PDMTASKSET::u32Magic. */
1191#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1192/** Pointer to a task set. */
1193typedef PDMTASKSET *PPDMTASKSET;
1194
1195/** @} */
1196
1197
1198/**
1199 * Queue device helper task operation.
1200 */
1201typedef enum PDMDEVHLPTASKOP
1202{
1203 /** The usual invalid 0 entry. */
1204 PDMDEVHLPTASKOP_INVALID = 0,
1205 /** IsaSetIrq, IoApicSetIrq */
1206 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1207 /** PciSetIrq */
1208 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1209 /** PciSetIrq */
1210 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1211 /** IoApicSendMsi */
1212 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1213 /** The usual 32-bit hack. */
1214 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1215} PDMDEVHLPTASKOP;
1216
1217/**
1218 * Queued Device Helper Task.
1219 */
1220typedef struct PDMDEVHLPTASK
1221{
1222 /** The queue item core (don't touch). */
1223 PDMQUEUEITEMCORE Core;
1224 /** Pointer to the device instance (R3 Ptr). */
1225 PPDMDEVINSR3 pDevInsR3;
1226 /** This operation to perform. */
1227 PDMDEVHLPTASKOP enmOp;
1228#if HC_ARCH_BITS == 64
1229 uint32_t Alignment0;
1230#endif
1231 /** Parameters to the operation. */
1232 union PDMDEVHLPTASKPARAMS
1233 {
1234 /**
1235 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1236 */
1237 struct PDMDEVHLPTASKISASETIRQ
1238 {
1239 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1240 PCIBDF uBusDevFn;
1241 /** The IRQ */
1242 int iIrq;
1243 /** The new level. */
1244 int iLevel;
1245 /** The IRQ tag and source. */
1246 uint32_t uTagSrc;
1247 } IsaSetIrq, IoApicSetIrq;
1248
1249 /**
1250 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1251 */
1252 struct PDMDEVHLPTASKPCISETIRQ
1253 {
1254 /** Pointer to the PCI device (R3 Ptr). */
1255 R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1256 /** The IRQ */
1257 int iIrq;
1258 /** The new level. */
1259 int iLevel;
1260 /** The IRQ tag and source. */
1261 uint32_t uTagSrc;
1262 } PciSetIrq;
1263
1264 /**
1265 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1266 */
1267 struct PDMDEVHLPTASKIOAPICSENDMSI
1268 {
1269 /** The bus:device:function of the device sending the MSI. */
1270 PCIBDF uBusDevFn;
1271 /** The MSI. */
1272 MSIMSG Msi;
1273 /** The IRQ tag and source. */
1274 uint32_t uTagSrc;
1275 } IoApicSendMsi;
1276
1277 /** Expanding the structure. */
1278 uint64_t au64[3];
1279 } u;
1280} PDMDEVHLPTASK;
1281/** Pointer to a queued Device Helper Task. */
1282typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1283/** Pointer to a const queued Device Helper Task. */
1284typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1285
1286
1287
1288/**
1289 * An USB hub registration record.
1290 */
1291typedef struct PDMUSBHUB
1292{
1293 /** The USB versions this hub support.
1294 * Note that 1.1 hubs can take on 2.0 devices. */
1295 uint32_t fVersions;
1296 /** The number of ports on the hub. */
1297 uint32_t cPorts;
1298 /** The number of available ports (0..cPorts). */
1299 uint32_t cAvailablePorts;
1300 /** The driver instance of the hub. */
1301 PPDMDRVINS pDrvIns;
1302 /** Copy of the to the registration structure. */
1303 PDMUSBHUBREG Reg;
1304
1305 /** Pointer to the next hub in the list. */
1306 struct PDMUSBHUB *pNext;
1307} PDMUSBHUB;
1308
1309/** Pointer to a const USB HUB registration record. */
1310typedef const PDMUSBHUB *PCPDMUSBHUB;
1311
1312/** Pointer to a PDM Async I/O template. */
1313typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1314
1315/** Pointer to the main PDM Async completion endpoint class. */
1316typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1317
1318/** Pointer to the global block cache structure. */
1319typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1320
1321/**
1322 * PDM VMCPU Instance data.
1323 * Changes to this must checked against the padding of the pdm union in VMCPU!
1324 */
1325typedef struct PDMCPU
1326{
1327 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1328 * in use. */
1329 uint32_t cQueuedCritSectLeaves;
1330 uint32_t uPadding0; /**< Alignment padding.*/
1331 /** Critical sections queued in RC/R0 because of contention preventing leave to
1332 * complete. (R3 Ptrs)
1333 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1334 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1335
1336 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1337 * currently in use. */
1338 uint32_t cQueuedCritSectRwExclLeaves;
1339 uint32_t uPadding1; /**< Alignment padding.*/
1340 /** Read/write critical sections queued in RC/R0 because of contention
1341 * preventing exclusive leave to complete. (R3 Ptrs)
1342 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1343 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1344
1345 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1346 * currently in use. */
1347 uint32_t cQueuedCritSectRwShrdLeaves;
1348 uint32_t uPadding2; /**< Alignment padding.*/
1349 /** Read/write critical sections queued in RC/R0 because of contention
1350 * preventing shared leave to complete. (R3 Ptrs)
1351 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1352 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1353} PDMCPU;
1354
1355
1356/**
1357 * PDM VM Instance data.
1358 * Changes to this must checked against the padding of the cfgm union in VM!
1359 */
1360typedef struct PDM
1361{
1362 /** The PDM lock.
1363 * This is used to protect everything that deals with interrupts, i.e.
1364 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1365 PDMCRITSECT CritSect;
1366 /** The NOP critical section.
1367 * This is a dummy critical section that will not do any thread
1368 * serialization but instead let all threads enter immediately and
1369 * concurrently. */
1370 PDMCRITSECT NopCritSect;
1371
1372 /** The ring-0 capable task sets (max 128). */
1373 PDMTASKSET aTaskSets[2];
1374 /** Pointer to task sets (max 512). */
1375 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1376
1377 /** PCI Buses. */
1378 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1379 /** IOMMU devices. */
1380 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1381 /** The register PIC device. */
1382 PDMPIC Pic;
1383 /** The registered APIC device. */
1384 PDMAPIC Apic;
1385 /** The registered I/O APIC device. */
1386 PDMIOAPIC IoApic;
1387 /** The registered HPET device. */
1388 PPDMDEVINSR3 pHpet;
1389
1390 /** List of registered devices. (FIFO) */
1391 R3PTRTYPE(PPDMDEV) pDevs;
1392 /** List of devices instances. (FIFO) */
1393 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1394 /** List of registered USB devices. (FIFO) */
1395 R3PTRTYPE(PPDMUSB) pUsbDevs;
1396 /** List of USB devices instances. (FIFO) */
1397 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1398 /** List of registered drivers. (FIFO) */
1399 R3PTRTYPE(PPDMDRV) pDrvs;
1400 /** The registered firmware device (can be NULL). */
1401 R3PTRTYPE(PPDMFW) pFirmware;
1402 /** The registered DMAC device. */
1403 R3PTRTYPE(PPDMDMAC) pDmac;
1404 /** The registered RTC device. */
1405 R3PTRTYPE(PPDMRTC) pRtc;
1406 /** The registered USB HUBs. (FIFO) */
1407 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1408
1409 /** @name Queues
1410 * @{ */
1411 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1412 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1413 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1414 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1415 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1416 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1417 /** Pointer to the queue which should be manually flushed - RC Ptr.
1418 * Only touched by EMT. */
1419 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1420 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1421 * Only touched by EMT. */
1422 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1423 /** Bitmask controlling the queue flushing.
1424 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1425 uint32_t volatile fQueueFlushing;
1426 /** @} */
1427
1428 /** The current IRQ tag (tracing purposes). */
1429 uint32_t volatile uIrqTag;
1430
1431 /** Pending reset flags (PDMVMRESET_F_XXX). */
1432 uint32_t volatile fResetFlags;
1433
1434 /** Set by pdmR3LoadExec for use in assertions. */
1435 bool fStateLoaded;
1436 /** Alignment padding. */
1437 bool afPadding[3];
1438
1439 /** The tracing ID of the next device instance.
1440 *
1441 * @remarks We keep the device tracing ID seperate from the rest as these are
1442 * then more likely to end up with the same ID from one run to
1443 * another, making analysis somewhat easier. Drivers and USB devices
1444 * are more volatile and can be changed at runtime, thus these are much
1445 * less likely to remain stable, so just heap them all together. */
1446 uint32_t idTracingDev;
1447 /** The tracing ID of the next driver instance, USB device instance or other
1448 * PDM entity requiring an ID. */
1449 uint32_t idTracingOther;
1450
1451 /** @name VMM device heap
1452 * @{ */
1453 /** The heap size. */
1454 uint32_t cbVMMDevHeap;
1455 /** Free space. */
1456 uint32_t cbVMMDevHeapLeft;
1457 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1458 RTR3PTR pvVMMDevHeap;
1459 /** Ring-3 mapping/unmapping notification callback for the user. */
1460 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1461 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1462 RTGCPHYS GCPhysVMMDevHeap;
1463 /** @} */
1464
1465 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1466 STAMCOUNTER StatQueuedCritSectLeaves;
1467} PDM;
1468AssertCompileMemberAlignment(PDM, CritSect, 8);
1469AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1470AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1471AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1472/** Pointer to PDM VM instance data. */
1473typedef PDM *PPDM;
1474
1475
1476/**
1477 * PDM data kept in the ring-0 GVM.
1478 */
1479typedef struct PDMR0PERVM
1480{
1481 /** PCI Buses, ring-0 data. */
1482 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1483 /** IOMMUs, ring-0 data. */
1484 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1485 /** Number of valid ring-0 device instances (apDevInstances). */
1486 uint32_t cDevInstances;
1487 uint32_t u32Padding;
1488 /** Pointer to ring-0 device instances. */
1489 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1490} PDMR0PERVM;
1491
1492
1493/**
1494 * PDM data kept in the UVM.
1495 */
1496typedef struct PDMUSERPERVM
1497{
1498 /** @todo move more stuff over here. */
1499
1500 /** Linked list of timer driven PDM queues.
1501 * Currently serialized by PDM::CritSect. */
1502 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1503 /** Linked list of force action driven PDM queues.
1504 * Currently serialized by PDM::CritSect. */
1505 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1506
1507 /** Lock protecting the lists below it. */
1508 RTCRITSECT ListCritSect;
1509 /** Pointer to list of loaded modules. */
1510 PPDMMOD pModules;
1511 /** List of initialized critical sections. (LIFO) */
1512 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1513 /** List of initialized read/write critical sections. (LIFO) */
1514 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1515 /** Head of the PDM Thread list. (singly linked) */
1516 R3PTRTYPE(PPDMTHREAD) pThreads;
1517 /** Tail of the PDM Thread list. (singly linked) */
1518 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1519
1520 /** @name PDM Async Completion
1521 * @{ */
1522 /** Pointer to the array of supported endpoint classes. */
1523 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1524 /** Head of the templates. Singly linked, protected by ListCritSect. */
1525 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1526 /** @} */
1527
1528 /** Global block cache data. */
1529 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1530#ifdef VBOX_WITH_NETSHAPER
1531 /** Pointer to network shaper instance. */
1532 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1533#endif /* VBOX_WITH_NETSHAPER */
1534
1535} PDMUSERPERVM;
1536/** Pointer to the PDM data kept in the UVM. */
1537typedef PDMUSERPERVM *PPDMUSERPERVM;
1538
1539
1540
1541/*******************************************************************************
1542* Global Variables *
1543*******************************************************************************/
1544#ifdef IN_RING3
1545extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1546extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1547# ifdef VBOX_WITH_DBGF_TRACING
1548extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1549# endif
1550extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1551extern const PDMPICHLP g_pdmR3DevPicHlp;
1552extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1553extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1554extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1555extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1556extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1557extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1558extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1559extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1560#endif
1561
1562
1563/*******************************************************************************
1564* Defined Constants And Macros *
1565*******************************************************************************/
1566/** @def PDMDEV_ASSERT_DEVINS
1567 * Asserts the validity of the device instance.
1568 */
1569#ifdef VBOX_STRICT
1570# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1571 do { \
1572 AssertPtr(pDevIns); \
1573 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1574 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1575 } while (0)
1576#else
1577# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1578#endif
1579
1580/** @def PDMDRV_ASSERT_DRVINS
1581 * Asserts the validity of the driver instance.
1582 */
1583#ifdef VBOX_STRICT
1584# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1585 do { \
1586 AssertPtr(pDrvIns); \
1587 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1588 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1589 } while (0)
1590#else
1591# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1592#endif
1593
1594
1595/*******************************************************************************
1596* Internal Functions *
1597*******************************************************************************/
1598#ifdef IN_RING3
1599bool pdmR3IsValidName(const char *pszName);
1600
1601int pdmR3CritSectBothInitStats(PVM pVM);
1602void pdmR3CritSectBothRelocate(PVM pVM);
1603int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1604int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1605int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1606 const char *pszNameFmt, va_list va);
1607int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1608 const char *pszNameFmt, ...);
1609int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1610 const char *pszNameFmt, ...);
1611int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1612 const char *pszNameFmt, va_list va);
1613int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1614 const char *pszNameFmt, ...);
1615int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1616 const char *pszNameFmt, ...);
1617
1618int pdmR3DevInit(PVM pVM);
1619int pdmR3DevInitComplete(PVM pVM);
1620PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1621int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1622DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1623
1624int pdmR3UsbLoadModules(PVM pVM);
1625int pdmR3UsbInstantiateDevices(PVM pVM);
1626PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1627int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1628int pdmR3UsbVMInitComplete(PVM pVM);
1629
1630int pdmR3DrvInit(PVM pVM);
1631int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1632 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1633int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1634void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1635PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1636
1637int pdmR3LdrInitU(PUVM pUVM);
1638void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1639char *pdmR3FileR3(const char *pszFile, bool fShared);
1640int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1641
1642void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1643
1644int pdmR3TaskInit(PVM pVM);
1645void pdmR3TaskTerm(PVM pVM);
1646
1647int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1648 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1649int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1650 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1651int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1652 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1653int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1654int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1655int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1656void pdmR3ThreadDestroyAll(PVM pVM);
1657int pdmR3ThreadResumeAll(PVM pVM);
1658int pdmR3ThreadSuspendAll(PVM pVM);
1659
1660#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1661int pdmR3AsyncCompletionInit(PVM pVM);
1662int pdmR3AsyncCompletionTerm(PVM pVM);
1663void pdmR3AsyncCompletionResume(PVM pVM);
1664int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1665int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1666 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1667int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1668int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1669int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1670int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1671#endif
1672
1673#ifdef VBOX_WITH_NETSHAPER
1674int pdmR3NetShaperInit(PVM pVM);
1675int pdmR3NetShaperTerm(PVM pVM);
1676#endif
1677
1678int pdmR3BlkCacheInit(PVM pVM);
1679void pdmR3BlkCacheTerm(PVM pVM);
1680int pdmR3BlkCacheResume(PVM pVM);
1681
1682#endif /* IN_RING3 */
1683
1684void pdmLock(PVMCC pVM);
1685int pdmLockEx(PVMCC pVM, int rc);
1686void pdmUnlock(PVMCC pVM);
1687bool pdmLockIsOwner(PCVMCC pVM);
1688
1689#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1690bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1691int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1692int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1693int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1694# ifdef IN_RING3
1695int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1696int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1697int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1698int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1699# endif
1700#endif
1701
1702#if defined(IN_RING3) || defined(IN_RING0)
1703void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1704void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1705#endif
1706
1707#ifdef IN_RING0
1708DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1709#endif
1710
1711#ifdef VBOX_WITH_DBGF_TRACING
1712# ifdef IN_RING3
1713DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1714 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1715 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1716 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1717DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1718DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1719DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1720 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1721 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1722 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1723DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1724DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1725DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1726DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1727DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1728DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1729DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1730DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1731DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1732DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1733# elif defined(IN_RING0)
1734DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1735 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1736 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1737 void *pvUser);
1738DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1739 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1740DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1741DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1742DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1743DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1744DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1745DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1746DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1747DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1748# else
1749# error "Invalid environment selected"
1750# endif
1751#endif
1752
1753
1754/** @} */
1755
1756RT_C_DECLS_END
1757
1758#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1759
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